| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright (c) 2020, Intel Corporation |
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| 3 | * DWMAC Intel header file |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __DWMAC_INTEL_H__ |
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| 7 | #define __DWMAC_INTEL_H__ |
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| 8 | |
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| 9 | #define POLL_DELAY_US 8 |
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| 10 | |
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| 11 | /* SERDES Register */ |
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| 12 | #define SERDES_GCR 0x0 /* Global Conguration */ |
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| 13 | #define SERDES_GSR0 0x5 /* Global Status Reg0 */ |
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| 14 | #define SERDES_GCR0 0xb /* Global Configuration Reg0 */ |
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| 15 | |
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| 16 | /* SERDES defines */ |
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| 17 | #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ |
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| 18 | #define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ |
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| 19 | #define SERDES_RST BIT(2) /* Serdes Reset */ |
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| 20 | #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ |
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| 21 | #define SERDES_RATE_MASK GENMASK(9, 8) |
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| 22 | #define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */ |
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| 23 | #define SERDES_LINK_MODE_MASK GENMASK(2, 1) |
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| 24 | #define SERDES_LINK_MODE_SHIFT 1 |
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| 25 | #define SERDES_PWR_ST_SHIFT 4 |
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| 26 | #define SERDES_PWR_ST_P0 0x0 |
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| 27 | #define SERDES_PWR_ST_P3 0x3 |
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| 28 | #define SERDES_LINK_MODE_2G5 0x3 |
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| 29 | #define SERSED_LINK_MODE_1G 0x2 |
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| 30 | #define SERDES_PCLK_37p5MHZ 0x0 |
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| 31 | #define SERDES_PCLK_70MHZ 0x1 |
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| 32 | #define SERDES_RATE_PCIE_GEN1 0x0 |
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| 33 | #define SERDES_RATE_PCIE_GEN2 0x1 |
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| 34 | #define SERDES_RATE_PCIE_SHIFT 8 |
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| 35 | #define SERDES_PCLK_SHIFT 12 |
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| 36 | |
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| 37 | #define INTEL_MGBE_ADHOC_ADDR 0x15 |
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| 38 | #define INTEL_MGBE_XPCS_ADDR 0x16 |
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| 39 | |
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| 40 | /* Cross-timestamping defines */ |
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| 41 | #define ART_CPUID_LEAF 0x15 |
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| 42 | #define EHL_PSE_ART_MHZ 19200000 |
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| 43 | |
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| 44 | /* Selection for PTP Clock Freq belongs to PSE & PCH GbE */ |
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| 45 | #define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3) |
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| 46 | #define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) |
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| 47 | #define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3) |
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| 48 | #define PSE_PTP_CLK_FREQ_256MHZ (0) |
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| 49 | #define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0) |
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| 50 | #define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) |
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| 51 | #define PCH_PTP_CLK_FREQ_200MHZ (0) |
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| 52 | |
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| 53 | #endif /* __DWMAC_INTEL_H__ */ |
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| 54 | |
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