1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Header File to describe the DMA descriptors and related definitions specific |
4 | * for DesignWare databook 4.xx. |
5 | * |
6 | * Copyright (C) 2015 STMicroelectronics Ltd |
7 | * |
8 | * Author: Alexandre Torgue <alexandre.torgue@st.com> |
9 | */ |
10 | |
11 | #ifndef __DWMAC4_DESCS_H__ |
12 | #define __DWMAC4_DESCS_H__ |
13 | |
14 | #include <linux/bitops.h> |
15 | |
16 | /* Normal transmit descriptor defines (without split feature) */ |
17 | |
18 | /* TDES2 (read format) */ |
19 | #define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0) |
20 | #define TDES2_VLAN_TAG_MASK GENMASK(15, 14) |
21 | #define TDES2_VLAN_TAG_SHIFT 14 |
22 | #define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16) |
23 | #define TDES2_BUFFER2_SIZE_MASK_SHIFT 16 |
24 | #define TDES3_IVTIR_MASK GENMASK(19, 18) |
25 | #define TDES3_IVTIR_SHIFT 18 |
26 | #define TDES3_IVLTV BIT(17) |
27 | #define TDES2_TIMESTAMP_ENABLE BIT(30) |
28 | #define TDES2_IVT_MASK GENMASK(31, 16) |
29 | #define TDES2_IVT_SHIFT 16 |
30 | #define TDES2_INTERRUPT_ON_COMPLETION BIT(31) |
31 | |
32 | /* TDES3 (read format) */ |
33 | #define TDES3_PACKET_SIZE_MASK GENMASK(14, 0) |
34 | #define TDES3_VLAN_TAG GENMASK(15, 0) |
35 | #define TDES3_VLTV BIT(16) |
36 | #define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16) |
37 | #define TDES3_CHECKSUM_INSERTION_SHIFT 16 |
38 | #define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0) |
39 | #define TDES3_TCP_SEGMENTATION_ENABLE BIT(18) |
40 | #define TDES3_HDR_LEN_SHIFT 19 |
41 | #define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19) |
42 | #define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23) |
43 | #define TDES3_SA_INSERT_CTRL_SHIFT 23 |
44 | #define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26) |
45 | |
46 | /* TDES3 (write back format) */ |
47 | #define TDES3_IP_HDR_ERROR BIT(0) |
48 | #define TDES3_DEFERRED BIT(1) |
49 | #define TDES3_UNDERFLOW_ERROR BIT(2) |
50 | #define TDES3_EXCESSIVE_DEFERRAL BIT(3) |
51 | #define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4) |
52 | #define TDES3_COLLISION_COUNT_SHIFT 4 |
53 | #define TDES3_EXCESSIVE_COLLISION BIT(8) |
54 | #define TDES3_LATE_COLLISION BIT(9) |
55 | #define TDES3_NO_CARRIER BIT(10) |
56 | #define TDES3_LOSS_CARRIER BIT(11) |
57 | #define TDES3_PAYLOAD_ERROR BIT(12) |
58 | #define TDES3_PACKET_FLUSHED BIT(13) |
59 | #define TDES3_JABBER_TIMEOUT BIT(14) |
60 | #define TDES3_ERROR_SUMMARY BIT(15) |
61 | #define TDES3_TIMESTAMP_STATUS BIT(17) |
62 | #define TDES3_TIMESTAMP_STATUS_SHIFT 17 |
63 | |
64 | /* TDES3 context */ |
65 | #define TDES3_CTXT_TCMSSV BIT(26) |
66 | |
67 | /* TDES3 Common */ |
68 | #define TDES3_RS1V BIT(26) |
69 | #define TDES3_RS1V_SHIFT 26 |
70 | #define TDES3_LAST_DESCRIPTOR BIT(28) |
71 | #define TDES3_LAST_DESCRIPTOR_SHIFT 28 |
72 | #define TDES3_FIRST_DESCRIPTOR BIT(29) |
73 | #define TDES3_CONTEXT_TYPE BIT(30) |
74 | #define TDES3_CONTEXT_TYPE_SHIFT 30 |
75 | |
76 | /* TDES4 */ |
77 | #define TDES4_LTV BIT(31) |
78 | #define TDES4_LT GENMASK(7, 0) |
79 | |
80 | /* TDES5 */ |
81 | #define TDES5_LT GENMASK(31, 8) |
82 | |
83 | /* TDS3 use for both format (read and write back) */ |
84 | #define TDES3_OWN BIT(31) |
85 | #define TDES3_OWN_SHIFT 31 |
86 | |
87 | /* Normal receive descriptor defines (without split feature) */ |
88 | |
89 | /* RDES0 (write back format) */ |
90 | #define RDES0_VLAN_TAG_MASK GENMASK(15, 0) |
91 | |
92 | /* RDES1 (write back format) */ |
93 | #define RDES1_IP_PAYLOAD_TYPE_MASK GENMASK(2, 0) |
94 | #define RDES1_IP_HDR_ERROR BIT(3) |
95 | #define BIT(4) |
96 | #define BIT(5) |
97 | #define RDES1_IP_CSUM_BYPASSED BIT(6) |
98 | #define RDES1_IP_CSUM_ERROR BIT(7) |
99 | #define RDES1_PTP_MSG_TYPE_MASK GENMASK(11, 8) |
100 | #define RDES1_PTP_PACKET_TYPE BIT(12) |
101 | #define RDES1_PTP_VER BIT(13) |
102 | #define RDES1_TIMESTAMP_AVAILABLE BIT(14) |
103 | #define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14 |
104 | #define RDES1_TIMESTAMP_DROPPED BIT(15) |
105 | #define RDES1_IP_TYPE1_CSUM_MASK GENMASK(31, 16) |
106 | |
107 | /* RDES2 (write back format) */ |
108 | #define GENMASK(9, 0) |
109 | #define RDES2_VLAN_FILTER_STATUS BIT(15) |
110 | #define RDES2_SA_FILTER_FAIL BIT(16) |
111 | #define RDES2_DA_FILTER_FAIL BIT(17) |
112 | #define RDES2_HASH_FILTER_STATUS BIT(18) |
113 | #define RDES2_MAC_ADDR_MATCH_MASK GENMASK(26, 19) |
114 | #define RDES2_HASH_VALUE_MATCH_MASK GENMASK(26, 19) |
115 | #define RDES2_L3_FILTER_MATCH BIT(27) |
116 | #define RDES2_L4_FILTER_MATCH BIT(28) |
117 | #define RDES2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26) |
118 | #define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26 |
119 | #define RDES2_HL GENMASK(9, 0) |
120 | |
121 | /* RDES3 (write back format) */ |
122 | #define RDES3_PACKET_SIZE_MASK GENMASK(14, 0) |
123 | #define RDES3_ERROR_SUMMARY BIT(15) |
124 | #define RDES3_PACKET_LEN_TYPE_MASK GENMASK(18, 16) |
125 | #define RDES3_DRIBBLE_ERROR BIT(19) |
126 | #define RDES3_RECEIVE_ERROR BIT(20) |
127 | #define RDES3_OVERFLOW_ERROR BIT(21) |
128 | #define RDES3_RECEIVE_WATCHDOG BIT(22) |
129 | #define RDES3_GIANT_PACKET BIT(23) |
130 | #define RDES3_CRC_ERROR BIT(24) |
131 | #define RDES3_RDES0_VALID BIT(25) |
132 | #define RDES3_RDES1_VALID BIT(26) |
133 | #define RDES3_RDES2_VALID BIT(27) |
134 | #define RDES3_LAST_DESCRIPTOR BIT(28) |
135 | #define RDES3_FIRST_DESCRIPTOR BIT(29) |
136 | #define RDES3_CONTEXT_DESCRIPTOR BIT(30) |
137 | #define RDES3_CONTEXT_DESCRIPTOR_SHIFT 30 |
138 | |
139 | /* RDES3 (read format) */ |
140 | #define RDES3_BUFFER1_VALID_ADDR BIT(24) |
141 | #define RDES3_BUFFER2_VALID_ADDR BIT(25) |
142 | #define RDES3_INT_ON_COMPLETION_EN BIT(30) |
143 | |
144 | /* TDS3 use for both format (read and write back) */ |
145 | #define RDES3_OWN BIT(31) |
146 | |
147 | #endif /* __DWMAC4_DESCS_H__ */ |
148 | |