1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2023, Intel Corporation |
4 | * stmmac EST(802.3 Qbv) handling |
5 | */ |
6 | |
7 | #define EST_GMAC4_OFFSET 0x00000c50 |
8 | #define EST_XGMAC_OFFSET 0x00001050 |
9 | |
10 | #define EST_CONTROL 0x00000000 |
11 | #define EST_GMAC5_PTOV GENMASK(31, 24) |
12 | #define EST_GMAC5_PTOV_SHIFT 24 |
13 | #define EST_GMAC5_PTOV_MUL 6 |
14 | #define EST_XGMAC_PTOV GENMASK(31, 23) |
15 | #define EST_XGMAC_PTOV_SHIFT 23 |
16 | #define EST_XGMAC_PTOV_MUL 9 |
17 | #define EST_SSWL BIT(1) |
18 | #define EST_EEST BIT(0) |
19 | |
20 | #define EST_STATUS 0x00000008 |
21 | #define EST_GMAC5_BTRL GENMASK(11, 8) |
22 | #define EST_XGMAC_BTRL GENMASK(15, 8) |
23 | #define EST_SWOL BIT(7) |
24 | #define EST_SWOL_SHIFT 7 |
25 | #define EST_CGCE BIT(4) |
26 | #define EST_HLBS BIT(3) |
27 | #define EST_HLBF BIT(2) |
28 | #define EST_BTRE BIT(1) |
29 | #define EST_SWLC BIT(0) |
30 | |
31 | #define EST_SCH_ERR 0x00000010 |
32 | |
33 | #define EST_FRM_SZ_ERR 0x00000014 |
34 | |
35 | #define EST_FRM_SZ_CAP 0x00000018 |
36 | #define EST_SZ_CAP_HBFS_MASK GENMASK(14, 0) |
37 | #define EST_SZ_CAP_HBFQ_SHIFT 16 |
38 | #define EST_SZ_CAP_HBFQ_MASK(val) \ |
39 | ({ \ |
40 | typeof(val) _val = (val); \ |
41 | (_val > 4 ? GENMASK(18, 16) : \ |
42 | _val > 2 ? GENMASK(17, 16) : \ |
43 | BIT(16)); \ |
44 | }) |
45 | |
46 | #define EST_INT_EN 0x00000020 |
47 | #define EST_IECGCE EST_CGCE |
48 | #define EST_IEHS EST_HLBS |
49 | #define EST_IEHF EST_HLBF |
50 | #define EST_IEBE EST_BTRE |
51 | #define EST_IECC EST_SWLC |
52 | |
53 | #define EST_GCL_CONTROL 0x00000030 |
54 | #define EST_BTR_LOW 0x0 |
55 | #define EST_BTR_HIGH 0x1 |
56 | #define EST_CTR_LOW 0x2 |
57 | #define EST_CTR_HIGH 0x3 |
58 | #define EST_TER 0x4 |
59 | #define EST_LLR 0x5 |
60 | #define EST_ADDR_SHIFT 8 |
61 | #define EST_GCRR BIT(2) |
62 | #define EST_SRWO BIT(0) |
63 | |
64 | #define EST_GCL_DATA 0x00000034 |
65 | |