| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /****************************************************************************** |
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| 3 | * |
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| 4 | * (C)Copyright 1998,1999 SysKonnect, |
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| 5 | * a business unit of Schneider & Koch & Co. Datensysteme GmbH. |
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| 6 | * |
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| 7 | * The information in this file is provided "AS IS" without warranty. |
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| 8 | * |
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| 9 | ******************************************************************************/ |
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| 10 | |
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| 11 | #ifndef _SKFBI_H_ |
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| 12 | #define _SKFBI_H_ |
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| 13 | |
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| 14 | /* |
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| 15 | * FDDI-Fx (x := {I(SA), P(CI)}) |
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| 16 | * address calculation & function defines |
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| 17 | */ |
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| 18 | |
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| 19 | /*--------------------------------------------------------------------------*/ |
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| 20 | #ifdef PCI |
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| 21 | |
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| 22 | /* |
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| 23 | * (DV) = only defined for Da Vinci |
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| 24 | * (ML) = only defined for Monalisa |
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| 25 | */ |
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| 26 | |
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| 27 | |
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| 28 | /* |
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| 29 | * I2C Address (PCI Config) |
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| 30 | * |
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| 31 | * Note: The temperature and voltage sensors are relocated on a different |
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| 32 | * I2C bus. |
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| 33 | */ |
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| 34 | #define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ |
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| 35 | |
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| 36 | /* |
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| 37 | * Control Register File: |
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| 38 | * Bank 0 |
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| 39 | */ |
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| 40 | #define B0_RAP 0x0000 /* 8 bit register address port */ |
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| 41 | /* 0x0001 - 0x0003: reserved */ |
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| 42 | #define B0_CTRL 0x0004 /* 8 bit control register */ |
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| 43 | #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */ |
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| 44 | #define B0_LED 0x0006 /* 8 Bit LED register */ |
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| 45 | #define B0_TST_CTRL 0x0007 /* 8 bit test control register */ |
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| 46 | #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */ |
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| 47 | #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */ |
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| 48 | |
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| 49 | /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ |
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| 50 | #define B0_CMDREG1 0x0010 /* write command reg 1 instruction */ |
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| 51 | #define B0_CMDREG2 0x0014 /* write command reg 2 instruction */ |
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| 52 | #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */ |
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| 53 | #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */ |
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| 54 | #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */ |
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| 55 | #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */ |
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| 56 | |
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| 57 | #define B0_MARR 0x0020 /* r/w the memory read addr register */ |
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| 58 | #define B0_MARW 0x0024 /* r/w the memory write addr register*/ |
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| 59 | #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */ |
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| 60 | #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */ |
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| 61 | |
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| 62 | #define B0_MDREG3 0x0030 /* r/w Mode Register 3 */ |
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| 63 | #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */ |
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| 64 | #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */ |
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| 65 | #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */ |
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| 66 | #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */ |
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| 67 | #define B0_IVR 0x0044 /* read Interrupt Vector register */ |
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| 68 | #define B0_IMR 0x0048 /* r/w Interrupt mask register */ |
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| 69 | /* 0x4c Hidden */ |
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| 70 | |
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| 71 | #define B0_CNTRL_A 0x0050 /* control register A (r/w) */ |
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| 72 | #define B0_CNTRL_B 0x0054 /* control register B (r/w) */ |
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| 73 | #define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */ |
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| 74 | #define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */ |
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| 75 | |
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| 76 | #define B0_STATUS_A 0x0060 /* status register A (read only) */ |
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| 77 | #define B0_STATUS_B 0x0064 /* status register B (read only) */ |
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| 78 | #define B0_CNTRL_C 0x0068 /* control register C (r/w) */ |
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| 79 | #define B0_MDREG1 0x006c /* r/w Mode Register 1 */ |
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| 80 | |
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| 81 | #define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */ |
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| 82 | #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ |
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| 83 | #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ |
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| 84 | #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ |
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| 85 | |
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| 86 | /* |
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| 87 | * Bank 1 |
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| 88 | * - completely empty (this is the RAP Block window) |
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| 89 | * Note: if RAP = 1 this page is reserved |
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| 90 | */ |
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| 91 | |
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| 92 | /* |
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| 93 | * Bank 2 |
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| 94 | */ |
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| 95 | #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */ |
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| 96 | #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */ |
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| 97 | #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */ |
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| 98 | #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */ |
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| 99 | #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */ |
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| 100 | #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */ |
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| 101 | #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */ |
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| 102 | #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */ |
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| 103 | |
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| 104 | #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */ |
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| 105 | #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */ |
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| 106 | /* 0x010a - 0x010b: reserved */ |
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| 107 | /* Eprom registers are currently of no use */ |
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| 108 | #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */ |
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| 109 | #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */ |
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| 110 | #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */ |
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| 111 | #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */ |
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| 112 | #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */ |
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| 113 | #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */ |
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| 114 | /* 0x0115 - 0x0117: reserved */ |
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| 115 | #define B2_LD_CRTL 0x0118 /* 8 bit loader control */ |
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| 116 | #define B2_LD_TEST 0x0119 /* 8 bit loader test */ |
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| 117 | /* 0x011a - 0x011f: reserved */ |
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| 118 | #define B2_TI_INI 0x0120 /* 32 bit Timer init value */ |
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| 119 | #define B2_TI_VAL 0x0124 /* 32 bit Timer value */ |
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| 120 | #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */ |
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| 121 | #define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */ |
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| 122 | /* 0x012a - 0x012f: reserved */ |
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| 123 | #define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */ |
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| 124 | #define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */ |
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| 125 | #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */ |
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| 126 | #define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */ |
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| 127 | /* 0x013a - 0x013f: reserved */ |
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| 128 | #define B2_RTM_INI 0x0140 /* 32 bit RTM init value */ |
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| 129 | #define B2_RTM_VAL 0x0144 /* 32 bit RTM value */ |
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| 130 | #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */ |
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| 131 | #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */ |
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| 132 | |
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| 133 | #define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */ |
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| 134 | #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */ |
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| 135 | #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */ |
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| 136 | #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */ |
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| 137 | /* 0x0156: reserved */ |
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| 138 | #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */ |
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| 139 | #define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */ |
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| 140 | #define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */ |
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| 141 | |
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| 142 | #define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */ |
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| 143 | #define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */ |
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| 144 | #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */ |
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| 145 | #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */ |
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| 146 | /* 0x016a - 0x017f: reserved */ |
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| 147 | |
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| 148 | /* |
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| 149 | * Bank 3 |
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| 150 | */ |
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| 151 | /* |
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| 152 | * This is a copy of the Configuration register file (lower half) |
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| 153 | */ |
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| 154 | #define B3_CFG_SPC 0x180 |
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| 155 | |
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| 156 | /* |
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| 157 | * Bank 4 |
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| 158 | */ |
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| 159 | #define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */ |
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| 160 | #define B4_R1_DA 0x0210 /* 32 bit current rec desc address */ |
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| 161 | #define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */ |
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| 162 | #define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */ |
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| 163 | #define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */ |
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| 164 | #define B4_R1_F 0x0220 /* 32 bit flag register */ |
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| 165 | #define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */ |
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| 166 | #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */ |
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| 167 | #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */ |
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| 168 | #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */ |
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| 169 | #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */ |
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| 170 | #define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */ |
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| 171 | #define B4_R1_T3 0x022c /* 32 bit Test Register 3 */ |
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| 172 | #define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */ |
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| 173 | #define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */ |
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| 174 | /* 0x0238 - 0x023f: reserved */ |
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| 175 | /* Receive queue 2 is removed on Monalisa */ |
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| 176 | #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */ |
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| 177 | #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */ |
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| 178 | #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */ |
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| 179 | #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */ |
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| 180 | #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */ |
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| 181 | #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */ |
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| 182 | #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */ |
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| 183 | #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */ |
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| 184 | #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */ |
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| 185 | #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */ |
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| 186 | #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */ |
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| 187 | #define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */ |
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| 188 | #define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */ |
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| 189 | /* 0x0270 - 0x027c: reserved */ |
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| 190 | |
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| 191 | /* |
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| 192 | * Bank 5 |
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| 193 | */ |
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| 194 | #define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */ |
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| 195 | #define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */ |
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| 196 | #define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */ |
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| 197 | #define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */ |
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| 198 | #define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */ |
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| 199 | #define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */ |
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| 200 | #define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */ |
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| 201 | #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */ |
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| 202 | #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */ |
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| 203 | #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */ |
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| 204 | #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */ |
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| 205 | #define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */ |
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| 206 | #define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */ |
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| 207 | #define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */ |
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| 208 | #define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */ |
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| 209 | /* 0x02b8 - 0x02bc: reserved */ |
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| 210 | #define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */ |
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| 211 | #define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */ |
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| 212 | #define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */ |
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| 213 | #define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */ |
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| 214 | #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */ |
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| 215 | #define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */ |
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| 216 | #define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */ |
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| 217 | #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */ |
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| 218 | #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */ |
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| 219 | #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */ |
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| 220 | #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */ |
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| 221 | #define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */ |
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| 222 | #define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */ |
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| 223 | #define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */ |
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| 224 | #define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */ |
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| 225 | /* 0x02f8 - 0x02fc: reserved */ |
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| 226 | |
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| 227 | /* |
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| 228 | * Bank 6 |
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| 229 | */ |
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| 230 | /* External PLC-S registers (SN2 compatibility for DV) */ |
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| 231 | /* External registers (ML) */ |
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| 232 | #define B6_EXT_REG 0x300 |
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| 233 | |
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| 234 | /* |
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| 235 | * Bank 7 |
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| 236 | */ |
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| 237 | /* DAS PLC-S Registers */ |
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| 238 | |
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| 239 | /* |
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| 240 | * Bank 8 - 15 |
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| 241 | */ |
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| 242 | /* IFCP registers */ |
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| 243 | |
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| 244 | /*---------------------------------------------------------------------------*/ |
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| 245 | /* Definitions of the Bits in the registers */ |
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| 246 | |
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| 247 | /* B0_RAP 16 bit register address port */ |
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| 248 | #define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */ |
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| 249 | |
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| 250 | /* B0_CTRL 8 bit control register */ |
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| 251 | #define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */ |
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| 252 | #define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */ |
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| 253 | #define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */ |
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| 254 | #define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */ |
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| 255 | #define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */ |
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| 256 | #define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */ |
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| 257 | #define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */ |
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| 258 | #define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */ |
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| 259 | |
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| 260 | /* B0_DAS 8 Bit control register (DAS) */ |
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| 261 | #define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */ |
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| 262 | #define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/ |
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| 263 | /* Bit 5..4: reserved */ |
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| 264 | #define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */ |
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| 265 | #define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */ |
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| 266 | #define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */ |
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| 267 | #define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */ |
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| 268 | |
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| 269 | /* B0_LED 8 Bit LED register */ |
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| 270 | /* Bit 7..6: reserved */ |
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| 271 | #define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/ |
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| 272 | #define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */ |
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| 273 | #define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/ |
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| 274 | #define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */ |
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| 275 | #define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/ |
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| 276 | #define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */ |
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| 277 | /* This hardware defines are very ugly therefore we define some others */ |
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| 278 | |
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| 279 | #define LED_GA_ON LED_2_ON /* S port = A port */ |
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| 280 | #define LED_GA_OFF LED_2_OFF /* S port = A port */ |
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| 281 | #define LED_MY_ON LED_1_ON |
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| 282 | #define LED_MY_OFF LED_1_OFF |
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| 283 | #define LED_GB_ON LED_0_ON |
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| 284 | #define LED_GB_OFF LED_0_OFF |
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| 285 | |
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| 286 | /* B0_TST_CTRL 8 bit test control register */ |
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| 287 | #define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */ |
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| 288 | #define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */ |
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| 289 | #define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */ |
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| 290 | #define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */ |
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| 291 | #define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */ |
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| 292 | #define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */ |
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| 293 | #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ |
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| 294 | #define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */ |
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| 295 | |
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| 296 | /* B0_ISRC 32 bit Interrupt source register */ |
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| 297 | /* Bit 31..28: reserved */ |
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| 298 | #define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ |
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| 299 | #define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ |
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| 300 | #define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ |
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| 301 | #define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ |
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| 302 | /* PERR, RMABORT, RTABORT DATAPERR */ |
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| 303 | #define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ |
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| 304 | /* RMABORT, RTABORT, DATAPERR */ |
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| 305 | #define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */ |
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| 306 | #define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */ |
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| 307 | /* |
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| 308 | * Note: The DAS is our First Port (!=PA) |
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| 309 | */ |
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| 310 | #define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */ |
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| 311 | #define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ |
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| 312 | #define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ |
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| 313 | #define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ |
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| 314 | #define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ |
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| 315 | /* Receive Queue 1 */ |
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| 316 | #define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ |
|---|
| 317 | #define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ |
|---|
| 318 | #define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ |
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| 319 | #define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ |
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| 320 | /* Receive Queue 2 */ |
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| 321 | #define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ |
|---|
| 322 | #define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ |
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| 323 | #define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ |
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| 324 | #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ |
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| 325 | /* Asynchronous Transmit queue */ |
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| 326 | /* Bit 7: reserved */ |
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| 327 | #define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ |
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| 328 | #define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ |
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| 329 | #define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ |
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| 330 | /* Synchronous Transmit queue */ |
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| 331 | /* Bit 3: reserved */ |
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| 332 | #define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ |
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| 333 | #define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ |
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| 334 | #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ |
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| 335 | |
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| 336 | /* |
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| 337 | * Define all valid interrupt source Bits from GET_ISR () |
|---|
| 338 | */ |
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| 339 | #define ALL_IRSR 0x01ffff77L /* (DV) */ |
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| 340 | #define ALL_IRSR_ML 0x0ffff077L /* (ML) */ |
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| 341 | |
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| 342 | |
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| 343 | /* B0_IMSK 32 bit Interrupt mask register */ |
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| 344 | /* |
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| 345 | * The Bit definnition of this register are the same as of the interrupt |
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| 346 | * source register. These definition are directly derived from the Hardware |
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| 347 | * spec. |
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| 348 | */ |
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| 349 | /* Bit 31..28: reserved */ |
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| 350 | #define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ |
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| 351 | #define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ |
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| 352 | #define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ |
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| 353 | #define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ |
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| 354 | /* PERR, RMABORT, RTABORT DATAPERR */ |
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| 355 | #define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ |
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| 356 | /* RMABORT, RTABORT, DATAPERR */ |
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| 357 | #define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */ |
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| 358 | #define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */ |
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| 359 | #define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */ |
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| 360 | #define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ |
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| 361 | #define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ |
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| 362 | #define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ |
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| 363 | #define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ |
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| 364 | /* Receive Queue 1 */ |
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| 365 | #define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ |
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| 366 | #define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ |
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| 367 | #define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ |
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| 368 | #define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ |
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| 369 | /* Receive Queue 2 */ |
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| 370 | #define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ |
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| 371 | #define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ |
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| 372 | #define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ |
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| 373 | #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ |
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| 374 | /* Asynchronous Transmit queue */ |
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| 375 | /* Bit 7: reserved */ |
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| 376 | #define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ |
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| 377 | #define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ |
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| 378 | #define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ |
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| 379 | /* Synchronous Transmit queue */ |
|---|
| 380 | /* Bit 3: reserved */ |
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| 381 | #define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ |
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| 382 | #define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ |
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| 383 | #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ |
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| 384 | |
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| 385 | /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ |
|---|
| 386 | /* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */ |
|---|
| 387 | /* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */ |
|---|
| 388 | /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */ |
|---|
| 389 | /* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */ |
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| 390 | /* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */ |
|---|
| 391 | |
|---|
| 392 | /* B2_MAC_0 8 bit MAC address Byte 0 */ |
|---|
| 393 | /* B2_MAC_1 8 bit MAC address Byte 1 */ |
|---|
| 394 | /* B2_MAC_2 8 bit MAC address Byte 2 */ |
|---|
| 395 | /* B2_MAC_3 8 bit MAC address Byte 3 */ |
|---|
| 396 | /* B2_MAC_4 8 bit MAC address Byte 4 */ |
|---|
| 397 | /* B2_MAC_5 8 bit MAC address Byte 5 */ |
|---|
| 398 | /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */ |
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| 399 | /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */ |
|---|
| 400 | |
|---|
| 401 | /* B2_CONN_TYP 8 bit Connector type */ |
|---|
| 402 | /* B2_PMD_TYP 8 bit PMD type */ |
|---|
| 403 | /* Values of connector and PMD type comply to SysKonnect internal std */ |
|---|
| 404 | |
|---|
| 405 | /* The EPROM register are currently of no use */ |
|---|
| 406 | /* B2_E_0 8 bit EPROM Byte 0 */ |
|---|
| 407 | /* B2_E_1 8 bit EPROM Byte 1 */ |
|---|
| 408 | /* B2_E_2 8 bit EPROM Byte 2 */ |
|---|
| 409 | /* B2_E_3 8 bit EPROM Byte 3 */ |
|---|
| 410 | |
|---|
| 411 | /* B2_FAR 32 bit Flash-Prom Address Register/Counter */ |
|---|
| 412 | #define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */ |
|---|
| 413 | |
|---|
| 414 | /* B2_FDP 8 bit Flash-Prom Data Port */ |
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| 415 | |
|---|
| 416 | /* B2_LD_CRTL 8 bit loader control */ |
|---|
| 417 | /* Bits are currently reserved */ |
|---|
| 418 | |
|---|
| 419 | /* B2_LD_TEST 8 bit loader test */ |
|---|
| 420 | #define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */ |
|---|
| 421 | #define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */ |
|---|
| 422 | #define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */ |
|---|
| 423 | #define LD_START (1<<0) /* Bit 0: Start loading FPROM */ |
|---|
| 424 | |
|---|
| 425 | /* B2_TI_INI 32 bit Timer init value */ |
|---|
| 426 | /* B2_TI_VAL 32 bit Timer value */ |
|---|
| 427 | /* B2_TI_CRTL 8 bit Timer control */ |
|---|
| 428 | /* B2_TI_TEST 8 Bit Timer Test */ |
|---|
| 429 | /* B2_WDOG_INI 32 bit Watchdog init value */ |
|---|
| 430 | /* B2_WDOG_VAL 32 bit Watchdog value */ |
|---|
| 431 | /* B2_WDOG_CRTL 8 bit Watchdog control */ |
|---|
| 432 | /* B2_WDOG_TEST 8 Bit Watchdog Test */ |
|---|
| 433 | /* B2_RTM_INI 32 bit RTM init value */ |
|---|
| 434 | /* B2_RTM_VAL 32 bit RTM value */ |
|---|
| 435 | /* B2_RTM_CRTL 8 bit RTM control */ |
|---|
| 436 | /* B2_RTM_TEST 8 Bit RTM Test */ |
|---|
| 437 | /* B2_<TIM>_CRTL 8 bit <TIM> control */ |
|---|
| 438 | /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */ |
|---|
| 439 | /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */ |
|---|
| 440 | /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */ |
|---|
| 441 | /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */ |
|---|
| 442 | #define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */ |
|---|
| 443 | #define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */ |
|---|
| 444 | #define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */ |
|---|
| 445 | #define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/ |
|---|
| 446 | #define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */ |
|---|
| 447 | #define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */ |
|---|
| 448 | /* B2_<TIM>_TEST 8 Bit <TIM> Test */ |
|---|
| 449 | #define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */ |
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| 450 | #define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */ |
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| 451 | #define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */ |
|---|
| 452 | |
|---|
| 453 | /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */ |
|---|
| 454 | /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */ |
|---|
| 455 | /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */ |
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| 456 | /* Bit 7..5: reserved */ |
|---|
| 457 | #define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */ |
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| 458 | #define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */ |
|---|
| 459 | #define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */ |
|---|
| 460 | #define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */ |
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| 461 | #define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/ |
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| 462 | |
|---|
| 463 | /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */ |
|---|
| 464 | /* Bit 7..3: reserved */ |
|---|
| 465 | #define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/ |
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| 466 | #define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */ |
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| 467 | #define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */ |
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| 468 | |
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| 469 | /* 0x0156: reserved */ |
|---|
| 470 | /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */ |
|---|
| 471 | /* Bit 7..4: reserved */ |
|---|
| 472 | /* force the following error on */ |
|---|
| 473 | /* the next master read/write */ |
|---|
| 474 | #define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */ |
|---|
| 475 | #define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */ |
|---|
| 476 | #define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */ |
|---|
| 477 | #define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */ |
|---|
| 478 | |
|---|
| 479 | /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */ |
|---|
| 480 | #define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */ |
|---|
| 481 | #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/ |
|---|
| 482 | #define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */ |
|---|
| 483 | /* Bit 5.. 8: reserved */ |
|---|
| 484 | #define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */ |
|---|
| 485 | #define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */ |
|---|
| 486 | #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/ |
|---|
| 487 | #define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ |
|---|
| 488 | #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ |
|---|
| 489 | #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ |
|---|
| 490 | #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ |
|---|
| 491 | #define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ |
|---|
| 492 | #define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ |
|---|
| 493 | #define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ |
|---|
| 494 | #define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */ |
|---|
| 495 | |
|---|
| 496 | /* |
|---|
| 497 | * I2C Addresses |
|---|
| 498 | * |
|---|
| 499 | * The temperature sensor and the voltage sensor are on the same I2C bus. |
|---|
| 500 | * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1 |
|---|
| 501 | * in PCI_OUR_REG 1. |
|---|
| 502 | */ |
|---|
| 503 | #define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */ |
|---|
| 504 | |
|---|
| 505 | /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */ |
|---|
| 506 | |
|---|
| 507 | /* B4_R1_D 4*32 bit current receive Descriptor (q1) */ |
|---|
| 508 | /* B4_R1_DA 32 bit current rec desc address (q1) */ |
|---|
| 509 | /* B4_R1_AC 32 bit current receive Address Count (q1) */ |
|---|
| 510 | /* B4_R1_BC 32 bit current receive Byte Counter (q1) */ |
|---|
| 511 | /* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */ |
|---|
| 512 | /* B4_R1_F 32 bit flag register (q1) */ |
|---|
| 513 | /* B4_R1_T1 32 bit Test Register 1 (q1) */ |
|---|
| 514 | /* B4_R1_T2 32 bit Test Register 2 (q1) */ |
|---|
| 515 | /* B4_R1_T3 32 bit Test Register 3 (q1) */ |
|---|
| 516 | /* B4_R2_D 4*32 bit current receive Descriptor (q2) */ |
|---|
| 517 | /* B4_R2_DA 32 bit current rec desc address (q2) */ |
|---|
| 518 | /* B4_R2_AC 32 bit current receive Address Count (q2) */ |
|---|
| 519 | /* B4_R2_BC 32 bit current receive Byte Counter (q2) */ |
|---|
| 520 | /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */ |
|---|
| 521 | /* B4_R2_F 32 bit flag register (q2) */ |
|---|
| 522 | /* B4_R2_T1 32 bit Test Register 1 (q2) */ |
|---|
| 523 | /* B4_R2_T2 32 bit Test Register 2 (q2) */ |
|---|
| 524 | /* B4_R2_T3 32 bit Test Register 3 (q2) */ |
|---|
| 525 | /* B5_XA_D 4*32 bit current receive Descriptor (xa) */ |
|---|
| 526 | /* B5_XA_DA 32 bit current rec desc address (xa) */ |
|---|
| 527 | /* B5_XA_AC 32 bit current receive Address Count (xa) */ |
|---|
| 528 | /* B5_XA_BC 32 bit current receive Byte Counter (xa) */ |
|---|
| 529 | /* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */ |
|---|
| 530 | /* B5_XA_F 32 bit flag register (xa) */ |
|---|
| 531 | /* B5_XA_T1 32 bit Test Register 1 (xa) */ |
|---|
| 532 | /* B5_XA_T2 32 bit Test Register 2 (xa) */ |
|---|
| 533 | /* B5_XA_T3 32 bit Test Register 3 (xa) */ |
|---|
| 534 | /* B5_XS_D 4*32 bit current receive Descriptor (xs) */ |
|---|
| 535 | /* B5_XS_DA 32 bit current rec desc address (xs) */ |
|---|
| 536 | /* B5_XS_AC 32 bit current receive Address Count (xs) */ |
|---|
| 537 | /* B5_XS_BC 32 bit current receive Byte Counter (xs) */ |
|---|
| 538 | /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */ |
|---|
| 539 | /* B5_XS_F 32 bit flag register (xs) */ |
|---|
| 540 | /* B5_XS_T1 32 bit Test Register 1 (xs) */ |
|---|
| 541 | /* B5_XS_T2 32 bit Test Register 2 (xs) */ |
|---|
| 542 | /* B5_XS_T3 32 bit Test Register 3 (xs) */ |
|---|
| 543 | /* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */ |
|---|
| 544 | #define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */ |
|---|
| 545 | #define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */ |
|---|
| 546 | #define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */ |
|---|
| 547 | #define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */ |
|---|
| 548 | #define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */ |
|---|
| 549 | #define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */ |
|---|
| 550 | #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */ |
|---|
| 551 | #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */ |
|---|
| 552 | #define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */ |
|---|
| 553 | #define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */ |
|---|
| 554 | #define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */ |
|---|
| 555 | #define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */ |
|---|
| 556 | #define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */ |
|---|
| 557 | #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */ |
|---|
| 558 | /* Bit 7..5: reserved */ |
|---|
| 559 | #define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */ |
|---|
| 560 | #define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */ |
|---|
| 561 | #define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */ |
|---|
| 562 | #define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */ |
|---|
| 563 | #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */ |
|---|
| 564 | |
|---|
| 565 | #define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\ |
|---|
| 566 | CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST) |
|---|
| 567 | #define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\ |
|---|
| 568 | CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN) |
|---|
| 569 | |
|---|
| 570 | |
|---|
| 571 | /* B5_<xx>_F 32 bit flag register (xx) */ |
|---|
| 572 | /* Bit 28..31: reserved */ |
|---|
| 573 | #define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */ |
|---|
| 574 | #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */ |
|---|
| 575 | #define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */ |
|---|
| 576 | #define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/ |
|---|
| 577 | /* Bit 23: reserved */ |
|---|
| 578 | #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/ |
|---|
| 579 | /* Bit 8..15: reserved */ |
|---|
| 580 | #define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */ |
|---|
| 581 | #define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/ |
|---|
| 582 | |
|---|
| 583 | /* B5_<xx>_T1 32 bit Test Register 1 (xx) */ |
|---|
| 584 | /* Holds four State Machine control Bytes */ |
|---|
| 585 | #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ |
|---|
| 586 | #define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ |
|---|
| 587 | #define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */ |
|---|
| 588 | #define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */ |
|---|
| 589 | |
|---|
| 590 | /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */ |
|---|
| 591 | /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */ |
|---|
| 592 | /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */ |
|---|
| 593 | /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */ |
|---|
| 594 | /* The control status byte of each machine looks like ... */ |
|---|
| 595 | #define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */ |
|---|
| 596 | #define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */ |
|---|
| 597 | #define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */ |
|---|
| 598 | #define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */ |
|---|
| 599 | #define SM_STEP 0x01 /* Bit 0: Step the State Machine */ |
|---|
| 600 | |
|---|
| 601 | /* The coding of the states */ |
|---|
| 602 | #define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */ |
|---|
| 603 | #define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */ |
|---|
| 604 | #define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */ |
|---|
| 605 | #define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */ |
|---|
| 606 | #define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */ |
|---|
| 607 | #define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */ |
|---|
| 608 | #define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */ |
|---|
| 609 | |
|---|
| 610 | #define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */ |
|---|
| 611 | #define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */ |
|---|
| 612 | #define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */ |
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| 613 | #define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */ |
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| 614 | #define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */ |
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| 615 | #define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */ |
|---|
| 616 | |
|---|
| 617 | #define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */ |
|---|
| 618 | #define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */ |
|---|
| 619 | #define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */ |
|---|
| 620 | #define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */ |
|---|
| 621 | #define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */ |
|---|
| 622 | |
|---|
| 623 | #define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */ |
|---|
| 624 | #define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */ |
|---|
| 625 | #define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */ |
|---|
| 626 | #define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */ |
|---|
| 627 | #define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */ |
|---|
| 628 | #define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */ |
|---|
| 629 | #define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */ |
|---|
| 630 | #define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */ |
|---|
| 631 | #define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */ |
|---|
| 632 | #define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */ |
|---|
| 633 | #define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */ |
|---|
| 634 | #define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */ |
|---|
| 635 | #define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */ |
|---|
| 636 | #define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */ |
|---|
| 637 | #define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */ |
|---|
| 638 | #define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */ |
|---|
| 639 | |
|---|
| 640 | /* B5_<xx>_T2 32 bit Test Register 2 (xx) */ |
|---|
| 641 | /* Note: This register is only defined for the transmit queues */ |
|---|
| 642 | /* Bit 31..8: reserved */ |
|---|
| 643 | #define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */ |
|---|
| 644 | #define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/ |
|---|
| 645 | #define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */ |
|---|
| 646 | #define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */ |
|---|
| 647 | #define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */ |
|---|
| 648 | #define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */ |
|---|
| 649 | #define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */ |
|---|
| 650 | #define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */ |
|---|
| 651 | |
|---|
| 652 | /* B5_<xx>_T3 32 bit Test Register 3 (xx) */ |
|---|
| 653 | /* Note: This register is only defined for the transmit queues */ |
|---|
| 654 | /* Bit 31..8: reserved */ |
|---|
| 655 | #define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */ |
|---|
| 656 | #define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */ |
|---|
| 657 | #define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */ |
|---|
| 658 | #define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */ |
|---|
| 659 | #define T3_MUX (3<<2) /* Bit 3..2: Mux position */ |
|---|
| 660 | #define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */ |
|---|
| 661 | |
|---|
| 662 | |
|---|
| 663 | /* |
|---|
| 664 | * address transmission from logical to physical offset address on board |
|---|
| 665 | */ |
|---|
| 666 | #define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */ |
|---|
| 667 | #define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */ |
|---|
| 668 | #define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */ |
|---|
| 669 | #define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */ |
|---|
| 670 | |
|---|
| 671 | /* |
|---|
| 672 | * FlashProm specification |
|---|
| 673 | */ |
|---|
| 674 | #define MAX_PAGES 0x20000L /* Every byte has a single page */ |
|---|
| 675 | #define MAX_FADDR 1 /* 1 byte per page */ |
|---|
| 676 | |
|---|
| 677 | /* |
|---|
| 678 | * Receive / Transmit Buffer Control word |
|---|
| 679 | */ |
|---|
| 680 | #define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */ |
|---|
| 681 | #define BMU_STF (1L<<30) /* Start of Frame ? */ |
|---|
| 682 | #define BMU_EOF (1L<<29) /* End of Frame ? */ |
|---|
| 683 | #define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */ |
|---|
| 684 | #define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */ |
|---|
| 685 | #define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */ |
|---|
| 686 | #define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */ |
|---|
| 687 | #define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */ |
|---|
| 688 | #define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */ |
|---|
| 689 | #define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */ |
|---|
| 690 | #define BMU_CHECK 0x00550000L /* To identify the control word */ |
|---|
| 691 | #define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */ |
|---|
| 692 | |
|---|
| 693 | /* |
|---|
| 694 | * physical address offset + IO-Port base address |
|---|
| 695 | */ |
|---|
| 696 | #ifdef MEM_MAPPED_IO |
|---|
| 697 | #define ADDR(a) (char far *) smc->hw.iop+(a) |
|---|
| 698 | #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a) |
|---|
| 699 | #else |
|---|
| 700 | #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ |
|---|
| 701 | (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ |
|---|
| 702 | (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) |
|---|
| 703 | #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \ |
|---|
| 704 | ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ |
|---|
| 705 | ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) |
|---|
| 706 | #endif |
|---|
| 707 | |
|---|
| 708 | /* |
|---|
| 709 | * Define a macro to access the configuration space |
|---|
| 710 | */ |
|---|
| 711 | #define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */ |
|---|
| 712 | |
|---|
| 713 | #define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */ |
|---|
| 714 | |
|---|
| 715 | /* |
|---|
| 716 | * Define some values needed for the MAC address (PROM) |
|---|
| 717 | */ |
|---|
| 718 | #define SA_MAC (0) /* start addr. MAC_AD within the PROM */ |
|---|
| 719 | #define PRA_OFF (0) /* offset correction when 4th byte reading */ |
|---|
| 720 | |
|---|
| 721 | #define SKFDDI_PSZ 8 /* address PROM size */ |
|---|
| 722 | |
|---|
| 723 | #define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ |
|---|
| 724 | #define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ |
|---|
| 725 | #define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ |
|---|
| 726 | #define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */ |
|---|
| 727 | |
|---|
| 728 | /* |
|---|
| 729 | * Macro to read the PROM |
|---|
| 730 | */ |
|---|
| 731 | #define READ_PROM(a) ((u_char)inp(a)) |
|---|
| 732 | |
|---|
| 733 | #define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank) |
|---|
| 734 | #define VPP_ON() |
|---|
| 735 | #define VPP_OFF() |
|---|
| 736 | |
|---|
| 737 | /* |
|---|
| 738 | * Note: Values of the Interrupt Source Register are defined above |
|---|
| 739 | */ |
|---|
| 740 | #define ISR_A ADDR(B0_ISRC) |
|---|
| 741 | #define GET_ISR() inpd(ISR_A) |
|---|
| 742 | #define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC) |
|---|
| 743 | #define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK))) |
|---|
| 744 | #define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK)) |
|---|
| 745 | |
|---|
| 746 | #define BUS_CHECK() |
|---|
| 747 | |
|---|
| 748 | /* |
|---|
| 749 | * CLI_FBI: Disable Board Interrupts |
|---|
| 750 | * STI_FBI: Enable Board Interrupts |
|---|
| 751 | */ |
|---|
| 752 | #ifndef UNIX |
|---|
| 753 | #define CLI_FBI() outpd(ADDR(B0_IMSK),0) |
|---|
| 754 | #else |
|---|
| 755 | #define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0) |
|---|
| 756 | #endif |
|---|
| 757 | |
|---|
| 758 | #ifndef UNIX |
|---|
| 759 | #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask) |
|---|
| 760 | #else |
|---|
| 761 | #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask) |
|---|
| 762 | #endif |
|---|
| 763 | |
|---|
| 764 | #define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0) |
|---|
| 765 | #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask) |
|---|
| 766 | |
|---|
| 767 | #endif /* PCI */ |
|---|
| 768 | /*--------------------------------------------------------------------------*/ |
|---|
| 769 | |
|---|
| 770 | /* |
|---|
| 771 | * 12 bit transfer (dword) counter: |
|---|
| 772 | * (ISA: 2*trc = number of byte) |
|---|
| 773 | * (EISA: 4*trc = number of byte) |
|---|
| 774 | * (MCA: 4*trc = number of byte) |
|---|
| 775 | */ |
|---|
| 776 | #define MAX_TRANS (0x0fff) |
|---|
| 777 | |
|---|
| 778 | /* |
|---|
| 779 | * PC PIC |
|---|
| 780 | */ |
|---|
| 781 | #define MST_8259 (0x20) |
|---|
| 782 | #define SLV_8259 (0xA0) |
|---|
| 783 | |
|---|
| 784 | #define TPS (18) /* ticks per second */ |
|---|
| 785 | |
|---|
| 786 | /* |
|---|
| 787 | * error timer defs |
|---|
| 788 | */ |
|---|
| 789 | #define TN (4) /* number of supported timer = TN+1 */ |
|---|
| 790 | #define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */ |
|---|
| 791 | |
|---|
| 792 | #define MAC_AD 0x405a0000 |
|---|
| 793 | |
|---|
| 794 | #define MODR1 FM_A(FM_MDREG1) /* mode register 1 */ |
|---|
| 795 | #define MODR2 FM_A(FM_MDREG2) /* mode register 2 */ |
|---|
| 796 | |
|---|
| 797 | #define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */ |
|---|
| 798 | #define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */ |
|---|
| 799 | |
|---|
| 800 | |
|---|
| 801 | /* |
|---|
| 802 | * function defines |
|---|
| 803 | */ |
|---|
| 804 | #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask))) |
|---|
| 805 | #define SET(io,mask) outpw((io),inpw(io)|(mask)) |
|---|
| 806 | #define GET(io,mask) (inpw(io)&(mask)) |
|---|
| 807 | #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) |
|---|
| 808 | |
|---|
| 809 | /* |
|---|
| 810 | * PHY Port A (PA) = PLC 1 |
|---|
| 811 | * With SuperNet 3 PHY-A and PHY S are identical. |
|---|
| 812 | */ |
|---|
| 813 | #define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) |
|---|
| 814 | |
|---|
| 815 | /* |
|---|
| 816 | * set memory address register for write and read |
|---|
| 817 | */ |
|---|
| 818 | #define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma)) |
|---|
| 819 | #define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma)) |
|---|
| 820 | |
|---|
| 821 | /* |
|---|
| 822 | * read/write from/to memory data register |
|---|
| 823 | */ |
|---|
| 824 | /* write double word */ |
|---|
| 825 | #define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\ |
|---|
| 826 | outpw(FM_A(FM_MDRL),(unsigned int)(dd)) |
|---|
| 827 | |
|---|
| 828 | #ifndef WINNT |
|---|
| 829 | /* read double word */ |
|---|
| 830 | #define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL))) |
|---|
| 831 | |
|---|
| 832 | /* read FORMAC+ 32-bit status register */ |
|---|
| 833 | #define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L))) |
|---|
| 834 | #define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L))) |
|---|
| 835 | #ifdef SUPERNET_3 |
|---|
| 836 | #define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L))) |
|---|
| 837 | #endif |
|---|
| 838 | #else |
|---|
| 839 | /* read double word */ |
|---|
| 840 | #define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL))) |
|---|
| 841 | |
|---|
| 842 | /* read FORMAC+ 32-bit status register */ |
|---|
| 843 | #define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L))) |
|---|
| 844 | #define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L))) |
|---|
| 845 | #ifdef SUPERNET_3 |
|---|
| 846 | #define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L))) |
|---|
| 847 | #endif |
|---|
| 848 | #endif |
|---|
| 849 | |
|---|
| 850 | /* Special timer macro for 82c54 */ |
|---|
| 851 | /* timer access over data bus bit 8..15 */ |
|---|
| 852 | #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8) |
|---|
| 853 | #define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff) |
|---|
| 854 | |
|---|
| 855 | |
|---|
| 856 | #ifdef DEBUG |
|---|
| 857 | #define DB_MAC(mac,st) {if (debug_mac & 0x1)\ |
|---|
| 858 | printf("M") ;\ |
|---|
| 859 | if (debug_mac & 0x2)\ |
|---|
| 860 | printf("\tMAC %d status 0x%08lx\n",mac,st) ;\ |
|---|
| 861 | if (debug_mac & 0x4)\ |
|---|
| 862 | dp_mac(mac,st) ;\ |
|---|
| 863 | } |
|---|
| 864 | |
|---|
| 865 | #define DB_PLC(p,iev) { if (debug_plc & 0x1)\ |
|---|
| 866 | printf("P") ;\ |
|---|
| 867 | if (debug_plc & 0x2)\ |
|---|
| 868 | printf("\tPLC %s Int 0x%04x\n", \ |
|---|
| 869 | (p == PA) ? "A" : "B", iev) ;\ |
|---|
| 870 | if (debug_plc & 0x4)\ |
|---|
| 871 | dp_plc(p,iev) ;\ |
|---|
| 872 | } |
|---|
| 873 | |
|---|
| 874 | #define DB_TIMER() { if (debug_timer & 0x1)\ |
|---|
| 875 | printf("T") ;\ |
|---|
| 876 | if (debug_timer & 0x2)\ |
|---|
| 877 | printf("\tTimer ISR\n") ;\ |
|---|
| 878 | } |
|---|
| 879 | |
|---|
| 880 | #else /* no DEBUG */ |
|---|
| 881 | |
|---|
| 882 | #define DB_MAC(mac,st) |
|---|
| 883 | #define DB_PLC(p,iev) |
|---|
| 884 | #define DB_TIMER() |
|---|
| 885 | |
|---|
| 886 | #endif /* no DEBUG */ |
|---|
| 887 | |
|---|
| 888 | #define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp |
|---|
| 889 | /* |
|---|
| 890 | * timer defs |
|---|
| 891 | */ |
|---|
| 892 | #define COUNT(t) ((t)<<6) /* counter */ |
|---|
| 893 | #define RW_OP(o) ((o)<<4) /* read/write operation */ |
|---|
| 894 | #define TMODE(m) ((m)<<1) /* timer mode */ |
|---|
| 895 | |
|---|
| 896 | #endif |
|---|
| 897 | |
|---|
