1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /****************************************************************************** |
3 | * |
4 | * (C)Copyright 1998,1999 SysKonnect, |
5 | * a business unit of Schneider & Koch & Co. Datensysteme GmbH. |
6 | * |
7 | * The information in this file is provided "AS IS" without warranty. |
8 | * |
9 | ******************************************************************************/ |
10 | |
11 | /* |
12 | defines for AMD Supernet II chip set |
13 | the chips are referred to as |
14 | FPLUS Formac Plus |
15 | PLC Physical Layer |
16 | |
17 | added defines for AMD Supernet III chip set |
18 | added comments on differences between Supernet II and Supernet III |
19 | added defines for the Motorola ELM (MOT_ELM) |
20 | */ |
21 | |
22 | #ifndef _SUPERNET_ |
23 | #define _SUPERNET_ |
24 | |
25 | /* |
26 | * Define Supernet 3 when used |
27 | */ |
28 | #ifdef PCI |
29 | #ifndef SUPERNET_3 |
30 | #define SUPERNET_3 |
31 | #endif |
32 | #define TAG |
33 | #endif |
34 | |
35 | #define MB 0xff |
36 | #define MW 0xffff |
37 | #define MD 0xffffffff |
38 | |
39 | /* |
40 | * FORMAC frame status (rx_msext) |
41 | */ |
42 | #define FS_EI (1<<2) |
43 | #define FS_AI (1<<1) |
44 | #define FS_CI (1<<0) |
45 | |
46 | #define FS_MSVALID (1<<15) /* end of queue */ |
47 | #define FS_MSRABT (1<<14) /* frame was aborted during reception*/ |
48 | #define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/ |
49 | #define FS_SEAC2 (FS_EI<<9) /* error indicator */ |
50 | #define FS_SEAC1 (FS_AI<<9) /* address indicator */ |
51 | #define FS_SEAC0 (FS_CI<<9) /* copy indicator */ |
52 | #define FS_SFRMERR (1<<8) /* error detected (CRC or length) */ |
53 | #define FS_SADRRG (1<<7) /* address recognized */ |
54 | #define FS_SFRMTY2 (1<<6) /* frame-class bit */ |
55 | #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */ |
56 | #define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */ |
57 | #define FS_ERFBB1 (1<<1) /* byte offset (depends on LSB bit) */ |
58 | #define FS_ERFBB0 (1<<0) /* - " - */ |
59 | |
60 | /* |
61 | * status frame type |
62 | */ |
63 | #define FRM_SMT (0) /* asynchr. frames */ |
64 | #define FRM_LLCA (1) |
65 | #define FRM_IMPA (2) |
66 | #define FRM_MAC (4) /* synchr. frames */ |
67 | #define FRM_LLCS (5) |
68 | #define FRM_IMPS (6) |
69 | |
70 | /* |
71 | * bits in rx_descr.i (receive frame status word) |
72 | */ |
73 | #define RX_MSVALID ((long)1<<31) /* memory status valid */ |
74 | #define RX_MSRABT ((long)1<<30) /* memory status receive abort */ |
75 | #define RX_FS_E ((long)FS_SEAC2<<16) /* error indicator */ |
76 | #define RX_FS_A ((long)FS_SEAC1<<16) /* address indicator */ |
77 | #define RX_FS_C ((long)FS_SEAC0<<16) /* copy indicator */ |
78 | #define RX_FS_CRC ((long)FS_SFRMERR<<16)/* error detected */ |
79 | #define RX_FS_ADDRESS ((long)FS_SADRRG<<16) /* address recognized */ |
80 | #define RX_FS_MAC ((long)FS_SFRMTY2<<16)/* MAC frame */ |
81 | #define RX_FS_SMT ((long)0<<16) /* SMT frame */ |
82 | #define RX_FS_IMPL ((long)FS_SFRMTY1<<16)/* implementer frame */ |
83 | #define RX_FS_LLC ((long)FS_SFRMTY0<<16)/* LLC frame */ |
84 | |
85 | /* |
86 | * receive frame descriptor |
87 | */ |
88 | union rx_descr { |
89 | struct { |
90 | #ifdef LITTLE_ENDIAN |
91 | unsigned int rx_length :16 ; /* frame length lower/upper byte */ |
92 | unsigned int rx_erfbb :2 ; /* received frame byte boundary */ |
93 | unsigned int rx_reserv2:2 ; /* reserved */ |
94 | unsigned int rx_sfrmty :3 ; /* frame type bits */ |
95 | unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */ |
96 | unsigned int rx_sfrmerr:1 ; /* received frame not valid */ |
97 | unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */ |
98 | unsigned int rx_seac1 :1 ; /* address-match A-indicator */ |
99 | unsigned int rx_seac2 :1 ; /* frame-error E-indicator */ |
100 | unsigned int rx_ssrcrtg:1 ; /* == 1 SA has MSB set */ |
101 | unsigned int rx_reserv1:1 ; /* reserved */ |
102 | unsigned int rx_msrabt :1 ; /* memory status receive abort */ |
103 | unsigned int rx_msvalid:1 ; /* memory status valid */ |
104 | #else |
105 | unsigned int rx_msvalid:1 ; /* memory status valid */ |
106 | unsigned int rx_msrabt :1 ; /* memory status receive abort */ |
107 | unsigned int rx_reserv1:1 ; /* reserved */ |
108 | unsigned int rx_ssrcrtg:1 ; /* == 1 SA has MSB set */ |
109 | unsigned int rx_seac2 :1 ; /* frame-error E-indicator */ |
110 | unsigned int rx_seac1 :1 ; /* address-match A-indicator */ |
111 | unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */ |
112 | unsigned int rx_sfrmerr:1 ; /* received frame not valid */ |
113 | unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */ |
114 | unsigned int rx_sfrmty :3 ; /* frame type bits */ |
115 | unsigned int rx_erfbb :2 ; /* received frame byte boundary */ |
116 | unsigned int rx_reserv2:2 ; /* reserved */ |
117 | unsigned int rx_length :16 ; /* frame length lower/upper byte */ |
118 | #endif |
119 | } r ; |
120 | long i ; |
121 | } ; |
122 | |
123 | /* defines for Receive Frame Descriptor access */ |
124 | #define RD_S_ERFBB 0x00030000L /* received frame byte boundary */ |
125 | #define RD_S_RES2 0x000c0000L /* reserved */ |
126 | #define RD_S_SFRMTY 0x00700000L /* frame type bits */ |
127 | #define RD_S_SADRRG 0x00800000L /* DA == MA or broad-/multicast */ |
128 | #define RD_S_SFRMERR 0x01000000L /* received frame not valid */ |
129 | #define RD_S_SEAC 0x0e000000L /* frame status indicators */ |
130 | #define RD_S_SEAC0 0x02000000L /* frame-copied case-indicator */ |
131 | #define RD_S_SEAC1 0x04000000L /* address-match A-indicator */ |
132 | #define RD_S_SEAC2 0x08000000L /* frame-error E-indicator */ |
133 | #define RD_S_SSRCRTG 0x10000000L /* == 1 SA has MSB set */ |
134 | #define RD_S_RES1 0x20000000L /* reserved */ |
135 | #define RD_S_MSRABT 0x40000000L /* memory status receive abort */ |
136 | #define RD_S_MSVALID 0x80000000L /* memory status valid */ |
137 | |
138 | #define RD_STATUS 0xffff0000L |
139 | #define RD_LENGTH 0x0000ffffL |
140 | |
141 | /* defines for Receive Frames Status Word values */ |
142 | /*RD_S_SFRMTY*/ |
143 | #define RD_FRM_SMT (unsigned long)(0<<20) /* asynchr. frames */ |
144 | #define RD_FRM_LLCA (unsigned long)(1<<20) |
145 | #define RD_FRM_IMPA (unsigned long)(2<<20) |
146 | #define RD_FRM_MAC (unsigned long)(4<<20) /* synchr. frames */ |
147 | #define RD_FRM_LLCS (unsigned long)(5<<20) |
148 | #define RD_FRM_IMPS (unsigned long)(6<<20) |
149 | |
150 | #define TX_DESCRIPTOR 0x40000000L |
151 | #define TX_OFFSET_3 0x18000000L |
152 | |
153 | #define TXP1 2 |
154 | |
155 | /* |
156 | * transmit frame descriptor |
157 | */ |
158 | union tx_descr { |
159 | struct { |
160 | #ifdef LITTLE_ENDIAN |
161 | unsigned int tx_length:16 ; /* frame length lower/upper byte */ |
162 | unsigned int tx_res :8 ; /* reserved (bit 16..23) */ |
163 | unsigned int tx_xmtabt:1 ; /* transmit abort */ |
164 | unsigned int tx_nfcs :1 ; /* no frame check sequence */ |
165 | unsigned int tx_xdone :1 ; /* give up token */ |
166 | unsigned int tx_rpxm :2 ; /* byte offset */ |
167 | unsigned int tx_pat1 :2 ; /* must be TXP1 */ |
168 | unsigned int tx_more :1 ; /* more frame in chain */ |
169 | #else |
170 | unsigned int tx_more :1 ; /* more frame in chain */ |
171 | unsigned int tx_pat1 :2 ; /* must be TXP1 */ |
172 | unsigned int tx_rpxm :2 ; /* byte offset */ |
173 | unsigned int tx_xdone :1 ; /* give up token */ |
174 | unsigned int tx_nfcs :1 ; /* no frame check sequence */ |
175 | unsigned int tx_xmtabt:1 ; /* transmit abort */ |
176 | unsigned int tx_res :8 ; /* reserved (bit 16..23) */ |
177 | unsigned int tx_length:16 ; /* frame length lower/upper byte */ |
178 | #endif |
179 | } t ; |
180 | long i ; |
181 | } ; |
182 | |
183 | /* defines for Transmit Descriptor access */ |
184 | #define TD_C_MORE 0x80000000L /* more frame in chain */ |
185 | #define TD_C_DESCR 0x60000000L /* must be TXP1 */ |
186 | #define TD_C_TXFBB 0x18000000L /* byte offset */ |
187 | #define TD_C_XDONE 0x04000000L /* give up token */ |
188 | #define TD_C_NFCS 0x02000000L /* no frame check sequence */ |
189 | #define TD_C_XMTABT 0x01000000L /* transmit abort */ |
190 | |
191 | #define TD_C_LNCNU 0x0000ff00L |
192 | #define TD_C_LNCNL 0x000000ffL |
193 | #define TD_C_LNCN 0x0000ffffL /* frame length lower/upper byte */ |
194 | |
195 | /* |
196 | * transmit pointer |
197 | */ |
198 | union tx_pointer { |
199 | struct t { |
200 | #ifdef LITTLE_ENDIAN |
201 | unsigned int tp_pointer:16 ; /* pointer to tx_descr (low/high) */ |
202 | unsigned int tp_res :8 ; /* reserved (bit 16..23) */ |
203 | unsigned int tp_pattern:8 ; /* fixed pattern (bit 24..31) */ |
204 | #else |
205 | unsigned int tp_pattern:8 ; /* fixed pattern (bit 24..31) */ |
206 | unsigned int tp_res :8 ; /* reserved (bit 16..23) */ |
207 | unsigned int tp_pointer:16 ; /* pointer to tx_descr (low/high) */ |
208 | #endif |
209 | } t ; |
210 | long i ; |
211 | } ; |
212 | |
213 | /* defines for Nontag Mode Pointer access */ |
214 | #define TD_P_CNTRL 0xff000000L |
215 | #define TD_P_RPXU 0x0000ff00L |
216 | #define TD_P_RPXL 0x000000ffL |
217 | #define TD_P_RPX 0x0000ffffL |
218 | |
219 | |
220 | #define TX_PATTERN 0xa0 |
221 | #define TX_POINTER_END 0xa0000000L |
222 | #define TX_INT_PATTERN 0xa0000000L |
223 | |
224 | struct tx_queue { |
225 | struct tx_queue *tq_next ; |
226 | u_short tq_pack_offset ; /* offset buffer memory */ |
227 | u_char tq_pad[2] ; |
228 | } ; |
229 | |
230 | /* |
231 | defines for FORMAC Plus (Am79C830) |
232 | */ |
233 | |
234 | /* |
235 | * FORMAC+ read/write (r/w) registers |
236 | */ |
237 | #define FM_CMDREG1 0x00 /* write command reg 1 instruction */ |
238 | #define FM_CMDREG2 0x01 /* write command reg 2 instruction */ |
239 | #define FM_ST1U 0x00 /* read upper 16-bit of status reg 1 */ |
240 | #define FM_ST1L 0x01 /* read lower 16-bit of status reg 1 */ |
241 | #define FM_ST2U 0x02 /* read upper 16-bit of status reg 2 */ |
242 | #define FM_ST2L 0x03 /* read lower 16-bit of status reg 2 */ |
243 | #define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */ |
244 | #define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */ |
245 | #define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */ |
246 | #define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */ |
247 | #define FM_SAID 0x08 /* r/w short addr.-individual */ |
248 | #define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */ |
249 | #define FM_LAIC 0x0a /* r/w long addr.-ind. (middle)*/ |
250 | #define FM_LAIL 0x0b /* r/w long addr.-ind. (LSW) */ |
251 | #define FM_SAGP 0x0c /* r/w short address-group */ |
252 | #define FM_LAGM 0x0d /* r/w long addr.-gr. (MSW of LAGP) */ |
253 | #define FM_LAGC 0x0e /* r/w long addr.-gr. (middle) */ |
254 | #define FM_LAGL 0x0f /* r/w long addr.-gr. (LSW) */ |
255 | #define FM_MDREG1 0x10 /* r/w 16-bit mode reg 1 */ |
256 | #define FM_STMCHN 0x11 /* read state-machine reg */ |
257 | #define FM_MIR1 0x12 /* read upper 16-bit of MAC Info Reg */ |
258 | #define FM_MIR0 0x13 /* read lower 16-bit of MAC Info Reg */ |
259 | #define FM_TMAX 0x14 /* r/w 16-bit TMAX reg */ |
260 | #define FM_TVX 0x15 /* write 8-bit TVX reg with NP7-0 |
261 | read TVX on NP7-0, timer on NP15-8*/ |
262 | #define FM_TRT 0x16 /* r/w upper 16-bit of TRT timer */ |
263 | #define FM_THT 0x17 /* r/w upper 16-bit of THT timer */ |
264 | #define FM_TNEG 0x18 /* read upper 16-bit of TNEG (TTRT) */ |
265 | #define FM_TMRS 0x19 /* read lower 5-bit of TNEG,TRT,THT */ |
266 | /* F E D C B A 9 8 7 6 5 4 3 2 1 0 |
267 | x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */ |
268 | #define FM_TREQ0 0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */ |
269 | #define FM_TREQ1 0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */ |
270 | #define FM_PRI0 0x1c /* r/w priority r. for asyn.-queue 0 */ |
271 | #define FM_PRI1 0x1d /* r/w priority r. for asyn.-queue 1 */ |
272 | #define FM_PRI2 0x1e /* r/w priority r. for asyn.-queue 2 */ |
273 | #define FM_TSYNC 0x1f /* r/w 16-bit of the TSYNC register */ |
274 | #define FM_MDREG2 0x20 /* r/w 16-bit mode reg 2 */ |
275 | #define FM_FRMTHR 0x21 /* r/w the frame threshold register */ |
276 | #define FM_EACB 0x22 /* r/w end addr of claim/beacon area */ |
277 | #define FM_EARV 0x23 /* r/w end addr of receive queue */ |
278 | /* Supernet 3 */ |
279 | #define FM_EARV1 FM_EARV |
280 | |
281 | #define FM_EAS 0x24 /* r/w end addr of synchr. queue */ |
282 | #define FM_EAA0 0x25 /* r/w end addr of asyn. queue 0 */ |
283 | #define FM_EAA1 0x26 /* r/w end addr of asyn. queue 1 */ |
284 | #define FM_EAA2 0x27 /* r/w end addr of asyn. queue 2 */ |
285 | #define FM_SACL 0x28 /* r/w start addr of claim frame */ |
286 | #define FM_SABC 0x29 /* r/w start addr of beacon frame */ |
287 | #define FM_WPXSF 0x2a /* r/w the write ptr. for special fr.*/ |
288 | #define FM_RPXSF 0x2b /* r/w the read ptr. for special fr. */ |
289 | #define FM_RPR 0x2d /* r/w the read ptr. for receive qu. */ |
290 | #define FM_WPR 0x2e /* r/w the write ptr. for receive qu.*/ |
291 | #define FM_SWPR 0x2f /* r/w the shadow wr.-ptr. for rec.q.*/ |
292 | /* Supernet 3 */ |
293 | #define FM_RPR1 FM_RPR |
294 | #define FM_WPR1 FM_WPR |
295 | #define FM_SWPR1 FM_SWPR |
296 | |
297 | #define FM_WPXS 0x30 /* r/w the write ptr. for synchr. qu.*/ |
298 | #define FM_WPXA0 0x31 /* r/w the write ptr. for asyn. qu.0 */ |
299 | #define FM_WPXA1 0x32 /* r/w the write ptr. for asyn. qu.1 */ |
300 | #define FM_WPXA2 0x33 /* r/w the write ptr. for asyn. qu.2 */ |
301 | #define FM_SWPXS 0x34 /* r/w the shadow wr.-ptr. for syn.q.*/ |
302 | #define FM_SWPXA0 0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/ |
303 | #define FM_SWPXA1 0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/ |
304 | #define FM_SWPXA2 0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/ |
305 | #define FM_RPXS 0x38 /* r/w the read ptr. for synchr. qu. */ |
306 | #define FM_RPXA0 0x39 /* r/w the read ptr. for asyn. qu. 0 */ |
307 | #define FM_RPXA1 0x3a /* r/w the read ptr. for asyn. qu. 1 */ |
308 | #define FM_RPXA2 0x3b /* r/w the read ptr. for asyn. qu. 2 */ |
309 | #define FM_MARR 0x3c /* r/w the memory read addr register */ |
310 | #define FM_MARW 0x3d /* r/w the memory write addr register*/ |
311 | #define FM_MDRU 0x3e /* r/w upper 16-bit of mem. data reg */ |
312 | #define FM_MDRL 0x3f /* r/w lower 16-bit of mem. data reg */ |
313 | |
314 | /* following instructions relate to MAC counters and timer */ |
315 | #define FM_TMSYNC 0x40 /* r/w upper 16 bits of TMSYNC timer */ |
316 | #define FM_FCNTR 0x41 /* r/w the 16-bit frame counter */ |
317 | #define FM_LCNTR 0x42 /* r/w the 16-bit lost counter */ |
318 | #define FM_ECNTR 0x43 /* r/w the 16-bit error counter */ |
319 | |
320 | /* Supernet 3: extensions to old register block */ |
321 | #define FM_FSCNTR 0x44 /* r/? Frame Strip Counter */ |
322 | #define FM_FRSELREG 0x45 /* r/w Frame Selection Register */ |
323 | |
324 | /* Supernet 3: extensions for 2. receive queue etc. */ |
325 | #define FM_MDREG3 0x60 /* r/w Mode Register 3 */ |
326 | #define FM_ST3U 0x61 /* read upper 16-bit of status reg 3 */ |
327 | #define FM_ST3L 0x62 /* read lower 16-bit of status reg 3 */ |
328 | #define FM_IMSK3U 0x63 /* r/w upper 16-bit of IMSK reg 3 */ |
329 | #define FM_IMSK3L 0x64 /* r/w lower 16-bit of IMSK reg 3 */ |
330 | #define FM_IVR 0x65 /* read Interrupt Vector register */ |
331 | #define FM_IMR 0x66 /* r/w Interrupt mask register */ |
332 | /* 0x67 Hidden */ |
333 | #define FM_RPR2 0x68 /* r/w the read ptr. for rec. qu. 2 */ |
334 | #define FM_WPR2 0x69 /* r/w the write ptr. for rec. qu. 2 */ |
335 | #define FM_SWPR2 0x6a /* r/w the shadow wptr. for rec. q. 2 */ |
336 | #define FM_EARV2 0x6b /* r/w end addr of rec. qu. 2 */ |
337 | #define FM_UNLCKDLY 0x6c /* r/w Auto Unlock Delay register */ |
338 | /* Bit 15-8: RECV2 unlock threshold */ |
339 | /* Bit 7-0: RECV1 unlock threshold */ |
340 | /* 0x6f-0x73 Hidden */ |
341 | #define FM_LTDPA1 0x79 /* r/w Last Trans desc ptr for A1 qu. */ |
342 | /* 0x80-0x9a PLCS registers of built-in PLCS (Supernet 3 only) */ |
343 | |
344 | /* Supernet 3: Adderss Filter Registers */ |
345 | #define FM_AFCMD 0xb0 /* r/w Address Filter Command Reg */ |
346 | #define FM_AFSTAT 0xb2 /* r/w Address Filter Status Reg */ |
347 | #define FM_AFBIST 0xb4 /* r/w Address Filter BIST signature */ |
348 | #define FM_AFCOMP2 0xb6 /* r/w Address Filter Comparand 2 */ |
349 | #define FM_AFCOMP1 0xb8 /* r/w Address Filter Comparand 1 */ |
350 | #define FM_AFCOMP0 0xba /* r/w Address Filter Comparand 0 */ |
351 | #define FM_AFMASK2 0xbc /* r/w Address Filter Mask 2 */ |
352 | #define FM_AFMASK1 0xbe /* r/w Address Filter Mask 1 */ |
353 | #define FM_AFMASK0 0xc0 /* r/w Address Filter Mask 0 */ |
354 | #define FM_AFPERS 0xc2 /* r/w Address Filter Personality Reg */ |
355 | |
356 | /* Supernet 3: Orion (PDX?) Registers */ |
357 | #define FM_ORBIST 0xd0 /* r/w Orion BIST signature */ |
358 | #define FM_ORSTAT 0xd2 /* r/w Orion Status Register */ |
359 | |
360 | |
361 | /* |
362 | * Mode Register 1 (MDREG1) |
363 | */ |
364 | #define FM_RES0 0x0001 /* reserved */ |
365 | /* SN3: other definition */ |
366 | #define FM_XMTINH_HOLD 0x0002 /* transmit-inhibit/hold bit */ |
367 | /* SN3: other definition */ |
368 | #define FM_HOFLXI 0x0003 /* SN3: Hold / Flush / Inhibit */ |
369 | #define FM_FULL_HALF 0x0004 /* full-duplex/half-duplex bit */ |
370 | #define FM_LOCKTX 0x0008 /* lock-transmit-asynchr.-queues bit */ |
371 | #define FM_EXGPA0 0x0010 /* extended-group-addressing bit 0 */ |
372 | #define FM_EXGPA1 0x0020 /* extended-group-addressing bit 1 */ |
373 | #define FM_DISCRY 0x0040 /* disable-carry bit */ |
374 | /* SN3: reserved */ |
375 | #define FM_SELRA 0x0080 /* select input from PHY (1=RA,0=RB) */ |
376 | |
377 | #define FM_ADDET 0x0700 /* address detection */ |
378 | #define FM_MDAMA (0<<8) /* address detection : DA = MA */ |
379 | #define FM_MDASAMA (1<<8) /* address detection : DA=MA||SA=MA */ |
380 | #define FM_MRNNSAFNMA (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */ |
381 | #define FM_MRNNSAF (3<<8) /* rec. non-NSA frames DA = MA */ |
382 | #define FM_MDISRCV (4<<8) /* disable receive function */ |
383 | #define FM_MRES0 (5<<8) /* reserve */ |
384 | #define FM_MLIMPROM (6<<8) /* limited-promiscuous mode */ |
385 | #define FM_MPROMISCOUS (7<<8) /* address detection : promiscuous */ |
386 | |
387 | #define FM_SELSA 0x0800 /* select-short-address bit */ |
388 | |
389 | #define FM_MMODE 0x7000 /* mode select */ |
390 | #define FM_MINIT (0<<12) /* initialize */ |
391 | #define FM_MMEMACT (1<<12) /* memory activate */ |
392 | #define FM_MONLINESP (2<<12) /* on-line special */ |
393 | #define FM_MONLINE (3<<12) /* on-line (FDDI operational mode) */ |
394 | #define FM_MILOOP (4<<12) /* internal loopback */ |
395 | #define FM_MRES1 (5<<12) /* reserved */ |
396 | #define FM_MRES2 (6<<12) /* reserved */ |
397 | #define FM_MELOOP (7<<12) /* external loopback */ |
398 | |
399 | #define FM_SNGLFRM 0x8000 /* single-frame-receive mode */ |
400 | /* SN3: reserved */ |
401 | |
402 | #define MDR1INIT (FM_MINIT | FM_MDAMA) |
403 | |
404 | /* |
405 | * Mode Register 2 (MDREG2) |
406 | */ |
407 | #define FM_AFULL 0x000f /* 4-bit value (empty loc.in txqueue)*/ |
408 | #define FM_RCVERR 0x0010 /* rec.-errored-frames bit */ |
409 | #define FM_SYMCTL 0x0020 /* sysmbol-control bit */ |
410 | /* SN3: reserved */ |
411 | #define FM_SYNPRQ 0x0040 /* synchron.-NP-DMA-request bit */ |
412 | #define FM_ENNPRQ 0x0080 /* enable-NP-DMA-request bit */ |
413 | #define FM_ENHSRQ 0x0100 /* enable-host-request bit */ |
414 | #define FM_RXFBB01 0x0600 /* rec. frame byte boundary bit0 & 1 */ |
415 | #define FM_LSB 0x0800 /* determ. ordering of bytes in buffer*/ |
416 | #define FM_PARITY 0x1000 /* 1 = even, 0 = odd */ |
417 | #define FM_CHKPAR 0x2000 /* 1 = parity of 32-bit buffer BD-bus*/ |
418 | #define FM_STRPFCS 0x4000 /* 1 = strips FCS field of rec.frame */ |
419 | #define FM_BMMODE 0x8000 /* Buffer-Memory-Mode (1 = tag mode) */ |
420 | /* SN3: 1 = tag, 0 = modified tag */ |
421 | |
422 | /* |
423 | * Status Register 1, Upper 16 Bits (ST1U) |
424 | */ |
425 | #define FM_STEFRMS 0x0001 /* transmit end of frame: synchr. qu.*/ |
426 | #define FM_STEFRMA0 0x0002 /* transmit end of frame: asyn. qu.0 */ |
427 | #define FM_STEFRMA1 0x0004 /* transmit end of frame: asyn. qu.1 */ |
428 | #define FM_STEFRMA2 0x0008 /* transmit end of frame: asyn. qu.2 */ |
429 | /* SN3: reserved */ |
430 | #define FM_STECFRMS 0x0010 /* transmit end of chain of syn. qu. */ |
431 | /* SN3: reserved */ |
432 | #define FM_STECFRMA0 0x0020 /* transmit end of chain of asyn. q0 */ |
433 | /* SN3: reserved */ |
434 | #define FM_STECFRMA1 0x0040 /* transmit end of chain of asyn. q1 */ |
435 | /* SN3: STECMDA1 */ |
436 | #define FM_STECMDA1 0x0040 /* SN3: 'no description' */ |
437 | #define FM_STECFRMA2 0x0080 /* transmit end of chain of asyn. q2 */ |
438 | /* SN3: reserved */ |
439 | #define FM_STEXDONS 0x0100 /* transmit until XDONE in syn. qu. */ |
440 | #define FM_STBFLA 0x0200 /* asynchr.-queue trans. buffer full */ |
441 | #define FM_STBFLS 0x0400 /* synchr.-queue transm. buffer full */ |
442 | #define FM_STXABRS 0x0800 /* synchr. queue transmit-abort */ |
443 | #define FM_STXABRA0 0x1000 /* asynchr. queue 0 transmit-abort */ |
444 | #define FM_STXABRA1 0x2000 /* asynchr. queue 1 transmit-abort */ |
445 | #define FM_STXABRA2 0x4000 /* asynchr. queue 2 transmit-abort */ |
446 | /* SN3: reserved */ |
447 | #define FM_SXMTABT 0x8000 /* transmit abort */ |
448 | |
449 | /* |
450 | * Status Register 1, Lower 16 Bits (ST1L) |
451 | */ |
452 | #define FM_SQLCKS 0x0001 /* queue lock for synchr. queue */ |
453 | #define FM_SQLCKA0 0x0002 /* queue lock for asynchr. queue 0 */ |
454 | #define FM_SQLCKA1 0x0004 /* queue lock for asynchr. queue 1 */ |
455 | #define FM_SQLCKA2 0x0008 /* queue lock for asynchr. queue 2 */ |
456 | /* SN3: reserved */ |
457 | #define FM_STXINFLS 0x0010 /* transmit instruction full: syn. */ |
458 | /* SN3: reserved */ |
459 | #define FM_STXINFLA0 0x0020 /* transmit instruction full: asyn.0 */ |
460 | /* SN3: reserved */ |
461 | #define FM_STXINFLA1 0x0040 /* transmit instruction full: asyn.1 */ |
462 | /* SN3: reserved */ |
463 | #define FM_STXINFLA2 0x0080 /* transmit instruction full: asyn.2 */ |
464 | /* SN3: reserved */ |
465 | #define FM_SPCEPDS 0x0100 /* parity/coding error: syn. queue */ |
466 | #define FM_SPCEPDA0 0x0200 /* parity/coding error: asyn. queue0 */ |
467 | #define FM_SPCEPDA1 0x0400 /* parity/coding error: asyn. queue1 */ |
468 | #define FM_SPCEPDA2 0x0800 /* parity/coding error: asyn. queue2 */ |
469 | /* SN3: reserved */ |
470 | #define FM_STBURS 0x1000 /* transmit buffer underrun: syn. q. */ |
471 | #define FM_STBURA0 0x2000 /* transmit buffer underrun: asyn.0 */ |
472 | #define FM_STBURA1 0x4000 /* transmit buffer underrun: asyn.1 */ |
473 | #define FM_STBURA2 0x8000 /* transmit buffer underrun: asyn.2 */ |
474 | /* SN3: reserved */ |
475 | |
476 | /* |
477 | * Status Register 2, Upper 16 Bits (ST2U) |
478 | */ |
479 | #define FM_SOTRBEC 0x0001 /* other beacon received */ |
480 | #define FM_SMYBEC 0x0002 /* my beacon received */ |
481 | #define FM_SBEC 0x0004 /* beacon state entered */ |
482 | #define FM_SLOCLM 0x0008 /* low claim received */ |
483 | #define FM_SHICLM 0x0010 /* high claim received */ |
484 | #define FM_SMYCLM 0x0020 /* my claim received */ |
485 | #define FM_SCLM 0x0040 /* claim state entered */ |
486 | #define FM_SERRSF 0x0080 /* error in special frame */ |
487 | #define FM_SNFSLD 0x0100 /* NP and FORMAC+ simultaneous load */ |
488 | #define FM_SRFRCTOV 0x0200 /* receive frame counter overflow */ |
489 | /* SN3: reserved */ |
490 | #define FM_SRCVFRM 0x0400 /* receive frame */ |
491 | /* SN3: reserved */ |
492 | #define FM_SRCVOVR 0x0800 /* receive FIFO overflow */ |
493 | #define FM_SRBFL 0x1000 /* receive buffer full */ |
494 | #define FM_SRABT 0x2000 /* receive abort */ |
495 | #define FM_SRBMT 0x4000 /* receive buffer empty */ |
496 | #define FM_SRCOMP 0x8000 /* receive complete. Nontag mode */ |
497 | |
498 | /* |
499 | * Status Register 2, Lower 16 Bits (ST2L) |
500 | * Attention: SN3 docu shows these bits the other way around |
501 | */ |
502 | #define FM_SRES0 0x0001 /* reserved */ |
503 | #define FM_SESTRIPTK 0x0001 /* SN3: 'no description' */ |
504 | #define FM_STRTEXR 0x0002 /* TRT expired in claim | beacon st. */ |
505 | #define FM_SDUPCLM 0x0004 /* duplicate claim received */ |
506 | #define FM_SSIFG 0x0008 /* short interframe gap */ |
507 | #define FM_SFRMCTR 0x0010 /* frame counter overflow */ |
508 | #define FM_SERRCTR 0x0020 /* error counter overflow */ |
509 | #define FM_SLSTCTR 0x0040 /* lost counter overflow */ |
510 | #define FM_SPHINV 0x0080 /* PHY invalid */ |
511 | #define FM_SADET 0x0100 /* address detect */ |
512 | #define FM_SMISFRM 0x0200 /* missed frame */ |
513 | #define FM_STRTEXP 0x0400 /* TRT expired and late count > 0 */ |
514 | #define FM_STVXEXP 0x0800 /* TVX expired */ |
515 | #define FM_STKISS 0x1000 /* token issued */ |
516 | #define FM_STKERR 0x2000 /* token error */ |
517 | #define FM_SMULTDA 0x4000 /* multiple destination address */ |
518 | #define FM_SRNGOP 0x8000 /* ring operational */ |
519 | |
520 | /* |
521 | * Supernet 3: |
522 | * Status Register 3, Upper 16 Bits (ST3U) |
523 | */ |
524 | #define FM_SRQUNLCK1 0x0001 /* receive queue unlocked queue 1 */ |
525 | #define FM_SRQUNLCK2 0x0002 /* receive queue unlocked queue 2 */ |
526 | #define FM_SRPERRQ1 0x0004 /* receive parity error rx queue 1 */ |
527 | #define FM_SRPERRQ2 0x0008 /* receive parity error rx queue 2 */ |
528 | /* Bit 4-10: reserved */ |
529 | #define FM_SRCVOVR2 0x0800 /* receive FIFO overfull rx queue 2 */ |
530 | #define FM_SRBFL2 0x1000 /* receive buffer full rx queue 2 */ |
531 | #define FM_SRABT2 0x2000 /* receive abort rx queue 2 */ |
532 | #define FM_SRBMT2 0x4000 /* receive buf empty rx queue 2 */ |
533 | #define FM_SRCOMP2 0x8000 /* receive comp rx queue 2 */ |
534 | |
535 | /* |
536 | * Supernet 3: |
537 | * Status Register 3, Lower 16 Bits (ST3L) |
538 | */ |
539 | #define FM_AF_BIST_DONE 0x0001 /* Address Filter BIST is done */ |
540 | #define FM_PLC_BIST_DONE 0x0002 /* internal PLC Bist is done */ |
541 | #define FM_PDX_BIST_DONE 0x0004 /* PDX BIST is done */ |
542 | /* Bit 3: reserved */ |
543 | #define FM_SICAMDAMAT 0x0010 /* Status internal CAM DA match */ |
544 | #define FM_SICAMDAXACT 0x0020 /* Status internal CAM DA exact match */ |
545 | #define FM_SICAMSAMAT 0x0040 /* Status internal CAM SA match */ |
546 | #define FM_SICAMSAXACT 0x0080 /* Status internal CAM SA exact match */ |
547 | |
548 | /* |
549 | * MAC State-Machine Register FM_STMCHN |
550 | */ |
551 | #define FM_MDRTAG 0x0004 /* tag bit of long word read */ |
552 | #define FM_SNPPND 0x0008 /* r/w from buffer mem. is pending */ |
553 | #define FM_TXSTAT 0x0070 /* transmitter state machine state */ |
554 | #define FM_RCSTAT 0x0380 /* receiver state machine state */ |
555 | #define FM_TM01 0x0c00 /* indicate token mode */ |
556 | #define FM_SIM 0x1000 /* indicate send immediate-mode */ |
557 | #define FM_REV 0xe000 /* FORMAC Plus revision number */ |
558 | |
559 | /* |
560 | * Supernet 3 |
561 | * Mode Register 3 |
562 | */ |
563 | #define FM_MENRS 0x0001 /* Ena enhanced rec status encoding */ |
564 | #define FM_MENXS 0x0002 /* Ena enhanced xmit status encoding */ |
565 | #define FM_MENXCT 0x0004 /* Ena EXACT/INEXACT matching */ |
566 | #define FM_MENAFULL 0x0008 /* Ena enh QCTRL encoding for AFULL */ |
567 | #define FM_MEIND 0x0030 /* Ena enh A,C indicator settings */ |
568 | #define FM_MENQCTRL 0x0040 /* Ena enh QCTRL encoding */ |
569 | #define FM_MENRQAUNLCK 0x0080 /* Ena rec q auto unlock */ |
570 | #define FM_MENDAS 0x0100 /* Ena DAS connections by cntr MUX */ |
571 | #define FM_MENPLCCST 0x0200 /* Ena Counter Segm test in PLC blck */ |
572 | #define FM_MENSGLINT 0x0400 /* Ena Vectored Interrupt reading */ |
573 | #define FM_MENDRCV 0x0800 /* Ena dual receive queue operation */ |
574 | #define FM_MENFCLOC 0x3000 /* Ena FC location within frm data */ |
575 | #define FM_MENTRCMD 0x4000 /* Ena ASYNC1 xmit only after command */ |
576 | #define FM_MENTDLPBK 0x8000 /* Ena TDAT to RDAT lkoopback */ |
577 | |
578 | /* |
579 | * Supernet 3 |
580 | * Frame Selection Register |
581 | */ |
582 | #define FM_RECV1 0x000f /* options for receive queue 1 */ |
583 | #define FM_RCV1_ALL (0<<0) /* receive all frames */ |
584 | #define FM_RCV1_LLC (1<<0) /* rec all LLC frames */ |
585 | #define FM_RCV1_SMT (2<<0) /* rec all SMT frames */ |
586 | #define FM_RCV1_NSMT (3<<0) /* rec non-SMT frames */ |
587 | #define FM_RCV1_IMP (4<<0) /* rec Implementor frames */ |
588 | #define FM_RCV1_MAC (5<<0) /* rec all MAC frames */ |
589 | #define FM_RCV1_SLLC (6<<0) /* rec all sync LLC frames */ |
590 | #define FM_RCV1_ALLC (7<<0) /* rec all async LLC frames */ |
591 | #define FM_RCV1_VOID (8<<0) /* rec all void frames */ |
592 | #define FM_RCV1_ALSMT (9<<0) /* rec all async LLC & SMT frames */ |
593 | #define FM_RECV2 0x00f0 /* options for receive queue 2 */ |
594 | #define FM_RCV2_ALL (0<<4) /* receive all other frames */ |
595 | #define FM_RCV2_LLC (1<<4) /* rec all LLC frames */ |
596 | #define FM_RCV2_SMT (2<<4) /* rec all SMT frames */ |
597 | #define FM_RCV2_NSMT (3<<4) /* rec non-SMT frames */ |
598 | #define FM_RCV2_IMP (4<<4) /* rec Implementor frames */ |
599 | #define FM_RCV2_MAC (5<<4) /* rec all MAC frames */ |
600 | #define FM_RCV2_SLLC (6<<4) /* rec all sync LLC frames */ |
601 | #define FM_RCV2_ALLC (7<<4) /* rec all async LLC frames */ |
602 | #define FM_RCV2_VOID (8<<4) /* rec all void frames */ |
603 | #define FM_RCV2_ALSMT (9<<4) /* rec all async LLC & SMT frames */ |
604 | #define FM_ENXMTADSWAP 0x4000 /* enh rec addr swap (phys -> can) */ |
605 | #define FM_ENRCVADSWAP 0x8000 /* enh tx addr swap (can -> phys) */ |
606 | |
607 | /* |
608 | * Supernet 3: |
609 | * Address Filter Command Register (AFCMD) |
610 | */ |
611 | #define FM_INST 0x0007 /* Address Filter Operation */ |
612 | #define FM_IINV_CAM (0<<0) /* Invalidate CAM */ |
613 | #define FM_IWRITE_CAM (1<<0) /* Write CAM */ |
614 | #define FM_IREAD_CAM (2<<0) /* Read CAM */ |
615 | #define FM_IRUN_BIST (3<<0) /* Run BIST */ |
616 | #define FM_IFIND (4<<0) /* Find */ |
617 | #define FM_IINV (5<<0) /* Invalidate */ |
618 | #define FM_ISKIP (6<<0) /* Skip */ |
619 | #define FM_ICL_SKIP (7<<0) /* Clear all SKIP bits */ |
620 | |
621 | /* |
622 | * Supernet 3: |
623 | * Address Filter Status Register (AFSTAT) |
624 | */ |
625 | /* Bit 0-4: reserved */ |
626 | #define FM_REV_NO 0x00e0 /* Revision Number of Address Filter */ |
627 | #define FM_BIST_DONE 0x0100 /* BIST complete */ |
628 | #define FM_EMPTY 0x0200 /* CAM empty */ |
629 | #define FM_ERROR 0x0400 /* Error (improper operation) */ |
630 | #define FM_MULT 0x0800 /* Multiple Match */ |
631 | #define FM_EXACT 0x1000 /* Exact Match */ |
632 | #define FM_FOUND 0x2000 /* Comparand found in CAM */ |
633 | #define FM_FULL 0x4000 /* CAM full */ |
634 | #define FM_DONE 0x8000 /* DONE indicator */ |
635 | |
636 | /* |
637 | * Supernet 3: |
638 | * BIST Signature Register (AFBIST) |
639 | */ |
640 | #define AF_BIST_SIGNAT 0x0553 /* Address Filter BIST Signature */ |
641 | |
642 | /* |
643 | * Supernet 3: |
644 | * Personality Register (AFPERS) |
645 | */ |
646 | #define FM_VALID 0x0001 /* CAM Entry Valid */ |
647 | #define FM_DA 0x0002 /* Destination Address */ |
648 | #define FM_DAX 0x0004 /* Destination Address Exact */ |
649 | #define FM_SA 0x0008 /* Source Address */ |
650 | #define FM_SAX 0x0010 /* Source Address Exact */ |
651 | #define FM_SKIP 0x0020 /* Skip this entry */ |
652 | |
653 | /* |
654 | * instruction set for command register 1 (NPADDR6-0 = 0x00) |
655 | */ |
656 | #define FM_IRESET 0x01 /* software reset */ |
657 | #define FM_IRMEMWI 0x02 /* load Memory Data Reg., inc MARR */ |
658 | #define FM_IRMEMWO 0x03 /* load MDR from buffer memory, n.i. */ |
659 | #define FM_IIL 0x04 /* idle/listen */ |
660 | #define FM_ICL 0x05 /* claim/listen */ |
661 | #define FM_IBL 0x06 /* beacon/listen */ |
662 | #define FM_ILTVX 0x07 /* load TVX timer from TVX reg */ |
663 | #define FM_INRTM 0x08 /* nonrestricted token mode */ |
664 | #define FM_IENTM 0x09 /* enter nonrestricted token mode */ |
665 | #define FM_IERTM 0x0a /* enter restricted token mode */ |
666 | #define FM_IRTM 0x0b /* restricted token mode */ |
667 | #define FM_ISURT 0x0c /* send unrestricted token */ |
668 | #define FM_ISRT 0x0d /* send restricted token */ |
669 | #define FM_ISIM 0x0e /* enter send-immediate mode */ |
670 | #define FM_IESIM 0x0f /* exit send-immediate mode */ |
671 | #define FM_ICLLS 0x11 /* clear synchronous queue lock */ |
672 | #define FM_ICLLA0 0x12 /* clear asynchronous queue 0 lock */ |
673 | #define FM_ICLLA1 0x14 /* clear asynchronous queue 1 lock */ |
674 | #define FM_ICLLA2 0x18 /* clear asynchronous queue 2 lock */ |
675 | /* SN3: reserved */ |
676 | #define FM_ICLLR 0x20 /* clear receive queue (SN3:1) lock */ |
677 | #define FM_ICLLR2 0x21 /* SN3: clear receive queue 2 lock */ |
678 | #define FM_ITRXBUS 0x22 /* SN3: Tristate X-Bus (SAS only) */ |
679 | #define FM_IDRXBUS 0x23 /* SN3: drive X-Bus */ |
680 | #define FM_ICLLAL 0x3f /* clear all queue locks */ |
681 | |
682 | /* |
683 | * instruction set for command register 2 (NPADDR6-0 = 0x01) |
684 | */ |
685 | #define FM_ITRS 0x01 /* transmit synchronous queue */ |
686 | /* SN3: reserved */ |
687 | #define FM_ITRA0 0x02 /* transmit asynchronous queue 0 */ |
688 | /* SN3: reserved */ |
689 | #define FM_ITRA1 0x04 /* transmit asynchronous queue 1 */ |
690 | /* SN3: reserved */ |
691 | #define FM_ITRA2 0x08 /* transmit asynchronous queue 2 */ |
692 | /* SN3: reserved */ |
693 | #define FM_IACTR 0x10 /* abort current transmit activity */ |
694 | #define FM_IRSTQ 0x20 /* reset transmit queues */ |
695 | #define FM_ISTTB 0x30 /* set tag bit */ |
696 | #define FM_IERSF 0x40 /* enable receive single frame */ |
697 | /* SN3: reserved */ |
698 | #define FM_ITR 0x50 /* SN3: Transmit Command */ |
699 | |
700 | |
701 | /* |
702 | * defines for PLC (Am79C864) |
703 | */ |
704 | |
705 | /* |
706 | * PLC read/write (r/w) registers |
707 | */ |
708 | #define PL_CNTRL_A 0x00 /* control register A (r/w) */ |
709 | #define PL_CNTRL_B 0x01 /* control register B (r/w) */ |
710 | #define PL_INTR_MASK 0x02 /* interrupt mask (r/w) */ |
711 | #define PL_XMIT_VECTOR 0x03 /* transmit vector register (r/w) */ |
712 | #define PL_VECTOR_LEN 0x04 /* transmit vector length (r/w) */ |
713 | #define PL_LE_THRESHOLD 0x05 /* link error event threshold (r/w) */ |
714 | #define PL_C_MIN 0x06 /* minimum connect state time (r/w) */ |
715 | #define PL_TL_MIN 0x07 /* min. line state transmit t. (r/w) */ |
716 | #define PL_TB_MIN 0x08 /* minimum break time (r/w) */ |
717 | #define PL_T_OUT 0x09 /* signal timeout (r/w) */ |
718 | #define PL_CNTRL_C 0x0a /* control register C (r/w) */ |
719 | #define PL_LC_LENGTH 0x0b /* link confidence test time (r/w) */ |
720 | #define PL_T_SCRUB 0x0c /* scrub time = MAC TVX (r/w) */ |
721 | #define PL_NS_MAX 0x0d /* max. noise time before break (r/w)*/ |
722 | #define PL_TPC_LOAD_V 0x0e /* TPC timer load value (write only) */ |
723 | #define PL_TNE_LOAD_V 0x0f /* TNE timer load value (write only) */ |
724 | #define PL_STATUS_A 0x10 /* status register A (read only) */ |
725 | #define PL_STATUS_B 0x11 /* status register B (read only) */ |
726 | #define PL_TPC 0x12 /* timer for PCM (ro) [20.48 us] */ |
727 | #define PL_TNE 0x13 /* time of noise event [0.32 us] */ |
728 | #define PL_CLK_DIV 0x14 /* TNE clock divider (read only) */ |
729 | #define PL_BIST_SIGNAT 0x15 /* built in self test signature (ro)*/ |
730 | #define PL_RCV_VECTOR 0x16 /* receive vector reg. (read only) */ |
731 | #define PL_INTR_EVENT 0x17 /* interrupt event reg. (read only) */ |
732 | #define PL_VIOL_SYM_CTR 0x18 /* violation symbol count. (read o) */ |
733 | #define PL_MIN_IDLE_CTR 0x19 /* minimum idle counter (read only) */ |
734 | #define PL_LINK_ERR_CTR 0x1a /* link error event ctr.(read only) */ |
735 | #ifdef MOT_ELM |
736 | #define PL_T_FOT_ASS 0x1e /* FOTOFF Assert Timer */ |
737 | #define PL_T_FOT_DEASS 0x1f /* FOTOFF Deassert Timer */ |
738 | #endif /* MOT_ELM */ |
739 | |
740 | #ifdef MOT_ELM |
741 | /* |
742 | * Special Quad-Elm Registers. |
743 | * A Quad-ELM consists of for ELMs and these additional registers. |
744 | */ |
745 | #define QELM_XBAR_W 0x80 /* Crossbar Control ELM W */ |
746 | #define QELM_XBAR_X 0x81 /* Crossbar Control ELM X */ |
747 | #define QELM_XBAR_Y 0x82 /* Crossbar Control ELM Y */ |
748 | #define QELM_XBAR_Z 0x83 /* Crossbar Control ELM Z */ |
749 | #define QELM_XBAR_P 0x84 /* Crossbar Control Bus P */ |
750 | #define QELM_XBAR_S 0x85 /* Crossbar Control Bus S */ |
751 | #define QELM_XBAR_R 0x86 /* Crossbar Control Bus R */ |
752 | #define QELM_WR_XBAR 0x87 /* Write the Crossbar now (write) */ |
753 | #define QELM_CTR_W 0x88 /* Counter W */ |
754 | #define QELM_CTR_X 0x89 /* Counter X */ |
755 | #define QELM_CTR_Y 0x8a /* Counter Y */ |
756 | #define QELM_CTR_Z 0x8b /* Counter Z */ |
757 | #define QELM_INT_MASK 0x8c /* Interrupt mask register */ |
758 | #define QELM_INT_DATA 0x8d /* Interrupt data (event) register */ |
759 | #define QELM_ELMB 0x00 /* Elm base */ |
760 | #define QELM_ELM_SIZE 0x20 /* ELM size */ |
761 | #endif /* MOT_ELM */ |
762 | /* |
763 | * PLC control register A (PL_CNTRL_A: log. addr. 0x00) |
764 | * It is used for timer configuration, specification of PCM MAINT state option, |
765 | * counter interrupt frequency, PLC data path config. and Built In Self Test. |
766 | */ |
767 | #define PL_RUN_BIST 0x0001 /* begin running its Built In Self T.*/ |
768 | #define PL_RF_DISABLE 0x0002 /* disable the Repeat Filter state m.*/ |
769 | #define PL_SC_REM_LOOP 0x0004 /* remote loopback path */ |
770 | #define PL_SC_BYPASS 0x0008 /* by providing a physical bypass */ |
771 | #define PL_LM_LOC_LOOP 0x0010 /* loop path just after elastic buff.*/ |
772 | #define PL_EB_LOC_LOOP 0x0020 /* loop path just prior to PDT/PDR IF*/ |
773 | #define PL_FOT_OFF 0x0040 /* assertion of /FOTOFF pin of PLC */ |
774 | #define PL_LOOPBACK 0x0080 /* it cause the /LPBCK pin ass. low */ |
775 | #define PL_MINI_CTR_INT 0x0100 /* partially contr. when bit is ass. */ |
776 | #define PL_VSYM_CTR_INT 0x0200 /* controls when int bit is asserted */ |
777 | #define PL_ENA_PAR_CHK 0x0400 /* enable parity check */ |
778 | #define PL_REQ_SCRUB 0x0800 /* limited access to scrub capability*/ |
779 | #define PL_TPC_16BIT 0x1000 /* causes the TPC as a 16 bit timer */ |
780 | #define PL_TNE_16BIT 0x2000 /* causes the TNE as a 16 bit timer */ |
781 | #define PL_NOISE_TIMER 0x4000 /* allows the noise timing function */ |
782 | |
783 | /* |
784 | * PLC control register B (PL_CNTRL_B: log. addr. 0x01) |
785 | * It contains signals and requeste to direct the process of PCM and it is also |
786 | * used to control the Line State Match interrupt. |
787 | */ |
788 | #define PL_PCM_CNTRL 0x0003 /* control PCM state machine */ |
789 | #define PL_PCM_NAF (0) /* state is not affected */ |
790 | #define PL_PCM_START (1) /* goes to the BREAK state */ |
791 | #define PL_PCM_TRACE (2) /* goes to the TRACE state */ |
792 | #define PL_PCM_STOP (3) /* goes to the OFF state */ |
793 | |
794 | #define PL_MAINT 0x0004 /* if OFF state --> MAINT state */ |
795 | #define PL_LONG 0x0008 /* perf. a long Link Confid.Test(LCT)*/ |
796 | #define PL_PC_JOIN 0x0010 /* if NEXT state --> JOIN state */ |
797 | |
798 | #define PL_PC_LOOP 0x0060 /* loopback used in the LCT */ |
799 | #define PL_NOLCT (0<<5) /* no LCT is performed */ |
800 | #define PL_TPDR (1<<5) /* PCM asserts transmit PDR */ |
801 | #define PL_TIDLE (2<<5) /* PCM asserts transmit idle */ |
802 | #define PL_RLBP (3<<5) /* trans. PDR & remote loopb. path */ |
803 | |
804 | #define PL_CLASS_S 0x0080 /* signif. that single att. station */ |
805 | |
806 | #define PL_MAINT_LS 0x0700 /* line state while in the MAINT st. */ |
807 | #define PL_M_QUI0 (0<<8) /* transmit QUIET line state */ |
808 | #define PL_M_IDLE (1<<8) /* transmit IDLE line state */ |
809 | #define PL_M_HALT (2<<8) /* transmit HALT line state */ |
810 | #define PL_M_MASTR (3<<8) /* transmit MASTER line state */ |
811 | #define PL_M_QUI1 (4<<8) /* transmit QUIET line state */ |
812 | #define PL_M_QUI2 (5<<8) /* transmit QUIET line state */ |
813 | #define PL_M_TPDR (6<<8) /* tr. PHY_DATA requ.-symbol is tr.ed*/ |
814 | #define PL_M_QUI3 (7<<8) /* transmit QUIET line state */ |
815 | |
816 | #define PL_MATCH_LS 0x7800 /* line state to be comp. with curr.*/ |
817 | #define PL_I_ANY (0<<11) /* Int. on any change in *_LINE_ST */ |
818 | #define PL_I_IDLE (1<<11) /* Interrupt on IDLE line state */ |
819 | #define PL_I_HALT (2<<11) /* Interrupt on HALT line state */ |
820 | #define PL_I_MASTR (4<<11) /* Interrupt on MASTER line state */ |
821 | #define PL_I_QUIET (8<<11) /* Interrupt on QUIET line state */ |
822 | |
823 | #define PL_CONFIG_CNTRL 0x8000 /* control over scrub, byp. & loopb.*/ |
824 | |
825 | /* |
826 | * PLC control register C (PL_CNTRL_C: log. addr. 0x0a) |
827 | * It contains the scrambling control registers (PLC-S only) |
828 | */ |
829 | #define PL_C_CIPHER_ENABLE (1<<0) /* enable scrambler */ |
830 | #define PL_C_CIPHER_LPBCK (1<<1) /* loopback scrambler */ |
831 | #define PL_C_SDOFF_ENABLE (1<<6) /* enable SDOFF timer */ |
832 | #define PL_C_SDON_ENABLE (1<<7) /* enable SDON timer */ |
833 | #ifdef MOT_ELM |
834 | #define PL_C_FOTOFF_CTRL (3<<2) /* FOTOFF timer control */ |
835 | #define PL_C_FOTOFF_TIM (0<<2) /* FOTOFF use timer for (de)-assert */ |
836 | #define PL_C_FOTOFF_INA (2<<2) /* FOTOFF forced inactive */ |
837 | #define PL_C_FOTOFF_ACT (3<<2) /* FOTOFF forced active */ |
838 | #define PL_C_FOTOFF_SRCE (1<<4) /* FOTOFF source is PCM state != OFF */ |
839 | #define PL_C_RXDATA_EN (1<<5) /* Rec scr data forced to 0 */ |
840 | #define PL_C_SDNRZEN (1<<8) /* Monitor rec descr. data for act */ |
841 | #else /* nMOT_ELM */ |
842 | #define PL_C_FOTOFF_CTRL (3<<8) /* FOTOFF timer control */ |
843 | #define PL_C_FOTOFF_0 (0<<8) /* timer off */ |
844 | #define PL_C_FOTOFF_30 (1<<8) /* 30uS */ |
845 | #define PL_C_FOTOFF_50 (2<<8) /* 50uS */ |
846 | #define PL_C_FOTOFF_NEVER (3<<8) /* never */ |
847 | #define PL_C_SDON_TIMER (3<<10) /* SDON timer control */ |
848 | #define PL_C_SDON_084 (0<<10) /* 0.84 uS */ |
849 | #define PL_C_SDON_132 (1<<10) /* 1.32 uS */ |
850 | #define PL_C_SDON_252 (2<<10) /* 2.52 uS */ |
851 | #define PL_C_SDON_512 (3<<10) /* 5.12 uS */ |
852 | #define PL_C_SOFF_TIMER (3<<12) /* SDOFF timer control */ |
853 | #define PL_C_SOFF_076 (0<<12) /* 0.76 uS */ |
854 | #define PL_C_SOFF_132 (1<<12) /* 1.32 uS */ |
855 | #define PL_C_SOFF_252 (2<<12) /* 2.52 uS */ |
856 | #define PL_C_SOFF_512 (3<<12) /* 5.12 uS */ |
857 | #define PL_C_TSEL (3<<14) /* scrambler path select */ |
858 | #endif /* nMOT_ELM */ |
859 | |
860 | /* |
861 | * PLC status register A (PL_STATUS_A: log. addr. 0x10) |
862 | * It is used to report status information to the Node Processor about the |
863 | * Line State Machine (LSM). |
864 | */ |
865 | #ifdef MOT_ELM |
866 | #define PLC_INT_MASK 0xc000 /* ELM integration bits in status A */ |
867 | #define PLC_INT_C 0x0000 /* ELM Revision Band C */ |
868 | #define PLC_INT_CAMEL 0x4000 /* ELM integrated into CAMEL */ |
869 | #define PLC_INT_QE 0x8000 /* ELM integrated into Quad ELM */ |
870 | #define PLC_REV_MASK 0x3800 /* revision bits in status A */ |
871 | #define PLC_REVISION_B 0x0000 /* rev bits for ELM Rev B */ |
872 | #define PLC_REVISION_QA 0x0800 /* rev bits for ELM core in QELM-A */ |
873 | #else /* nMOT_ELM */ |
874 | #define PLC_REV_MASK 0xf800 /* revision bits in status A */ |
875 | #define PLC_REVISION_A 0x0000 /* revision bits for PLC */ |
876 | #define PLC_REVISION_S 0xf800 /* revision bits for PLC-S */ |
877 | #define PLC_REV_SN3 0x7800 /* revision bits for PLC-S in IFCP */ |
878 | #endif /* nMOT_ELM */ |
879 | #define PL_SYM_PR_CTR 0x0007 /* contains the LSM symbol pair Ctr. */ |
880 | #define PL_UNKN_LINE_ST 0x0008 /* unknown line state bit from LSM */ |
881 | #define PL_LSM_STATE 0x0010 /* state bit of LSM */ |
882 | |
883 | #define PL_LINE_ST 0x00e0 /* contains recogn. line state of LSM*/ |
884 | #define PL_L_NLS (0<<5) /* noise line state */ |
885 | #define PL_L_ALS (1<<5) /* activ line state */ |
886 | #define PL_L_UND (2<<5) /* undefined */ |
887 | #define PL_L_ILS4 (3<<5) /* idle l. s. (after 4 idle symbols) */ |
888 | #define PL_L_QLS (4<<5) /* quiet line state */ |
889 | #define PL_L_MLS (5<<5) /* master line state */ |
890 | #define PL_L_HLS (6<<5) /* halt line state */ |
891 | #define PL_L_ILS16 (7<<5) /* idle line state (after 16 idle s.)*/ |
892 | |
893 | #define PL_PREV_LINE_ST 0x0300 /* value of previous line state */ |
894 | #define PL_P_QLS (0<<8) /* quiet line state */ |
895 | #define PL_P_MLS (1<<8) /* master line state */ |
896 | #define PL_P_HLS (2<<8) /* halt line state */ |
897 | #define PL_P_ILS16 (3<<8) /* idle line state (after 16 idle s.)*/ |
898 | |
899 | #define PL_SIGNAL_DET 0x0400 /* 1=that signal detect is deasserted*/ |
900 | |
901 | |
902 | /* |
903 | * PLC status register B (PL_STATUS_B: log. addr. 0x11) |
904 | * It contains signals and status from the repeat filter and PCM state machine. |
905 | */ |
906 | #define PL_BREAK_REASON 0x0007 /* reason for PCM state mach.s to br.*/ |
907 | #define PL_B_NOT (0) /* PCM SM has not gone to BREAK state*/ |
908 | #define PL_B_PCS (1) /* PC_Start issued */ |
909 | #define PL_B_TPC (2) /* TPC timer expired after T_OUT */ |
910 | #define PL_B_TNE (3) /* TNE timer expired after NS_MAX */ |
911 | #define PL_B_QLS (4) /* quit line state detected */ |
912 | #define PL_B_ILS (5) /* idle line state detected */ |
913 | #define PL_B_HLS (6) /* halt line state detected */ |
914 | |
915 | #define PL_TCF 0x0008 /* transmit code flag (start exec.) */ |
916 | #define PL_RCF 0x0010 /* receive code flag (start exec.) */ |
917 | #define PL_LSF 0x0020 /* line state flag (l.s. has been r.)*/ |
918 | #define PL_PCM_SIGNAL 0x0040 /* indic. that XMIT_VECTOR hb.written*/ |
919 | |
920 | #define PL_PCM_STATE 0x0780 /* state bits of PCM state machine */ |
921 | #define PL_PC0 (0<<7) /* OFF - when /RST or PCM_CNTRL */ |
922 | #define PL_PC1 (1<<7) /* BREAK - entry point in start PCM*/ |
923 | #define PL_PC2 (2<<7) /* TRACE - to localize stuck Beacon*/ |
924 | #define PL_PC3 (3<<7) /* CONNECT - synchronize ends of conn*/ |
925 | #define PL_PC4 (4<<7) /* NEXT - to separate the signalng*/ |
926 | #define PL_PC5 (5<<7) /* SIGNAL - PCM trans/rec. bit infos*/ |
927 | #define PL_PC6 (6<<7) /* JOIN - 1. state to activ conn. */ |
928 | #define PL_PC7 (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */ |
929 | #define PL_PC8 (8<<7) /* ACTIVE - PHY has been incorporated*/ |
930 | #define PL_PC9 (9<<7) /* MAINT - for test purposes or so |
931 | that PCM op. completely in softw. */ |
932 | |
933 | #define PL_PCI_SCRUB 0x0800 /* scrubbing function is being exec. */ |
934 | |
935 | #define PL_PCI_STATE 0x3000 /* Physical Connect. Insertion SM */ |
936 | #define PL_CI_REMV (0<<12) /* REMOVED */ |
937 | #define PL_CI_ISCR (1<<12) /* INSERT_SCRUB */ |
938 | #define PL_CI_RSCR (2<<12) /* REMOVE_SCRUB */ |
939 | #define PL_CI_INS (3<<12) /* INSERTED */ |
940 | |
941 | #define PL_RF_STATE 0xc000 /* state bit of repeate filter SM */ |
942 | #define PL_RF_REPT (0<<14) /* REPEAT */ |
943 | #define PL_RF_IDLE (1<<14) /* IDLE */ |
944 | #define PL_RF_HALT1 (2<<14) /* HALT1 */ |
945 | #define PL_RF_HALT2 (3<<14) /* HALT2 */ |
946 | |
947 | |
948 | /* |
949 | * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17) |
950 | * It is read only and is clearde whenever it is read! |
951 | * It is used by the PLC to report events to the node processor. |
952 | */ |
953 | #define PL_PARITY_ERR 0x0001 /* p. error h.b.detected on TX9-0 inp*/ |
954 | #define PL_LS_MATCH 0x0002 /* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/ |
955 | #define PL_PCM_CODE 0x0004 /* transmit&receive | LCT complete */ |
956 | #define PL_TRACE_PROP 0x0008 /* master l.s. while PCM ACTIV|TRACE */ |
957 | #define PL_SELF_TEST 0x0010 /* QUIET|HALT while PCM in TRACE st. */ |
958 | #define PL_PCM_BREAK 0x0020 /* PCM has entered the BREAK state */ |
959 | #define PL_PCM_ENABLED 0x0040 /* asserted SC_JOIN, scrub. & ACTIV */ |
960 | #define PL_TPC_EXPIRED 0x0080 /* TPC timer reached zero */ |
961 | #define PL_TNE_EXPIRED 0x0100 /* TNE timer reached zero */ |
962 | #define PL_EBUF_ERR 0x0200 /* elastic buff. det. over-|underflow*/ |
963 | #define PL_PHYINV 0x0400 /* physical layer invalid signal */ |
964 | #define PL_VSYM_CTR 0x0800 /* violation symbol counter has incr.*/ |
965 | #define PL_MINI_CTR 0x1000 /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/ |
966 | #define PL_LE_CTR 0x2000 /* link error event counter */ |
967 | #define PL_LSDO 0x4000 /* SDO input pin changed to a 1 */ |
968 | #define PL_NP_ERR 0x8000 /* NP has requested to r/w an inv. r.*/ |
969 | |
970 | /* |
971 | * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is |
972 | * equal PL_INTR_EVENT register. |
973 | * For each set bit, the setting of corresponding bit generate an int to NP. |
974 | */ |
975 | |
976 | #ifdef MOT_ELM |
977 | /* |
978 | * Quad ELM Crosbar Control register values (QELM_XBAR_?) |
979 | */ |
980 | #define QELM_XOUT_IDLE 0x0000 /* Idles/Passthrough */ |
981 | #define QELM_XOUT_P 0x0001 /* Output to: Bus P */ |
982 | #define QELM_XOUT_S 0x0002 /* Output to: Bus S */ |
983 | #define QELM_XOUT_R 0x0003 /* Output to: Bus R */ |
984 | #define QELM_XOUT_W 0x0004 /* Output to: ELM W */ |
985 | #define QELM_XOUT_X 0x0005 /* Output to: ELM X */ |
986 | #define QELM_XOUT_Y 0x0006 /* Output to: ELM Y */ |
987 | #define QELM_XOUT_Z 0x0007 /* Output to: ELM Z */ |
988 | |
989 | /* |
990 | * Quad ELM Interrupt data and event registers. |
991 | */ |
992 | #define QELM_NP_ERR (1<<15) /* Node Processor Error */ |
993 | #define QELM_COUNT_Z (1<<7) /* Counter Z Interrupt */ |
994 | #define QELM_COUNT_Y (1<<6) /* Counter Y Interrupt */ |
995 | #define QELM_COUNT_X (1<<5) /* Counter X Interrupt */ |
996 | #define QELM_COUNT_W (1<<4) /* Counter W Interrupt */ |
997 | #define QELM_ELM_Z (1<<3) /* ELM Z Interrupt */ |
998 | #define QELM_ELM_Y (1<<2) /* ELM Y Interrupt */ |
999 | #define QELM_ELM_X (1<<1) /* ELM X Interrupt */ |
1000 | #define QELM_ELM_W (1<<0) /* ELM W Interrupt */ |
1001 | #endif /* MOT_ELM */ |
1002 | /* |
1003 | * PLC Timing Parameters |
1004 | */ |
1005 | #define TP_C_MIN 0xff9c /* 2 ms */ |
1006 | #define TP_TL_MIN 0xfff0 /* 0.3 ms */ |
1007 | #define TP_TB_MIN 0xff10 /* 5 ms */ |
1008 | #define TP_T_OUT 0xd9db /* 200 ms */ |
1009 | #define TP_LC_LENGTH 0xf676 /* 50 ms */ |
1010 | #define TP_LC_LONGLN 0xa0a2 /* 500 ms */ |
1011 | #define TP_T_SCRUB 0xff6d /* 3.5 ms */ |
1012 | #define TP_NS_MAX 0xf021 /* 1.3 ms */ |
1013 | |
1014 | /* |
1015 | * BIST values |
1016 | */ |
1017 | #define PLC_BIST 0x6ecd /* BIST signature for PLC */ |
1018 | #define PLCS_BIST 0x5b6b /* BIST signature for PLC-S */ |
1019 | #define PLC_ELM_B_BIST 0x6ecd /* BIST signature of ELM Rev. B */ |
1020 | #define PLC_ELM_D_BIST 0x5b6b /* BIST signature of ELM Rev. D */ |
1021 | #define PLC_CAM_A_BIST 0x9e75 /* BIST signature of CAMEL Rev. A */ |
1022 | #define PLC_CAM_B_BIST 0x5b6b /* BIST signature of CAMEL Rev. B */ |
1023 | #define PLC_IFD_A_BIST 0x9e75 /* BIST signature of IFDDI Rev. A */ |
1024 | #define PLC_IFD_B_BIST 0x5b6b /* BIST signature of IFDDI Rev. B */ |
1025 | #define PLC_QELM_A_BIST 0x5b6b /* BIST signature of QELM Rev. A */ |
1026 | |
1027 | /* |
1028 | FDDI board recources |
1029 | */ |
1030 | |
1031 | /* |
1032 | * request register array (log. addr: RQA_A + a<<1 {a=0..7}) write only. |
1033 | * It specifies to FORMAC+ the type of buffer memory access the host requires. |
1034 | */ |
1035 | #define RQ_NOT 0 /* not request */ |
1036 | #define RQ_RES 1 /* reserved */ |
1037 | #define RQ_SFW 2 /* special frame write */ |
1038 | #define RQ_RRQ 3 /* read request: receive queue */ |
1039 | #define RQ_WSQ 4 /* write request: synchronous queue */ |
1040 | #define RQ_WA0 5 /* write requ.: asynchronous queue 0 */ |
1041 | #define RQ_WA1 6 /* write requ.: asynchronous queue 1 */ |
1042 | #define RQ_WA2 7 /* write requ.: asynchronous queue 2 */ |
1043 | |
1044 | #define SZ_LONG (sizeof(long)) |
1045 | |
1046 | /* |
1047 | * FDDI defaults |
1048 | * NOTE : In the ANSI docs, times are specified in units of "symbol time". |
1049 | * AMD chips use BCLK as unit. 1 BCKL == 2 symbols |
1050 | */ |
1051 | #define COMPLREF ((u_long)32*256*256) /* two's complement 21 bit */ |
1052 | #define MSTOBCLK(x) ((u_long)(x)*12500L) |
1053 | #define MSTOTVX(x) (((u_long)(x)*1000L)/80/255) |
1054 | |
1055 | #endif /* _SUPERNET_ */ |
1056 | |