1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * Copyright (C) 2015 Microchip Technology |
4 | */ |
5 | #ifndef _LAN78XX_H |
6 | #define _LAN78XX_H |
7 | |
8 | /* USB Vendor Requests */ |
9 | #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 |
10 | #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 |
11 | #define USB_VENDOR_REQUEST_GET_STATS 0xA2 |
12 | |
13 | /* Interrupt Endpoint status word bitfields */ |
14 | #define INT_ENP_EEE_START_TX_LPI_INT BIT(26) |
15 | #define INT_ENP_EEE_STOP_TX_LPI_INT BIT(25) |
16 | #define INT_ENP_EEE_RX_LPI_INT BIT(24) |
17 | #define INT_ENP_RDFO_INT BIT(22) |
18 | #define INT_ENP_TXE_INT BIT(21) |
19 | #define INT_ENP_TX_DIS_INT BIT(19) |
20 | #define INT_ENP_RX_DIS_INT BIT(18) |
21 | #define INT_ENP_PHY_INT BIT(17) |
22 | #define INT_ENP_DP_INT BIT(16) |
23 | #define INT_ENP_MAC_ERR_INT BIT(15) |
24 | #define INT_ENP_TDFU_INT BIT(14) |
25 | #define INT_ENP_TDFO_INT BIT(13) |
26 | #define INT_ENP_UTX_FP_INT BIT(12) |
27 | |
28 | #define TX_PKT_ALIGNMENT 4 |
29 | #define RX_PKT_ALIGNMENT 4 |
30 | |
31 | /* Tx Command A */ |
32 | #define TX_CMD_A_IGE_ (0x20000000) |
33 | #define TX_CMD_A_ICE_ (0x10000000) |
34 | #define TX_CMD_A_LSO_ (0x08000000) |
35 | #define TX_CMD_A_IPE_ (0x04000000) |
36 | #define TX_CMD_A_TPE_ (0x02000000) |
37 | #define TX_CMD_A_IVTG_ (0x01000000) |
38 | #define TX_CMD_A_RVTG_ (0x00800000) |
39 | #define TX_CMD_A_FCS_ (0x00400000) |
40 | #define TX_CMD_A_LEN_MASK_ (0x000FFFFF) |
41 | |
42 | /* Tx Command B */ |
43 | #define TX_CMD_B_MSS_SHIFT_ (16) |
44 | #define TX_CMD_B_MSS_MASK_ (0x3FFF0000) |
45 | #define TX_CMD_B_MSS_MIN_ ((unsigned short)8) |
46 | #define TX_CMD_B_VTAG_MASK_ (0x0000FFFF) |
47 | #define TX_CMD_B_VTAG_PRI_MASK_ (0x0000E000) |
48 | #define TX_CMD_B_VTAG_CFI_MASK_ (0x00001000) |
49 | #define TX_CMD_B_VTAG_VID_MASK_ (0x00000FFF) |
50 | |
51 | /* Rx Command A */ |
52 | #define RX_CMD_A_ICE_ (0x80000000) |
53 | #define RX_CMD_A_TCE_ (0x40000000) |
54 | #define RX_CMD_A_CSE_MASK_ (0xC0000000) |
55 | #define RX_CMD_A_IPV_ (0x20000000) |
56 | #define RX_CMD_A_PID_MASK_ (0x18000000) |
57 | #define RX_CMD_A_PID_NONE_IP_ (0x00000000) |
58 | #define RX_CMD_A_PID_TCP_IP_ (0x08000000) |
59 | #define RX_CMD_A_PID_UDP_IP_ (0x10000000) |
60 | #define RX_CMD_A_PID_IP_ (0x18000000) |
61 | #define RX_CMD_A_PFF_ (0x04000000) |
62 | #define RX_CMD_A_BAM_ (0x02000000) |
63 | #define RX_CMD_A_MAM_ (0x01000000) |
64 | #define RX_CMD_A_FVTG_ (0x00800000) |
65 | #define RX_CMD_A_RED_ (0x00400000) |
66 | #define RX_CMD_A_RX_ERRS_MASK_ (0xC03F0000) |
67 | #define RX_CMD_A_RWT_ (0x00200000) |
68 | #define RX_CMD_A_RUNT_ (0x00100000) |
69 | #define RX_CMD_A_LONG_ (0x00080000) |
70 | #define RX_CMD_A_RXE_ (0x00040000) |
71 | #define RX_CMD_A_DRB_ (0x00020000) |
72 | #define RX_CMD_A_FCS_ (0x00010000) |
73 | #define RX_CMD_A_UAM_ (0x00008000) |
74 | #define RX_CMD_A_ICSM_ (0x00004000) |
75 | #define RX_CMD_A_LEN_MASK_ (0x00003FFF) |
76 | |
77 | /* Rx Command B */ |
78 | #define RX_CMD_B_CSUM_SHIFT_ (16) |
79 | #define RX_CMD_B_CSUM_MASK_ (0xFFFF0000) |
80 | #define RX_CMD_B_VTAG_MASK_ (0x0000FFFF) |
81 | #define RX_CMD_B_VTAG_PRI_MASK_ (0x0000E000) |
82 | #define RX_CMD_B_VTAG_CFI_MASK_ (0x00001000) |
83 | #define RX_CMD_B_VTAG_VID_MASK_ (0x00000FFF) |
84 | |
85 | /* Rx Command C */ |
86 | #define RX_CMD_C_WAKE_SHIFT_ (15) |
87 | #define RX_CMD_C_WAKE_ (0x8000) |
88 | #define RX_CMD_C_REF_FAIL_SHIFT_ (14) |
89 | #define RX_CMD_C_REF_FAIL_ (0x4000) |
90 | |
91 | /* SCSRs */ |
92 | #define NUMBER_OF_REGS (193) |
93 | |
94 | #define ID_REV (0x00) |
95 | #define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) |
96 | #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) |
97 | #define ID_REV_CHIP_ID_7800_ (0x7800) |
98 | #define ID_REV_CHIP_ID_7850_ (0x7850) |
99 | #define ID_REV_CHIP_ID_7801_ (0x7801) |
100 | |
101 | #define FPGA_REV (0x04) |
102 | #define FPGA_REV_MINOR_MASK_ (0x0000FF00) |
103 | #define FPGA_REV_MAJOR_MASK_ (0x000000FF) |
104 | |
105 | #define INT_STS (0x0C) |
106 | #define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) |
107 | #define INT_STS_EEE_TX_LPI_STRT_ (0x04000000) |
108 | #define INT_STS_EEE_TX_LPI_STOP_ (0x02000000) |
109 | #define INT_STS_EEE_RX_LPI_ (0x01000000) |
110 | #define INT_STS_RDFO_ (0x00400000) |
111 | #define INT_STS_TXE_ (0x00200000) |
112 | #define INT_STS_TX_DIS_ (0x00080000) |
113 | #define INT_STS_RX_DIS_ (0x00040000) |
114 | #define INT_STS_PHY_INT_ (0x00020000) |
115 | #define INT_STS_DP_INT_ (0x00010000) |
116 | #define INT_STS_MAC_ERR_ (0x00008000) |
117 | #define INT_STS_TDFU_ (0x00004000) |
118 | #define INT_STS_TDFO_ (0x00002000) |
119 | #define INT_STS_UFX_FP_ (0x00001000) |
120 | #define INT_STS_GPIO_MASK_ (0x00000FFF) |
121 | #define INT_STS_GPIO11_ (0x00000800) |
122 | #define INT_STS_GPIO10_ (0x00000400) |
123 | #define INT_STS_GPIO9_ (0x00000200) |
124 | #define INT_STS_GPIO8_ (0x00000100) |
125 | #define INT_STS_GPIO7_ (0x00000080) |
126 | #define INT_STS_GPIO6_ (0x00000040) |
127 | #define INT_STS_GPIO5_ (0x00000020) |
128 | #define INT_STS_GPIO4_ (0x00000010) |
129 | #define INT_STS_GPIO3_ (0x00000008) |
130 | #define INT_STS_GPIO2_ (0x00000004) |
131 | #define INT_STS_GPIO1_ (0x00000002) |
132 | #define INT_STS_GPIO0_ (0x00000001) |
133 | |
134 | #define HW_CFG (0x010) |
135 | #define HW_CFG_CLK125_EN_ (0x02000000) |
136 | #define HW_CFG_REFCLK25_EN_ (0x01000000) |
137 | #define HW_CFG_LED3_EN_ (0x00800000) |
138 | #define HW_CFG_LED2_EN_ (0x00400000) |
139 | #define HW_CFG_LED1_EN_ (0x00200000) |
140 | #define HW_CFG_LED0_EN_ (0x00100000) |
141 | #define HW_CFG_EEE_PHY_LUSU_ (0x00020000) |
142 | #define HW_CFG_EEE_TSU_ (0x00010000) |
143 | #define HW_CFG_NETDET_STS_ (0x00008000) |
144 | #define HW_CFG_NETDET_EN_ (0x00004000) |
145 | #define HW_CFG_EEM_ (0x00002000) |
146 | #define HW_CFG_RST_PROTECT_ (0x00001000) |
147 | #define HW_CFG_CONNECT_BUF_ (0x00000400) |
148 | #define HW_CFG_CONNECT_EN_ (0x00000200) |
149 | #define HW_CFG_CONNECT_POL_ (0x00000100) |
150 | #define HW_CFG_SUSPEND_N_SEL_MASK_ (0x000000C0) |
151 | #define HW_CFG_SUSPEND_N_SEL_2 (0x00000000) |
152 | #define HW_CFG_SUSPEND_N_SEL_12N (0x00000040) |
153 | #define HW_CFG_SUSPEND_N_SEL_012N (0x00000080) |
154 | #define HW_CFG_SUSPEND_N_SEL_0123N (0x000000C0) |
155 | #define HW_CFG_SUSPEND_N_POL_ (0x00000020) |
156 | #define HW_CFG_MEF_ (0x00000010) |
157 | #define HW_CFG_ETC_ (0x00000008) |
158 | #define HW_CFG_LRST_ (0x00000002) |
159 | #define HW_CFG_SRST_ (0x00000001) |
160 | |
161 | #define PMT_CTL (0x014) |
162 | #define PMT_CTL_EEE_WAKEUP_EN_ (0x00002000) |
163 | #define PMT_CTL_EEE_WUPS_ (0x00001000) |
164 | #define PMT_CTL_MAC_SRST_ (0x00000800) |
165 | #define PMT_CTL_PHY_PWRUP_ (0x00000400) |
166 | #define PMT_CTL_RES_CLR_WKP_MASK_ (0x00000300) |
167 | #define PMT_CTL_RES_CLR_WKP_STS_ (0x00000200) |
168 | #define PMT_CTL_RES_CLR_WKP_EN_ (0x00000100) |
169 | #define PMT_CTL_READY_ (0x00000080) |
170 | #define PMT_CTL_SUS_MODE_MASK_ (0x00000060) |
171 | #define PMT_CTL_SUS_MODE_0_ (0x00000000) |
172 | #define PMT_CTL_SUS_MODE_1_ (0x00000020) |
173 | #define PMT_CTL_SUS_MODE_2_ (0x00000040) |
174 | #define PMT_CTL_SUS_MODE_3_ (0x00000060) |
175 | #define PMT_CTL_PHY_RST_ (0x00000010) |
176 | #define PMT_CTL_WOL_EN_ (0x00000008) |
177 | #define PMT_CTL_PHY_WAKE_EN_ (0x00000004) |
178 | #define PMT_CTL_WUPS_MASK_ (0x00000003) |
179 | #define PMT_CTL_WUPS_MLT_ (0x00000003) |
180 | #define PMT_CTL_WUPS_MAC_ (0x00000002) |
181 | #define PMT_CTL_WUPS_PHY_ (0x00000001) |
182 | |
183 | #define GPIO_CFG0 (0x018) |
184 | #define GPIO_CFG0_GPIOEN_MASK_ (0x0000F000) |
185 | #define GPIO_CFG0_GPIOEN3_ (0x00008000) |
186 | #define GPIO_CFG0_GPIOEN2_ (0x00004000) |
187 | #define GPIO_CFG0_GPIOEN1_ (0x00002000) |
188 | #define GPIO_CFG0_GPIOEN0_ (0x00001000) |
189 | #define GPIO_CFG0_GPIOBUF_MASK_ (0x00000F00) |
190 | #define GPIO_CFG0_GPIOBUF3_ (0x00000800) |
191 | #define GPIO_CFG0_GPIOBUF2_ (0x00000400) |
192 | #define GPIO_CFG0_GPIOBUF1_ (0x00000200) |
193 | #define GPIO_CFG0_GPIOBUF0_ (0x00000100) |
194 | #define GPIO_CFG0_GPIODIR_MASK_ (0x000000F0) |
195 | #define GPIO_CFG0_GPIODIR3_ (0x00000080) |
196 | #define GPIO_CFG0_GPIODIR2_ (0x00000040) |
197 | #define GPIO_CFG0_GPIODIR1_ (0x00000020) |
198 | #define GPIO_CFG0_GPIODIR0_ (0x00000010) |
199 | #define GPIO_CFG0_GPIOD_MASK_ (0x0000000F) |
200 | #define GPIO_CFG0_GPIOD3_ (0x00000008) |
201 | #define GPIO_CFG0_GPIOD2_ (0x00000004) |
202 | #define GPIO_CFG0_GPIOD1_ (0x00000002) |
203 | #define GPIO_CFG0_GPIOD0_ (0x00000001) |
204 | |
205 | #define GPIO_CFG1 (0x01C) |
206 | #define GPIO_CFG1_GPIOEN_MASK_ (0xFF000000) |
207 | #define GPIO_CFG1_GPIOEN11_ (0x80000000) |
208 | #define GPIO_CFG1_GPIOEN10_ (0x40000000) |
209 | #define GPIO_CFG1_GPIOEN9_ (0x20000000) |
210 | #define GPIO_CFG1_GPIOEN8_ (0x10000000) |
211 | #define GPIO_CFG1_GPIOEN7_ (0x08000000) |
212 | #define GPIO_CFG1_GPIOEN6_ (0x04000000) |
213 | #define GPIO_CFG1_GPIOEN5_ (0x02000000) |
214 | #define GPIO_CFG1_GPIOEN4_ (0x01000000) |
215 | #define GPIO_CFG1_GPIOBUF_MASK_ (0x00FF0000) |
216 | #define GPIO_CFG1_GPIOBUF11_ (0x00800000) |
217 | #define GPIO_CFG1_GPIOBUF10_ (0x00400000) |
218 | #define GPIO_CFG1_GPIOBUF9_ (0x00200000) |
219 | #define GPIO_CFG1_GPIOBUF8_ (0x00100000) |
220 | #define GPIO_CFG1_GPIOBUF7_ (0x00080000) |
221 | #define GPIO_CFG1_GPIOBUF6_ (0x00040000) |
222 | #define GPIO_CFG1_GPIOBUF5_ (0x00020000) |
223 | #define GPIO_CFG1_GPIOBUF4_ (0x00010000) |
224 | #define GPIO_CFG1_GPIODIR_MASK_ (0x0000FF00) |
225 | #define GPIO_CFG1_GPIODIR11_ (0x00008000) |
226 | #define GPIO_CFG1_GPIODIR10_ (0x00004000) |
227 | #define GPIO_CFG1_GPIODIR9_ (0x00002000) |
228 | #define GPIO_CFG1_GPIODIR8_ (0x00001000) |
229 | #define GPIO_CFG1_GPIODIR7_ (0x00000800) |
230 | #define GPIO_CFG1_GPIODIR6_ (0x00000400) |
231 | #define GPIO_CFG1_GPIODIR5_ (0x00000200) |
232 | #define GPIO_CFG1_GPIODIR4_ (0x00000100) |
233 | #define GPIO_CFG1_GPIOD_MASK_ (0x000000FF) |
234 | #define GPIO_CFG1_GPIOD11_ (0x00000080) |
235 | #define GPIO_CFG1_GPIOD10_ (0x00000040) |
236 | #define GPIO_CFG1_GPIOD9_ (0x00000020) |
237 | #define GPIO_CFG1_GPIOD8_ (0x00000010) |
238 | #define GPIO_CFG1_GPIOD7_ (0x00000008) |
239 | #define GPIO_CFG1_GPIOD6_ (0x00000004) |
240 | #define GPIO_CFG1_GPIOD6_ (0x00000004) |
241 | #define GPIO_CFG1_GPIOD5_ (0x00000002) |
242 | #define GPIO_CFG1_GPIOD4_ (0x00000001) |
243 | |
244 | #define GPIO_WAKE (0x020) |
245 | #define GPIO_WAKE_GPIOPOL_MASK_ (0x0FFF0000) |
246 | #define GPIO_WAKE_GPIOPOL11_ (0x08000000) |
247 | #define GPIO_WAKE_GPIOPOL10_ (0x04000000) |
248 | #define GPIO_WAKE_GPIOPOL9_ (0x02000000) |
249 | #define GPIO_WAKE_GPIOPOL8_ (0x01000000) |
250 | #define GPIO_WAKE_GPIOPOL7_ (0x00800000) |
251 | #define GPIO_WAKE_GPIOPOL6_ (0x00400000) |
252 | #define GPIO_WAKE_GPIOPOL5_ (0x00200000) |
253 | #define GPIO_WAKE_GPIOPOL4_ (0x00100000) |
254 | #define GPIO_WAKE_GPIOPOL3_ (0x00080000) |
255 | #define GPIO_WAKE_GPIOPOL2_ (0x00040000) |
256 | #define GPIO_WAKE_GPIOPOL1_ (0x00020000) |
257 | #define GPIO_WAKE_GPIOPOL0_ (0x00010000) |
258 | #define GPIO_WAKE_GPIOWK_MASK_ (0x00000FFF) |
259 | #define GPIO_WAKE_GPIOWK11_ (0x00000800) |
260 | #define GPIO_WAKE_GPIOWK10_ (0x00000400) |
261 | #define GPIO_WAKE_GPIOWK9_ (0x00000200) |
262 | #define GPIO_WAKE_GPIOWK8_ (0x00000100) |
263 | #define GPIO_WAKE_GPIOWK7_ (0x00000080) |
264 | #define GPIO_WAKE_GPIOWK6_ (0x00000040) |
265 | #define GPIO_WAKE_GPIOWK5_ (0x00000020) |
266 | #define GPIO_WAKE_GPIOWK4_ (0x00000010) |
267 | #define GPIO_WAKE_GPIOWK3_ (0x00000008) |
268 | #define GPIO_WAKE_GPIOWK2_ (0x00000004) |
269 | #define GPIO_WAKE_GPIOWK1_ (0x00000002) |
270 | #define GPIO_WAKE_GPIOWK0_ (0x00000001) |
271 | |
272 | #define DP_SEL (0x024) |
273 | #define DP_SEL_DPRDY_ (0x80000000) |
274 | #define DP_SEL_RSEL_MASK_ (0x0000000F) |
275 | #define DP_SEL_RSEL_USB_PHY_CSRS_ (0x0000000F) |
276 | #define DP_SEL_RSEL_OTP_64BIT_ (0x00000009) |
277 | #define DP_SEL_RSEL_OTP_8BIT_ (0x00000008) |
278 | #define DP_SEL_RSEL_UTX_BUF_RAM_ (0x00000007) |
279 | #define DP_SEL_RSEL_DESC_RAM_ (0x00000005) |
280 | #define DP_SEL_RSEL_TXFIFO_ (0x00000004) |
281 | #define DP_SEL_RSEL_RXFIFO_ (0x00000003) |
282 | #define DP_SEL_RSEL_LSO_ (0x00000002) |
283 | #define DP_SEL_RSEL_VLAN_DA_ (0x00000001) |
284 | #define DP_SEL_RSEL_URXBUF_ (0x00000000) |
285 | #define DP_SEL_VHF_HASH_LEN (16) |
286 | #define DP_SEL_VHF_VLAN_LEN (128) |
287 | |
288 | #define DP_CMD (0x028) |
289 | #define DP_CMD_WRITE_ (0x00000001) |
290 | #define DP_CMD_READ_ (0x00000000) |
291 | |
292 | #define DP_ADDR (0x02C) |
293 | #define DP_ADDR_MASK_ (0x00003FFF) |
294 | |
295 | #define DP_DATA (0x030) |
296 | |
297 | #define E2P_CMD (0x040) |
298 | #define E2P_CMD_EPC_BUSY_ (0x80000000) |
299 | #define E2P_CMD_EPC_CMD_MASK_ (0x70000000) |
300 | #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) |
301 | #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) |
302 | #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) |
303 | #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) |
304 | #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) |
305 | #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) |
306 | #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) |
307 | #define E2P_CMD_EPC_CMD_READ_ (0x00000000) |
308 | #define E2P_CMD_EPC_TIMEOUT_ (0x00000400) |
309 | #define E2P_CMD_EPC_DL_ (0x00000200) |
310 | #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) |
311 | |
312 | #define E2P_DATA (0x044) |
313 | #define E2P_DATA_EEPROM_DATA_MASK_ (0x000000FF) |
314 | |
315 | #define BOS_ATTR (0x050) |
316 | #define BOS_ATTR_BLOCK_SIZE_MASK_ (0x000000FF) |
317 | |
318 | #define SS_ATTR (0x054) |
319 | #define SS_ATTR_POLL_INT_MASK_ (0x00FF0000) |
320 | #define SS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00) |
321 | #define SS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF) |
322 | |
323 | #define HS_ATTR (0x058) |
324 | #define HS_ATTR_POLL_INT_MASK_ (0x00FF0000) |
325 | #define HS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00) |
326 | #define HS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF) |
327 | |
328 | #define FS_ATTR (0x05C) |
329 | #define FS_ATTR_POLL_INT_MASK_ (0x00FF0000) |
330 | #define FS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00) |
331 | #define FS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF) |
332 | |
333 | #define STR_ATTR0 (0x060) |
334 | #define STR_ATTR0_CFGSTR_DESC_SIZE_MASK_ (0xFF000000) |
335 | #define STR_ATTR0_SERSTR_DESC_SIZE_MASK_ (0x00FF0000) |
336 | #define STR_ATTR0_PRODSTR_DESC_SIZE_MASK_ (0x0000FF00) |
337 | #define STR_ATTR0_MANUF_DESC_SIZE_MASK_ (0x000000FF) |
338 | |
339 | #define STR_ATTR1 (0x064) |
340 | #define STR_ATTR1_INTSTR_DESC_SIZE_MASK_ (0x000000FF) |
341 | |
342 | #define STR_FLAG_ATTR (0x068) |
343 | #define STR_FLAG_ATTR_PME_FLAGS_MASK_ (0x000000FF) |
344 | |
345 | #define USB_CFG0 (0x080) |
346 | #define USB_CFG_LPM_RESPONSE_ (0x80000000) |
347 | #define USB_CFG_LPM_CAPABILITY_ (0x40000000) |
348 | #define USB_CFG_LPM_ENBL_SLPM_ (0x20000000) |
349 | #define USB_CFG_HIRD_THR_MASK_ (0x1F000000) |
350 | #define USB_CFG_HIRD_THR_960_ (0x1C000000) |
351 | #define USB_CFG_HIRD_THR_885_ (0x1B000000) |
352 | #define USB_CFG_HIRD_THR_810_ (0x1A000000) |
353 | #define USB_CFG_HIRD_THR_735_ (0x19000000) |
354 | #define USB_CFG_HIRD_THR_660_ (0x18000000) |
355 | #define USB_CFG_HIRD_THR_585_ (0x17000000) |
356 | #define USB_CFG_HIRD_THR_510_ (0x16000000) |
357 | #define USB_CFG_HIRD_THR_435_ (0x15000000) |
358 | #define USB_CFG_HIRD_THR_360_ (0x14000000) |
359 | #define USB_CFG_HIRD_THR_285_ (0x13000000) |
360 | #define USB_CFG_HIRD_THR_210_ (0x12000000) |
361 | #define USB_CFG_HIRD_THR_135_ (0x11000000) |
362 | #define USB_CFG_HIRD_THR_60_ (0x10000000) |
363 | #define USB_CFG_MAX_BURST_BI_MASK_ (0x00F00000) |
364 | #define USB_CFG_MAX_BURST_BO_MASK_ (0x000F0000) |
365 | #define USB_CFG_MAX_DEV_SPEED_MASK_ (0x0000E000) |
366 | #define USB_CFG_MAX_DEV_SPEED_SS_ (0x00008000) |
367 | #define USB_CFG_MAX_DEV_SPEED_HS_ (0x00000000) |
368 | #define USB_CFG_MAX_DEV_SPEED_FS_ (0x00002000) |
369 | #define USB_CFG_PHY_BOOST_MASK_ (0x00000180) |
370 | #define USB_CFG_PHY_BOOST_PLUS_12_ (0x00000180) |
371 | #define USB_CFG_PHY_BOOST_PLUS_8_ (0x00000100) |
372 | #define USB_CFG_PHY_BOOST_PLUS_4_ (0x00000080) |
373 | #define USB_CFG_PHY_BOOST_NORMAL_ (0x00000000) |
374 | #define USB_CFG_BIR_ (0x00000040) |
375 | #define USB_CFG_BCE_ (0x00000020) |
376 | #define USB_CFG_PORT_SWAP_ (0x00000010) |
377 | #define USB_CFG_LPM_EN_ (0x00000008) |
378 | #define USB_CFG_RMT_WKP_ (0x00000004) |
379 | #define USB_CFG_PWR_SEL_ (0x00000002) |
380 | #define USB_CFG_STALL_BO_DIS_ (0x00000001) |
381 | |
382 | #define USB_CFG1 (0x084) |
383 | #define USB_CFG1_U1_TIMEOUT_MASK_ (0xFF000000) |
384 | #define USB_CFG1_U2_TIMEOUT_MASK_ (0x00FF0000) |
385 | #define USB_CFG1_HS_TOUT_CAL_MASK_ (0x0000E000) |
386 | #define USB_CFG1_DEV_U2_INIT_EN_ (0x00001000) |
387 | #define USB_CFG1_DEV_U2_EN_ (0x00000800) |
388 | #define USB_CFG1_DEV_U1_INIT_EN_ (0x00000400) |
389 | #define USB_CFG1_DEV_U1_EN_ (0x00000200) |
390 | #define USB_CFG1_LTM_ENABLE_ (0x00000100) |
391 | #define USB_CFG1_FS_TOUT_CAL_MASK_ (0x00000070) |
392 | #define USB_CFG1_SCALE_DOWN_MASK_ (0x00000003) |
393 | #define USB_CFG1_SCALE_DOWN_MODE3_ (0x00000003) |
394 | #define USB_CFG1_SCALE_DOWN_MODE2_ (0x00000002) |
395 | #define USB_CFG1_SCALE_DOWN_MODE1_ (0x00000001) |
396 | #define USB_CFG1_SCALE_DOWN_MODE0_ (0x00000000) |
397 | |
398 | #define USB_CFG2 (0x088) |
399 | #define USB_CFG2_SS_DETACH_TIME_MASK_ (0xFFFF0000) |
400 | #define USB_CFG2_HS_DETACH_TIME_MASK_ (0x0000FFFF) |
401 | |
402 | #define BURST_CAP (0x090) |
403 | #define BURST_CAP_SIZE_MASK_ (0x000000FF) |
404 | |
405 | #define BULK_IN_DLY (0x094) |
406 | #define BULK_IN_DLY_MASK_ (0x0000FFFF) |
407 | |
408 | #define INT_EP_CTL (0x098) |
409 | #define INT_EP_INTEP_ON_ (0x80000000) |
410 | #define INT_STS_EEE_TX_LPI_STRT_EN_ (0x04000000) |
411 | #define INT_STS_EEE_TX_LPI_STOP_EN_ (0x02000000) |
412 | #define INT_STS_EEE_RX_LPI_EN_ (0x01000000) |
413 | #define INT_EP_RDFO_EN_ (0x00400000) |
414 | #define INT_EP_TXE_EN_ (0x00200000) |
415 | #define INT_EP_TX_DIS_EN_ (0x00080000) |
416 | #define INT_EP_RX_DIS_EN_ (0x00040000) |
417 | #define INT_EP_PHY_INT_EN_ (0x00020000) |
418 | #define INT_EP_DP_INT_EN_ (0x00010000) |
419 | #define INT_EP_MAC_ERR_EN_ (0x00008000) |
420 | #define INT_EP_TDFU_EN_ (0x00004000) |
421 | #define INT_EP_TDFO_EN_ (0x00002000) |
422 | #define INT_EP_UTX_FP_EN_ (0x00001000) |
423 | #define INT_EP_GPIO_EN_MASK_ (0x00000FFF) |
424 | |
425 | #define PIPE_CTL (0x09C) |
426 | #define PIPE_CTL_TXSWING_ (0x00000040) |
427 | #define PIPE_CTL_TXMARGIN_MASK_ (0x00000038) |
428 | #define PIPE_CTL_TXDEEMPHASIS_MASK_ (0x00000006) |
429 | #define PIPE_CTL_ELASTICITYBUFFERMODE_ (0x00000001) |
430 | |
431 | #define U1_LATENCY (0xA0) |
432 | #define U2_LATENCY (0xA4) |
433 | |
434 | #define USB_STATUS (0x0A8) |
435 | #define USB_STATUS_REMOTE_WK_ (0x00100000) |
436 | #define USB_STATUS_FUNC_REMOTE_WK_ (0x00080000) |
437 | #define USB_STATUS_LTM_ENABLE_ (0x00040000) |
438 | #define USB_STATUS_U2_ENABLE_ (0x00020000) |
439 | #define USB_STATUS_U1_ENABLE_ (0x00010000) |
440 | #define USB_STATUS_SET_SEL_ (0x00000020) |
441 | #define USB_STATUS_REMOTE_WK_STS_ (0x00000010) |
442 | #define USB_STATUS_FUNC_REMOTE_WK_STS_ (0x00000008) |
443 | #define USB_STATUS_LTM_ENABLE_STS_ (0x00000004) |
444 | #define USB_STATUS_U2_ENABLE_STS_ (0x00000002) |
445 | #define USB_STATUS_U1_ENABLE_STS_ (0x00000001) |
446 | |
447 | #define USB_CFG3 (0x0AC) |
448 | #define USB_CFG3_EN_U2_LTM_ (0x40000000) |
449 | #define USB_CFG3_BULK_OUT_NUMP_OVR_ (0x20000000) |
450 | #define USB_CFG3_DIS_FAST_U1_EXIT_ (0x10000000) |
451 | #define USB_CFG3_LPM_NYET_THR_ (0x0F000000) |
452 | #define USB_CFG3_RX_DET_2_POL_LFPS_ (0x00800000) |
453 | #define USB_CFG3_LFPS_FILT_ (0x00400000) |
454 | #define USB_CFG3_SKIP_RX_DET_ (0x00200000) |
455 | #define USB_CFG3_DELAY_P1P2P3_ (0x001C0000) |
456 | #define USB_CFG3_DELAY_PHY_PWR_CHG_ (0x00020000) |
457 | #define USB_CFG3_U1U2_EXIT_FR_ (0x00010000) |
458 | #define USB_CFG3_REQ_P1P2P3 (0x00008000) |
459 | #define USB_CFG3_HST_PRT_CMPL_ (0x00004000) |
460 | #define USB_CFG3_DIS_SCRAMB_ (0x00002000) |
461 | #define USB_CFG3_PWR_DN_SCALE_ (0x00001FFF) |
462 | |
463 | #define RFE_CTL (0x0B0) |
464 | #define RFE_CTL_IGMP_COE_ (0x00004000) |
465 | #define RFE_CTL_ICMP_COE_ (0x00002000) |
466 | #define RFE_CTL_TCPUDP_COE_ (0x00001000) |
467 | #define RFE_CTL_IP_COE_ (0x00000800) |
468 | #define RFE_CTL_BCAST_EN_ (0x00000400) |
469 | #define RFE_CTL_MCAST_EN_ (0x00000200) |
470 | #define RFE_CTL_UCAST_EN_ (0x00000100) |
471 | #define RFE_CTL_VLAN_STRIP_ (0x00000080) |
472 | #define RFE_CTL_DISCARD_UNTAGGED_ (0x00000040) |
473 | #define RFE_CTL_VLAN_FILTER_ (0x00000020) |
474 | #define RFE_CTL_SA_FILTER_ (0x00000010) |
475 | #define RFE_CTL_MCAST_HASH_ (0x00000008) |
476 | #define RFE_CTL_DA_HASH_ (0x00000004) |
477 | #define RFE_CTL_DA_PERFECT_ (0x00000002) |
478 | #define RFE_CTL_RST_ (0x00000001) |
479 | |
480 | #define VLAN_TYPE (0x0B4) |
481 | #define VLAN_TYPE_MASK_ (0x0000FFFF) |
482 | |
483 | #define FCT_RX_CTL (0x0C0) |
484 | #define FCT_RX_CTL_EN_ (0x80000000) |
485 | #define FCT_RX_CTL_RST_ (0x40000000) |
486 | #define FCT_RX_CTL_SBF_ (0x02000000) |
487 | #define FCT_RX_CTL_OVFL_ (0x01000000) |
488 | #define FCT_RX_CTL_DROP_ (0x00800000) |
489 | #define FCT_RX_CTL_NOT_EMPTY_ (0x00400000) |
490 | #define FCT_RX_CTL_EMPTY_ (0x00200000) |
491 | #define FCT_RX_CTL_DIS_ (0x00100000) |
492 | #define FCT_RX_CTL_USED_MASK_ (0x0000FFFF) |
493 | |
494 | #define FCT_TX_CTL (0x0C4) |
495 | #define FCT_TX_CTL_EN_ (0x80000000) |
496 | #define FCT_TX_CTL_RST_ (0x40000000) |
497 | #define FCT_TX_CTL_NOT_EMPTY_ (0x00400000) |
498 | #define FCT_TX_CTL_EMPTY_ (0x00200000) |
499 | #define FCT_TX_CTL_DIS_ (0x00100000) |
500 | #define FCT_TX_CTL_USED_MASK_ (0x0000FFFF) |
501 | |
502 | #define FCT_RX_FIFO_END (0x0C8) |
503 | #define FCT_RX_FIFO_END_MASK_ (0x0000007F) |
504 | |
505 | #define FCT_TX_FIFO_END (0x0CC) |
506 | #define FCT_TX_FIFO_END_MASK_ (0x0000003F) |
507 | |
508 | #define FCT_FLOW (0x0D0) |
509 | #define FCT_FLOW_OFF_MASK_ (0x00007F00) |
510 | #define FCT_FLOW_ON_MASK_ (0x0000007F) |
511 | |
512 | #define RX_DP_STOR (0x0D4) |
513 | #define RX_DP_STORE_TOT_RXUSED_MASK_ (0xFFFF0000) |
514 | #define RX_DP_STORE_UTX_RXUSED_MASK_ (0x0000FFFF) |
515 | |
516 | #define TX_DP_STOR (0x0D8) |
517 | #define TX_DP_STORE_TOT_TXUSED_MASK_ (0xFFFF0000) |
518 | #define TX_DP_STORE_URX_TXUSED_MASK_ (0x0000FFFF) |
519 | |
520 | #define LTM_BELT_IDLE0 (0x0E0) |
521 | #define LTM_BELT_IDLE0_IDLE1000_ (0x0FFF0000) |
522 | #define LTM_BELT_IDLE0_IDLE100_ (0x00000FFF) |
523 | |
524 | #define LTM_BELT_IDLE1 (0x0E4) |
525 | #define LTM_BELT_IDLE1_IDLE10_ (0x00000FFF) |
526 | |
527 | #define LTM_BELT_ACT0 (0x0E8) |
528 | #define LTM_BELT_ACT0_ACT1000_ (0x0FFF0000) |
529 | #define LTM_BELT_ACT0_ACT100_ (0x00000FFF) |
530 | |
531 | #define LTM_BELT_ACT1 (0x0EC) |
532 | #define LTM_BELT_ACT1_ACT10_ (0x00000FFF) |
533 | |
534 | #define LTM_INACTIVE0 (0x0F0) |
535 | #define LTM_INACTIVE0_TIMER1000_ (0xFFFF0000) |
536 | #define LTM_INACTIVE0_TIMER100_ (0x0000FFFF) |
537 | |
538 | #define LTM_INACTIVE1 (0x0F4) |
539 | #define LTM_INACTIVE1_TIMER10_ (0x0000FFFF) |
540 | |
541 | #define MAC_CR (0x100) |
542 | #define MAC_CR_GMII_EN_ (0x00080000) |
543 | #define MAC_CR_EEE_TX_CLK_STOP_EN_ (0x00040000) |
544 | #define MAC_CR_EEE_EN_ (0x00020000) |
545 | #define MAC_CR_EEE_TLAR_EN_ (0x00010000) |
546 | #define MAC_CR_ADP_ (0x00002000) |
547 | #define MAC_CR_AUTO_DUPLEX_ (0x00001000) |
548 | #define MAC_CR_AUTO_SPEED_ (0x00000800) |
549 | #define MAC_CR_LOOPBACK_ (0x00000400) |
550 | #define MAC_CR_BOLMT_MASK_ (0x000000C0) |
551 | #define MAC_CR_FULL_DUPLEX_ (0x00000008) |
552 | #define MAC_CR_SPEED_MASK_ (0x00000006) |
553 | #define MAC_CR_SPEED_1000_ (0x00000004) |
554 | #define MAC_CR_SPEED_100_ (0x00000002) |
555 | #define MAC_CR_SPEED_10_ (0x00000000) |
556 | #define MAC_CR_RST_ (0x00000001) |
557 | |
558 | #define MAC_RX (0x104) |
559 | #define MAC_RX_MAX_SIZE_SHIFT_ (16) |
560 | #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) |
561 | #define MAC_RX_FCS_STRIP_ (0x00000010) |
562 | #define MAC_RX_VLAN_FSE_ (0x00000004) |
563 | #define MAC_RX_RXD_ (0x00000002) |
564 | #define MAC_RX_RXEN_ (0x00000001) |
565 | |
566 | #define MAC_TX (0x108) |
567 | #define MAC_TX_BAD_FCS_ (0x00000004) |
568 | #define MAC_TX_TXD_ (0x00000002) |
569 | #define MAC_TX_TXEN_ (0x00000001) |
570 | |
571 | #define FLOW (0x10C) |
572 | #define FLOW_CR_FORCE_FC_ (0x80000000) |
573 | #define FLOW_CR_TX_FCEN_ (0x40000000) |
574 | #define FLOW_CR_RX_FCEN_ (0x20000000) |
575 | #define FLOW_CR_FPF_ (0x10000000) |
576 | #define FLOW_CR_FCPT_MASK_ (0x0000FFFF) |
577 | |
578 | #define RAND_SEED (0x110) |
579 | #define RAND_SEED_MASK_ (0x0000FFFF) |
580 | |
581 | #define ERR_STS (0x114) |
582 | #define ERR_STS_FERR_ (0x00000100) |
583 | #define ERR_STS_LERR_ (0x00000080) |
584 | #define ERR_STS_RFERR_ (0x00000040) |
585 | #define ERR_STS_ECERR_ (0x00000010) |
586 | #define ERR_STS_ALERR_ (0x00000008) |
587 | #define ERR_STS_URERR_ (0x00000004) |
588 | |
589 | #define RX_ADDRH (0x118) |
590 | #define RX_ADDRH_MASK_ (0x0000FFFF) |
591 | |
592 | #define RX_ADDRL (0x11C) |
593 | #define RX_ADDRL_MASK_ (0xFFFFFFFF) |
594 | |
595 | #define MII_ACC (0x120) |
596 | #define MII_ACC_PHY_ADDR_SHIFT_ (11) |
597 | #define MII_ACC_PHY_ADDR_MASK_ (0x0000F800) |
598 | #define MII_ACC_MIIRINDA_SHIFT_ (6) |
599 | #define MII_ACC_MIIRINDA_MASK_ (0x000007C0) |
600 | #define MII_ACC_MII_READ_ (0x00000000) |
601 | #define MII_ACC_MII_WRITE_ (0x00000002) |
602 | #define MII_ACC_MII_BUSY_ (0x00000001) |
603 | |
604 | #define MII_DATA (0x124) |
605 | #define MII_DATA_MASK_ (0x0000FFFF) |
606 | |
607 | #define MAC_RGMII_ID (0x128) |
608 | #define MAC_RGMII_ID_TXC_DELAY_EN_ (0x00000002) |
609 | #define MAC_RGMII_ID_RXC_DELAY_EN_ (0x00000001) |
610 | |
611 | #define EEE_TX_LPI_REQ_DLY (0x130) |
612 | #define EEE_TX_LPI_REQ_DLY_CNT_MASK_ (0xFFFFFFFF) |
613 | |
614 | #define EEE_TW_TX_SYS (0x134) |
615 | #define EEE_TW_TX_SYS_CNT1G_MASK_ (0xFFFF0000) |
616 | #define EEE_TW_TX_SYS_CNT100M_MASK_ (0x0000FFFF) |
617 | |
618 | #define EEE_TX_LPI_REM_DLY (0x138) |
619 | #define EEE_TX_LPI_REM_DLY_CNT_ (0x00FFFFFF) |
620 | |
621 | #define WUCSR (0x140) |
622 | #define WUCSR_TESTMODE_ (0x80000000) |
623 | #define WUCSR_RFE_WAKE_EN_ (0x00004000) |
624 | #define WUCSR_EEE_TX_WAKE_ (0x00002000) |
625 | #define WUCSR_EEE_TX_WAKE_EN_ (0x00001000) |
626 | #define WUCSR_EEE_RX_WAKE_ (0x00000800) |
627 | #define WUCSR_EEE_RX_WAKE_EN_ (0x00000400) |
628 | #define WUCSR_RFE_WAKE_FR_ (0x00000200) |
629 | #define WUCSR_STORE_WAKE_ (0x00000100) |
630 | #define WUCSR_PFDA_FR_ (0x00000080) |
631 | #define WUCSR_WUFR_ (0x00000040) |
632 | #define WUCSR_MPR_ (0x00000020) |
633 | #define WUCSR_BCST_FR_ (0x00000010) |
634 | #define WUCSR_PFDA_EN_ (0x00000008) |
635 | #define WUCSR_WAKE_EN_ (0x00000004) |
636 | #define WUCSR_MPEN_ (0x00000002) |
637 | #define WUCSR_BCST_EN_ (0x00000001) |
638 | |
639 | #define WK_SRC (0x144) |
640 | #define WK_SRC_GPIOX_INT_WK_SHIFT_ (20) |
641 | #define WK_SRC_GPIOX_INT_WK_MASK_ (0xFFF00000) |
642 | #define WK_SRC_IPV6_TCPSYN_RCD_WK_ (0x00010000) |
643 | #define WK_SRC_IPV4_TCPSYN_RCD_WK_ (0x00008000) |
644 | #define WK_SRC_EEE_TX_WK_ (0x00004000) |
645 | #define WK_SRC_EEE_RX_WK_ (0x00002000) |
646 | #define WK_SRC_GOOD_FR_WK_ (0x00001000) |
647 | #define WK_SRC_PFDA_FR_WK_ (0x00000800) |
648 | #define WK_SRC_MP_FR_WK_ (0x00000400) |
649 | #define WK_SRC_BCAST_FR_WK_ (0x00000200) |
650 | #define WK_SRC_WU_FR_WK_ (0x00000100) |
651 | #define WK_SRC_WUFF_MATCH_MASK_ (0x0000001F) |
652 | |
653 | #define WUF_CFG0 (0x150) |
654 | #define NUM_OF_WUF_CFG (32) |
655 | #define WUF_CFG_BEGIN (WUF_CFG0) |
656 | #define WUF_CFG(index) (WUF_CFG_BEGIN + (4 * (index))) |
657 | #define WUF_CFGX_EN_ (0x80000000) |
658 | #define WUF_CFGX_TYPE_MASK_ (0x03000000) |
659 | #define WUF_CFGX_TYPE_MCAST_ (0x02000000) |
660 | #define WUF_CFGX_TYPE_ALL_ (0x01000000) |
661 | #define WUF_CFGX_TYPE_UCAST_ (0x00000000) |
662 | #define WUF_CFGX_OFFSET_SHIFT_ (16) |
663 | #define WUF_CFGX_OFFSET_MASK_ (0x00FF0000) |
664 | #define WUF_CFGX_CRC16_MASK_ (0x0000FFFF) |
665 | |
666 | #define WUF_MASK0_0 (0x200) |
667 | #define WUF_MASK0_1 (0x204) |
668 | #define WUF_MASK0_2 (0x208) |
669 | #define WUF_MASK0_3 (0x20C) |
670 | #define NUM_OF_WUF_MASK (32) |
671 | #define WUF_MASK0_BEGIN (WUF_MASK0_0) |
672 | #define WUF_MASK1_BEGIN (WUF_MASK0_1) |
673 | #define WUF_MASK2_BEGIN (WUF_MASK0_2) |
674 | #define WUF_MASK3_BEGIN (WUF_MASK0_3) |
675 | #define WUF_MASK0(index) (WUF_MASK0_BEGIN + (0x10 * (index))) |
676 | #define WUF_MASK1(index) (WUF_MASK1_BEGIN + (0x10 * (index))) |
677 | #define WUF_MASK2(index) (WUF_MASK2_BEGIN + (0x10 * (index))) |
678 | #define WUF_MASK3(index) (WUF_MASK3_BEGIN + (0x10 * (index))) |
679 | |
680 | #define MAF_BASE (0x400) |
681 | #define MAF_HIX (0x00) |
682 | #define MAF_LOX (0x04) |
683 | #define NUM_OF_MAF (33) |
684 | #define MAF_HI_BEGIN (MAF_BASE + MAF_HIX) |
685 | #define MAF_LO_BEGIN (MAF_BASE + MAF_LOX) |
686 | #define MAF_HI(index) (MAF_BASE + (8 * (index)) + (MAF_HIX)) |
687 | #define MAF_LO(index) (MAF_BASE + (8 * (index)) + (MAF_LOX)) |
688 | #define MAF_HI_VALID_ (0x80000000) |
689 | #define MAF_HI_TYPE_MASK_ (0x40000000) |
690 | #define MAF_HI_TYPE_SRC_ (0x40000000) |
691 | #define MAF_HI_TYPE_DST_ (0x00000000) |
692 | #define MAF_HI_ADDR_MASK (0x0000FFFF) |
693 | #define MAF_LO_ADDR_MASK (0xFFFFFFFF) |
694 | |
695 | #define WUCSR2 (0x600) |
696 | #define WUCSR2_CSUM_DISABLE_ (0x80000000) |
697 | #define WUCSR2_NA_SA_SEL_ (0x00000100) |
698 | #define WUCSR2_NS_RCD_ (0x00000080) |
699 | #define WUCSR2_ARP_RCD_ (0x00000040) |
700 | #define WUCSR2_IPV6_TCPSYN_RCD_ (0x00000020) |
701 | #define WUCSR2_IPV4_TCPSYN_RCD_ (0x00000010) |
702 | #define WUCSR2_NS_OFFLOAD_EN_ (0x00000008) |
703 | #define WUCSR2_ARP_OFFLOAD_EN_ (0x00000004) |
704 | #define WUCSR2_IPV6_TCPSYN_WAKE_EN_ (0x00000002) |
705 | #define WUCSR2_IPV4_TCPSYN_WAKE_EN_ (0x00000001) |
706 | |
707 | #define NS1_IPV6_ADDR_DEST0 (0x610) |
708 | #define NS1_IPV6_ADDR_DEST1 (0x614) |
709 | #define NS1_IPV6_ADDR_DEST2 (0x618) |
710 | #define NS1_IPV6_ADDR_DEST3 (0x61C) |
711 | |
712 | #define NS1_IPV6_ADDR_SRC0 (0x620) |
713 | #define NS1_IPV6_ADDR_SRC1 (0x624) |
714 | #define NS1_IPV6_ADDR_SRC2 (0x628) |
715 | #define NS1_IPV6_ADDR_SRC3 (0x62C) |
716 | |
717 | #define NS1_ICMPV6_ADDR0_0 (0x630) |
718 | #define NS1_ICMPV6_ADDR0_1 (0x634) |
719 | #define NS1_ICMPV6_ADDR0_2 (0x638) |
720 | #define NS1_ICMPV6_ADDR0_3 (0x63C) |
721 | |
722 | #define NS1_ICMPV6_ADDR1_0 (0x640) |
723 | #define NS1_ICMPV6_ADDR1_1 (0x644) |
724 | #define NS1_ICMPV6_ADDR1_2 (0x648) |
725 | #define NS1_ICMPV6_ADDR1_3 (0x64C) |
726 | |
727 | #define NS2_IPV6_ADDR_DEST0 (0x650) |
728 | #define NS2_IPV6_ADDR_DEST1 (0x654) |
729 | #define NS2_IPV6_ADDR_DEST2 (0x658) |
730 | #define NS2_IPV6_ADDR_DEST3 (0x65C) |
731 | |
732 | #define NS2_IPV6_ADDR_SRC0 (0x660) |
733 | #define NS2_IPV6_ADDR_SRC1 (0x664) |
734 | #define NS2_IPV6_ADDR_SRC2 (0x668) |
735 | #define NS2_IPV6_ADDR_SRC3 (0x66C) |
736 | |
737 | #define NS2_ICMPV6_ADDR0_0 (0x670) |
738 | #define NS2_ICMPV6_ADDR0_1 (0x674) |
739 | #define NS2_ICMPV6_ADDR0_2 (0x678) |
740 | #define NS2_ICMPV6_ADDR0_3 (0x67C) |
741 | |
742 | #define NS2_ICMPV6_ADDR1_0 (0x680) |
743 | #define NS2_ICMPV6_ADDR1_1 (0x684) |
744 | #define NS2_ICMPV6_ADDR1_2 (0x688) |
745 | #define NS2_ICMPV6_ADDR1_3 (0x68C) |
746 | |
747 | #define SYN_IPV4_ADDR_SRC (0x690) |
748 | #define SYN_IPV4_ADDR_DEST (0x694) |
749 | #define SYN_IPV4_TCP_PORTS (0x698) |
750 | #define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_SHIFT_ (16) |
751 | #define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_MASK_ (0xFFFF0000) |
752 | #define SYN_IPV4_TCP_PORTS_IPV4_SRC_PORT_MASK_ (0x0000FFFF) |
753 | |
754 | #define SYN_IPV6_ADDR_SRC0 (0x69C) |
755 | #define SYN_IPV6_ADDR_SRC1 (0x6A0) |
756 | #define SYN_IPV6_ADDR_SRC2 (0x6A4) |
757 | #define SYN_IPV6_ADDR_SRC3 (0x6A8) |
758 | |
759 | #define SYN_IPV6_ADDR_DEST0 (0x6AC) |
760 | #define SYN_IPV6_ADDR_DEST1 (0x6B0) |
761 | #define SYN_IPV6_ADDR_DEST2 (0x6B4) |
762 | #define SYN_IPV6_ADDR_DEST3 (0x6B8) |
763 | |
764 | #define SYN_IPV6_TCP_PORTS (0x6BC) |
765 | #define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_SHIFT_ (16) |
766 | #define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_MASK_ (0xFFFF0000) |
767 | #define SYN_IPV6_TCP_PORTS_IPV6_SRC_PORT_MASK_ (0x0000FFFF) |
768 | |
769 | #define ARP_SPA (0x6C0) |
770 | #define ARP_TPA (0x6C4) |
771 | |
772 | #define PHY_DEV_ID (0x700) |
773 | #define PHY_DEV_ID_REV_SHIFT_ (28) |
774 | #define PHY_DEV_ID_REV_SHIFT_ (28) |
775 | #define PHY_DEV_ID_REV_MASK_ (0xF0000000) |
776 | #define PHY_DEV_ID_MODEL_SHIFT_ (22) |
777 | #define PHY_DEV_ID_MODEL_MASK_ (0x0FC00000) |
778 | #define PHY_DEV_ID_OUI_MASK_ (0x003FFFFF) |
779 | |
780 | #define RGMII_TX_BYP_DLL (0x708) |
781 | #define RGMII_TX_BYP_DLL_TX_TUNE_ADJ_MASK_ (0x000FC00) |
782 | #define RGMII_TX_BYP_DLL_TX_TUNE_SEL_MASK_ (0x00003F0) |
783 | #define RGMII_TX_BYP_DLL_TX_DLL_RESET_ (0x0000002) |
784 | #define RGMII_TX_BYP_DLL_TX_DLL_BYPASS_ (0x0000001) |
785 | |
786 | #define RGMII_RX_BYP_DLL (0x70C) |
787 | #define RGMII_RX_BYP_DLL_RX_TUNE_ADJ_MASK_ (0x000FC00) |
788 | #define RGMII_RX_BYP_DLL_RX_TUNE_SEL_MASK_ (0x00003F0) |
789 | #define RGMII_RX_BYP_DLL_RX_DLL_RESET_ (0x0000002) |
790 | #define RGMII_RX_BYP_DLL_RX_DLL_BYPASS_ (0x0000001) |
791 | |
792 | #define OTP_BASE_ADDR (0x00001000) |
793 | #define OTP_ADDR_RANGE_ (0x1FF) |
794 | |
795 | #define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00) |
796 | #define OTP_PWR_DN_PWRDN_N_ (0x01) |
797 | |
798 | #define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01) |
799 | #define OTP_ADDR1_15_11 (0x1F) |
800 | |
801 | #define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02) |
802 | #define OTP_ADDR2_10_3 (0xFF) |
803 | |
804 | #define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03) |
805 | #define OTP_ADDR3_2_0 (0x03) |
806 | |
807 | #define OTP_PRGM_DATA (OTP_BASE_ADDR + 4 * 0x04) |
808 | |
809 | #define OTP_PRGM_MODE (OTP_BASE_ADDR + 4 * 0x05) |
810 | #define OTP_PRGM_MODE_BYTE_ (0x01) |
811 | |
812 | #define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06) |
813 | |
814 | #define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08) |
815 | #define OTP_FUNC_CMD_RESET_ (0x04) |
816 | #define OTP_FUNC_CMD_PROGRAM_ (0x02) |
817 | #define OTP_FUNC_CMD_READ_ (0x01) |
818 | |
819 | #define OTP_TST_CMD (OTP_BASE_ADDR + 4 * 0x09) |
820 | #define OTP_TST_CMD_TEST_DEC_SEL_ (0x10) |
821 | #define OTP_TST_CMD_PRGVRFY_ (0x08) |
822 | #define OTP_TST_CMD_WRTEST_ (0x04) |
823 | #define OTP_TST_CMD_TESTDEC_ (0x02) |
824 | #define OTP_TST_CMD_BLANKCHECK_ (0x01) |
825 | |
826 | #define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A) |
827 | #define OTP_CMD_GO_GO_ (0x01) |
828 | |
829 | #define OTP_PASS_FAIL (OTP_BASE_ADDR + 4 * 0x0B) |
830 | #define OTP_PASS_FAIL_PASS_ (0x02) |
831 | #define OTP_PASS_FAIL_FAIL_ (0x01) |
832 | |
833 | #define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0C) |
834 | #define OTP_STATUS_OTP_LOCK_ (0x10) |
835 | #define OTP_STATUS_WEB_ (0x08) |
836 | #define OTP_STATUS_PGMEN (0x04) |
837 | #define OTP_STATUS_CPUMPEN_ (0x02) |
838 | #define OTP_STATUS_BUSY_ (0x01) |
839 | |
840 | #define OTP_MAX_PRG (OTP_BASE_ADDR + 4 * 0x0D) |
841 | #define OTP_MAX_PRG_MAX_PROG (0x1F) |
842 | |
843 | #define OTP_INTR_STATUS (OTP_BASE_ADDR + 4 * 0x10) |
844 | #define OTP_INTR_STATUS_READY_ (0x01) |
845 | |
846 | #define OTP_INTR_MASK (OTP_BASE_ADDR + 4 * 0x11) |
847 | #define OTP_INTR_MASK_READY_ (0x01) |
848 | |
849 | #define OTP_RSTB_PW1 (OTP_BASE_ADDR + 4 * 0x14) |
850 | #define OTP_RSTB_PW2 (OTP_BASE_ADDR + 4 * 0x15) |
851 | #define OTP_PGM_PW1 (OTP_BASE_ADDR + 4 * 0x18) |
852 | #define OTP_PGM_PW2 (OTP_BASE_ADDR + 4 * 0x19) |
853 | #define OTP_READ_PW1 (OTP_BASE_ADDR + 4 * 0x1C) |
854 | #define OTP_READ_PW2 (OTP_BASE_ADDR + 4 * 0x1D) |
855 | #define OTP_TCRST (OTP_BASE_ADDR + 4 * 0x20) |
856 | #define OTP_RSRD (OTP_BASE_ADDR + 4 * 0x21) |
857 | #define OTP_TREADEN_VAL (OTP_BASE_ADDR + 4 * 0x22) |
858 | #define OTP_TDLES_VAL (OTP_BASE_ADDR + 4 * 0x23) |
859 | #define OTP_TWWL_VAL (OTP_BASE_ADDR + 4 * 0x24) |
860 | #define OTP_TDLEH_VAL (OTP_BASE_ADDR + 4 * 0x25) |
861 | #define OTP_TWPED_VAL (OTP_BASE_ADDR + 4 * 0x26) |
862 | #define OTP_TPES_VAL (OTP_BASE_ADDR + 4 * 0x27) |
863 | #define OTP_TCPS_VAL (OTP_BASE_ADDR + 4 * 0x28) |
864 | #define OTP_TCPH_VAL (OTP_BASE_ADDR + 4 * 0x29) |
865 | #define OTP_TPGMVFY_VAL (OTP_BASE_ADDR + 4 * 0x2A) |
866 | #define OTP_TPEH_VAL (OTP_BASE_ADDR + 4 * 0x2B) |
867 | #define OTP_TPGRST_VAL (OTP_BASE_ADDR + 4 * 0x2C) |
868 | #define OTP_TCLES_VAL (OTP_BASE_ADDR + 4 * 0x2D) |
869 | #define OTP_TCLEH_VAL (OTP_BASE_ADDR + 4 * 0x2E) |
870 | #define OTP_TRDES_VAL (OTP_BASE_ADDR + 4 * 0x2F) |
871 | #define OTP_TBCACC_VAL (OTP_BASE_ADDR + 4 * 0x30) |
872 | #define OTP_TAAC_VAL (OTP_BASE_ADDR + 4 * 0x31) |
873 | #define OTP_TACCT_VAL (OTP_BASE_ADDR + 4 * 0x32) |
874 | #define OTP_TRDEP_VAL (OTP_BASE_ADDR + 4 * 0x38) |
875 | #define OTP_TPGSV_VAL (OTP_BASE_ADDR + 4 * 0x39) |
876 | #define OTP_TPVSR_VAL (OTP_BASE_ADDR + 4 * 0x3A) |
877 | #define OTP_TPVHR_VAL (OTP_BASE_ADDR + 4 * 0x3B) |
878 | #define OTP_TPVSA_VAL (OTP_BASE_ADDR + 4 * 0x3C) |
879 | #endif /* _LAN78XX_H */ |
880 | |