| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /*************************************************************************** |
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| 3 | * |
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| 4 | * Copyright (C) 2007-2010 SMSC |
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| 5 | * |
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| 6 | *****************************************************************************/ |
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| 7 | |
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| 8 | #ifndef _SMSC75XX_H |
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| 9 | #define _SMSC75XX_H |
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| 10 | |
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| 11 | /* Tx command words */ |
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| 12 | #define TX_CMD_A_LSO (0x08000000) |
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| 13 | #define TX_CMD_A_IPE (0x04000000) |
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| 14 | #define TX_CMD_A_TPE (0x02000000) |
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| 15 | #define TX_CMD_A_IVTG (0x01000000) |
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| 16 | #define TX_CMD_A_RVTG (0x00800000) |
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| 17 | #define TX_CMD_A_FCS (0x00400000) |
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| 18 | #define TX_CMD_A_LEN (0x000FFFFF) |
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| 19 | |
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| 20 | #define TX_CMD_B_MSS (0x3FFF0000) |
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| 21 | #define TX_CMD_B_MSS_SHIFT (16) |
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| 22 | #define TX_MSS_MIN ((u16)8) |
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| 23 | #define TX_CMD_B_VTAG (0x0000FFFF) |
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| 24 | |
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| 25 | /* Rx command words */ |
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| 26 | #define RX_CMD_A_ICE (0x80000000) |
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| 27 | #define RX_CMD_A_TCE (0x40000000) |
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| 28 | #define RX_CMD_A_IPV (0x20000000) |
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| 29 | #define RX_CMD_A_PID (0x18000000) |
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| 30 | #define RX_CMD_A_PID_NIP (0x00000000) |
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| 31 | #define RX_CMD_A_PID_TCP (0x08000000) |
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| 32 | #define RX_CMD_A_PID_UDP (0x10000000) |
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| 33 | #define RX_CMD_A_PID_PP (0x18000000) |
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| 34 | #define RX_CMD_A_PFF (0x04000000) |
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| 35 | #define RX_CMD_A_BAM (0x02000000) |
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| 36 | #define RX_CMD_A_MAM (0x01000000) |
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| 37 | #define RX_CMD_A_FVTG (0x00800000) |
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| 38 | #define RX_CMD_A_RED (0x00400000) |
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| 39 | #define RX_CMD_A_RWT (0x00200000) |
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| 40 | #define RX_CMD_A_RUNT (0x00100000) |
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| 41 | #define RX_CMD_A_LONG (0x00080000) |
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| 42 | #define RX_CMD_A_RXE (0x00040000) |
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| 43 | #define RX_CMD_A_DRB (0x00020000) |
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| 44 | #define RX_CMD_A_FCS (0x00010000) |
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| 45 | #define RX_CMD_A_UAM (0x00008000) |
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| 46 | #define RX_CMD_A_LCSM (0x00004000) |
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| 47 | #define RX_CMD_A_LEN (0x00003FFF) |
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| 48 | |
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| 49 | #define RX_CMD_B_CSUM (0xFFFF0000) |
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| 50 | #define RX_CMD_B_CSUM_SHIFT (16) |
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| 51 | #define RX_CMD_B_VTAG (0x0000FFFF) |
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| 52 | |
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| 53 | /* SCSRs */ |
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| 54 | #define ID_REV (0x0000) |
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| 55 | |
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| 56 | #define FPGA_REV (0x0004) |
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| 57 | |
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| 58 | #define BOND_CTL (0x0008) |
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| 59 | |
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| 60 | #define INT_STS (0x000C) |
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| 61 | #define INT_STS_RDFO_INT (0x00400000) |
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| 62 | #define INT_STS_TXE_INT (0x00200000) |
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| 63 | #define INT_STS_MACRTO_INT (0x00100000) |
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| 64 | #define INT_STS_TX_DIS_INT (0x00080000) |
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| 65 | #define INT_STS_RX_DIS_INT (0x00040000) |
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| 66 | #define INT_STS_PHY_INT_ (0x00020000) |
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| 67 | #define INT_STS_MAC_ERR_INT (0x00008000) |
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| 68 | #define INT_STS_TDFU (0x00004000) |
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| 69 | #define INT_STS_TDFO (0x00002000) |
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| 70 | #define INT_STS_GPIOS (0x00000FFF) |
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| 71 | #define INT_STS_CLEAR_ALL (0xFFFFFFFF) |
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| 72 | |
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| 73 | #define HW_CFG (0x0010) |
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| 74 | #define HW_CFG_SMDET_STS (0x00008000) |
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| 75 | #define HW_CFG_SMDET_EN (0x00004000) |
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| 76 | #define HW_CFG_EEM (0x00002000) |
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| 77 | #define HW_CFG_RST_PROTECT (0x00001000) |
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| 78 | #define HW_CFG_PORT_SWAP (0x00000800) |
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| 79 | #define HW_CFG_PHY_BOOST (0x00000600) |
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| 80 | #define HW_CFG_PHY_BOOST_NORMAL (0x00000000) |
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| 81 | #define HW_CFG_PHY_BOOST_4 (0x00002000) |
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| 82 | #define HW_CFG_PHY_BOOST_8 (0x00004000) |
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| 83 | #define HW_CFG_PHY_BOOST_12 (0x00006000) |
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| 84 | #define HW_CFG_LEDB (0x00000100) |
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| 85 | #define HW_CFG_BIR (0x00000080) |
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| 86 | #define HW_CFG_SBP (0x00000040) |
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| 87 | #define HW_CFG_IME (0x00000020) |
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| 88 | #define HW_CFG_MEF (0x00000010) |
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| 89 | #define HW_CFG_ETC (0x00000008) |
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| 90 | #define HW_CFG_BCE (0x00000004) |
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| 91 | #define HW_CFG_LRST (0x00000002) |
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| 92 | #define HW_CFG_SRST (0x00000001) |
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| 93 | |
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| 94 | #define PMT_CTL (0x0014) |
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| 95 | #define PMT_CTL_PHY_PWRUP (0x00000400) |
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| 96 | #define PMT_CTL_RES_CLR_WKP_EN (0x00000100) |
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| 97 | #define PMT_CTL_DEV_RDY (0x00000080) |
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| 98 | #define PMT_CTL_SUS_MODE (0x00000060) |
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| 99 | #define PMT_CTL_SUS_MODE_0 (0x00000000) |
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| 100 | #define PMT_CTL_SUS_MODE_1 (0x00000020) |
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| 101 | #define PMT_CTL_SUS_MODE_2 (0x00000040) |
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| 102 | #define PMT_CTL_SUS_MODE_3 (0x00000060) |
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| 103 | #define PMT_CTL_PHY_RST (0x00000010) |
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| 104 | #define PMT_CTL_WOL_EN (0x00000008) |
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| 105 | #define PMT_CTL_ED_EN (0x00000004) |
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| 106 | #define PMT_CTL_WUPS (0x00000003) |
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| 107 | #define PMT_CTL_WUPS_NO (0x00000000) |
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| 108 | #define PMT_CTL_WUPS_ED (0x00000001) |
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| 109 | #define PMT_CTL_WUPS_WOL (0x00000002) |
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| 110 | #define PMT_CTL_WUPS_MULTI (0x00000003) |
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| 111 | |
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| 112 | #define LED_GPIO_CFG (0x0018) |
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| 113 | #define LED_GPIO_CFG_LED2_FUN_SEL (0x80000000) |
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| 114 | #define LED_GPIO_CFG_LED10_FUN_SEL (0x40000000) |
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| 115 | #define LED_GPIO_CFG_LEDGPIO_EN (0x0000F000) |
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| 116 | #define LED_GPIO_CFG_LEDGPIO_EN_0 (0x00001000) |
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| 117 | #define LED_GPIO_CFG_LEDGPIO_EN_1 (0x00002000) |
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| 118 | #define LED_GPIO_CFG_LEDGPIO_EN_2 (0x00004000) |
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| 119 | #define LED_GPIO_CFG_LEDGPIO_EN_3 (0x00008000) |
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| 120 | #define LED_GPIO_CFG_GPBUF (0x00000F00) |
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| 121 | #define LED_GPIO_CFG_GPBUF_0 (0x00000100) |
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| 122 | #define LED_GPIO_CFG_GPBUF_1 (0x00000200) |
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| 123 | #define LED_GPIO_CFG_GPBUF_2 (0x00000400) |
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| 124 | #define LED_GPIO_CFG_GPBUF_3 (0x00000800) |
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| 125 | #define LED_GPIO_CFG_GPDIR (0x000000F0) |
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| 126 | #define LED_GPIO_CFG_GPDIR_0 (0x00000010) |
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| 127 | #define LED_GPIO_CFG_GPDIR_1 (0x00000020) |
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| 128 | #define LED_GPIO_CFG_GPDIR_2 (0x00000040) |
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| 129 | #define LED_GPIO_CFG_GPDIR_3 (0x00000080) |
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| 130 | #define LED_GPIO_CFG_GPDATA (0x0000000F) |
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| 131 | #define LED_GPIO_CFG_GPDATA_0 (0x00000001) |
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| 132 | #define LED_GPIO_CFG_GPDATA_1 (0x00000002) |
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| 133 | #define LED_GPIO_CFG_GPDATA_2 (0x00000004) |
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| 134 | #define LED_GPIO_CFG_GPDATA_3 (0x00000008) |
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| 135 | |
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| 136 | #define GPIO_CFG (0x001C) |
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| 137 | #define GPIO_CFG_SHIFT (24) |
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| 138 | #define GPIO_CFG_GPEN (0xFF000000) |
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| 139 | #define GPIO_CFG_GPBUF (0x00FF0000) |
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| 140 | #define GPIO_CFG_GPDIR (0x0000FF00) |
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| 141 | #define GPIO_CFG_GPDATA (0x000000FF) |
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| 142 | |
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| 143 | #define GPIO_WAKE (0x0020) |
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| 144 | #define GPIO_WAKE_PHY_LINKUP_EN (0x80000000) |
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| 145 | #define GPIO_WAKE_POL (0x0FFF0000) |
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| 146 | #define GPIO_WAKE_POL_SHIFT (16) |
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| 147 | #define GPIO_WAKE_WK (0x00000FFF) |
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| 148 | |
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| 149 | #define DP_SEL (0x0024) |
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| 150 | #define DP_SEL_DPRDY (0x80000000) |
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| 151 | #define DP_SEL_RSEL (0x0000000F) |
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| 152 | #define DP_SEL_URX (0x00000000) |
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| 153 | #define DP_SEL_VHF (0x00000001) |
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| 154 | #define DP_SEL_VHF_HASH_LEN (16) |
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| 155 | #define DP_SEL_VHF_VLAN_LEN (128) |
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| 156 | #define DP_SEL_LSO_HEAD (0x00000002) |
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| 157 | #define DP_SEL_FCT_RX (0x00000003) |
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| 158 | #define DP_SEL_FCT_TX (0x00000004) |
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| 159 | #define DP_SEL_DESCRIPTOR (0x00000005) |
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| 160 | #define DP_SEL_WOL (0x00000006) |
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| 161 | |
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| 162 | #define DP_CMD (0x0028) |
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| 163 | #define DP_CMD_WRITE (0x01) |
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| 164 | #define DP_CMD_READ (0x00) |
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| 165 | |
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| 166 | #define DP_ADDR (0x002C) |
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| 167 | |
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| 168 | #define DP_DATA (0x0030) |
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| 169 | |
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| 170 | #define BURST_CAP (0x0034) |
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| 171 | #define BURST_CAP_MASK (0x0000000F) |
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| 172 | |
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| 173 | #define INT_EP_CTL (0x0038) |
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| 174 | #define INT_EP_CTL_INTEP_ON (0x80000000) |
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| 175 | #define INT_EP_CTL_RDFO_EN (0x00400000) |
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| 176 | #define INT_EP_CTL_TXE_EN (0x00200000) |
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| 177 | #define INT_EP_CTL_MACROTO_EN (0x00100000) |
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| 178 | #define INT_EP_CTL_TX_DIS_EN (0x00080000) |
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| 179 | #define INT_EP_CTL_RX_DIS_EN (0x00040000) |
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| 180 | #define INT_EP_CTL_PHY_EN_ (0x00020000) |
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| 181 | #define INT_EP_CTL_MAC_ERR_EN (0x00008000) |
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| 182 | #define INT_EP_CTL_TDFU_EN (0x00004000) |
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| 183 | #define INT_EP_CTL_TDFO_EN (0x00002000) |
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| 184 | #define INT_EP_CTL_RX_FIFO_EN (0x00001000) |
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| 185 | #define INT_EP_CTL_GPIOX_EN (0x00000FFF) |
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| 186 | |
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| 187 | #define BULK_IN_DLY (0x003C) |
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| 188 | #define BULK_IN_DLY_MASK (0xFFFF) |
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| 189 | |
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| 190 | #define E2P_CMD (0x0040) |
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| 191 | #define E2P_CMD_BUSY (0x80000000) |
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| 192 | #define E2P_CMD_MASK (0x70000000) |
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| 193 | #define E2P_CMD_READ (0x00000000) |
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| 194 | #define E2P_CMD_EWDS (0x10000000) |
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| 195 | #define E2P_CMD_EWEN (0x20000000) |
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| 196 | #define E2P_CMD_WRITE (0x30000000) |
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| 197 | #define E2P_CMD_WRAL (0x40000000) |
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| 198 | #define E2P_CMD_ERASE (0x50000000) |
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| 199 | #define E2P_CMD_ERAL (0x60000000) |
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| 200 | #define E2P_CMD_RELOAD (0x70000000) |
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| 201 | #define E2P_CMD_TIMEOUT (0x00000400) |
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| 202 | #define E2P_CMD_LOADED (0x00000200) |
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| 203 | #define E2P_CMD_ADDR (0x000001FF) |
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| 204 | |
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| 205 | #define MAX_EEPROM_SIZE (512) |
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| 206 | |
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| 207 | #define E2P_DATA (0x0044) |
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| 208 | #define E2P_DATA_MASK_ (0x000000FF) |
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| 209 | |
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| 210 | #define RFE_CTL (0x0060) |
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| 211 | #define RFE_CTL_TCPUDP_CKM (0x00001000) |
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| 212 | #define RFE_CTL_IP_CKM (0x00000800) |
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| 213 | #define RFE_CTL_AB (0x00000400) |
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| 214 | #define RFE_CTL_AM (0x00000200) |
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| 215 | #define RFE_CTL_AU (0x00000100) |
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| 216 | #define RFE_CTL_VS (0x00000080) |
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| 217 | #define RFE_CTL_UF (0x00000040) |
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| 218 | #define RFE_CTL_VF (0x00000020) |
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| 219 | #define RFE_CTL_SPF (0x00000010) |
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| 220 | #define RFE_CTL_MHF (0x00000008) |
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| 221 | #define RFE_CTL_DHF (0x00000004) |
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| 222 | #define RFE_CTL_DPF (0x00000002) |
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| 223 | #define RFE_CTL_RST_RF (0x00000001) |
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| 224 | |
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| 225 | #define VLAN_TYPE (0x0064) |
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| 226 | #define VLAN_TYPE_MASK (0x0000FFFF) |
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| 227 | |
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| 228 | #define FCT_RX_CTL (0x0090) |
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| 229 | #define FCT_RX_CTL_EN (0x80000000) |
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| 230 | #define FCT_RX_CTL_RST (0x40000000) |
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| 231 | #define FCT_RX_CTL_SBF (0x02000000) |
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| 232 | #define FCT_RX_CTL_OVERFLOW (0x01000000) |
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| 233 | #define FCT_RX_CTL_FRM_DROP (0x00800000) |
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| 234 | #define FCT_RX_CTL_RX_NOT_EMPTY (0x00400000) |
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| 235 | #define FCT_RX_CTL_RX_EMPTY (0x00200000) |
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| 236 | #define FCT_RX_CTL_RX_DISABLED (0x00100000) |
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| 237 | #define FCT_RX_CTL_RXUSED (0x0000FFFF) |
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| 238 | |
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| 239 | #define FCT_TX_CTL (0x0094) |
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| 240 | #define FCT_TX_CTL_EN (0x80000000) |
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| 241 | #define FCT_TX_CTL_RST (0x40000000) |
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| 242 | #define FCT_TX_CTL_TX_NOT_EMPTY (0x00400000) |
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| 243 | #define FCT_TX_CTL_TX_EMPTY (0x00200000) |
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| 244 | #define FCT_TX_CTL_TX_DISABLED (0x00100000) |
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| 245 | #define FCT_TX_CTL_TXUSED (0x0000FFFF) |
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| 246 | |
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| 247 | #define FCT_RX_FIFO_END (0x0098) |
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| 248 | #define FCT_RX_FIFO_END_MASK (0x0000007F) |
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| 249 | |
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| 250 | #define FCT_TX_FIFO_END (0x009C) |
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| 251 | #define FCT_TX_FIFO_END_MASK (0x0000003F) |
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| 252 | |
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| 253 | #define FCT_FLOW (0x00A0) |
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| 254 | #define FCT_FLOW_THRESHOLD_OFF (0x00007F00) |
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| 255 | #define FCT_FLOW_THRESHOLD_OFF_SHIFT (8) |
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| 256 | #define FCT_FLOW_THRESHOLD_ON (0x0000007F) |
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| 257 | |
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| 258 | /* MAC CSRs */ |
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| 259 | #define MAC_CR (0x100) |
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| 260 | #define MAC_CR_ADP (0x00002000) |
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| 261 | #define MAC_CR_ADD (0x00001000) |
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| 262 | #define MAC_CR_ASD (0x00000800) |
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| 263 | #define MAC_CR_INT_LOOP (0x00000400) |
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| 264 | #define MAC_CR_BOLMT (0x000000C0) |
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| 265 | #define MAC_CR_FDPX (0x00000008) |
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| 266 | #define MAC_CR_CFG (0x00000006) |
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| 267 | #define MAC_CR_CFG_10 (0x00000000) |
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| 268 | #define MAC_CR_CFG_100 (0x00000002) |
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| 269 | #define MAC_CR_CFG_1000 (0x00000004) |
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| 270 | #define MAC_CR_RST (0x00000001) |
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| 271 | |
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| 272 | #define MAC_RX (0x104) |
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| 273 | #define MAC_RX_MAX_SIZE (0x3FFF0000) |
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| 274 | #define MAC_RX_MAX_SIZE_SHIFT (16) |
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| 275 | #define MAC_RX_FCS_STRIP (0x00000010) |
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| 276 | #define MAC_RX_FSE (0x00000004) |
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| 277 | #define MAC_RX_RXD (0x00000002) |
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| 278 | #define MAC_RX_RXEN (0x00000001) |
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| 279 | |
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| 280 | #define MAC_TX (0x108) |
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| 281 | #define MAC_TX_BFCS (0x00000004) |
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| 282 | #define MAC_TX_TXD (0x00000002) |
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| 283 | #define MAC_TX_TXEN (0x00000001) |
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| 284 | |
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| 285 | #define FLOW (0x10C) |
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| 286 | #define FLOW_FORCE_FC (0x80000000) |
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| 287 | #define FLOW_TX_FCEN (0x40000000) |
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| 288 | #define FLOW_RX_FCEN (0x20000000) |
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| 289 | #define FLOW_FPF (0x10000000) |
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| 290 | #define FLOW_PAUSE_TIME (0x0000FFFF) |
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| 291 | |
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| 292 | #define RAND_SEED (0x110) |
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| 293 | #define RAND_SEED_MASK (0x0000FFFF) |
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| 294 | |
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| 295 | #define ERR_STS (0x114) |
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| 296 | #define ERR_STS_FCS_ERR (0x00000100) |
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| 297 | #define ERR_STS_LFRM_ERR (0x00000080) |
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| 298 | #define ERR_STS_RUNT_ERR (0x00000040) |
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| 299 | #define ERR_STS_COLLISION_ERR (0x00000010) |
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| 300 | #define ERR_STS_ALIGN_ERR (0x00000008) |
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| 301 | #define ERR_STS_URUN_ERR (0x00000004) |
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| 302 | |
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| 303 | #define RX_ADDRH (0x118) |
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| 304 | #define RX_ADDRH_MASK (0x0000FFFF) |
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| 305 | |
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| 306 | #define RX_ADDRL (0x11C) |
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| 307 | |
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| 308 | #define MII_ACCESS (0x120) |
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| 309 | #define MII_ACCESS_PHY_ADDR (0x0000F800) |
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| 310 | #define MII_ACCESS_PHY_ADDR_SHIFT (11) |
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| 311 | #define MII_ACCESS_REG_ADDR (0x000007C0) |
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| 312 | #define MII_ACCESS_REG_ADDR_SHIFT (6) |
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| 313 | #define MII_ACCESS_READ (0x00000000) |
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| 314 | #define MII_ACCESS_WRITE (0x00000002) |
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| 315 | #define MII_ACCESS_BUSY (0x00000001) |
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| 316 | |
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| 317 | #define MII_DATA (0x124) |
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| 318 | #define MII_DATA_MASK (0x0000FFFF) |
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| 319 | |
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| 320 | #define WUCSR (0x140) |
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| 321 | #define WUCSR_PFDA_FR (0x00000080) |
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| 322 | #define WUCSR_WUFR (0x00000040) |
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| 323 | #define WUCSR_MPR (0x00000020) |
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| 324 | #define WUCSR_BCAST_FR (0x00000010) |
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| 325 | #define WUCSR_PFDA_EN (0x00000008) |
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| 326 | #define WUCSR_WUEN (0x00000004) |
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| 327 | #define WUCSR_MPEN (0x00000002) |
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| 328 | #define WUCSR_BCST_EN (0x00000001) |
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| 329 | |
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| 330 | #define WUF_CFGX (0x144) |
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| 331 | #define WUF_CFGX_EN (0x80000000) |
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| 332 | #define WUF_CFGX_ATYPE (0x03000000) |
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| 333 | #define WUF_CFGX_ATYPE_UNICAST (0x00000000) |
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| 334 | #define WUF_CFGX_ATYPE_MULTICAST (0x02000000) |
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| 335 | #define WUF_CFGX_ATYPE_ALL (0x03000000) |
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| 336 | #define WUF_CFGX_PATTERN_OFFSET (0x007F0000) |
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| 337 | #define WUF_CFGX_PATTERN_OFFSET_SHIFT (16) |
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| 338 | #define WUF_CFGX_CRC16 (0x0000FFFF) |
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| 339 | #define WUF_NUM (8) |
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| 340 | |
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| 341 | #define WUF_MASKX (0x170) |
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| 342 | #define WUF_MASKX_AVALID (0x80000000) |
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| 343 | #define WUF_MASKX_ATYPE (0x40000000) |
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| 344 | |
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| 345 | #define ADDR_FILTX (0x300) |
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| 346 | #define ADDR_FILTX_FB_VALID (0x80000000) |
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| 347 | #define ADDR_FILTX_FB_TYPE (0x40000000) |
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| 348 | #define ADDR_FILTX_FB_ADDRHI (0x0000FFFF) |
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| 349 | #define ADDR_FILTX_SB_ADDRLO (0xFFFFFFFF) |
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| 350 | |
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| 351 | #define WUCSR2 (0x500) |
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| 352 | #define WUCSR2_NS_RCD (0x00000040) |
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| 353 | #define WUCSR2_ARP_RCD (0x00000020) |
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| 354 | #define WUCSR2_TCPSYN_RCD (0x00000010) |
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| 355 | #define WUCSR2_NS_OFFLOAD (0x00000004) |
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| 356 | #define WUCSR2_ARP_OFFLOAD (0x00000002) |
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| 357 | #define WUCSR2_TCPSYN_OFFLOAD (0x00000001) |
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| 358 | |
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| 359 | #define WOL_FIFO_STS (0x504) |
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| 360 | |
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| 361 | #define IPV6_ADDRX (0x510) |
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| 362 | |
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| 363 | #define IPV4_ADDRX (0x590) |
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| 364 | |
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| 365 | |
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| 366 | /* Vendor-specific PHY Definitions */ |
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| 367 | |
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| 368 | /* Mode Control/Status Register */ |
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| 369 | #define PHY_MODE_CTRL_STS (17) |
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| 370 | #define MODE_CTRL_STS_EDPWRDOWN ((u16)0x2000) |
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| 371 | #define MODE_CTRL_STS_ENERGYON ((u16)0x0002) |
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| 372 | |
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| 373 | #define PHY_INT_SRC (29) |
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| 374 | #define PHY_INT_SRC_ENERGY_ON ((u16)0x0080) |
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| 375 | #define PHY_INT_SRC_ANEG_COMP ((u16)0x0040) |
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| 376 | #define PHY_INT_SRC_REMOTE_FAULT ((u16)0x0020) |
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| 377 | #define PHY_INT_SRC_LINK_DOWN ((u16)0x0010) |
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| 378 | #define PHY_INT_SRC_CLEAR_ALL ((u16)0xffff) |
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| 379 | |
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| 380 | #define PHY_INT_MASK (30) |
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| 381 | #define PHY_INT_MASK_ENERGY_ON ((u16)0x0080) |
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| 382 | #define PHY_INT_MASK_ANEG_COMP ((u16)0x0040) |
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| 383 | #define PHY_INT_MASK_REMOTE_FAULT ((u16)0x0020) |
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| 384 | #define PHY_INT_MASK_LINK_DOWN ((u16)0x0010) |
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| 385 | #define PHY_INT_MASK_DEFAULT (PHY_INT_MASK_ANEG_COMP | \ |
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| 386 | PHY_INT_MASK_LINK_DOWN) |
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| 387 | |
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| 388 | #define PHY_SPECIAL (31) |
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| 389 | #define PHY_SPECIAL_SPD ((u16)0x001C) |
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| 390 | #define PHY_SPECIAL_SPD_10HALF ((u16)0x0004) |
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| 391 | #define PHY_SPECIAL_SPD_10FULL ((u16)0x0014) |
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| 392 | #define PHY_SPECIAL_SPD_100HALF ((u16)0x0008) |
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| 393 | #define PHY_SPECIAL_SPD_100FULL ((u16)0x0018) |
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| 394 | |
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| 395 | /* USB Vendor Requests */ |
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| 396 | #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 |
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| 397 | #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 |
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| 398 | #define USB_VENDOR_REQUEST_GET_STATS 0xA2 |
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| 399 | |
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| 400 | /* Interrupt Endpoint status word bitfields */ |
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| 401 | #define INT_ENP_RDFO_INT ((u32)BIT(22)) |
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| 402 | #define INT_ENP_TXE_INT ((u32)BIT(21)) |
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| 403 | #define INT_ENP_TX_DIS_INT ((u32)BIT(19)) |
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| 404 | #define INT_ENP_RX_DIS_INT ((u32)BIT(18)) |
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| 405 | #define INT_ENP_PHY_INT ((u32)BIT(17)) |
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| 406 | #define INT_ENP_MAC_ERR_INT ((u32)BIT(15)) |
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| 407 | #define INT_ENP_RX_FIFO_DATA_INT ((u32)BIT(12)) |
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| 408 | |
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| 409 | #endif /* _SMSC75XX_H */ |
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| 410 | |
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