| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * drivers/tdm/line_ctrl/slic_ds26522.h |
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| 4 | * |
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| 5 | * Copyright 2016 Freescale Semiconductor, Inc. |
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| 6 | * |
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| 7 | * Author: Zhao Qiang <B45475@freescale.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #define DS26522_RF_ADDR_START 0x00 |
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| 11 | #define DS26522_RF_ADDR_END 0xef |
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| 12 | #define DS26522_GLB_ADDR_START 0xf0 |
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| 13 | #define DS26522_GLB_ADDR_END 0xff |
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| 14 | #define DS26522_TF_ADDR_START 0x100 |
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| 15 | #define DS26522_TF_ADDR_END 0x1ef |
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| 16 | #define DS26522_LIU_ADDR_START 0x1000 |
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| 17 | #define DS26522_LIU_ADDR_END 0x101f |
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| 18 | #define DS26522_TEST_ADDR_START 0x1008 |
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| 19 | #define DS26522_TEST_ADDR_END 0x101f |
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| 20 | #define DS26522_BERT_ADDR_START 0x1100 |
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| 21 | #define DS26522_BERT_ADDR_END 0x110f |
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| 22 | |
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| 23 | #define DS26522_RMMR_ADDR 0x80 |
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| 24 | #define DS26522_RCR1_ADDR 0x81 |
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| 25 | #define DS26522_RCR3_ADDR 0x83 |
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| 26 | #define DS26522_RIOCR_ADDR 0x84 |
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| 27 | |
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| 28 | #define DS26522_GTCR1_ADDR 0xf0 |
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| 29 | #define DS26522_GFCR_ADDR 0xf1 |
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| 30 | #define DS26522_GTCR2_ADDR 0xf2 |
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| 31 | #define DS26522_GTCCR_ADDR 0xf3 |
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| 32 | #define DS26522_GLSRR_ADDR 0xf5 |
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| 33 | #define DS26522_GFSRR_ADDR 0xf6 |
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| 34 | #define DS26522_IDR_ADDR 0xf8 |
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| 35 | |
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| 36 | #define DS26522_E1TAF_ADDR 0x164 |
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| 37 | #define DS26522_E1TNAF_ADDR 0x165 |
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| 38 | #define DS26522_TMMR_ADDR 0x180 |
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| 39 | #define DS26522_TCR1_ADDR 0x181 |
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| 40 | #define DS26522_TIOCR_ADDR 0x184 |
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| 41 | |
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| 42 | #define DS26522_LTRCR_ADDR 0x1000 |
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| 43 | #define DS26522_LTITSR_ADDR 0x1001 |
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| 44 | #define DS26522_LMCR_ADDR 0x1002 |
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| 45 | #define DS26522_LRISMR_ADDR 0x1007 |
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| 46 | |
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| 47 | #define MAX_NUM_OF_CHANNELS 8 |
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| 48 | #define PQ_MDS_8E1T1_BRD_REV 0x00 |
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| 49 | #define PQ_MDS_8E1T1_PLD_REV 0x00 |
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| 50 | |
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| 51 | #define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0 |
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| 52 | #define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08 |
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| 53 | #define DS26522_GTCCR_FREQSEL_1544KHZ 0x04 |
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| 54 | #define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00 |
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| 55 | #define DS26522_GTCCR_FREQSEL_2048KHZ 0x00 |
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| 56 | |
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| 57 | #define DS26522_GFCR_BPCLK_2048KHZ 0x00 |
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| 58 | |
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| 59 | #define DS26522_GTCR2_TSSYNCOUT 0x02 |
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| 60 | #define DS26522_GTCR1 0x00 |
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| 61 | |
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| 62 | #define DS26522_GFSRR_RESET 0x01 |
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| 63 | #define DS26522_GFSRR_NORMAL 0x00 |
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| 64 | |
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| 65 | #define DS26522_GLSRR_RESET 0x01 |
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| 66 | #define DS26522_GLSRR_NORMAL 0x00 |
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| 67 | |
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| 68 | #define DS26522_RMMR_SFTRST 0x02 |
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| 69 | #define DS26522_RMMR_FRM_EN 0x80 |
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| 70 | #define DS26522_RMMR_INIT_DONE 0x40 |
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| 71 | #define DS26522_RMMR_T1 0x00 |
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| 72 | #define DS26522_RMMR_E1 0x01 |
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| 73 | |
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| 74 | #define DS26522_E1TAF_DEFAULT 0x1b |
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| 75 | #define DS26522_E1TNAF_DEFAULT 0x40 |
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| 76 | |
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| 77 | #define DS26522_TMMR_SFTRST 0x02 |
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| 78 | #define DS26522_TMMR_FRM_EN 0x80 |
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| 79 | #define DS26522_TMMR_INIT_DONE 0x40 |
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| 80 | #define DS26522_TMMR_T1 0x00 |
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| 81 | #define DS26522_TMMR_E1 0x01 |
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| 82 | |
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| 83 | #define DS26522_RCR1_T1_SYNCT 0x80 |
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| 84 | #define DS26522_RCR1_T1_RB8ZS 0x40 |
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| 85 | #define DS26522_RCR1_T1_SYNCC 0x08 |
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| 86 | |
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| 87 | #define DS26522_RCR1_E1_HDB3 0x40 |
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| 88 | #define DS26522_RCR1_E1_CCS 0x20 |
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| 89 | |
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| 90 | #define DS26522_RIOCR_1544KHZ 0x00 |
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| 91 | #define DS26522_RIOCR_2048KHZ 0x10 |
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| 92 | #define DS26522_RIOCR_RSIO_OUT 0x00 |
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| 93 | |
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| 94 | #define DS26522_RCR3_FLB 0x01 |
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| 95 | |
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| 96 | #define DS26522_TIOCR_1544KHZ 0x00 |
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| 97 | #define DS26522_TIOCR_2048KHZ 0x10 |
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| 98 | #define DS26522_TIOCR_TSIO_OUT 0x04 |
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| 99 | |
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| 100 | #define DS26522_TCR1_TB8ZS 0x04 |
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| 101 | |
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| 102 | #define DS26522_LTRCR_T1 0x02 |
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| 103 | #define DS26522_LTRCR_E1 0x00 |
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| 104 | |
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| 105 | #define DS26522_LTITSR_TLIS_75OHM 0x00 |
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| 106 | #define DS26522_LTITSR_LBOS_75OHM 0x00 |
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| 107 | #define DS26522_LTITSR_TLIS_100OHM 0x10 |
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| 108 | #define DS26522_LTITSR_TLIS_0DB_CSU 0x00 |
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| 109 | |
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| 110 | #define DS26522_LRISMR_75OHM 0x00 |
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| 111 | #define DS26522_LRISMR_100OHM 0x10 |
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| 112 | #define DS26522_LRISMR_MAX 0x03 |
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| 113 | |
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| 114 | #define DS26522_LMCR_TE 0x01 |
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| 115 | |
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| 116 | enum line_rate { |
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| 117 | LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */ |
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| 118 | LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */ |
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| 119 | }; |
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| 120 | |
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| 121 | enum tdm_trans_mode { |
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| 122 | NORMAL = 0, |
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| 123 | FRAMER_LB |
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| 124 | }; |
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| 125 | |
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| 126 | enum card_support_type { |
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| 127 | LM_CARD = 0, |
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| 128 | DS26522_CARD, |
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| 129 | NO_CARD |
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| 130 | }; |
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| 131 | |
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