1 | /* |
2 | * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> |
3 | * Copyright (c) 2006 Sam Leffler, Errno Consulting |
4 | * Copyright (c) 2007 Christoph Hellwig <hch@lst.de> |
5 | * Copyright (c) 2008-2009 Weongyo Jeong <weongyo@freebsd.org> |
6 | * Copyright (c) 2012 Pontus Fuchs <pontus.fuchs@gmail.com> |
7 | * |
8 | * Permission to use, copy, modify, and/or distribute this software for any |
9 | * purpose with or without fee is hereby granted, provided that the above |
10 | * copyright notice and this permission notice appear in all copies. |
11 | * |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | */ |
20 | |
21 | /* all fields are big endian */ |
22 | struct ar5523_fwblock { |
23 | __be32 flags; |
24 | #define AR5523_WRITE_BLOCK (1 << 4) |
25 | |
26 | __be32 len; |
27 | #define AR5523_MAX_FWBLOCK_SIZE 2048 |
28 | |
29 | __be32 total; |
30 | __be32 remain; |
31 | __be32 rxtotal; |
32 | __be32 pad[123]; |
33 | } __packed; |
34 | |
35 | #define AR5523_MAX_RXCMDSZ 1024 |
36 | #define AR5523_MAX_TXCMDSZ 1024 |
37 | |
38 | struct ar5523_cmd_hdr { |
39 | __be32 len; |
40 | __be32 code; |
41 | /* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ |
42 | /* messages from Host -> Target */ |
43 | #define WDCMSG_HOST_AVAILABLE 0x01 |
44 | #define WDCMSG_BIND 0x02 |
45 | #define WDCMSG_TARGET_RESET 0x03 |
46 | #define WDCMSG_TARGET_GET_CAPABILITY 0x04 |
47 | #define WDCMSG_TARGET_SET_CONFIG 0x05 |
48 | #define WDCMSG_TARGET_GET_STATUS 0x06 |
49 | #define WDCMSG_TARGET_GET_STATS 0x07 |
50 | #define WDCMSG_TARGET_START 0x08 |
51 | #define WDCMSG_TARGET_STOP 0x09 |
52 | #define WDCMSG_TARGET_ENABLE 0x0a |
53 | #define WDCMSG_TARGET_DISABLE 0x0b |
54 | #define WDCMSG_CREATE_CONNECTION 0x0c |
55 | #define WDCMSG_UPDATE_CONNECT_ATTR 0x0d |
56 | #define WDCMSG_DELETE_CONNECT 0x0e |
57 | #define WDCMSG_SEND 0x0f |
58 | #define WDCMSG_FLUSH 0x10 |
59 | /* messages from Target -> Host */ |
60 | #define WDCMSG_STATS_UPDATE 0x11 |
61 | #define WDCMSG_BMISS 0x12 |
62 | #define WDCMSG_DEVICE_AVAIL 0x13 |
63 | #define WDCMSG_SEND_COMPLETE 0x14 |
64 | #define WDCMSG_DATA_AVAIL 0x15 |
65 | #define WDCMSG_SET_PWR_MODE 0x16 |
66 | #define WDCMSG_BMISS_ACK 0x17 |
67 | #define WDCMSG_SET_LED_STEADY 0x18 |
68 | #define WDCMSG_SET_LED_BLINK 0x19 |
69 | /* more messages */ |
70 | #define WDCMSG_SETUP_BEACON_DESC 0x1a |
71 | #define WDCMSG_BEACON_INIT 0x1b |
72 | #define WDCMSG_RESET_KEY_CACHE 0x1c |
73 | #define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d |
74 | #define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e |
75 | #define WDCMSG_SET_DECOMP_MASK 0x1f |
76 | #define WDCMSG_SET_REGULATORY_DOMAIN 0x20 |
77 | #define WDCMSG_SET_LED_STATE 0x21 |
78 | #define WDCMSG_WRITE_ASSOCID 0x22 |
79 | #define WDCMSG_SET_STA_BEACON_TIMERS 0x23 |
80 | #define WDCMSG_GET_TSF 0x24 |
81 | #define WDCMSG_RESET_TSF 0x25 |
82 | #define WDCMSG_SET_ADHOC_MODE 0x26 |
83 | #define WDCMSG_SET_BASIC_RATE 0x27 |
84 | #define WDCMSG_MIB_CONTROL 0x28 |
85 | #define WDCMSG_GET_CHANNEL_DATA 0x29 |
86 | #define 0x2a |
87 | #define WDCMSG_SET_ANTENNA_SWITCH 0x2b |
88 | #define WDCMSG_USE_SHORT_SLOT_TIME 0x2f |
89 | #define WDCMSG_SET_POWER_MODE 0x30 |
90 | #define WDCMSG_SETUP_PSPOLL_DESC 0x31 |
91 | #define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 |
92 | #define WDCMSG_RX_FILTER 0x33 |
93 | #define WDCMSG_PER_CALIBRATION 0x34 |
94 | #define WDCMSG_RESET 0x35 |
95 | #define WDCMSG_DISABLE 0x36 |
96 | #define WDCMSG_PHY_DISABLE 0x37 |
97 | #define WDCMSG_SET_TX_POWER_LIMIT 0x38 |
98 | #define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 |
99 | #define WDCMSG_SETUP_TX_QUEUE 0x3a |
100 | #define WDCMSG_RELEASE_TX_QUEUE 0x3b |
101 | #define WDCMSG_SET_DEFAULT_KEY 0x43 |
102 | |
103 | __u32 priv; /* driver private data, |
104 | don't care about endianess */ |
105 | __be32 magic; |
106 | __be32 reserved2[4]; |
107 | }; |
108 | |
109 | struct ar5523_cmd_host_available { |
110 | __be32 sw_ver_major; |
111 | __be32 sw_ver_minor; |
112 | __be32 sw_ver_patch; |
113 | __be32 sw_ver_build; |
114 | } __packed; |
115 | |
116 | #define ATH_SW_VER_MAJOR 1 |
117 | #define ATH_SW_VER_MINOR 5 |
118 | #define ATH_SW_VER_PATCH 0 |
119 | #define ATH_SW_VER_BUILD 9999 |
120 | |
121 | struct ar5523_chunk { |
122 | u8 seqnum; /* sequence number for ordering */ |
123 | u8 flags; |
124 | #define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ |
125 | #define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ |
126 | #define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ |
127 | __be16 length; /* chunk size in bytes */ |
128 | /* chunk data follows */ |
129 | } __packed; |
130 | |
131 | /* |
132 | * Message format for a WDCMSG_DATA_AVAIL message from Target to Host. |
133 | */ |
134 | struct ar5523_rx_desc { |
135 | __be32 len; /* msg length including header */ |
136 | __be32 code; /* WDCMSG_DATA_AVAIL */ |
137 | __be32 gennum; /* generation number */ |
138 | __be32 status; /* start of RECEIVE_INFO */ |
139 | #define UATH_STATUS_OK 0 |
140 | #define UATH_STATUS_STOP_IN_PROGRESS 1 |
141 | #define UATH_STATUS_CRC_ERR 2 |
142 | #define UATH_STATUS_PHY_ERR 3 |
143 | #define UATH_STATUS_DECRYPT_CRC_ERR 4 |
144 | #define UATH_STATUS_DECRYPT_MIC_ERR 5 |
145 | #define UATH_STATUS_DECOMP_ERR 6 |
146 | #define UATH_STATUS_KEY_ERR 7 |
147 | #define UATH_STATUS_ERR 8 |
148 | __be32 tstamp_low; /* low-order 32-bits of rx timestamp */ |
149 | __be32 tstamp_high; /* high-order 32-bits of rx timestamp */ |
150 | __be32 framelen; /* frame length */ |
151 | __be32 rate; /* rx rate code */ |
152 | __be32 antenna; |
153 | __be32 ; |
154 | __be32 channel; |
155 | __be32 phyerror; |
156 | __be32 connix; /* key table ix for bss traffic */ |
157 | __be32 decrypterror; |
158 | __be32 keycachemiss; |
159 | __be32 pad; /* XXX? */ |
160 | } __packed; |
161 | |
162 | struct ar5523_tx_desc { |
163 | __be32 msglen; |
164 | u32 msgid; /* msg id (supplied by host) */ |
165 | __be32 type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ |
166 | __be32 txqid; /* tx queue id and flags */ |
167 | #define UATH_TXQID_MASK 0x0f |
168 | #define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ |
169 | #define UATH_TXQID_FF 0x20 /* content is fast frame */ |
170 | __be32 connid; /* tx connection id */ |
171 | #define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ |
172 | __be32 flags; /* non-zero if response desired */ |
173 | #define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ |
174 | __be32 buflen; /* payload length */ |
175 | } __packed; |
176 | |
177 | |
178 | #define AR5523_ID_BSS 2 |
179 | #define AR5523_ID_BROADCAST 0xffffffff |
180 | |
181 | /* structure for command UATH_CMD_WRITE_MAC */ |
182 | struct ar5523_write_mac { |
183 | __be32 reg; |
184 | __be32 len; |
185 | u8 data[32]; |
186 | } __packed; |
187 | |
188 | struct ar5523_cmd_rateset { |
189 | __u8 length; |
190 | #define AR5523_MAX_NRATES 32 |
191 | __u8 set[AR5523_MAX_NRATES]; |
192 | }; |
193 | |
194 | struct ar5523_cmd_set_associd { /* AR5523_WRITE_ASSOCID */ |
195 | __be32 defaultrateix; |
196 | __be32 associd; |
197 | __be32 timoffset; |
198 | __be32 turboprime; |
199 | __u8 bssid[6]; |
200 | } __packed; |
201 | |
202 | /* structure for command WDCMSG_RESET */ |
203 | struct ar5523_cmd_reset { |
204 | __be32 flags; /* channel flags */ |
205 | #define UATH_CHAN_TURBO 0x0100 |
206 | #define UATH_CHAN_CCK 0x0200 |
207 | #define UATH_CHAN_OFDM 0x0400 |
208 | #define UATH_CHAN_2GHZ 0x1000 |
209 | #define UATH_CHAN_5GHZ 0x2000 |
210 | __be32 freq; /* channel frequency */ |
211 | __be32 maxrdpower; |
212 | __be32 cfgctl; |
213 | __be32 twiceantennareduction; |
214 | __be32 channelchange; |
215 | __be32 keeprccontent; |
216 | } __packed; |
217 | |
218 | /* structure for command WDCMSG_SET_BASIC_RATE */ |
219 | struct ar5523_cmd_rates { |
220 | __be32 connid; |
221 | __be32 keeprccontent; |
222 | __be32 size; |
223 | struct ar5523_cmd_rateset rateset; |
224 | } __packed; |
225 | |
226 | enum { |
227 | WLAN_MODE_NONE = 0, |
228 | WLAN_MODE_11b, |
229 | WLAN_MODE_11a, |
230 | WLAN_MODE_11g, |
231 | WLAN_MODE_11a_TURBO, |
232 | WLAN_MODE_11g_TURBO, |
233 | WLAN_MODE_11a_TURBO_PRIME, |
234 | WLAN_MODE_11g_TURBO_PRIME, |
235 | WLAN_MODE_11a_XR, |
236 | WLAN_MODE_11g_XR, |
237 | }; |
238 | |
239 | struct ar5523_cmd_connection_attr { |
240 | __be32 longpreambleonly; |
241 | struct ar5523_cmd_rateset rateset; |
242 | __be32 wlanmode; |
243 | } __packed; |
244 | |
245 | /* structure for command AR5523_CREATE_CONNECTION */ |
246 | struct ar5523_cmd_create_connection { |
247 | __be32 connid; |
248 | __be32 bssid; |
249 | __be32 size; |
250 | struct ar5523_cmd_connection_attr connattr; |
251 | } __packed; |
252 | |
253 | struct ar5523_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ |
254 | __be32 lednum; |
255 | #define UATH_LED_LINK 0 |
256 | #define UATH_LED_ACTIVITY 1 |
257 | __be32 ledmode; |
258 | #define UATH_LED_OFF 0 |
259 | #define UATH_LED_ON 1 |
260 | } __packed; |
261 | |
262 | struct ar5523_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ |
263 | __be32 lednum; |
264 | __be32 ledmode; |
265 | __be32 blinkrate; |
266 | __be32 slowmode; |
267 | } __packed; |
268 | |
269 | struct ar5523_cmd_ledstate { /* WDCMSG_SET_LED_STATE */ |
270 | __be32 connected; |
271 | } __packed; |
272 | |
273 | struct ar5523_cmd_txq_attr { |
274 | __be32 priority; |
275 | __be32 aifs; |
276 | __be32 logcwmin; |
277 | __be32 logcwmax; |
278 | __be32 bursttime; |
279 | __be32 mode; |
280 | __be32 qflags; |
281 | } __packed; |
282 | |
283 | struct ar5523_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ |
284 | __be32 qid; |
285 | __be32 len; |
286 | struct ar5523_cmd_txq_attr attr; |
287 | } __packed; |
288 | |
289 | struct ar5523_cmd_rx_filter { /* WDCMSG_RX_FILTER */ |
290 | __be32 bits; |
291 | #define UATH_FILTER_RX_UCAST 0x00000001 |
292 | #define UATH_FILTER_RX_MCAST 0x00000002 |
293 | #define UATH_FILTER_RX_BCAST 0x00000004 |
294 | #define UATH_FILTER_RX_CONTROL 0x00000008 |
295 | #define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ |
296 | #define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ |
297 | #define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ |
298 | #define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ |
299 | #define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ |
300 | #define UATH_FILTER_RX_PROBE_REQ 0x00000800 |
301 | __be32 op; |
302 | #define UATH_FILTER_OP_INIT 0x0 |
303 | #define UATH_FILTER_OP_SET 0x1 |
304 | #define UATH_FILTER_OP_CLEAR 0x2 |
305 | #define UATH_FILTER_OP_TEMP 0x3 |
306 | #define UATH_FILTER_OP_RESTORE 0x4 |
307 | } __packed; |
308 | |
309 | enum { |
310 | CFG_NONE, /* Sentinal to indicate "no config" */ |
311 | CFG_REG_DOMAIN, /* Regulatory Domain */ |
312 | CFG_RATE_CONTROL_ENABLE, |
313 | CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ |
314 | CFG_HW_TX_RETRIES, |
315 | CFG_SW_TX_RETRIES, |
316 | CFG_SLOW_CLOCK_ENABLE, |
317 | CFG_COMP_PROC, |
318 | CFG_USER_RTS_THRESHOLD, |
319 | CFG_XR2NORM_RATE_THRESHOLD, |
320 | CFG_XRMODE_SWITCH_COUNT, |
321 | CFG_PROTECTION_TYPE, |
322 | CFG_BURST_SEQ_THRESHOLD, |
323 | CFG_ABOLT, |
324 | CFG_IQ_LOG_COUNT_MAX, |
325 | CFG_MODE_CTS, |
326 | CFG_WME_ENABLED, |
327 | CFG_GPRS_CBR_PERIOD, |
328 | CFG_SERVICE_TYPE, |
329 | /* MAC Address to use. Overrides EEPROM */ |
330 | CFG_MAC_ADDR, |
331 | CFG_DEBUG_EAR, |
332 | CFG_INIT_REGS, |
333 | /* An ID for use in error & debug messages */ |
334 | CFG_DEBUG_ID, |
335 | CFG_COMP_WIN_SZ, |
336 | CFG_DIVERSITY_CTL, |
337 | CFG_TP_SCALE, |
338 | CFG_TPC_HALF_DBM5, |
339 | CFG_TPC_HALF_DBM2, |
340 | CFG_OVERRD_TX_POWER, |
341 | CFG_USE_32KHZ_CLOCK, |
342 | CFG_GMODE_PROTECTION, |
343 | CFG_GMODE_PROTECT_RATE_INDEX, |
344 | CFG_GMODE_NON_ERP_PREAMBLE, |
345 | CFG_WDC_TRANSPORT_CHUNK_SIZE, |
346 | }; |
347 | |
348 | enum { |
349 | /* Sentinal to indicate "no capability" */ |
350 | CAP_NONE, |
351 | CAP_ALL, /* ALL capabilities */ |
352 | CAP_TARGET_VERSION, |
353 | CAP_TARGET_REVISION, |
354 | CAP_MAC_VERSION, |
355 | CAP_MAC_REVISION, |
356 | CAP_PHY_REVISION, |
357 | CAP_ANALOG_5GHz_REVISION, |
358 | CAP_ANALOG_2GHz_REVISION, |
359 | /* Target supports WDC message debug features */ |
360 | CAP_DEBUG_WDCMSG_SUPPORT, |
361 | |
362 | CAP_REG_DOMAIN, |
363 | CAP_COUNTRY_CODE, |
364 | CAP_REG_CAP_BITS, |
365 | |
366 | CAP_WIRELESS_MODES, |
367 | CAP_CHAN_SPREAD_SUPPORT, |
368 | CAP_SLEEP_AFTER_BEACON_BROKEN, |
369 | CAP_COMPRESS_SUPPORT, |
370 | CAP_BURST_SUPPORT, |
371 | CAP_FAST_FRAMES_SUPPORT, |
372 | CAP_CHAP_TUNING_SUPPORT, |
373 | CAP_TURBOG_SUPPORT, |
374 | CAP_TURBO_PRIME_SUPPORT, |
375 | CAP_DEVICE_TYPE, |
376 | CAP_XR_SUPPORT, |
377 | CAP_WME_SUPPORT, |
378 | CAP_TOTAL_QUEUES, |
379 | CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ |
380 | |
381 | CAP_LOW_5GHZ_CHAN, |
382 | CAP_HIGH_5GHZ_CHAN, |
383 | CAP_LOW_2GHZ_CHAN, |
384 | CAP_HIGH_2GHZ_CHAN, |
385 | |
386 | CAP_MIC_AES_CCM, |
387 | CAP_MIC_CKIP, |
388 | CAP_MIC_TKIP, |
389 | CAP_MIC_TKIP_WME, |
390 | CAP_CIPHER_AES_CCM, |
391 | CAP_CIPHER_CKIP, |
392 | CAP_CIPHER_TKIP, |
393 | |
394 | CAP_TWICE_ANTENNAGAIN_5G, |
395 | CAP_TWICE_ANTENNAGAIN_2G, |
396 | }; |
397 | |
398 | enum { |
399 | ST_NONE, /* Sentinal to indicate "no status" */ |
400 | ST_ALL, |
401 | ST_SERVICE_TYPE, |
402 | ST_WLAN_MODE, |
403 | ST_FREQ, |
404 | ST_BAND, |
405 | , |
406 | ST_PS_FRAMES_DROPPED, |
407 | ST_CACHED_DEF_ANT, |
408 | ST_COUNT_OTHER_RX_ANT, |
409 | ST_USE_FAST_DIVERSITY, |
410 | ST_MAC_ADDR, |
411 | ST_RX_GENERATION_NUM, |
412 | ST_TX_QUEUE_DEPTH, |
413 | ST_SERIAL_NUMBER, |
414 | ST_WDC_TRANSPORT_CHUNK_SIZE, |
415 | }; |
416 | |
417 | enum { |
418 | TARGET_DEVICE_AWAKE, |
419 | TARGET_DEVICE_SLEEP, |
420 | TARGET_DEVICE_PWRDN, |
421 | TARGET_DEVICE_PWRSAVE, |
422 | TARGET_DEVICE_SUSPEND, |
423 | TARGET_DEVICE_RESUME, |
424 | }; |
425 | |
426 | /* this is in net/ieee80211.h, but that conflicts with the mac80211 headers */ |
427 | #define IEEE80211_2ADDR_LEN 16 |
428 | |
429 | #define AR5523_MIN_RXBUFSZ \ |
430 | (((sizeof(__be32) + IEEE80211_2ADDR_LEN + \ |
431 | sizeof(struct ar5523_rx_desc)) + 3) & ~3) |
432 | |