1 | /* SPDX-License-Identifier: BSD-3-Clause-Clear */ |
2 | /* |
3 | * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. |
5 | */ |
6 | |
7 | #ifndef ATH11K_HAL_RX_H |
8 | #define ATH11K_HAL_RX_H |
9 | |
10 | struct hal_rx_wbm_rel_info { |
11 | u32 cookie; |
12 | enum hal_wbm_rel_src_module err_rel_src; |
13 | enum hal_reo_dest_ring_push_reason push_reason; |
14 | u32 err_code; |
15 | bool first_msdu; |
16 | bool last_msdu; |
17 | }; |
18 | |
19 | #define HAL_INVALID_PEERID 0xffff |
20 | #define VHT_SIG_SU_NSS_MASK 0x7 |
21 | |
22 | #define HAL_RX_MAX_MCS 12 |
23 | #define HAL_RX_MAX_NSS 8 |
24 | |
25 | struct hal_rx_mon_status_tlv_hdr { |
26 | u32 hdr; |
27 | u8 value[]; |
28 | }; |
29 | |
30 | enum hal_rx_su_mu_coding { |
31 | HAL_RX_SU_MU_CODING_BCC, |
32 | HAL_RX_SU_MU_CODING_LDPC, |
33 | HAL_RX_SU_MU_CODING_MAX, |
34 | }; |
35 | |
36 | enum hal_rx_gi { |
37 | HAL_RX_GI_0_8_US, |
38 | HAL_RX_GI_0_4_US, |
39 | HAL_RX_GI_1_6_US, |
40 | HAL_RX_GI_3_2_US, |
41 | HAL_RX_GI_MAX, |
42 | }; |
43 | |
44 | enum hal_rx_bw { |
45 | HAL_RX_BW_20MHZ, |
46 | HAL_RX_BW_40MHZ, |
47 | HAL_RX_BW_80MHZ, |
48 | HAL_RX_BW_160MHZ, |
49 | HAL_RX_BW_MAX, |
50 | }; |
51 | |
52 | enum hal_rx_preamble { |
53 | HAL_RX_PREAMBLE_11A, |
54 | HAL_RX_PREAMBLE_11B, |
55 | HAL_RX_PREAMBLE_11N, |
56 | HAL_RX_PREAMBLE_11AC, |
57 | HAL_RX_PREAMBLE_11AX, |
58 | HAL_RX_PREAMBLE_MAX, |
59 | }; |
60 | |
61 | enum hal_rx_reception_type { |
62 | HAL_RX_RECEPTION_TYPE_SU, |
63 | HAL_RX_RECEPTION_TYPE_MU_MIMO, |
64 | HAL_RX_RECEPTION_TYPE_MU_OFDMA, |
65 | HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO, |
66 | HAL_RX_RECEPTION_TYPE_MAX, |
67 | }; |
68 | |
69 | #define HAL_RX_FCS_LEN 4 |
70 | |
71 | enum hal_rx_mon_status { |
72 | HAL_RX_MON_STATUS_PPDU_NOT_DONE, |
73 | HAL_RX_MON_STATUS_PPDU_DONE, |
74 | HAL_RX_MON_STATUS_BUF_DONE, |
75 | }; |
76 | |
77 | struct hal_rx_user_status { |
78 | u32 mcs:4, |
79 | nss:3, |
80 | ofdma_info_valid:1, |
81 | dl_ofdma_ru_start_index:7, |
82 | dl_ofdma_ru_width:7, |
83 | dl_ofdma_ru_size:8; |
84 | u32 ul_ofdma_user_v0_word0; |
85 | u32 ul_ofdma_user_v0_word1; |
86 | u32 ast_index; |
87 | u32 tid; |
88 | u16 tcp_msdu_count; |
89 | u16 udp_msdu_count; |
90 | u16 other_msdu_count; |
91 | u16 frame_control; |
92 | u8 frame_control_info_valid; |
93 | u8 data_sequence_control_info_valid; |
94 | u16 first_data_seq_ctrl; |
95 | u32 preamble_type; |
96 | u16 ht_flags; |
97 | u16 vht_flags; |
98 | u16 he_flags; |
99 | u8 rs_flags; |
100 | u32 mpdu_cnt_fcs_ok; |
101 | u32 mpdu_cnt_fcs_err; |
102 | u32 mpdu_fcs_ok_bitmap[8]; |
103 | u32 mpdu_ok_byte_count; |
104 | u32 mpdu_err_byte_count; |
105 | }; |
106 | |
107 | #define HAL_TLV_STATUS_PPDU_NOT_DONE HAL_RX_MON_STATUS_PPDU_NOT_DONE |
108 | #define HAL_TLV_STATUS_PPDU_DONE HAL_RX_MON_STATUS_PPDU_DONE |
109 | #define HAL_TLV_STATUS_BUF_DONE HAL_RX_MON_STATUS_BUF_DONE |
110 | |
111 | struct hal_sw_mon_ring_entries { |
112 | dma_addr_t mon_dst_paddr; |
113 | dma_addr_t mon_status_paddr; |
114 | u32 mon_dst_sw_cookie; |
115 | u32 mon_status_sw_cookie; |
116 | void *dst_buf_addr_info; |
117 | void *status_buf_addr_info; |
118 | u16 ppdu_id; |
119 | u8 status_buf_count; |
120 | u8 msdu_cnt; |
121 | bool end_of_ppdu; |
122 | bool drop_ppdu; |
123 | }; |
124 | |
125 | struct hal_rx_mon_ppdu_info { |
126 | u32 ppdu_id; |
127 | u32 ppdu_ts; |
128 | u32 num_mpdu_fcs_ok; |
129 | u32 num_mpdu_fcs_err; |
130 | u32 preamble_type; |
131 | u16 chan_num; |
132 | u16 tcp_msdu_count; |
133 | u16 tcp_ack_msdu_count; |
134 | u16 udp_msdu_count; |
135 | u16 other_msdu_count; |
136 | u16 peer_id; |
137 | u8 rate; |
138 | u8 mcs; |
139 | u8 nss; |
140 | u8 bw; |
141 | u8 vht_flag_values1; |
142 | u8 vht_flag_values2; |
143 | u8 vht_flag_values3[4]; |
144 | u8 vht_flag_values4; |
145 | u8 vht_flag_values5; |
146 | u16 vht_flag_values6; |
147 | u8 is_stbc; |
148 | u8 gi; |
149 | u8 ldpc; |
150 | u8 beamformed; |
151 | u8 ; |
152 | u8 [HAL_RX_MAX_NSS]; |
153 | u16 tid; |
154 | u16 ht_flags; |
155 | u16 vht_flags; |
156 | u16 he_flags; |
157 | u16 he_mu_flags; |
158 | u8 dcm; |
159 | u8 ru_alloc; |
160 | u8 reception_type; |
161 | u64 tsft; |
162 | u64 rx_duration; |
163 | u16 frame_control; |
164 | u32 ast_index; |
165 | u8 rs_fcs_err; |
166 | u8 rs_flags; |
167 | u8 cck_flag; |
168 | u8 ofdm_flag; |
169 | u8 ulofdma_flag; |
170 | u8 frame_control_info_valid; |
171 | u16 he_per_user_1; |
172 | u16 he_per_user_2; |
173 | u8 he_per_user_position; |
174 | u8 he_per_user_known; |
175 | u16 he_flags1; |
176 | u16 he_flags2; |
177 | u8 he_RU[4]; |
178 | u16 he_data1; |
179 | u16 he_data2; |
180 | u16 he_data3; |
181 | u16 he_data4; |
182 | u16 he_data5; |
183 | u16 he_data6; |
184 | u32 ppdu_len; |
185 | u32 prev_ppdu_id; |
186 | u32 device_id; |
187 | u16 first_data_seq_ctrl; |
188 | u8 monitor_direct_used; |
189 | u8 data_sequence_control_info_valid; |
190 | u8 ltf_size; |
191 | u8 rxpcu_filter_pass; |
192 | char [8][8]; |
193 | struct hal_rx_user_status userstats; |
194 | }; |
195 | |
196 | #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0) |
197 | |
198 | struct hal_rx_ppdu_start { |
199 | __le32 info0; |
200 | __le32 chan_num; |
201 | __le32 ppdu_start_ts; |
202 | } __packed; |
203 | |
204 | #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16) |
205 | |
206 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0) |
207 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9) |
208 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10) |
209 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11) |
210 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20) |
211 | |
212 | #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0) |
213 | #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16) |
214 | |
215 | #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16) |
216 | |
217 | #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0) |
218 | #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16) |
219 | |
220 | #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0) |
221 | #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16) |
222 | |
223 | #define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_BITMAP GENMASK(15, 0) |
224 | #define HAL_RX_PPDU_END_USER_STATS_INFO7_TID_EOSP_BITMAP GENMASK(31, 16) |
225 | |
226 | #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_OK_BYTE_COUNT GENMASK(24, 0) |
227 | #define HAL_RX_PPDU_END_USER_STATS_INFO9_MPDU_ERR_BYTE_COUNT GENMASK(24, 0) |
228 | |
229 | struct hal_rx_ppdu_end_user_stats { |
230 | __le32 rsvd0[2]; |
231 | __le32 info0; |
232 | __le32 info1; |
233 | __le32 info2; |
234 | __le32 info3; |
235 | __le32 ht_ctrl; |
236 | __le32 rsvd1[2]; |
237 | __le32 info4; |
238 | __le32 info5; |
239 | __le32 info6; |
240 | __le32 info7; |
241 | __le32 rsvd2[4]; |
242 | __le32 info8; |
243 | __le32 rsvd3; |
244 | __le32 info9; |
245 | __le32 rsvd4[2]; |
246 | __le32 info10; |
247 | } __packed; |
248 | |
249 | struct hal_rx_ppdu_end_user_stats_ext { |
250 | u32 info0; |
251 | u32 info1; |
252 | u32 info2; |
253 | u32 info3; |
254 | u32 info4; |
255 | u32 info5; |
256 | u32 info6; |
257 | } __packed; |
258 | |
259 | #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0) |
260 | #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7) |
261 | |
262 | #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4) |
263 | #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6) |
264 | #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7) |
265 | |
266 | struct hal_rx_ht_sig_info { |
267 | __le32 info0; |
268 | __le32 info1; |
269 | } __packed; |
270 | |
271 | #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0) |
272 | #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4) |
273 | |
274 | struct hal_rx_lsig_b_info { |
275 | __le32 info0; |
276 | } __packed; |
277 | |
278 | #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0) |
279 | #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5) |
280 | #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24) |
281 | |
282 | struct hal_rx_lsig_a_info { |
283 | __le32 info0; |
284 | } __packed; |
285 | |
286 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0) |
287 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3) |
288 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4) |
289 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10) |
290 | |
291 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0) |
292 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2) |
293 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4) |
294 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8) |
295 | |
296 | struct hal_rx_vht_sig_a_info { |
297 | __le32 info0; |
298 | __le32 info1; |
299 | } __packed; |
300 | |
301 | enum hal_rx_vht_sig_a_gi_setting { |
302 | HAL_RX_VHT_SIG_A_NORMAL_GI = 0, |
303 | HAL_RX_VHT_SIG_A_SHORT_GI = 1, |
304 | HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3, |
305 | }; |
306 | |
307 | #define HAL_RX_SU_MU_CODING_LDPC 0x01 |
308 | |
309 | #define HE_GI_0_8 0 |
310 | #define HE_GI_0_4 1 |
311 | #define HE_GI_1_6 2 |
312 | #define HE_GI_3_2 3 |
313 | |
314 | #define HE_LTF_1_X 0 |
315 | #define HE_LTF_2_X 1 |
316 | #define HE_LTF_4_X 2 |
317 | #define HE_LTF_UNKNOWN 3 |
318 | |
319 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3) |
320 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7) |
321 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19) |
322 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21) |
323 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23) |
324 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8) |
325 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15) |
326 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0) |
327 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1) |
328 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2) |
329 | |
330 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0) |
331 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7) |
332 | #define BIT(8) |
333 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9) |
334 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10) |
335 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11) |
336 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13) |
337 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15) |
338 | |
339 | struct hal_rx_he_sig_a_su_info { |
340 | __le32 info0; |
341 | __le32 info1; |
342 | } __packed; |
343 | |
344 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG BIT(1) |
345 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB GENMASK(3, 1) |
346 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB BIT(4) |
347 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR GENMASK(10, 5) |
348 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE GENMASK(14, 11) |
349 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW GENMASK(17, 15) |
350 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB GENMASK(21, 18) |
351 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB BIT(22) |
352 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE GENMASK(24, 23) |
353 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION BIT(25) |
354 | |
355 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION GENMASK(6, 0) |
356 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_CODING BIT(7) |
357 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB GENMASK(10, 8) |
358 | #define BIT(11) |
359 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC BIT(12) |
360 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXBF BIT(10) |
361 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR GENMASK(14, 13) |
362 | #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM BIT(15) |
363 | |
364 | struct hal_rx_he_sig_a_mu_dl_info { |
365 | __le32 info0; |
366 | __le32 info1; |
367 | } __packed; |
368 | |
369 | #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0) |
370 | |
371 | struct hal_rx_he_sig_b1_mu_info { |
372 | __le32 info0; |
373 | } __packed; |
374 | |
375 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0) |
376 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15) |
377 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20) |
378 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29) |
379 | |
380 | struct hal_rx_he_sig_b2_mu_info { |
381 | __le32 info0; |
382 | } __packed; |
383 | |
384 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0) |
385 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11) |
386 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19) |
387 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15) |
388 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19) |
389 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20) |
390 | |
391 | struct hal_rx_he_sig_b2_ofdma_info { |
392 | __le32 info0; |
393 | } __packed; |
394 | |
395 | #define GENMASK(15, 8) |
396 | |
397 | #define GENMASK(7, 0) |
398 | |
399 | struct { |
400 | __le32 ; |
401 | __le32 ; |
402 | } __packed; |
403 | |
404 | struct { |
405 | __le32 [3]; |
406 | struct hal_rx_phyrx_chain_rssi [HAL_RX_MAX_NSS]; |
407 | struct hal_rx_phyrx_chain_rssi [HAL_RX_MAX_NSS]; |
408 | __le32 ; |
409 | } __packed; |
410 | |
411 | #define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16) |
412 | #define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0) |
413 | #define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN GENMASK(13, 0) |
414 | |
415 | struct hal_rx_mpdu_info_ipq8074 { |
416 | __le32 rsvd0; |
417 | __le32 info0; |
418 | __le32 rsvd1[11]; |
419 | __le32 info1; |
420 | __le32 rsvd2[9]; |
421 | } __packed; |
422 | |
423 | struct hal_rx_mpdu_info_qcn9074 { |
424 | __le32 rsvd0[10]; |
425 | __le32 info0; |
426 | __le32 rsvd1[2]; |
427 | __le32 info1; |
428 | __le32 rsvd2[9]; |
429 | } __packed; |
430 | |
431 | struct hal_rx_mpdu_info_wcn6855 { |
432 | __le32 rsvd0[8]; |
433 | __le32 info0; |
434 | __le32 rsvd1[14]; |
435 | } __packed; |
436 | |
437 | struct hal_rx_mpdu_info { |
438 | union { |
439 | struct hal_rx_mpdu_info_ipq8074 ipq8074; |
440 | struct hal_rx_mpdu_info_qcn9074 qcn9074; |
441 | struct hal_rx_mpdu_info_wcn6855 wcn6855; |
442 | } u; |
443 | } __packed; |
444 | |
445 | #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0) |
446 | struct hal_rx_ppdu_end_duration { |
447 | __le32 rsvd0[9]; |
448 | __le32 info0; |
449 | __le32 rsvd1[4]; |
450 | } __packed; |
451 | |
452 | struct hal_rx_rxpcu_classification_overview { |
453 | u32 rsvd0; |
454 | } __packed; |
455 | |
456 | struct hal_rx_msdu_desc_info { |
457 | u32 msdu_flags; |
458 | u16 msdu_len; /* 14 bits for length */ |
459 | }; |
460 | |
461 | #define HAL_RX_NUM_MSDU_DESC 6 |
462 | struct hal_rx_msdu_list { |
463 | struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; |
464 | u32 sw_cookie[HAL_RX_NUM_MSDU_DESC]; |
465 | u8 rbm[HAL_RX_NUM_MSDU_DESC]; |
466 | }; |
467 | |
468 | void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc, |
469 | struct hal_reo_status *status); |
470 | void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc, |
471 | struct hal_reo_status *status); |
472 | void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, |
473 | struct hal_reo_status *status); |
474 | void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, |
475 | struct hal_reo_status *status); |
476 | void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc, |
477 | struct hal_reo_status *status); |
478 | void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab, |
479 | u32 *reo_desc, |
480 | struct hal_reo_status *status); |
481 | void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab, |
482 | u32 *reo_desc, |
483 | struct hal_reo_status *status); |
484 | void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab, |
485 | u32 *reo_desc, |
486 | struct hal_reo_status *status); |
487 | int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status); |
488 | void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus, |
489 | u32 *msdu_cookies, |
490 | enum hal_rx_buf_return_buf_manager *rbm); |
491 | void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc, |
492 | void *link_desc, |
493 | enum hal_wbm_rel_bm_act action); |
494 | void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr, |
495 | u32 cookie, u8 manager); |
496 | void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr, |
497 | u32 *cookie, u8 *rbm); |
498 | int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc, |
499 | dma_addr_t *paddr, u32 *desc_bank); |
500 | int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc, |
501 | struct hal_rx_wbm_rel_info *rel_info); |
502 | void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc, |
503 | dma_addr_t *paddr, u32 *desc_bank); |
504 | void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, |
505 | dma_addr_t *paddr, u32 *sw_cookie, |
506 | void **pp_buf_addr_info, u8 *rbm, |
507 | u32 *msdu_cnt); |
508 | void |
509 | ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc, |
510 | struct hal_sw_mon_ring_entries *sw_mon_ent); |
511 | enum hal_rx_mon_status |
512 | ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab, |
513 | struct hal_rx_mon_ppdu_info *ppdu_info, |
514 | struct sk_buff *skb); |
515 | |
516 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF |
517 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF |
518 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF |
519 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF |
520 | #endif |
521 | |