1 | /* SPDX-License-Identifier: BSD-3-Clause-Clear */ |
2 | /* |
3 | * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. |
5 | */ |
6 | |
7 | #ifndef ATH12K_HAL_RX_H |
8 | #define ATH12K_HAL_RX_H |
9 | |
10 | struct hal_rx_wbm_rel_info { |
11 | u32 cookie; |
12 | enum hal_wbm_rel_src_module err_rel_src; |
13 | enum hal_reo_dest_ring_push_reason push_reason; |
14 | u32 err_code; |
15 | bool first_msdu; |
16 | bool last_msdu; |
17 | bool continuation; |
18 | void *rx_desc; |
19 | bool hw_cc_done; |
20 | }; |
21 | |
22 | #define HAL_INVALID_PEERID 0xffff |
23 | #define VHT_SIG_SU_NSS_MASK 0x7 |
24 | |
25 | #define HAL_RX_MAX_MCS 12 |
26 | #define HAL_RX_MAX_NSS 8 |
27 | |
28 | #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \ |
29 | le32_get_bits((__val), GENMASK(7, 0)) |
30 | |
31 | #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \ |
32 | le32_get_bits((__val), GENMASK(15, 8)) |
33 | |
34 | #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \ |
35 | le32_get_bits((__val), GENMASK(23, 16)) |
36 | |
37 | #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \ |
38 | le32_get_bits((__val), GENMASK(31, 24)) |
39 | |
40 | struct hal_rx_mon_status_tlv_hdr { |
41 | u32 hdr; |
42 | u8 value[]; |
43 | }; |
44 | |
45 | enum hal_rx_su_mu_coding { |
46 | HAL_RX_SU_MU_CODING_BCC, |
47 | HAL_RX_SU_MU_CODING_LDPC, |
48 | HAL_RX_SU_MU_CODING_MAX, |
49 | }; |
50 | |
51 | enum hal_rx_gi { |
52 | HAL_RX_GI_0_8_US, |
53 | HAL_RX_GI_0_4_US, |
54 | HAL_RX_GI_1_6_US, |
55 | HAL_RX_GI_3_2_US, |
56 | HAL_RX_GI_MAX, |
57 | }; |
58 | |
59 | enum hal_rx_bw { |
60 | HAL_RX_BW_20MHZ, |
61 | HAL_RX_BW_40MHZ, |
62 | HAL_RX_BW_80MHZ, |
63 | HAL_RX_BW_160MHZ, |
64 | HAL_RX_BW_320MHZ, |
65 | HAL_RX_BW_MAX, |
66 | }; |
67 | |
68 | enum hal_rx_preamble { |
69 | HAL_RX_PREAMBLE_11A, |
70 | HAL_RX_PREAMBLE_11B, |
71 | HAL_RX_PREAMBLE_11N, |
72 | HAL_RX_PREAMBLE_11AC, |
73 | HAL_RX_PREAMBLE_11AX, |
74 | HAL_RX_PREAMBLE_MAX, |
75 | }; |
76 | |
77 | enum hal_rx_reception_type { |
78 | HAL_RX_RECEPTION_TYPE_SU, |
79 | HAL_RX_RECEPTION_TYPE_MU_MIMO, |
80 | HAL_RX_RECEPTION_TYPE_MU_OFDMA, |
81 | HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO, |
82 | HAL_RX_RECEPTION_TYPE_MAX, |
83 | }; |
84 | |
85 | enum hal_rx_legacy_rate { |
86 | HAL_RX_LEGACY_RATE_1_MBPS, |
87 | HAL_RX_LEGACY_RATE_2_MBPS, |
88 | HAL_RX_LEGACY_RATE_5_5_MBPS, |
89 | HAL_RX_LEGACY_RATE_6_MBPS, |
90 | HAL_RX_LEGACY_RATE_9_MBPS, |
91 | HAL_RX_LEGACY_RATE_11_MBPS, |
92 | HAL_RX_LEGACY_RATE_12_MBPS, |
93 | HAL_RX_LEGACY_RATE_18_MBPS, |
94 | HAL_RX_LEGACY_RATE_24_MBPS, |
95 | HAL_RX_LEGACY_RATE_36_MBPS, |
96 | HAL_RX_LEGACY_RATE_48_MBPS, |
97 | HAL_RX_LEGACY_RATE_54_MBPS, |
98 | HAL_RX_LEGACY_RATE_INVALID, |
99 | }; |
100 | |
101 | #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 |
102 | #define HAL_TLV_STATUS_PPDU_DONE 1 |
103 | #define HAL_TLV_STATUS_BUF_DONE 2 |
104 | #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 |
105 | #define HAL_RX_FCS_LEN 4 |
106 | |
107 | enum hal_rx_mon_status { |
108 | HAL_RX_MON_STATUS_PPDU_NOT_DONE, |
109 | HAL_RX_MON_STATUS_PPDU_DONE, |
110 | HAL_RX_MON_STATUS_BUF_DONE, |
111 | }; |
112 | |
113 | #define HAL_RX_MAX_MPDU 256 |
114 | #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) |
115 | |
116 | struct hal_rx_user_status { |
117 | u32 mcs:4, |
118 | nss:3, |
119 | ofdma_info_valid:1, |
120 | ul_ofdma_ru_start_index:7, |
121 | ul_ofdma_ru_width:7, |
122 | ul_ofdma_ru_size:8; |
123 | u32 ul_ofdma_user_v0_word0; |
124 | u32 ul_ofdma_user_v0_word1; |
125 | u32 ast_index; |
126 | u32 tid; |
127 | u16 tcp_msdu_count; |
128 | u16 tcp_ack_msdu_count; |
129 | u16 udp_msdu_count; |
130 | u16 other_msdu_count; |
131 | u16 frame_control; |
132 | u8 frame_control_info_valid; |
133 | u8 data_sequence_control_info_valid; |
134 | u16 first_data_seq_ctrl; |
135 | u32 preamble_type; |
136 | u16 ht_flags; |
137 | u16 vht_flags; |
138 | u16 he_flags; |
139 | u8 rs_flags; |
140 | u8 ldpc; |
141 | u32 mpdu_cnt_fcs_ok; |
142 | u32 mpdu_cnt_fcs_err; |
143 | u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; |
144 | u32 mpdu_ok_byte_count; |
145 | u32 mpdu_err_byte_count; |
146 | }; |
147 | |
148 | #define HAL_MAX_UL_MU_USERS 37 |
149 | |
150 | struct hal_rx_mon_ppdu_info { |
151 | u32 ppdu_id; |
152 | u32 last_ppdu_id; |
153 | u64 ppdu_ts; |
154 | u32 num_mpdu_fcs_ok; |
155 | u32 num_mpdu_fcs_err; |
156 | u32 preamble_type; |
157 | u32 mpdu_len; |
158 | u16 chan_num; |
159 | u16 tcp_msdu_count; |
160 | u16 tcp_ack_msdu_count; |
161 | u16 udp_msdu_count; |
162 | u16 other_msdu_count; |
163 | u16 peer_id; |
164 | u8 rate; |
165 | u8 mcs; |
166 | u8 nss; |
167 | u8 bw; |
168 | u8 vht_flag_values1; |
169 | u8 vht_flag_values2; |
170 | u8 vht_flag_values3[4]; |
171 | u8 vht_flag_values4; |
172 | u8 vht_flag_values5; |
173 | u16 vht_flag_values6; |
174 | u8 is_stbc; |
175 | u8 gi; |
176 | u8 sgi; |
177 | u8 ldpc; |
178 | u8 beamformed; |
179 | u8 ; |
180 | u16 tid; |
181 | u8 fc_valid; |
182 | u16 ht_flags; |
183 | u16 vht_flags; |
184 | u16 he_flags; |
185 | u16 he_mu_flags; |
186 | u8 dcm; |
187 | u8 ru_alloc; |
188 | u8 reception_type; |
189 | u64 tsft; |
190 | u64 rx_duration; |
191 | u16 frame_control; |
192 | u32 ast_index; |
193 | u8 rs_fcs_err; |
194 | u8 rs_flags; |
195 | u8 cck_flag; |
196 | u8 ofdm_flag; |
197 | u8 ulofdma_flag; |
198 | u8 frame_control_info_valid; |
199 | u16 he_per_user_1; |
200 | u16 he_per_user_2; |
201 | u8 he_per_user_position; |
202 | u8 he_per_user_known; |
203 | u16 he_flags1; |
204 | u16 he_flags2; |
205 | u8 he_RU[4]; |
206 | u16 he_data1; |
207 | u16 he_data2; |
208 | u16 he_data3; |
209 | u16 he_data4; |
210 | u16 he_data5; |
211 | u16 he_data6; |
212 | u32 ppdu_len; |
213 | u32 prev_ppdu_id; |
214 | u32 device_id; |
215 | u16 first_data_seq_ctrl; |
216 | u8 monitor_direct_used; |
217 | u8 data_sequence_control_info_valid; |
218 | u8 ltf_size; |
219 | u8 rxpcu_filter_pass; |
220 | s8 [8][8]; |
221 | u32 num_users; |
222 | u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; |
223 | u8 addr1[ETH_ALEN]; |
224 | u8 addr2[ETH_ALEN]; |
225 | u8 addr3[ETH_ALEN]; |
226 | u8 addr4[ETH_ALEN]; |
227 | struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS]; |
228 | u8 userid; |
229 | u16 ampdu_id[HAL_MAX_UL_MU_USERS]; |
230 | bool first_msdu_in_mpdu; |
231 | bool is_ampdu; |
232 | u8 medium_prot_type; |
233 | }; |
234 | |
235 | #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0) |
236 | |
237 | struct hal_rx_ppdu_start { |
238 | __le32 info0; |
239 | __le32 chan_num; |
240 | __le32 ppdu_start_ts; |
241 | } __packed; |
242 | |
243 | #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16) |
244 | |
245 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0) |
246 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9) |
247 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10) |
248 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11) |
249 | #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20) |
250 | |
251 | #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0) |
252 | #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16) |
253 | |
254 | #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16) |
255 | |
256 | #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0) |
257 | #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16) |
258 | |
259 | #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0) |
260 | #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16) |
261 | |
262 | #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0) |
263 | #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16) |
264 | |
265 | #define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT GENMASK(24, 0) |
266 | #define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT GENMASK(24, 0) |
267 | |
268 | struct hal_rx_ppdu_end_user_stats { |
269 | __le32 rsvd0[2]; |
270 | __le32 info0; |
271 | __le32 info1; |
272 | __le32 info2; |
273 | __le32 info3; |
274 | __le32 ht_ctrl; |
275 | __le32 rsvd1[2]; |
276 | __le32 info4; |
277 | __le32 info5; |
278 | __le32 usr_resp_ref; |
279 | __le32 info6; |
280 | __le32 rsvd3[4]; |
281 | __le32 mpdu_ok_cnt; |
282 | __le32 rsvd4; |
283 | __le32 mpdu_err_cnt; |
284 | __le32 rsvd5[2]; |
285 | __le32 usr_resp_ref_ext; |
286 | __le32 rsvd6; |
287 | } __packed; |
288 | |
289 | struct hal_rx_ppdu_end_user_stats_ext { |
290 | __le32 info0; |
291 | __le32 info1; |
292 | __le32 info2; |
293 | __le32 info3; |
294 | __le32 info4; |
295 | __le32 info5; |
296 | __le32 info6; |
297 | } __packed; |
298 | |
299 | #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0) |
300 | #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7) |
301 | |
302 | #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4) |
303 | #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6) |
304 | #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7) |
305 | |
306 | struct hal_rx_ht_sig_info { |
307 | __le32 info0; |
308 | __le32 info1; |
309 | } __packed; |
310 | |
311 | #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0) |
312 | #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4) |
313 | |
314 | struct hal_rx_lsig_b_info { |
315 | __le32 info0; |
316 | } __packed; |
317 | |
318 | #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0) |
319 | #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5) |
320 | #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24) |
321 | |
322 | struct hal_rx_lsig_a_info { |
323 | __le32 info0; |
324 | } __packed; |
325 | |
326 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0) |
327 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3) |
328 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4) |
329 | #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10) |
330 | |
331 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0) |
332 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2) |
333 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4) |
334 | #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8) |
335 | |
336 | struct hal_rx_vht_sig_a_info { |
337 | __le32 info0; |
338 | __le32 info1; |
339 | } __packed; |
340 | |
341 | enum hal_rx_vht_sig_a_gi_setting { |
342 | HAL_RX_VHT_SIG_A_NORMAL_GI = 0, |
343 | HAL_RX_VHT_SIG_A_SHORT_GI = 1, |
344 | HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3, |
345 | }; |
346 | |
347 | #define HE_GI_0_8 0 |
348 | #define HE_GI_0_4 1 |
349 | #define HE_GI_1_6 2 |
350 | #define HE_GI_3_2 3 |
351 | |
352 | #define HE_LTF_1_X 0 |
353 | #define HE_LTF_2_X 1 |
354 | #define HE_LTF_4_X 2 |
355 | |
356 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3) |
357 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7) |
358 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19) |
359 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21) |
360 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23) |
361 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8) |
362 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15) |
363 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0) |
364 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1) |
365 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2) |
366 | |
367 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0) |
368 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7) |
369 | #define BIT(8) |
370 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9) |
371 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10) |
372 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11) |
373 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13) |
374 | #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15) |
375 | |
376 | struct hal_rx_he_sig_a_su_info { |
377 | __le32 info0; |
378 | __le32 info1; |
379 | } __packed; |
380 | |
381 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1) |
382 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1) |
383 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4) |
384 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5) |
385 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11) |
386 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15) |
387 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18) |
388 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22) |
389 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23) |
390 | #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25) |
391 | |
392 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0) |
393 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING BIT(7) |
394 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8) |
395 | #define BIT(11) |
396 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12) |
397 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF BIT(10) |
398 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13) |
399 | #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15) |
400 | |
401 | struct hal_rx_he_sig_a_mu_dl_info { |
402 | __le32 info0; |
403 | __le32 info1; |
404 | } __packed; |
405 | |
406 | #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0) |
407 | |
408 | struct hal_rx_he_sig_b1_mu_info { |
409 | __le32 info0; |
410 | } __packed; |
411 | |
412 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0) |
413 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15) |
414 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20) |
415 | #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29) |
416 | |
417 | struct hal_rx_he_sig_b2_mu_info { |
418 | __le32 info0; |
419 | } __packed; |
420 | |
421 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0) |
422 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11) |
423 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19) |
424 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15) |
425 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19) |
426 | #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20) |
427 | |
428 | struct hal_rx_he_sig_b2_ofdma_info { |
429 | __le32 info0; |
430 | } __packed; |
431 | |
432 | enum hal_rx_ul_reception_type { |
433 | HAL_RECEPTION_TYPE_ULOFMDA, |
434 | HAL_RECEPTION_TYPE_ULMIMO, |
435 | HAL_RECEPTION_TYPE_OTHER, |
436 | HAL_RECEPTION_TYPE_FRAMELESS |
437 | }; |
438 | |
439 | #define GENMASK(15, 8) |
440 | #define GENMASK(3, 0) |
441 | |
442 | struct { |
443 | __le32 [35]; |
444 | __le32 ; |
445 | } __packed; |
446 | |
447 | #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) |
448 | #define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(31, 16) |
449 | #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0) |
450 | struct hal_rx_mpdu_start { |
451 | __le32 info0; |
452 | __le32 info1; |
453 | __le32 rsvd1[11]; |
454 | __le32 info2; |
455 | __le32 rsvd2[9]; |
456 | } __packed; |
457 | |
458 | #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0) |
459 | struct hal_rx_ppdu_end_duration { |
460 | __le32 rsvd0[9]; |
461 | __le32 info0; |
462 | __le32 rsvd1[4]; |
463 | } __packed; |
464 | |
465 | struct hal_rx_rxpcu_classification_overview { |
466 | u32 rsvd0; |
467 | } __packed; |
468 | |
469 | struct hal_rx_msdu_desc_info { |
470 | u32 msdu_flags; |
471 | u16 msdu_len; /* 14 bits for length */ |
472 | }; |
473 | |
474 | #define HAL_RX_NUM_MSDU_DESC 6 |
475 | struct hal_rx_msdu_list { |
476 | struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; |
477 | u32 sw_cookie[HAL_RX_NUM_MSDU_DESC]; |
478 | u8 rbm[HAL_RX_NUM_MSDU_DESC]; |
479 | }; |
480 | |
481 | #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0) |
482 | #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0) |
483 | #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16) |
484 | #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0) |
485 | |
486 | struct hal_rx_frame_bitmap_ack { |
487 | __le32 reserved; |
488 | __le32 info0; |
489 | __le32 info1; |
490 | __le32 info2; |
491 | __le32 reserved1[10]; |
492 | } __packed; |
493 | |
494 | #define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0) |
495 | #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16) |
496 | #define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0) |
497 | #define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21) |
498 | #define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25) |
499 | #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27) |
500 | #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28) |
501 | #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29) |
502 | #define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0) |
503 | #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0) |
504 | #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0) |
505 | #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16) |
506 | #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0) |
507 | |
508 | struct hal_rx_resp_req_info { |
509 | __le32 info0; |
510 | __le32 reserved[1]; |
511 | __le32 info1; |
512 | __le32 info2; |
513 | __le32 reserved1[2]; |
514 | __le32 info3; |
515 | __le32 info4; |
516 | __le32 info5; |
517 | __le32 reserved2[5]; |
518 | } __packed; |
519 | |
520 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF |
521 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF |
522 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF |
523 | #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF |
524 | |
525 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30) |
526 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31) |
527 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0) |
528 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3) |
529 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7) |
530 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8) |
531 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9) |
532 | #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16) |
533 | |
534 | /* HE Radiotap data1 Mask */ |
535 | #define HE_SU_FORMAT_TYPE 0x0000 |
536 | #define HE_EXT_SU_FORMAT_TYPE 0x0001 |
537 | #define HE_MU_FORMAT_TYPE 0x0002 |
538 | #define HE_TRIG_FORMAT_TYPE 0x0003 |
539 | #define HE_BEAM_CHANGE_KNOWN 0x0008 |
540 | #define HE_DL_UL_KNOWN 0x0010 |
541 | #define HE_MCS_KNOWN 0x0020 |
542 | #define HE_DCM_KNOWN 0x0040 |
543 | #define HE_CODING_KNOWN 0x0080 |
544 | #define 0x0100 |
545 | #define HE_STBC_KNOWN 0x0200 |
546 | #define HE_DATA_BW_RU_KNOWN 0x4000 |
547 | #define HE_DOPPLER_KNOWN 0x8000 |
548 | #define HE_BSS_COLOR_KNOWN 0x0004 |
549 | |
550 | /* HE Radiotap data2 Mask */ |
551 | #define HE_GI_KNOWN 0x0002 |
552 | #define HE_TXBF_KNOWN 0x0010 |
553 | #define HE_PE_DISAMBIGUITY_KNOWN 0x0020 |
554 | #define HE_TXOP_KNOWN 0x0040 |
555 | #define HE_LTF_SYMBOLS_KNOWN 0x0004 |
556 | #define HE_PRE_FEC_PADDING_KNOWN 0x0008 |
557 | #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080 |
558 | |
559 | /* HE radiotap data3 shift values */ |
560 | #define HE_BEAM_CHANGE_SHIFT 6 |
561 | #define HE_DL_UL_SHIFT 7 |
562 | #define HE_TRANSMIT_MCS_SHIFT 8 |
563 | #define HE_DCM_SHIFT 12 |
564 | #define HE_CODING_SHIFT 13 |
565 | #define 14 |
566 | #define HE_STBC_SHIFT 15 |
567 | |
568 | /* HE radiotap data4 shift values */ |
569 | #define HE_STA_ID_SHIFT 4 |
570 | |
571 | /* HE radiotap data5 */ |
572 | #define HE_GI_SHIFT 4 |
573 | #define HE_LTF_SIZE_SHIFT 6 |
574 | #define HE_LTF_SYM_SHIFT 8 |
575 | #define HE_TXBF_SHIFT 14 |
576 | #define HE_PE_DISAMBIGUITY_SHIFT 15 |
577 | #define HE_PRE_FEC_PAD_SHIFT 12 |
578 | |
579 | /* HE radiotap data6 */ |
580 | #define HE_DOPPLER_SHIFT 4 |
581 | #define HE_TXOP_SHIFT 8 |
582 | |
583 | /* HE radiotap HE-MU flags1 */ |
584 | #define HE_SIG_B_MCS_KNOWN 0x0010 |
585 | #define HE_SIG_B_DCM_KNOWN 0x0040 |
586 | #define HE_SIG_B_SYM_NUM_KNOWN 0x8000 |
587 | #define HE_RU_0_KNOWN 0x0100 |
588 | #define HE_RU_1_KNOWN 0x0200 |
589 | #define HE_RU_2_KNOWN 0x0400 |
590 | #define HE_RU_3_KNOWN 0x0800 |
591 | #define HE_DCM_FLAG_1_SHIFT 5 |
592 | #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100 |
593 | #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000 |
594 | |
595 | /* HE radiotap HE-MU flags2 */ |
596 | #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3 |
597 | #define HE_BW_KNOWN 0x0004 |
598 | #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4 |
599 | #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100 |
600 | #define HE_NUM_SIG_B_FLAG_2_SHIFT 9 |
601 | #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12 |
602 | #define HE_LTF_KNOWN 0x8000 |
603 | |
604 | /* HE radiotap per_user_1 */ |
605 | #define HE_STA_SPATIAL_SHIFT 11 |
606 | #define HE_TXBF_SHIFT 14 |
607 | #define HE_RESERVED_SET_TO_1_SHIFT 19 |
608 | #define HE_STA_CODING_SHIFT 20 |
609 | |
610 | /* HE radiotap per_user_2 */ |
611 | #define HE_STA_MCS_SHIFT 4 |
612 | #define HE_STA_DCM_SHIFT 5 |
613 | |
614 | /* HE radiotap per user known */ |
615 | #define HE_USER_FIELD_POSITION_KNOWN 0x01 |
616 | #define HE_STA_ID_PER_USER_KNOWN 0x02 |
617 | #define HE_STA_NSTS_KNOWN 0x04 |
618 | #define HE_STA_TX_BF_KNOWN 0x08 |
619 | #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10 |
620 | #define HE_STA_MCS_KNOWN 0x20 |
621 | #define HE_STA_DCM_KNOWN 0x40 |
622 | #define HE_STA_CODING_KNOWN 0x80 |
623 | |
624 | #define HAL_RX_MPDU_ERR_FCS BIT(0) |
625 | #define HAL_RX_MPDU_ERR_DECRYPT BIT(1) |
626 | #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2) |
627 | #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3) |
628 | #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4) |
629 | #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5) |
630 | #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6) |
631 | #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) |
632 | |
633 | static inline |
634 | enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) |
635 | { |
636 | enum nl80211_he_ru_alloc ret; |
637 | |
638 | switch (ru_tones) { |
639 | case RU_52: |
640 | ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; |
641 | break; |
642 | case RU_106: |
643 | ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; |
644 | break; |
645 | case RU_242: |
646 | ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; |
647 | break; |
648 | case RU_484: |
649 | ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; |
650 | break; |
651 | case RU_996: |
652 | ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; |
653 | break; |
654 | case RU_26: |
655 | fallthrough; |
656 | default: |
657 | ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; |
658 | break; |
659 | } |
660 | return ret; |
661 | } |
662 | |
663 | void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, |
664 | struct hal_tlv_64_hdr *tlv, |
665 | struct hal_reo_status *status); |
666 | void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, |
667 | struct hal_tlv_64_hdr *tlv, |
668 | struct hal_reo_status *status); |
669 | void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, |
670 | struct hal_tlv_64_hdr *tlv, |
671 | struct hal_reo_status *status); |
672 | void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, |
673 | struct hal_tlv_64_hdr *tlv, |
674 | struct hal_reo_status *status); |
675 | void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, |
676 | struct hal_tlv_64_hdr *tlv, |
677 | struct hal_reo_status *status); |
678 | void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, |
679 | struct hal_tlv_64_hdr *tlv, |
680 | struct hal_reo_status *status); |
681 | void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, |
682 | struct hal_tlv_64_hdr *tlv, |
683 | struct hal_reo_status *status); |
684 | void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus, |
685 | u32 *msdu_cookies, |
686 | enum hal_rx_buf_return_buf_manager *rbm); |
687 | void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, |
688 | struct hal_wbm_release_ring *dst_desc, |
689 | struct hal_wbm_release_ring *src_desc, |
690 | enum hal_wbm_rel_bm_act action); |
691 | void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, |
692 | dma_addr_t paddr, u32 cookie, u8 manager); |
693 | void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, |
694 | dma_addr_t *paddr, |
695 | u32 *cookie, u8 *rbm); |
696 | int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab, |
697 | struct hal_reo_dest_ring *desc, |
698 | dma_addr_t *paddr, u32 *desc_bank); |
699 | int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc, |
700 | struct hal_rx_wbm_rel_info *rel_info); |
701 | void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab, |
702 | struct ath12k_buffer_addr *buff_addr, |
703 | dma_addr_t *paddr, u32 *cookie); |
704 | |
705 | #endif |
706 | |