1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6#ifndef ATH12K_PCI_H
7#define ATH12K_PCI_H
8
9#include <linux/mhi.h>
10
11#include "core.h"
12
13#define PCIE_SOC_GLOBAL_RESET 0x3008
14#define PCIE_SOC_GLOBAL_RESET_V 1
15
16#define WLAON_WARM_SW_ENTRY 0x1f80504
17#define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
18
19#define PCIE_Q6_COOKIE_ADDR 0x01f80500
20#define PCIE_Q6_COOKIE_DATA 0xc0000000
21
22/* register to wake the UMAC from power collapse */
23#define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
24
25/* register used for handshake mechanism to validate UMAC is awake */
26#define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
27
28#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
29#define PARM_LTSSM_VALUE 0x111
30
31#define GCC_GCC_PCIE_HOT_RST 0x1e38338
32#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
33
34#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
35#define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2
36#define PCIE_INT_CLEAR_ALL 0xffffffff
37
38#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab) \
39 ((ab)->hw_params->regs->pcie_qserdes_sysclk_en_sel)
40#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10
41#define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff
42#define PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab) \
43 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base)
44#define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02
45#define PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab) \
46 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0x4)
47#define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52
48#define PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab) \
49 ((ab)->hw_params->regs->pcie_pcs_osc_dtct_config_base + 0xc)
50#define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff
51#define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff
52
53#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
54#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
55
56#define QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB 0x1E20338
57#define OTP_BOARD_ID_MASK GENMASK(15, 0)
58
59#define PCI_BAR_WINDOW0_BASE 0x1E00000
60#define PCI_BAR_WINDOW0_END 0x1E7FFFC
61#define PCI_SOC_RANGE_MASK 0x3FFF
62#define PCI_SOC_PCI_REG_BASE 0x1E04000
63#define PCI_SOC_PCI_REG_END 0x1E07FFC
64#define PCI_PARF_BASE 0x1E08000
65#define PCI_PARF_END 0x1E0BFFC
66#define PCI_MHIREGLEN_REG 0x1E0E100
67#define PCI_MHI_REGION_END 0x1E0EFFC
68#define QRTR_PCI_DOMAIN_NR_MASK GENMASK(7, 4)
69#define QRTR_PCI_BUS_NUMBER_MASK GENMASK(3, 0)
70
71#define ATH12K_PCI_SOC_HW_VERSION_1 1
72#define ATH12K_PCI_SOC_HW_VERSION_2 2
73
74struct ath12k_msi_user {
75 const char *name;
76 int num_vectors;
77 u32 base_vector;
78};
79
80struct ath12k_msi_config {
81 int total_vectors;
82 int total_users;
83 const struct ath12k_msi_user *users;
84};
85
86enum ath12k_pci_flags {
87 ATH12K_PCI_FLAG_INIT_DONE,
88 ATH12K_PCI_FLAG_IS_MSI_64,
89 ATH12K_PCI_ASPM_RESTORE,
90 ATH12K_PCI_FLAG_MULTI_MSI_VECTORS,
91};
92
93struct ath12k_pci_ops {
94 int (*wakeup)(struct ath12k_base *ab);
95 void (*release)(struct ath12k_base *ab);
96};
97
98struct ath12k_pci {
99 struct pci_dev *pdev;
100 struct ath12k_base *ab;
101 u16 dev_id;
102 char amss_path[100];
103 u32 msi_ep_base_data;
104 struct mhi_controller *mhi_ctrl;
105 const struct ath12k_msi_config *msi_config;
106 unsigned long mhi_state;
107 u32 register_window;
108
109 /* protects register_window above */
110 spinlock_t window_lock;
111
112 /* enum ath12k_pci_flags */
113 unsigned long flags;
114 u16 link_ctl;
115 unsigned long irq_flags;
116 const struct ath12k_pci_ops *pci_ops;
117 u32 qmi_instance;
118};
119
120static inline struct ath12k_pci *ath12k_pci_priv(struct ath12k_base *ab)
121{
122 return (struct ath12k_pci *)ab->drv_priv;
123}
124
125int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
126 int *num_vectors, u32 *user_base_data,
127 u32 *base_vector);
128int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector);
129void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value);
130u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset);
131int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
132 u8 *ul_pipe, u8 *dl_pipe);
133void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
134 u32 *msi_addr_hi);
135void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
136 u32 *msi_idx);
137void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab);
138void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab);
139void ath12k_pci_ext_irq_enable(struct ath12k_base *ab);
140void ath12k_pci_ext_irq_disable(struct ath12k_base *ab);
141int ath12k_pci_hif_suspend(struct ath12k_base *ab);
142int ath12k_pci_hif_resume(struct ath12k_base *ab);
143void ath12k_pci_stop(struct ath12k_base *ab);
144int ath12k_pci_start(struct ath12k_base *ab);
145int ath12k_pci_power_up(struct ath12k_base *ab);
146void ath12k_pci_power_down(struct ath12k_base *ab);
147#endif /* ATH12K_PCI_H */
148

source code of linux/drivers/net/wireless/ath/ath12k/pci.h