1 | /* |
2 | * Copyright (c) 2010-2011 Atheros Communications Inc. |
3 | * Copyright (c) 2011-2012 Qualcomm Atheros Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | */ |
17 | |
18 | #ifndef INITVALS_9565_1P1_H |
19 | #define INITVALS_9565_1P1_H |
20 | |
21 | /* AR9565 1.1 */ |
22 | |
23 | #define ar9565_1p1_mac_core ar9565_1p0_mac_core |
24 | |
25 | #define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble |
26 | |
27 | #define ar9565_1p1_baseband_core ar9565_1p0_baseband_core |
28 | |
29 | #define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble |
30 | |
31 | #define ar9565_1p1_radio_core ar9565_1p0_radio_core |
32 | |
33 | #define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble |
34 | |
35 | #define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble |
36 | |
37 | #define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table |
38 | |
39 | #define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table |
40 | |
41 | #define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1 |
42 | |
43 | #define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock |
44 | |
45 | #define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table |
46 | |
47 | #define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table |
48 | |
49 | #define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table |
50 | |
51 | #define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table |
52 | |
53 | #define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484 |
54 | |
55 | static const u32 ar9565_1p1_radio_postamble[][5] = { |
56 | /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
57 | {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, |
58 | {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, |
59 | {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, |
60 | {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000}, |
61 | {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, |
62 | }; |
63 | |
64 | #endif /* INITVALS_9565_1P1_H */ |
65 | |