| 1 | /* |
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| 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
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| 3 | * |
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| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
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| 5 | * purpose with or without fee is hereby granted, provided that the above |
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| 6 | * copyright notice and this permission notice appear in all copies. |
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| 7 | * |
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| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef PHY_H |
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| 18 | #define PHY_H |
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| 19 | |
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| 20 | #define CHANSEL_DIV 15 |
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| 21 | #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) |
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| 22 | #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) |
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| 23 | |
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| 24 | #define AR_PHY_BASE 0x9800 |
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| 25 | #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) |
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| 26 | |
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| 27 | #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 |
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| 28 | #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 |
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| 29 | #define AR_PHY_TX_GAIN_CLC 0x0000001E |
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| 30 | #define AR_PHY_TX_GAIN_CLC_S 1 |
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| 31 | #define AR_PHY_TX_GAIN 0x0007F000 |
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| 32 | #define AR_PHY_TX_GAIN_S 12 |
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| 33 | |
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| 34 | #define AR_PHY_CLC_TBL1 0xa35c |
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| 35 | #define AR_PHY_CLC_I0 0x07ff0000 |
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| 36 | #define AR_PHY_CLC_I0_S 16 |
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| 37 | #define AR_PHY_CLC_Q0 0x0000ffd0 |
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| 38 | #define AR_PHY_CLC_Q0_S 5 |
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| 39 | |
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| 40 | #define ANTSWAP_AB 0x0001 |
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| 41 | #define REDUCE_CHAIN_0 0x00000050 |
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| 42 | #define REDUCE_CHAIN_1 0x00000051 |
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| 43 | #define AR_PHY_CHIP_ID 0x9818 |
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| 44 | |
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| 45 | #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 |
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| 46 | #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 |
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| 47 | |
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| 48 | #define AR_PHY_PLL_CONTROL 0x16180 |
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| 49 | #define AR_PHY_PLL_MODE 0x16184 |
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| 50 | |
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| 51 | enum ath9k_ant_div_comb_lna_conf { |
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| 52 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, |
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| 53 | ATH_ANT_DIV_COMB_LNA2, |
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| 54 | ATH_ANT_DIV_COMB_LNA1, |
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| 55 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, |
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| 56 | }; |
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| 57 | |
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| 58 | #endif |
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| 59 | |
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