1 | /* |
2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any |
5 | * purpose with or without fee is hereby granted, provided that the above |
6 | * copyright notice and this permission notice appear in all copies. |
7 | * |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
15 | */ |
16 | |
17 | #ifndef REG_H |
18 | #define REG_H |
19 | |
20 | #include "../reg.h" |
21 | |
22 | #define AR_CR 0x0008 |
23 | #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004) |
24 | #define AR_CR_RXD 0x00000020 |
25 | #define AR_CR_SWI 0x00000040 |
26 | |
27 | #define AR_RXDP 0x000C |
28 | |
29 | #define AR_CFG 0x0014 |
30 | #define AR_CFG_SWTD 0x00000001 |
31 | #define AR_CFG_SWTB 0x00000002 |
32 | #define AR_CFG_SWRD 0x00000004 |
33 | #define AR_CFG_SWRB 0x00000008 |
34 | #define AR_CFG_SWRG 0x00000010 |
35 | #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 |
36 | #define AR_CFG_PHOK 0x00000100 |
37 | #define AR_CFG_EEBS 0x00000200 |
38 | #define AR_CFG_CLK_GATE_DIS 0x00000400 |
39 | #define AR_CFG_HALT_REQ 0x00000800 |
40 | #define AR_CFG_HALT_ACK 0x00001000 |
41 | #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 |
42 | #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 |
43 | |
44 | #define AR_RXBP_THRESH 0x0018 |
45 | #define AR_RXBP_THRESH_HP 0x0000000f |
46 | #define AR_RXBP_THRESH_HP_S 0 |
47 | #define AR_RXBP_THRESH_LP 0x00003f00 |
48 | #define AR_RXBP_THRESH_LP_S 8 |
49 | |
50 | #define AR_MIRT 0x0020 |
51 | #define AR_MIRT_VAL 0x0000ffff |
52 | #define AR_MIRT_VAL_S 16 |
53 | |
54 | #define AR_IER 0x0024 |
55 | #define AR_IER_ENABLE 0x00000001 |
56 | #define AR_IER_DISABLE 0x00000000 |
57 | |
58 | #define AR_TIMT 0x0028 |
59 | #define AR_TIMT_LAST 0x0000ffff |
60 | #define AR_TIMT_LAST_S 0 |
61 | #define AR_TIMT_FIRST 0xffff0000 |
62 | #define AR_TIMT_FIRST_S 16 |
63 | |
64 | #define AR_RIMT 0x002C |
65 | #define AR_RIMT_LAST 0x0000ffff |
66 | #define AR_RIMT_LAST_S 0 |
67 | #define AR_RIMT_FIRST 0xffff0000 |
68 | #define AR_RIMT_FIRST_S 16 |
69 | |
70 | #define AR_DMASIZE_4B 0x00000000 |
71 | #define AR_DMASIZE_8B 0x00000001 |
72 | #define AR_DMASIZE_16B 0x00000002 |
73 | #define AR_DMASIZE_32B 0x00000003 |
74 | #define AR_DMASIZE_64B 0x00000004 |
75 | #define AR_DMASIZE_128B 0x00000005 |
76 | #define AR_DMASIZE_256B 0x00000006 |
77 | #define AR_DMASIZE_512B 0x00000007 |
78 | |
79 | #define AR_TXCFG 0x0030 |
80 | #define AR_TXCFG_DMASZ_MASK 0x00000007 |
81 | #define AR_TXCFG_DMASZ_4B 0 |
82 | #define AR_TXCFG_DMASZ_8B 1 |
83 | #define AR_TXCFG_DMASZ_16B 2 |
84 | #define AR_TXCFG_DMASZ_32B 3 |
85 | #define AR_TXCFG_DMASZ_64B 4 |
86 | #define AR_TXCFG_DMASZ_128B 5 |
87 | #define AR_TXCFG_DMASZ_256B 6 |
88 | #define AR_TXCFG_DMASZ_512B 7 |
89 | #define AR_FTRIG 0x000003F0 |
90 | #define AR_FTRIG_S 4 |
91 | #define AR_FTRIG_IMMED 0x00000000 |
92 | #define AR_FTRIG_64B 0x00000010 |
93 | #define AR_FTRIG_128B 0x00000020 |
94 | #define AR_FTRIG_192B 0x00000030 |
95 | #define AR_FTRIG_256B 0x00000040 |
96 | #define AR_FTRIG_512B 0x00000080 |
97 | #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 |
98 | |
99 | #define AR_RXCFG 0x0034 |
100 | #define AR_RXCFG_CHIRP 0x00000008 |
101 | #define AR_RXCFG_ZLFDMA 0x00000010 |
102 | #define AR_RXCFG_DMASZ_MASK 0x00000007 |
103 | #define AR_RXCFG_DMASZ_4B 0 |
104 | #define AR_RXCFG_DMASZ_8B 1 |
105 | #define AR_RXCFG_DMASZ_16B 2 |
106 | #define AR_RXCFG_DMASZ_32B 3 |
107 | #define AR_RXCFG_DMASZ_64B 4 |
108 | #define AR_RXCFG_DMASZ_128B 5 |
109 | #define AR_RXCFG_DMASZ_256B 6 |
110 | #define AR_RXCFG_DMASZ_512B 7 |
111 | |
112 | #define AR_TOPS 0x0044 |
113 | #define AR_TOPS_MASK 0x0000FFFF |
114 | |
115 | #define AR_RXNPTO 0x0048 |
116 | #define AR_RXNPTO_MASK 0x000003FF |
117 | |
118 | #define AR_TXNPTO 0x004C |
119 | #define AR_TXNPTO_MASK 0x000003FF |
120 | #define AR_TXNPTO_QCU_MASK 0x000FFC00 |
121 | |
122 | #define AR_RPGTO 0x0050 |
123 | #define AR_RPGTO_MASK 0x000003FF |
124 | |
125 | #define AR_RPCNT 0x0054 |
126 | #define AR_RPCNT_MASK 0x0000001F |
127 | |
128 | #define AR_MACMISC 0x0058 |
129 | #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 |
130 | #define AR_MACMISC_DMA_OBS 0x000001E0 |
131 | #define AR_MACMISC_DMA_OBS_S 5 |
132 | #define AR_MACMISC_DMA_OBS_LINE_0 0 |
133 | #define AR_MACMISC_DMA_OBS_LINE_1 1 |
134 | #define AR_MACMISC_DMA_OBS_LINE_2 2 |
135 | #define AR_MACMISC_DMA_OBS_LINE_3 3 |
136 | #define AR_MACMISC_DMA_OBS_LINE_4 4 |
137 | #define AR_MACMISC_DMA_OBS_LINE_5 5 |
138 | #define AR_MACMISC_DMA_OBS_LINE_6 6 |
139 | #define AR_MACMISC_DMA_OBS_LINE_7 7 |
140 | #define AR_MACMISC_DMA_OBS_LINE_8 8 |
141 | #define AR_MACMISC_MISC_OBS 0x00000E00 |
142 | #define AR_MACMISC_MISC_OBS_S 9 |
143 | #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 |
144 | #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 |
145 | #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 |
146 | #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 |
147 | #define AR_MACMISC_MISC_OBS_BUS_1 1 |
148 | |
149 | #define AR_INTCFG 0x005C |
150 | #define AR_INTCFG_MSI_RXOK 0x00000000 |
151 | #define AR_INTCFG_MSI_RXINTM 0x00000004 |
152 | #define AR_INTCFG_MSI_RXMINTR 0x00000006 |
153 | #define AR_INTCFG_MSI_TXOK 0x00000000 |
154 | #define AR_INTCFG_MSI_TXINTM 0x00000010 |
155 | #define AR_INTCFG_MSI_TXMINTR 0x00000018 |
156 | |
157 | #define AR_DATABUF_SIZE 0x0060 |
158 | #define AR_DATABUF_SIZE_MASK 0x00000FFF |
159 | |
160 | #define AR_GTXTO 0x0064 |
161 | #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF |
162 | #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 |
163 | #define AR_GTXTO_TIMEOUT_LIMIT_S 16 |
164 | |
165 | #define AR_GTTM 0x0068 |
166 | #define AR_GTTM_USEC 0x00000001 |
167 | #define AR_GTTM_IGNORE_IDLE 0x00000002 |
168 | #define AR_GTTM_RESET_IDLE 0x00000004 |
169 | #define AR_GTTM_CST_USEC 0x00000008 |
170 | |
171 | #define AR_CST 0x006C |
172 | #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF |
173 | #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 |
174 | #define AR_CST_TIMEOUT_LIMIT_S 16 |
175 | |
176 | #define AR_HP_RXDP 0x0074 |
177 | #define AR_LP_RXDP 0x0078 |
178 | |
179 | #define AR_ISR 0x0080 |
180 | #define AR_ISR_RXOK 0x00000001 |
181 | #define AR_ISR_RXDESC 0x00000002 |
182 | #define AR_ISR_HP_RXOK 0x00000001 |
183 | #define AR_ISR_LP_RXOK 0x00000002 |
184 | #define AR_ISR_RXERR 0x00000004 |
185 | #define AR_ISR_RXNOPKT 0x00000008 |
186 | #define AR_ISR_RXEOL 0x00000010 |
187 | #define AR_ISR_RXORN 0x00000020 |
188 | #define AR_ISR_TXOK 0x00000040 |
189 | #define AR_ISR_TXDESC 0x00000080 |
190 | #define AR_ISR_TXERR 0x00000100 |
191 | #define AR_ISR_TXNOPKT 0x00000200 |
192 | #define AR_ISR_TXEOL 0x00000400 |
193 | #define AR_ISR_TXURN 0x00000800 |
194 | #define AR_ISR_MIB 0x00001000 |
195 | #define AR_ISR_SWI 0x00002000 |
196 | #define AR_ISR_RXPHY 0x00004000 |
197 | #define AR_ISR_RXKCM 0x00008000 |
198 | #define AR_ISR_SWBA 0x00010000 |
199 | #define 0x00020000 |
200 | #define AR_ISR_BMISS 0x00040000 |
201 | #define AR_ISR_BNR 0x00100000 |
202 | #define AR_ISR_RXCHIRP 0x00200000 |
203 | #define AR_ISR_BCNMISC 0x00800000 |
204 | #define AR_ISR_TIM 0x00800000 |
205 | #define AR_ISR_QCBROVF 0x02000000 |
206 | #define AR_ISR_QCBRURN 0x04000000 |
207 | #define AR_ISR_QTRIG 0x08000000 |
208 | #define AR_ISR_GENTMR 0x10000000 |
209 | |
210 | #define AR_ISR_TXMINTR 0x00080000 |
211 | #define AR_ISR_RXMINTR 0x01000000 |
212 | #define AR_ISR_TXINTM 0x40000000 |
213 | #define AR_ISR_RXINTM 0x80000000 |
214 | |
215 | #define AR_ISR_S0 0x0084 |
216 | #define AR_ISR_S0_QCU_TXOK 0x000003FF |
217 | #define AR_ISR_S0_QCU_TXOK_S 0 |
218 | #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 |
219 | #define AR_ISR_S0_QCU_TXDESC_S 16 |
220 | |
221 | #define AR_ISR_S1 0x0088 |
222 | #define AR_ISR_S1_QCU_TXERR 0x000003FF |
223 | #define AR_ISR_S1_QCU_TXERR_S 0 |
224 | #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 |
225 | #define AR_ISR_S1_QCU_TXEOL_S 16 |
226 | |
227 | #define AR_ISR_S2 0x008c |
228 | #define AR_ISR_S2_QCU_TXURN 0x000003FF |
229 | #define AR_ISR_S2_BB_WATCHDOG 0x00010000 |
230 | #define AR_ISR_S2_CST 0x00400000 |
231 | #define AR_ISR_S2_GTT 0x00800000 |
232 | #define AR_ISR_S2_TIM 0x01000000 |
233 | #define AR_ISR_S2_CABEND 0x02000000 |
234 | #define AR_ISR_S2_DTIMSYNC 0x04000000 |
235 | #define AR_ISR_S2_BCNTO 0x08000000 |
236 | #define AR_ISR_S2_CABTO 0x10000000 |
237 | #define AR_ISR_S2_DTIM 0x20000000 |
238 | #define AR_ISR_S2_TSFOOR 0x40000000 |
239 | #define AR_ISR_S2_TBTT_TIME 0x80000000 |
240 | |
241 | #define AR_ISR_S3 0x0090 |
242 | #define AR_ISR_S3_QCU_QCBROVF 0x000003FF |
243 | #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 |
244 | |
245 | #define AR_ISR_S4 0x0094 |
246 | #define AR_ISR_S4_QCU_QTRIG 0x000003FF |
247 | #define AR_ISR_S4_RESV0 0xFFFFFC00 |
248 | |
249 | #define AR_ISR_S5 0x0098 |
250 | #define AR_ISR_S5_TIMER_TRIG 0x000000FF |
251 | #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 |
252 | #define AR_ISR_S5_TIM_TIMER 0x00000010 |
253 | #define AR_ISR_S5_DTIM_TIMER 0x00000020 |
254 | #define AR_IMR_S5 0x00b8 |
255 | #define AR_IMR_S5_TIM_TIMER 0x00000010 |
256 | #define AR_IMR_S5_DTIM_TIMER 0x00000020 |
257 | #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 |
258 | #define AR_ISR_S5_GENTIMER_TRIG_S 0 |
259 | #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 |
260 | #define AR_ISR_S5_GENTIMER_THRESH_S 16 |
261 | #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 |
262 | #define AR_IMR_S5_GENTIMER_TRIG_S 0 |
263 | #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 |
264 | #define AR_IMR_S5_GENTIMER_THRESH_S 16 |
265 | |
266 | #define AR_IMR 0x00a0 |
267 | #define AR_IMR_RXOK 0x00000001 |
268 | #define AR_IMR_RXDESC 0x00000002 |
269 | #define AR_IMR_RXOK_HP 0x00000001 |
270 | #define AR_IMR_RXOK_LP 0x00000002 |
271 | #define AR_IMR_RXERR 0x00000004 |
272 | #define AR_IMR_RXNOPKT 0x00000008 |
273 | #define AR_IMR_RXEOL 0x00000010 |
274 | #define AR_IMR_RXORN 0x00000020 |
275 | #define AR_IMR_TXOK 0x00000040 |
276 | #define AR_IMR_TXDESC 0x00000080 |
277 | #define AR_IMR_TXERR 0x00000100 |
278 | #define AR_IMR_TXNOPKT 0x00000200 |
279 | #define AR_IMR_TXEOL 0x00000400 |
280 | #define AR_IMR_TXURN 0x00000800 |
281 | #define AR_IMR_MIB 0x00001000 |
282 | #define AR_IMR_SWI 0x00002000 |
283 | #define AR_IMR_RXPHY 0x00004000 |
284 | #define AR_IMR_RXKCM 0x00008000 |
285 | #define AR_IMR_SWBA 0x00010000 |
286 | #define 0x00020000 |
287 | #define AR_IMR_BMISS 0x00040000 |
288 | #define AR_IMR_BNR 0x00100000 |
289 | #define AR_IMR_RXCHIRP 0x00200000 |
290 | #define AR_IMR_BCNMISC 0x00800000 |
291 | #define AR_IMR_TIM 0x00800000 |
292 | #define AR_IMR_QCBROVF 0x02000000 |
293 | #define AR_IMR_QCBRURN 0x04000000 |
294 | #define AR_IMR_QTRIG 0x08000000 |
295 | #define AR_IMR_GENTMR 0x10000000 |
296 | |
297 | #define AR_IMR_TXMINTR 0x00080000 |
298 | #define AR_IMR_RXMINTR 0x01000000 |
299 | #define AR_IMR_TXINTM 0x40000000 |
300 | #define AR_IMR_RXINTM 0x80000000 |
301 | |
302 | #define AR_IMR_S0 0x00a4 |
303 | #define AR_IMR_S0_QCU_TXOK 0x000003FF |
304 | #define AR_IMR_S0_QCU_TXOK_S 0 |
305 | #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 |
306 | #define AR_IMR_S0_QCU_TXDESC_S 16 |
307 | |
308 | #define AR_IMR_S1 0x00a8 |
309 | #define AR_IMR_S1_QCU_TXERR 0x000003FF |
310 | #define AR_IMR_S1_QCU_TXERR_S 0 |
311 | #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 |
312 | #define AR_IMR_S1_QCU_TXEOL_S 16 |
313 | |
314 | #define AR_IMR_S2 0x00ac |
315 | #define AR_IMR_S2_QCU_TXURN 0x000003FF |
316 | #define AR_IMR_S2_QCU_TXURN_S 0 |
317 | #define AR_IMR_S2_BB_WATCHDOG 0x00010000 |
318 | #define AR_IMR_S2_CST 0x00400000 |
319 | #define AR_IMR_S2_GTT 0x00800000 |
320 | #define AR_IMR_S2_TIM 0x01000000 |
321 | #define AR_IMR_S2_CABEND 0x02000000 |
322 | #define AR_IMR_S2_DTIMSYNC 0x04000000 |
323 | #define AR_IMR_S2_BCNTO 0x08000000 |
324 | #define AR_IMR_S2_CABTO 0x10000000 |
325 | #define AR_IMR_S2_DTIM 0x20000000 |
326 | #define AR_IMR_S2_TSFOOR 0x40000000 |
327 | |
328 | #define AR_IMR_S3 0x00b0 |
329 | #define AR_IMR_S3_QCU_QCBROVF 0x000003FF |
330 | #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 |
331 | #define AR_IMR_S3_QCU_QCBRURN_S 16 |
332 | |
333 | #define AR_IMR_S4 0x00b4 |
334 | #define AR_IMR_S4_QCU_QTRIG 0x000003FF |
335 | #define AR_IMR_S4_RESV0 0xFFFFFC00 |
336 | |
337 | #define AR_IMR_S5 0x00b8 |
338 | #define AR_IMR_S5_TIMER_TRIG 0x000000FF |
339 | #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 |
340 | |
341 | |
342 | #define AR_ISR_RAC 0x00c0 |
343 | #define AR_ISR_S0_S 0x00c4 |
344 | #define AR_ISR_S0_QCU_TXOK 0x000003FF |
345 | #define AR_ISR_S0_QCU_TXOK_S 0 |
346 | #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 |
347 | #define AR_ISR_S0_QCU_TXDESC_S 16 |
348 | |
349 | #define AR_ISR_S1_S 0x00c8 |
350 | #define AR_ISR_S1_QCU_TXERR 0x000003FF |
351 | #define AR_ISR_S1_QCU_TXERR_S 0 |
352 | #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 |
353 | #define AR_ISR_S1_QCU_TXEOL_S 16 |
354 | |
355 | #define AR_ISR_S2_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d0 : 0x00cc) |
356 | #define AR_ISR_S3_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d4 : 0x00d0) |
357 | #define AR_ISR_S4_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d8 : 0x00d4) |
358 | #define AR_ISR_S5_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00dc : 0x00d8) |
359 | #define AR_DMADBG_0 0x00e0 |
360 | #define AR_DMADBG_1 0x00e4 |
361 | #define AR_DMADBG_2 0x00e8 |
362 | #define AR_DMADBG_3 0x00ec |
363 | #define AR_DMADBG_4 0x00f0 |
364 | #define AR_DMADBG_5 0x00f4 |
365 | #define AR_DMADBG_6 0x00f8 |
366 | #define AR_DMADBG_7 0x00fc |
367 | |
368 | #define AR_NUM_QCU 10 |
369 | #define AR_QCU_0 0x0001 |
370 | #define AR_QCU_1 0x0002 |
371 | #define AR_QCU_2 0x0004 |
372 | #define AR_QCU_3 0x0008 |
373 | #define AR_QCU_4 0x0010 |
374 | #define AR_QCU_5 0x0020 |
375 | #define AR_QCU_6 0x0040 |
376 | #define AR_QCU_7 0x0080 |
377 | #define AR_QCU_8 0x0100 |
378 | #define AR_QCU_9 0x0200 |
379 | |
380 | #define AR_Q0_TXDP 0x0800 |
381 | #define AR_Q1_TXDP 0x0804 |
382 | #define AR_Q2_TXDP 0x0808 |
383 | #define AR_Q3_TXDP 0x080c |
384 | #define AR_Q4_TXDP 0x0810 |
385 | #define AR_Q5_TXDP 0x0814 |
386 | #define AR_Q6_TXDP 0x0818 |
387 | #define AR_Q7_TXDP 0x081c |
388 | #define AR_Q8_TXDP 0x0820 |
389 | #define AR_Q9_TXDP 0x0824 |
390 | #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) |
391 | |
392 | #define AR_Q_STATUS_RING_START 0x830 |
393 | #define AR_Q_STATUS_RING_END 0x834 |
394 | |
395 | #define AR_Q_TXE 0x0840 |
396 | #define AR_Q_TXE_M 0x000003FF |
397 | |
398 | #define AR_Q_TXD 0x0880 |
399 | #define AR_Q_TXD_M 0x000003FF |
400 | |
401 | #define AR_Q0_CBRCFG 0x08c0 |
402 | #define AR_Q1_CBRCFG 0x08c4 |
403 | #define AR_Q2_CBRCFG 0x08c8 |
404 | #define AR_Q3_CBRCFG 0x08cc |
405 | #define AR_Q4_CBRCFG 0x08d0 |
406 | #define AR_Q5_CBRCFG 0x08d4 |
407 | #define AR_Q6_CBRCFG 0x08d8 |
408 | #define AR_Q7_CBRCFG 0x08dc |
409 | #define AR_Q8_CBRCFG 0x08e0 |
410 | #define AR_Q9_CBRCFG 0x08e4 |
411 | #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) |
412 | #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF |
413 | #define AR_Q_CBRCFG_INTERVAL_S 0 |
414 | #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 |
415 | #define AR_Q_CBRCFG_OVF_THRESH_S 24 |
416 | |
417 | #define AR_Q0_RDYTIMECFG 0x0900 |
418 | #define AR_Q1_RDYTIMECFG 0x0904 |
419 | #define AR_Q2_RDYTIMECFG 0x0908 |
420 | #define AR_Q3_RDYTIMECFG 0x090c |
421 | #define AR_Q4_RDYTIMECFG 0x0910 |
422 | #define AR_Q5_RDYTIMECFG 0x0914 |
423 | #define AR_Q6_RDYTIMECFG 0x0918 |
424 | #define AR_Q7_RDYTIMECFG 0x091c |
425 | #define AR_Q8_RDYTIMECFG 0x0920 |
426 | #define AR_Q9_RDYTIMECFG 0x0924 |
427 | #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) |
428 | #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF |
429 | #define AR_Q_RDYTIMECFG_DURATION_S 0 |
430 | #define AR_Q_RDYTIMECFG_EN 0x01000000 |
431 | |
432 | #define AR_Q_ONESHOTARM_SC 0x0940 |
433 | #define AR_Q_ONESHOTARM_SC_M 0x000003FF |
434 | #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 |
435 | |
436 | #define AR_Q_ONESHOTARM_CC 0x0980 |
437 | #define AR_Q_ONESHOTARM_CC_M 0x000003FF |
438 | #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 |
439 | |
440 | #define AR_Q0_MISC 0x09c0 |
441 | #define AR_Q1_MISC 0x09c4 |
442 | #define AR_Q2_MISC 0x09c8 |
443 | #define AR_Q3_MISC 0x09cc |
444 | #define AR_Q4_MISC 0x09d0 |
445 | #define AR_Q5_MISC 0x09d4 |
446 | #define AR_Q6_MISC 0x09d8 |
447 | #define AR_Q7_MISC 0x09dc |
448 | #define AR_Q8_MISC 0x09e0 |
449 | #define AR_Q9_MISC 0x09e4 |
450 | #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) |
451 | #define AR_Q_MISC_FSP 0x0000000F |
452 | #define AR_Q_MISC_FSP_ASAP 0 |
453 | #define AR_Q_MISC_FSP_CBR 1 |
454 | #define AR_Q_MISC_FSP_DBA_GATED 2 |
455 | #define AR_Q_MISC_FSP_TIM_GATED 3 |
456 | #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 |
457 | #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 |
458 | #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 |
459 | #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 |
460 | #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 |
461 | #define AR_Q_MISC_BEACON_USE 0x00000080 |
462 | #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 |
463 | #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 |
464 | #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 |
465 | #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 |
466 | #define AR_Q_MISC_RESV0 0xFFFFF000 |
467 | |
468 | #define AR_Q0_STS 0x0a00 |
469 | #define AR_Q1_STS 0x0a04 |
470 | #define AR_Q2_STS 0x0a08 |
471 | #define AR_Q3_STS 0x0a0c |
472 | #define AR_Q4_STS 0x0a10 |
473 | #define AR_Q5_STS 0x0a14 |
474 | #define AR_Q6_STS 0x0a18 |
475 | #define AR_Q7_STS 0x0a1c |
476 | #define AR_Q8_STS 0x0a20 |
477 | #define AR_Q9_STS 0x0a24 |
478 | #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) |
479 | #define AR_Q_STS_PEND_FR_CNT 0x00000003 |
480 | #define AR_Q_STS_RESV0 0x000000FC |
481 | #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 |
482 | #define AR_Q_STS_RESV1 0xFFFF0000 |
483 | |
484 | #define AR_Q_RDYTIMESHDN 0x0a40 |
485 | #define AR_Q_RDYTIMESHDN_M 0x000003FF |
486 | |
487 | /* MAC Descriptor CRC check */ |
488 | #define AR_Q_DESC_CRCCHK 0xa44 |
489 | /* Enable CRC check on the descriptor fetched from host */ |
490 | #define AR_Q_DESC_CRCCHK_EN 1 |
491 | |
492 | #define AR_NUM_DCU 10 |
493 | #define AR_DCU_0 0x0001 |
494 | #define AR_DCU_1 0x0002 |
495 | #define AR_DCU_2 0x0004 |
496 | #define AR_DCU_3 0x0008 |
497 | #define AR_DCU_4 0x0010 |
498 | #define AR_DCU_5 0x0020 |
499 | #define AR_DCU_6 0x0040 |
500 | #define AR_DCU_7 0x0080 |
501 | #define AR_DCU_8 0x0100 |
502 | #define AR_DCU_9 0x0200 |
503 | |
504 | #define AR_D0_QCUMASK 0x1000 |
505 | #define AR_D1_QCUMASK 0x1004 |
506 | #define AR_D2_QCUMASK 0x1008 |
507 | #define AR_D3_QCUMASK 0x100c |
508 | #define AR_D4_QCUMASK 0x1010 |
509 | #define AR_D5_QCUMASK 0x1014 |
510 | #define AR_D6_QCUMASK 0x1018 |
511 | #define AR_D7_QCUMASK 0x101c |
512 | #define AR_D8_QCUMASK 0x1020 |
513 | #define AR_D9_QCUMASK 0x1024 |
514 | #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) |
515 | #define AR_D_QCUMASK 0x000003FF |
516 | #define AR_D_QCUMASK_RESV0 0xFFFFFC00 |
517 | |
518 | #define AR_D0_LCL_IFS 0x1040 |
519 | #define AR_D1_LCL_IFS 0x1044 |
520 | #define AR_D2_LCL_IFS 0x1048 |
521 | #define AR_D3_LCL_IFS 0x104c |
522 | #define AR_D4_LCL_IFS 0x1050 |
523 | #define AR_D5_LCL_IFS 0x1054 |
524 | #define AR_D6_LCL_IFS 0x1058 |
525 | #define AR_D7_LCL_IFS 0x105c |
526 | #define AR_D8_LCL_IFS 0x1060 |
527 | #define AR_D9_LCL_IFS 0x1064 |
528 | #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) |
529 | #define AR_D_LCL_IFS_CWMIN 0x000003FF |
530 | #define AR_D_LCL_IFS_CWMIN_S 0 |
531 | #define AR_D_LCL_IFS_CWMAX 0x000FFC00 |
532 | #define AR_D_LCL_IFS_CWMAX_S 10 |
533 | #define AR_D_LCL_IFS_AIFS 0x0FF00000 |
534 | #define AR_D_LCL_IFS_AIFS_S 20 |
535 | |
536 | #define AR_D_LCL_IFS_RESV0 0xF0000000 |
537 | |
538 | #define AR_D0_RETRY_LIMIT 0x1080 |
539 | #define AR_D1_RETRY_LIMIT 0x1084 |
540 | #define AR_D2_RETRY_LIMIT 0x1088 |
541 | #define AR_D3_RETRY_LIMIT 0x108c |
542 | #define AR_D4_RETRY_LIMIT 0x1090 |
543 | #define AR_D5_RETRY_LIMIT 0x1094 |
544 | #define AR_D6_RETRY_LIMIT 0x1098 |
545 | #define AR_D7_RETRY_LIMIT 0x109c |
546 | #define AR_D8_RETRY_LIMIT 0x10a0 |
547 | #define AR_D9_RETRY_LIMIT 0x10a4 |
548 | #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) |
549 | #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F |
550 | #define AR_D_RETRY_LIMIT_FR_SH_S 0 |
551 | #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 |
552 | #define AR_D_RETRY_LIMIT_STA_SH_S 8 |
553 | #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 |
554 | #define AR_D_RETRY_LIMIT_STA_LG_S 14 |
555 | #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 |
556 | |
557 | #define AR_D0_CHNTIME 0x10c0 |
558 | #define AR_D1_CHNTIME 0x10c4 |
559 | #define AR_D2_CHNTIME 0x10c8 |
560 | #define AR_D3_CHNTIME 0x10cc |
561 | #define AR_D4_CHNTIME 0x10d0 |
562 | #define AR_D5_CHNTIME 0x10d4 |
563 | #define AR_D6_CHNTIME 0x10d8 |
564 | #define AR_D7_CHNTIME 0x10dc |
565 | #define AR_D8_CHNTIME 0x10e0 |
566 | #define AR_D9_CHNTIME 0x10e4 |
567 | #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) |
568 | #define AR_D_CHNTIME_DUR 0x000FFFFF |
569 | #define AR_D_CHNTIME_DUR_S 0 |
570 | #define AR_D_CHNTIME_EN 0x00100000 |
571 | #define AR_D_CHNTIME_RESV0 0xFFE00000 |
572 | |
573 | #define AR_D0_MISC 0x1100 |
574 | #define AR_D1_MISC 0x1104 |
575 | #define AR_D2_MISC 0x1108 |
576 | #define AR_D3_MISC 0x110c |
577 | #define AR_D4_MISC 0x1110 |
578 | #define AR_D5_MISC 0x1114 |
579 | #define AR_D6_MISC 0x1118 |
580 | #define AR_D7_MISC 0x111c |
581 | #define AR_D8_MISC 0x1120 |
582 | #define AR_D9_MISC 0x1124 |
583 | #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) |
584 | #define AR_D_MISC_BKOFF_THRESH 0x0000003F |
585 | #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 |
586 | #define AR_D_MISC_CW_RESET_EN 0x00000080 |
587 | #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 |
588 | #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 |
589 | #define AR_D_MISC_CW_BKOFF_EN 0x00001000 |
590 | #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 |
591 | #define AR_D_MISC_VIR_COL_HANDLING_S 14 |
592 | #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 |
593 | #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 |
594 | #define AR_D_MISC_BEACON_USE 0x00010000 |
595 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 |
596 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 |
597 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 |
598 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 |
599 | #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 |
600 | #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 |
601 | #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 |
602 | #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 |
603 | #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 |
604 | #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 |
605 | #define AR_D_MISC_RESV0 0xFF000000 |
606 | |
607 | #define AR_D_SEQNUM 0x1140 |
608 | |
609 | #define AR_D_GBL_IFS_SIFS 0x1030 |
610 | #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF |
611 | #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF |
612 | |
613 | #define AR_D_TXBLK_BASE 0x1038 |
614 | #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF |
615 | #define AR_D_TXBLK_WRITE_BITMASK_S 0 |
616 | #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 |
617 | #define AR_D_TXBLK_WRITE_SLICE_S 16 |
618 | #define AR_D_TXBLK_WRITE_DCU 0x00F00000 |
619 | #define AR_D_TXBLK_WRITE_DCU_S 20 |
620 | #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 |
621 | #define AR_D_TXBLK_WRITE_COMMAND_S 24 |
622 | |
623 | #define AR_D_GBL_IFS_SLOT 0x1070 |
624 | #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF |
625 | #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 |
626 | |
627 | #define AR_D_GBL_IFS_EIFS 0x10b0 |
628 | #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF |
629 | #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 |
630 | #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO 363 |
631 | |
632 | #define AR_D_GBL_IFS_MISC 0x10f0 |
633 | #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 |
634 | #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 |
635 | #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 |
636 | #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 |
637 | #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 |
638 | #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 |
639 | #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 |
640 | #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 |
641 | |
642 | #define AR_D_FPCTL 0x1230 |
643 | #define AR_D_FPCTL_DCU 0x0000000F |
644 | #define AR_D_FPCTL_DCU_S 0 |
645 | #define AR_D_FPCTL_PREFETCH_EN 0x00000010 |
646 | #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 |
647 | #define AR_D_FPCTL_BURST_PREFETCH_S 5 |
648 | |
649 | #define AR_D_TXPSE 0x1270 |
650 | #define AR_D_TXPSE_CTRL 0x000003FF |
651 | #define AR_D_TXPSE_RESV0 0x0000FC00 |
652 | #define AR_D_TXPSE_STATUS 0x00010000 |
653 | #define AR_D_TXPSE_RESV1 0xFFFE0000 |
654 | |
655 | #define AR_D_TXSLOTMASK 0x12f0 |
656 | #define AR_D_TXSLOTMASK_NUM 0x0000000F |
657 | |
658 | #define AR_CFG_LED 0x1f04 |
659 | #define AR_CFG_SCLK_RATE_IND 0x00000003 |
660 | #define AR_CFG_SCLK_RATE_IND_S 0 |
661 | #define AR_CFG_SCLK_32MHZ 0x00000000 |
662 | #define AR_CFG_SCLK_4MHZ 0x00000001 |
663 | #define AR_CFG_SCLK_1MHZ 0x00000002 |
664 | #define AR_CFG_SCLK_32KHZ 0x00000003 |
665 | #define AR_CFG_LED_BLINK_SLOW 0x00000008 |
666 | #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 |
667 | #define AR_CFG_LED_MODE_SEL 0x00000380 |
668 | #define AR_CFG_LED_MODE_SEL_S 7 |
669 | #define AR_CFG_LED_POWER 0x00000280 |
670 | #define AR_CFG_LED_POWER_S 7 |
671 | #define AR_CFG_LED_NETWORK 0x00000300 |
672 | #define AR_CFG_LED_NETWORK_S 7 |
673 | #define AR_CFG_LED_MODE_PROP 0x0 |
674 | #define AR_CFG_LED_MODE_RPROP 0x1 |
675 | #define AR_CFG_LED_MODE_SPLIT 0x2 |
676 | #define AR_CFG_LED_MODE_RAND 0x3 |
677 | #define AR_CFG_LED_MODE_POWER_OFF 0x4 |
678 | #define AR_CFG_LED_MODE_POWER_ON 0x5 |
679 | #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 |
680 | #define AR_CFG_LED_MODE_NETWORK_ON 0x6 |
681 | #define AR_CFG_LED_ASSOC_CTL 0x00000c00 |
682 | #define AR_CFG_LED_ASSOC_CTL_S 10 |
683 | #define AR_CFG_LED_ASSOC_NONE 0x0 |
684 | #define AR_CFG_LED_ASSOC_ACTIVE 0x1 |
685 | #define AR_CFG_LED_ASSOC_PENDING 0x2 |
686 | |
687 | #define AR_CFG_LED_BLINK_SLOW 0x00000008 |
688 | #define AR_CFG_LED_BLINK_SLOW_S 3 |
689 | |
690 | #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 |
691 | #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 |
692 | |
693 | #define AR_MAC_SLEEP 0x1f00 |
694 | #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 |
695 | #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 |
696 | |
697 | #define AR_RC 0x4000 |
698 | #define AR_RC_AHB 0x00000001 |
699 | #define AR_RC_APB 0x00000002 |
700 | #define AR_RC_HOSTIF 0x00000100 |
701 | |
702 | #define AR_WA(_ah) (AR_SREV_9340(_ah) ? 0x40c4 : 0x4004) |
703 | #define AR_WA_BIT6 (1 << 6) |
704 | #define AR_WA_BIT7 (1 << 7) |
705 | #define AR_WA_BIT23 (1 << 23) |
706 | #define AR_WA_D3_L1_DISABLE (1 << 14) |
707 | #define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset |
708 | to POR (power-on-reset) */ |
709 | #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) |
710 | #define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) |
711 | #define AR_WA_RESET_EN (1 << 18) /* Enable PCI-Reset to |
712 | POR (bit 15) */ |
713 | #define AR_WA_ANALOG_SHIFT (1 << 20) |
714 | #define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ |
715 | #define AR_WA_BIT22 (1 << 22) |
716 | #define AR9285_WA_DEFAULT 0x004a050b |
717 | #define AR9280_WA_DEFAULT 0x0040073b |
718 | #define AR_WA_DEFAULT 0x0000073f |
719 | |
720 | |
721 | #define AR_PM_STATE 0x4008 |
722 | #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 |
723 | |
724 | #define AR_HOST_TIMEOUT(_ah) (AR_SREV_9340(_ah) ? 0x4008 : 0x4018) |
725 | #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF |
726 | #define AR_HOST_TIMEOUT_APB_CNTR_S 0 |
727 | #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 |
728 | #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 |
729 | |
730 | #define AR_EEPROM 0x401c |
731 | #define AR_EEPROM_ABSENT 0x00000100 |
732 | #define AR_EEPROM_CORRUPT 0x00000200 |
733 | #define AR_EEPROM_PROT_MASK 0x03FFFC00 |
734 | #define AR_EEPROM_PROT_MASK_S 10 |
735 | |
736 | #define EEPROM_PROTECT_RP_0_31 0x0001 |
737 | #define EEPROM_PROTECT_WP_0_31 0x0002 |
738 | #define EEPROM_PROTECT_RP_32_63 0x0004 |
739 | #define EEPROM_PROTECT_WP_32_63 0x0008 |
740 | #define EEPROM_PROTECT_RP_64_127 0x0010 |
741 | #define EEPROM_PROTECT_WP_64_127 0x0020 |
742 | #define EEPROM_PROTECT_RP_128_191 0x0040 |
743 | #define EEPROM_PROTECT_WP_128_191 0x0080 |
744 | #define EEPROM_PROTECT_RP_192_255 0x0100 |
745 | #define EEPROM_PROTECT_WP_192_255 0x0200 |
746 | #define EEPROM_PROTECT_RP_256_511 0x0400 |
747 | #define EEPROM_PROTECT_WP_256_511 0x0800 |
748 | #define EEPROM_PROTECT_RP_512_1023 0x1000 |
749 | #define EEPROM_PROTECT_WP_512_1023 0x2000 |
750 | #define EEPROM_PROTECT_RP_1024_2047 0x4000 |
751 | #define EEPROM_PROTECT_WP_1024_2047 0x8000 |
752 | |
753 | #define AR_SREV(_ah) \ |
754 | ((AR_SREV_9100(_ah)) ? 0x0600 : (AR_SREV_9340(_ah) \ |
755 | ? 0x400c : 0x4020)) |
756 | |
757 | #define AR_SREV_ID(_ah) \ |
758 | ((AR_SREV_9100(_ah)) ? 0x00000FFF : 0x000000FF) |
759 | #define AR_SREV_VERSION 0x000000F0 |
760 | #define AR_SREV_VERSION_S 4 |
761 | #define AR_SREV_REVISION 0x00000007 |
762 | |
763 | #define AR_SREV_ID2 0xFFFFFFFF |
764 | #define AR_SREV_VERSION2 0xFFFC0000 |
765 | #define AR_SREV_VERSION2_S 18 |
766 | #define AR_SREV_TYPE2 0x0003F000 |
767 | #define AR_SREV_TYPE2_S 12 |
768 | #define AR_SREV_TYPE2_CHAIN 0x00001000 |
769 | #define AR_SREV_TYPE2_HOST_MODE 0x00002000 |
770 | #define AR_SREV_REVISION2 0x00000F00 |
771 | #define AR_SREV_REVISION2_S 8 |
772 | |
773 | #define AR_SREV_VERSION_5416_PCI 0xD |
774 | #define AR_SREV_VERSION_5416_PCIE 0xC |
775 | #define AR_SREV_REVISION_5416_10 0 |
776 | #define AR_SREV_REVISION_5416_20 1 |
777 | #define AR_SREV_REVISION_5416_22 2 |
778 | #define AR_SREV_VERSION_9100 0x14 |
779 | #define AR_SREV_VERSION_9160 0x40 |
780 | #define AR_SREV_REVISION_9160_10 0 |
781 | #define AR_SREV_REVISION_9160_11 1 |
782 | #define AR_SREV_VERSION_9280 0x80 |
783 | #define AR_SREV_REVISION_9280_10 0 |
784 | #define AR_SREV_REVISION_9280_20 1 |
785 | #define AR_SREV_REVISION_9280_21 2 |
786 | #define AR_SREV_VERSION_9285 0xC0 |
787 | #define AR_SREV_REVISION_9285_10 0 |
788 | #define AR_SREV_REVISION_9285_11 1 |
789 | #define AR_SREV_REVISION_9285_12 2 |
790 | #define AR_SREV_VERSION_9287 0x180 |
791 | #define AR_SREV_REVISION_9287_10 0 |
792 | #define AR_SREV_REVISION_9287_11 1 |
793 | #define AR_SREV_REVISION_9287_12 2 |
794 | #define AR_SREV_REVISION_9287_13 3 |
795 | #define AR_SREV_VERSION_9271 0x140 |
796 | #define AR_SREV_REVISION_9271_10 0 |
797 | #define AR_SREV_REVISION_9271_11 1 |
798 | #define AR_SREV_VERSION_9300 0x1c0 |
799 | #define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ |
800 | #define AR_SREV_REVISION_9300_22 3 |
801 | #define AR_SREV_VERSION_9330 0x200 |
802 | #define AR_SREV_REVISION_9330_10 0 |
803 | #define AR_SREV_REVISION_9330_11 1 |
804 | #define AR_SREV_REVISION_9330_12 2 |
805 | #define AR_SREV_VERSION_9485 0x240 |
806 | #define AR_SREV_REVISION_9485_10 0 |
807 | #define AR_SREV_REVISION_9485_11 1 |
808 | #define AR_SREV_VERSION_9340 0x300 |
809 | #define AR_SREV_REVISION_9340_10 0 |
810 | #define AR_SREV_REVISION_9340_11 1 |
811 | #define AR_SREV_REVISION_9340_12 2 |
812 | #define AR_SREV_REVISION_9340_13 3 |
813 | #define AR_SREV_VERSION_9580 0x1C0 |
814 | #define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ |
815 | #define AR_SREV_VERSION_9462 0x280 |
816 | #define AR_SREV_REVISION_9462_20 2 |
817 | #define AR_SREV_REVISION_9462_21 3 |
818 | #define AR_SREV_VERSION_9565 0x2C0 |
819 | #define AR_SREV_REVISION_9565_10 0 |
820 | #define AR_SREV_REVISION_9565_101 1 |
821 | #define AR_SREV_REVISION_9565_11 2 |
822 | #define AR_SREV_VERSION_9550 0x400 |
823 | #define AR_SREV_VERSION_9531 0x500 |
824 | #define AR_SREV_REVISION_9531_10 0 |
825 | #define AR_SREV_REVISION_9531_11 1 |
826 | #define AR_SREV_REVISION_9531_20 2 |
827 | #define AR_SREV_VERSION_9561 0x600 |
828 | |
829 | #define AR_SREV_5416(_ah) \ |
830 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ |
831 | ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)) |
832 | #define AR_SREV_5416_22_OR_LATER(_ah) \ |
833 | (((AR_SREV_5416(_ah)) && \ |
834 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \ |
835 | ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) |
836 | |
837 | #define AR_SREV_9100(_ah) \ |
838 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9100)) |
839 | #define AR_SREV_9100_OR_LATER(_ah) \ |
840 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) |
841 | |
842 | #define AR_SREV_9160(_ah) \ |
843 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) |
844 | #define AR_SREV_9160_10_OR_LATER(_ah) \ |
845 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160)) |
846 | #define AR_SREV_9160_11(_ah) \ |
847 | (AR_SREV_9160(_ah) && \ |
848 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) |
849 | #define AR_SREV_9280(_ah) \ |
850 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) |
851 | #define AR_SREV_9280_20_OR_LATER(_ah) \ |
852 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) |
853 | #define AR_SREV_9280_20(_ah) \ |
854 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) |
855 | |
856 | #define AR_SREV_9285(_ah) \ |
857 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) |
858 | #define AR_SREV_9285_12_OR_LATER(_ah) \ |
859 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285)) |
860 | |
861 | #define AR_SREV_9287(_ah) \ |
862 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287)) |
863 | #define AR_SREV_9287_11_OR_LATER(_ah) \ |
864 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287)) |
865 | #define AR_SREV_9287_11(_ah) \ |
866 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ |
867 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11)) |
868 | #define AR_SREV_9287_12(_ah) \ |
869 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ |
870 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12)) |
871 | #define AR_SREV_9287_12_OR_LATER(_ah) \ |
872 | (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ |
873 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ |
874 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12))) |
875 | #define AR_SREV_9287_13_OR_LATER(_ah) \ |
876 | (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ |
877 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ |
878 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13))) |
879 | |
880 | #define AR_SREV_9271(_ah) \ |
881 | (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271) |
882 | #define AR_SREV_9271_10(_ah) \ |
883 | (AR_SREV_9271(_ah) && \ |
884 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10)) |
885 | #define AR_SREV_9271_11(_ah) \ |
886 | (AR_SREV_9271(_ah) && \ |
887 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) |
888 | |
889 | #define AR_SREV_9300(_ah) \ |
890 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300)) |
891 | #define AR_SREV_9300_20_OR_LATER(_ah) \ |
892 | ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300) |
893 | #define AR_SREV_9300_22(_ah) \ |
894 | (AR_SREV_9300((_ah)) && \ |
895 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_22)) |
896 | |
897 | #define AR_SREV_9330(_ah) \ |
898 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330)) |
899 | #define AR_SREV_9330_11(_ah) \ |
900 | (AR_SREV_9330((_ah)) && \ |
901 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11)) |
902 | #define AR_SREV_9330_12(_ah) \ |
903 | (AR_SREV_9330((_ah)) && \ |
904 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_12)) |
905 | |
906 | #ifdef CONFIG_ATH9K_PCOEM |
907 | #define AR_SREV_9462(_ah) \ |
908 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462)) |
909 | #define AR_SREV_9485(_ah) \ |
910 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485)) |
911 | #define AR_SREV_9565(_ah) \ |
912 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565)) |
913 | #define AR_SREV_9003_PCOEM(_ah) \ |
914 | (AR_SREV_9462(_ah) || AR_SREV_9485(_ah) || AR_SREV_9565(_ah)) |
915 | #else |
916 | #define AR_SREV_9462(_ah) 0 |
917 | #define AR_SREV_9485(_ah) 0 |
918 | #define AR_SREV_9565(_ah) 0 |
919 | #define AR_SREV_9003_PCOEM(_ah) 0 |
920 | #endif |
921 | |
922 | #define AR_SREV_9485_11_OR_LATER(_ah) \ |
923 | (AR_SREV_9485(_ah) && \ |
924 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9485_11)) |
925 | #define AR_SREV_9485_OR_LATER(_ah) \ |
926 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485)) |
927 | |
928 | #define AR_SREV_9340(_ah) \ |
929 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340)) |
930 | |
931 | #define AR_SREV_9340_13(_ah) \ |
932 | (AR_SREV_9340((_ah)) && \ |
933 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9340_13)) |
934 | |
935 | #define AR_SREV_9340_13_OR_LATER(_ah) \ |
936 | (AR_SREV_9340((_ah)) && \ |
937 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13)) |
938 | |
939 | #define AR_SREV_9285E_20(_ah) \ |
940 | (AR_SREV_9285_12_OR_LATER(_ah) && \ |
941 | ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) |
942 | |
943 | #define AR_SREV_9462_20(_ah) \ |
944 | (AR_SREV_9462(_ah) && \ |
945 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20)) |
946 | #define AR_SREV_9462_21(_ah) \ |
947 | (AR_SREV_9462(_ah) && \ |
948 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_21)) |
949 | #define AR_SREV_9462_20_OR_LATER(_ah) \ |
950 | (AR_SREV_9462(_ah) && \ |
951 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20)) |
952 | #define AR_SREV_9462_21_OR_LATER(_ah) \ |
953 | (AR_SREV_9462(_ah) && \ |
954 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_21)) |
955 | |
956 | #define AR_SREV_9565_10(_ah) \ |
957 | (AR_SREV_9565(_ah) && \ |
958 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10)) |
959 | #define AR_SREV_9565_101(_ah) \ |
960 | (AR_SREV_9565(_ah) && \ |
961 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101)) |
962 | #define AR_SREV_9565_11(_ah) \ |
963 | (AR_SREV_9565(_ah) && \ |
964 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11)) |
965 | #define AR_SREV_9565_11_OR_LATER(_ah) \ |
966 | (AR_SREV_9565(_ah) && \ |
967 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11)) |
968 | |
969 | #define AR_SREV_9550(_ah) \ |
970 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550)) |
971 | #define AR_SREV_9550_OR_LATER(_ah) \ |
972 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9550)) |
973 | |
974 | #define AR_SREV_9580(_ah) \ |
975 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ |
976 | ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10)) |
977 | #define AR_SREV_9580_10(_ah) \ |
978 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ |
979 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9580_10)) |
980 | |
981 | #define AR_SREV_9531(_ah) \ |
982 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531)) |
983 | #define AR_SREV_9531_10(_ah) \ |
984 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \ |
985 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_10)) |
986 | #define AR_SREV_9531_11(_ah) \ |
987 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \ |
988 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_11)) |
989 | #define AR_SREV_9531_20(_ah) \ |
990 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \ |
991 | ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_20)) |
992 | |
993 | #define AR_SREV_9561(_ah) \ |
994 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9561)) |
995 | |
996 | #define AR_SREV_SOC(_ah) \ |
997 | (AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(_ah) || \ |
998 | AR_SREV_9561(_ah)) |
999 | |
1000 | /* NOTE: When adding chips newer than Peacock, add chip check here */ |
1001 | #define AR_SREV_9580_10_OR_LATER(_ah) \ |
1002 | (AR_SREV_9580(_ah)) |
1003 | |
1004 | enum ath_usb_dev { |
1005 | AR9280_USB = 1, /* AR7010 + AR9280, UB94 */ |
1006 | AR9287_USB = 2, /* AR7010 + AR9287, UB95 */ |
1007 | STORAGE_DEVICE = 3, |
1008 | }; |
1009 | |
1010 | #define AR_DEVID_7010(_ah) \ |
1011 | (((_ah)->hw_version.usbdev == AR9280_USB) || \ |
1012 | ((_ah)->hw_version.usbdev == AR9287_USB)) |
1013 | |
1014 | #define AR_RADIO_SREV_MAJOR 0xf0 |
1015 | #define AR_RAD5133_SREV_MAJOR 0xc0 |
1016 | #define AR_RAD2133_SREV_MAJOR 0xd0 |
1017 | #define AR_RAD5122_SREV_MAJOR 0xe0 |
1018 | #define AR_RAD2122_SREV_MAJOR 0xf0 |
1019 | |
1020 | #define AR_AHB_MODE 0x4024 |
1021 | #define AR_AHB_EXACT_WR_EN 0x00000000 |
1022 | #define AR_AHB_BUF_WR_EN 0x00000001 |
1023 | #define AR_AHB_EXACT_RD_EN 0x00000000 |
1024 | #define AR_AHB_CACHELINE_RD_EN 0x00000002 |
1025 | #define AR_AHB_PREFETCH_RD_EN 0x00000004 |
1026 | #define AR_AHB_PAGE_SIZE_1K 0x00000000 |
1027 | #define AR_AHB_PAGE_SIZE_2K 0x00000008 |
1028 | #define AR_AHB_PAGE_SIZE_4K 0x00000010 |
1029 | #define AR_AHB_CUSTOM_BURST_EN 0x000000C0 |
1030 | #define AR_AHB_CUSTOM_BURST_EN_S 6 |
1031 | #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 |
1032 | |
1033 | #define AR_INTR_RTC_IRQ 0x00000001 |
1034 | #define AR_INTR_MAC_IRQ 0x00000002 |
1035 | #define AR_INTR_EEP_PROT_ACCESS 0x00000004 |
1036 | #define AR_INTR_MAC_AWAKE 0x00020000 |
1037 | #define AR_INTR_MAC_ASLEEP 0x00040000 |
1038 | #define AR_INTR_SPURIOUS 0xFFFFFFFF |
1039 | |
1040 | |
1041 | #define AR_INTR_SYNC_CAUSE(_ah) (AR_SREV_9340(_ah) ? 0x4010 : 0x4028) |
1042 | #define AR_INTR_SYNC_CAUSE_CLR(_ah) (AR_SREV_9340(_ah) ? 0x4010 : 0x4028) |
1043 | |
1044 | |
1045 | #define AR_INTR_SYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4014 : 0x402c) |
1046 | #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 |
1047 | #define AR_INTR_SYNC_ENABLE_GPIO_S 18 |
1048 | |
1049 | enum { |
1050 | AR_INTR_SYNC_RTC_IRQ = 0x00000001, |
1051 | AR_INTR_SYNC_MAC_IRQ = 0x00000002, |
1052 | AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, |
1053 | AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, |
1054 | AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, |
1055 | AR_INTR_SYNC_HOST1_FATAL = 0x00000020, |
1056 | AR_INTR_SYNC_HOST1_PERR = 0x00000040, |
1057 | AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, |
1058 | AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, |
1059 | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, |
1060 | AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, |
1061 | AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, |
1062 | AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, |
1063 | AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, |
1064 | AR_INTR_SYNC_PM_ACCESS = 0x00004000, |
1065 | AR_INTR_SYNC_MAC_AWAKE = 0x00008000, |
1066 | AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, |
1067 | AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, |
1068 | AR_INTR_SYNC_ALL = 0x0003FFFF, |
1069 | |
1070 | |
1071 | AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | |
1072 | AR_INTR_SYNC_HOST1_PERR | |
1073 | AR_INTR_SYNC_RADM_CPL_EP | |
1074 | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | |
1075 | AR_INTR_SYNC_RADM_CPL_TLP_ABORT | |
1076 | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | |
1077 | AR_INTR_SYNC_RADM_CPL_TIMEOUT | |
1078 | AR_INTR_SYNC_LOCAL_TIMEOUT | |
1079 | AR_INTR_SYNC_MAC_SLEEP_ACCESS), |
1080 | |
1081 | AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010, |
1082 | |
1083 | AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, |
1084 | |
1085 | }; |
1086 | |
1087 | #define AR_INTR_ASYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x4018 : 0x4030) |
1088 | #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 |
1089 | #define AR_INTR_ASYNC_MASK_GPIO_S 18 |
1090 | #define AR_INTR_ASYNC_MASK_MCI 0x00000080 |
1091 | #define AR_INTR_ASYNC_MASK_MCI_S 7 |
1092 | |
1093 | #define AR_INTR_SYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x401c : 0x4034) |
1094 | #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 |
1095 | #define AR_INTR_SYNC_MASK_GPIO_S 18 |
1096 | |
1097 | #define AR_INTR_ASYNC_CAUSE_CLR(_ah) (AR_SREV_9340(_ah) ? 0x4020 : 0x4038) |
1098 | #define AR_INTR_ASYNC_CAUSE(_ah) (AR_SREV_9340(_ah) ? 0x4020 : 0x4038) |
1099 | #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 |
1100 | #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \ |
1101 | AR_INTR_ASYNC_CAUSE_MCI) |
1102 | |
1103 | /* Asynchronous Interrupt Enable Register */ |
1104 | #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 |
1105 | #define AR_INTR_ASYNC_ENABLE_MCI_S 7 |
1106 | |
1107 | |
1108 | #define AR_INTR_ASYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4024 : 0x403c) |
1109 | #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 |
1110 | #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 |
1111 | |
1112 | #define AR_PCIE_SERDES 0x4040 |
1113 | #define AR_PCIE_SERDES2 0x4044 |
1114 | #define AR_PCIE_PM_CTRL(_ah) (AR_SREV_9340(_ah) ? 0x4004 : 0x4014) |
1115 | #define AR_PCIE_PM_CTRL_ENA 0x00080000 |
1116 | |
1117 | #define AR_PCIE_PHY_REG3 0x18c08 |
1118 | |
1119 | /* Define correct GPIO numbers and MASK bits to indicate the WMAC |
1120 | * GPIO resource. |
1121 | * Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs |
1122 | * which rely on gpiolib framework. But restrict SOC AR9330 only to |
1123 | * access WMAC GPIO which has the same design with the old chips. |
1124 | */ |
1125 | #define AR_NUM_GPIO 14 |
1126 | #define AR9280_NUM_GPIO 10 |
1127 | #define AR9285_NUM_GPIO 12 |
1128 | #define AR9287_NUM_GPIO 10 |
1129 | #define AR9271_NUM_GPIO 16 |
1130 | #define AR9300_NUM_GPIO 16 |
1131 | #define AR9330_NUM_GPIO 16 |
1132 | #define AR9340_NUM_GPIO 23 |
1133 | #define AR9462_NUM_GPIO 14 |
1134 | #define AR9485_NUM_GPIO 12 |
1135 | #define AR9531_NUM_GPIO 18 |
1136 | #define AR9550_NUM_GPIO 24 |
1137 | #define AR9561_NUM_GPIO 23 |
1138 | #define AR9565_NUM_GPIO 14 |
1139 | #define AR9580_NUM_GPIO 16 |
1140 | #define AR7010_NUM_GPIO 16 |
1141 | |
1142 | #define AR_GPIO_MASK 0x00003FFF |
1143 | #define AR9271_GPIO_MASK 0x0000FFFF |
1144 | #define AR9280_GPIO_MASK 0x000003FF |
1145 | #define AR9285_GPIO_MASK 0x00000FFF |
1146 | #define AR9287_GPIO_MASK 0x000003FF |
1147 | #define AR9300_GPIO_MASK 0x0000F4FF |
1148 | #define AR9330_GPIO_MASK 0x0000F4FF |
1149 | #define AR9340_GPIO_MASK 0x0000000F |
1150 | #define AR9462_GPIO_MASK 0x00003FFF |
1151 | #define AR9485_GPIO_MASK 0x00000FFF |
1152 | #define AR9531_GPIO_MASK 0x0000000F |
1153 | #define AR9550_GPIO_MASK 0x0000000F |
1154 | #define AR9561_GPIO_MASK 0x0000000F |
1155 | #define AR9565_GPIO_MASK 0x00003FFF |
1156 | #define AR9580_GPIO_MASK 0x0000F4FF |
1157 | #define AR7010_GPIO_MASK 0x0000FFFF |
1158 | |
1159 | #define AR_GPIO_IN_OUT(_ah) (AR_SREV_9340(_ah) ? 0x4028 : 0x4048) |
1160 | #define AR_GPIO_IN_VAL 0x0FFFC000 |
1161 | #define AR_GPIO_IN_VAL_S 14 |
1162 | #define AR928X_GPIO_IN_VAL 0x000FFC00 |
1163 | #define AR928X_GPIO_IN_VAL_S 10 |
1164 | #define AR9285_GPIO_IN_VAL 0x00FFF000 |
1165 | #define AR9285_GPIO_IN_VAL_S 12 |
1166 | #define AR9287_GPIO_IN_VAL 0x003FF800 |
1167 | #define AR9287_GPIO_IN_VAL_S 11 |
1168 | #define AR9271_GPIO_IN_VAL 0xFFFF0000 |
1169 | #define AR9271_GPIO_IN_VAL_S 16 |
1170 | #define AR7010_GPIO_IN_VAL 0x0000FFFF |
1171 | #define AR7010_GPIO_IN_VAL_S 0 |
1172 | |
1173 | #define AR_GPIO_IN(_ah) (AR_SREV_9340(_ah) ? 0x402c : 0x404c) |
1174 | #define AR9300_GPIO_IN_VAL 0x0001FFFF |
1175 | #define AR9300_GPIO_IN_VAL_S 0 |
1176 | |
1177 | #define AR_GPIO_OE_OUT(_ah) (AR_SREV_9340(_ah) ? 0x4030 : \ |
1178 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4050 : 0x404c)) |
1179 | #define AR_GPIO_OE_OUT_DRV 0x3 |
1180 | #define AR_GPIO_OE_OUT_DRV_NO 0x0 |
1181 | #define AR_GPIO_OE_OUT_DRV_LOW 0x1 |
1182 | #define AR_GPIO_OE_OUT_DRV_HI 0x2 |
1183 | #define AR_GPIO_OE_OUT_DRV_ALL 0x3 |
1184 | |
1185 | #define AR7010_GPIO_OE 0x52000 |
1186 | #define AR7010_GPIO_OE_MASK 0x1 |
1187 | #define AR7010_GPIO_OE_AS_OUTPUT 0x0 |
1188 | #define AR7010_GPIO_OE_AS_INPUT 0x1 |
1189 | #define AR7010_GPIO_IN 0x52004 |
1190 | #define AR7010_GPIO_OUT 0x52008 |
1191 | #define AR7010_GPIO_SET 0x5200C |
1192 | #define AR7010_GPIO_CLEAR 0x52010 |
1193 | #define AR7010_GPIO_INT 0x52014 |
1194 | #define AR7010_GPIO_INT_TYPE 0x52018 |
1195 | #define AR7010_GPIO_INT_POLARITY 0x5201C |
1196 | #define AR7010_GPIO_PENDING 0x52020 |
1197 | #define AR7010_GPIO_INT_MASK 0x52024 |
1198 | #define AR7010_GPIO_FUNCTION 0x52028 |
1199 | |
1200 | #define AR_GPIO_INTR_POL(_ah) (AR_SREV_9340(_ah) ? 0x4038 : \ |
1201 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4058 : 0x4050)) |
1202 | #define AR_GPIO_INTR_POL_VAL 0x0001FFFF |
1203 | #define AR_GPIO_INTR_POL_VAL_S 0 |
1204 | |
1205 | #define AR_GPIO_INPUT_EN_VAL(_ah) (AR_SREV_9340(_ah) ? 0x403c : \ |
1206 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x405c : 0x4054)) |
1207 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 |
1208 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 |
1209 | #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 |
1210 | #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 |
1211 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 |
1212 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 |
1213 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 |
1214 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 |
1215 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 |
1216 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 |
1217 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 |
1218 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 |
1219 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 |
1220 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 |
1221 | #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 |
1222 | #define AR_GPIO_JTAG_DISABLE 0x00020000 |
1223 | |
1224 | #define AR_GPIO_INPUT_MUX1(_ah) (AR_SREV_9340(_ah) ? 0x4040 : \ |
1225 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4060 : 0x4058)) |
1226 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 |
1227 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 |
1228 | #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 |
1229 | #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 |
1230 | |
1231 | #define AR_GPIO_INPUT_MUX2(_ah) (AR_SREV_9340(_ah) ? 0x4044 : \ |
1232 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4064 : 0x405c)) |
1233 | #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f |
1234 | #define AR_GPIO_INPUT_MUX2_CLK25_S 0 |
1235 | #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 |
1236 | #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 |
1237 | #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 |
1238 | #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 |
1239 | |
1240 | #define AR_GPIO_OUTPUT_MUX1(_ah) (AR_SREV_9340(_ah) ? 0x4048 : \ |
1241 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4068 : 0x4060)) |
1242 | #define AR_GPIO_OUTPUT_MUX2(_ah) (AR_SREV_9340(_ah) ? 0x404c : \ |
1243 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x406c : 0x4064)) |
1244 | #define AR_GPIO_OUTPUT_MUX3(_ah) (AR_SREV_9340(_ah) ? 0x4050 : \ |
1245 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4070 : 0x4068)) |
1246 | |
1247 | #define AR_INPUT_STATE(_ah) (AR_SREV_9340(_ah) ? 0x4054 : \ |
1248 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4074 : 0x406c)) |
1249 | |
1250 | #define AR_EEPROM_STATUS_DATA(_ah) (AR_SREV_9340(_ah) ? 0x40c8 : \ |
1251 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4084 : 0x407c)) |
1252 | #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff |
1253 | #define AR_EEPROM_STATUS_DATA_VAL_S 0 |
1254 | #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 |
1255 | #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 |
1256 | #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 |
1257 | #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 |
1258 | |
1259 | #define AR_OBS(_ah) (AR_SREV_9340(_ah) ? 0x405c : \ |
1260 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4088 : 0x4080)) |
1261 | |
1262 | #define AR_GPIO_PDPU(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4090 : 0x4088) |
1263 | |
1264 | #define AR_PCIE_MSI(_ah) (AR_SREV_9340(_ah) ? 0x40d8 : \ |
1265 | (AR_SREV_9300_20_OR_LATER(_ah) ? 0x40a4 : 0x4094)) |
1266 | #define AR_PCIE_MSI_ENABLE 0x00000001 |
1267 | #define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000 |
1268 | #define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF /* bits 8..11: value must be 0x5060 */ |
1269 | #define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF /* bits 8..11: value must be 0x5064 */ |
1270 | |
1271 | #define AR_INTR_PRIO_TX 0x00000001 |
1272 | #define AR_INTR_PRIO_RXLP 0x00000002 |
1273 | #define AR_INTR_PRIO_RXHP 0x00000004 |
1274 | |
1275 | #define AR_INTR_PRIO_SYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4088 : 0x40c4) |
1276 | #define AR_INTR_PRIO_ASYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x408c : 0x40c8) |
1277 | #define AR_INTR_PRIO_SYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x4090 : 0x40cc) |
1278 | #define AR_INTR_PRIO_ASYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4094 : 0x40d4) |
1279 | #define AR_ENT_OTP 0x40d8 |
1280 | #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 |
1281 | #define AR_ENT_OTP_49GHZ_DISABLE 0x00100000 |
1282 | #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 |
1283 | |
1284 | #define AR_CH0_BB_DPLL1 0x16180 |
1285 | #define AR_CH0_BB_DPLL1_REFDIV 0xF8000000 |
1286 | #define AR_CH0_BB_DPLL1_REFDIV_S 27 |
1287 | #define AR_CH0_BB_DPLL1_NINI 0x07FC0000 |
1288 | #define AR_CH0_BB_DPLL1_NINI_S 18 |
1289 | #define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF |
1290 | #define AR_CH0_BB_DPLL1_NFRAC_S 0 |
1291 | |
1292 | #define AR_CH0_BB_DPLL2 0x16184 |
1293 | #define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000 |
1294 | #define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30 |
1295 | #define AR_CH0_DPLL2_KI 0x3C000000 |
1296 | #define AR_CH0_DPLL2_KI_S 26 |
1297 | #define AR_CH0_DPLL2_KD 0x03F80000 |
1298 | #define AR_CH0_DPLL2_KD_S 19 |
1299 | #define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000 |
1300 | #define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18 |
1301 | #define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000 |
1302 | #define AR_CH0_BB_DPLL2_PLL_PWD_S 16 |
1303 | #define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000 |
1304 | #define AR_CH0_BB_DPLL2_OUTDIV_S 13 |
1305 | |
1306 | #define AR_CH0_BB_DPLL3 0x16188 |
1307 | #define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000 |
1308 | #define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23 |
1309 | |
1310 | #define AR_CH0_DDR_DPLL2 0x16244 |
1311 | #define AR_CH0_DDR_DPLL3 0x16248 |
1312 | #define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000 |
1313 | #define AR_CH0_DPLL3_PHASE_SHIFT_S 23 |
1314 | #define AR_PHY_CCA_NOM_VAL_2GHZ -118 |
1315 | |
1316 | #define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f |
1317 | #define AR_RTC_9300_SOC_PLL_DIV_INT_S 0 |
1318 | #define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0 |
1319 | #define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6 |
1320 | #define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000 |
1321 | #define AR_RTC_9300_SOC_PLL_REFDIV_S 20 |
1322 | #define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000 |
1323 | #define AR_RTC_9300_SOC_PLL_CLKSEL_S 25 |
1324 | #define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000 |
1325 | |
1326 | #define AR_RTC_9300_PLL_DIV 0x000003ff |
1327 | #define AR_RTC_9300_PLL_DIV_S 0 |
1328 | #define AR_RTC_9300_PLL_REFDIV 0x00003C00 |
1329 | #define AR_RTC_9300_PLL_REFDIV_S 10 |
1330 | #define AR_RTC_9300_PLL_CLKSEL 0x0000C000 |
1331 | #define AR_RTC_9300_PLL_CLKSEL_S 14 |
1332 | #define AR_RTC_9300_PLL_BYPASS 0x00010000 |
1333 | |
1334 | #define AR_RTC_9160_PLL_DIV 0x000003ff |
1335 | #define AR_RTC_9160_PLL_DIV_S 0 |
1336 | #define AR_RTC_9160_PLL_REFDIV 0x00003C00 |
1337 | #define AR_RTC_9160_PLL_REFDIV_S 10 |
1338 | #define AR_RTC_9160_PLL_CLKSEL 0x0000C000 |
1339 | #define AR_RTC_9160_PLL_CLKSEL_S 14 |
1340 | |
1341 | #define AR_RTC_BASE 0x00020000 |
1342 | #define AR_RTC_RC(_ah) \ |
1343 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000) |
1344 | #define AR_RTC_RC_M 0x00000003 |
1345 | #define AR_RTC_RC_MAC_WARM 0x00000001 |
1346 | #define AR_RTC_RC_MAC_COLD 0x00000002 |
1347 | #define AR_RTC_RC_COLD_RESET 0x00000004 |
1348 | #define AR_RTC_RC_WARM_RESET 0x00000008 |
1349 | |
1350 | /* Crystal Control */ |
1351 | #define AR_RTC_XTAL_CONTROL 0x7004 |
1352 | |
1353 | /* Reg Control 0 */ |
1354 | #define AR_RTC_REG_CONTROL0 0x7008 |
1355 | |
1356 | /* Reg Control 1 */ |
1357 | #define AR_RTC_REG_CONTROL1 0x700c |
1358 | #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 |
1359 | |
1360 | #define AR_RTC_PLL_CONTROL(_ah) \ |
1361 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) |
1362 | |
1363 | #define AR_RTC_PLL_CONTROL2 0x703c |
1364 | |
1365 | #define AR_RTC_PLL_DIV 0x0000001f |
1366 | #define AR_RTC_PLL_DIV_S 0 |
1367 | #define AR_RTC_PLL_DIV2 0x00000020 |
1368 | #define AR_RTC_PLL_REFDIV_5 0x000000c0 |
1369 | #define AR_RTC_PLL_CLKSEL 0x00000300 |
1370 | #define AR_RTC_PLL_CLKSEL_S 8 |
1371 | #define AR_RTC_PLL_BYPASS 0x00010000 |
1372 | #define AR_RTC_PLL_NOPWD 0x00040000 |
1373 | #define AR_RTC_PLL_NOPWD_S 18 |
1374 | |
1375 | #define PLL3 0x16188 |
1376 | #define PLL3_DO_MEAS_MASK 0x40000000 |
1377 | #define PLL4 0x1618c |
1378 | #define PLL4_MEAS_DONE 0x8 |
1379 | #define SQSUM_DVC_MASK 0x007ffff8 |
1380 | |
1381 | #define AR_RTC_RESET(_ah) \ |
1382 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) |
1383 | #define AR_RTC_RESET_EN (0x00000001) |
1384 | |
1385 | #define AR_RTC_STATUS(_ah) \ |
1386 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) |
1387 | |
1388 | #define AR_RTC_STATUS_M(_ah) \ |
1389 | ((AR_SREV_9100(_ah)) ? 0x0000003f : 0x0000000f) |
1390 | |
1391 | #define AR_RTC_PM_STATUS_M 0x0000000f |
1392 | |
1393 | #define AR_RTC_STATUS_SHUTDOWN 0x00000001 |
1394 | #define AR_RTC_STATUS_ON 0x00000002 |
1395 | #define AR_RTC_STATUS_SLEEP 0x00000004 |
1396 | #define AR_RTC_STATUS_WAKEUP 0x00000008 |
1397 | |
1398 | #define AR_RTC_SLEEP_CLK(_ah) \ |
1399 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) |
1400 | #define AR_RTC_FORCE_DERIVED_CLK 0x2 |
1401 | #define AR_RTC_FORCE_SWREG_PRD 0x00000004 |
1402 | |
1403 | #define AR_RTC_FORCE_WAKE(_ah) \ |
1404 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) |
1405 | #define AR_RTC_FORCE_WAKE_EN 0x00000001 |
1406 | #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 |
1407 | |
1408 | |
1409 | #define AR_RTC_INTR_CAUSE(_ah) \ |
1410 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) |
1411 | |
1412 | #define AR_RTC_INTR_ENABLE(_ah) \ |
1413 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) |
1414 | |
1415 | #define AR_RTC_INTR_MASK(_ah) \ |
1416 | ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) |
1417 | |
1418 | #define AR_RTC_KEEP_AWAKE 0x7034 |
1419 | |
1420 | /* RTC_DERIVED_* - only for AR9100 */ |
1421 | |
1422 | #define AR_RTC_DERIVED_CLK(_ah) \ |
1423 | (AR_SREV_9100(_ah) ? (AR_RTC_BASE + 0x0038) : 0x7038) |
1424 | #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe |
1425 | #define AR_RTC_DERIVED_CLK_PERIOD_S 1 |
1426 | |
1427 | #define AR_SEQ_MASK 0x8060 |
1428 | |
1429 | #define AR_AN_RF2G1_CH0 0x7810 |
1430 | #define AR_AN_RF2G1_CH0_OB 0x03800000 |
1431 | #define AR_AN_RF2G1_CH0_OB_S 23 |
1432 | #define AR_AN_RF2G1_CH0_DB 0x1C000000 |
1433 | #define AR_AN_RF2G1_CH0_DB_S 26 |
1434 | |
1435 | #define AR_AN_RF5G1_CH0 0x7818 |
1436 | #define AR_AN_RF5G1_CH0_OB5 0x00070000 |
1437 | #define AR_AN_RF5G1_CH0_OB5_S 16 |
1438 | #define AR_AN_RF5G1_CH0_DB5 0x00380000 |
1439 | #define AR_AN_RF5G1_CH0_DB5_S 19 |
1440 | |
1441 | #define AR_AN_RF2G1_CH1 0x7834 |
1442 | #define AR_AN_RF2G1_CH1_OB 0x03800000 |
1443 | #define AR_AN_RF2G1_CH1_OB_S 23 |
1444 | #define AR_AN_RF2G1_CH1_DB 0x1C000000 |
1445 | #define AR_AN_RF2G1_CH1_DB_S 26 |
1446 | |
1447 | #define AR_AN_RF5G1_CH1 0x783C |
1448 | #define AR_AN_RF5G1_CH1_OB5 0x00070000 |
1449 | #define AR_AN_RF5G1_CH1_OB5_S 16 |
1450 | #define AR_AN_RF5G1_CH1_DB5 0x00380000 |
1451 | #define AR_AN_RF5G1_CH1_DB5_S 19 |
1452 | |
1453 | #define AR_AN_TOP1 0x7890 |
1454 | #define AR_AN_TOP1_DACIPMODE 0x00040000 |
1455 | #define AR_AN_TOP1_DACIPMODE_S 18 |
1456 | |
1457 | #define AR_AN_TOP2 0x7894 |
1458 | #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 |
1459 | #define AR_AN_TOP2_XPABIAS_LVL_S 30 |
1460 | #define AR_AN_TOP2_LOCALBIAS 0x00200000 |
1461 | #define AR_AN_TOP2_LOCALBIAS_S 21 |
1462 | #define AR_AN_TOP2_PWDCLKIND 0x00400000 |
1463 | #define AR_AN_TOP2_PWDCLKIND_S 22 |
1464 | |
1465 | #define AR_AN_SYNTH9 0x7868 |
1466 | #define AR_AN_SYNTH9_REFDIVA 0xf8000000 |
1467 | #define AR_AN_SYNTH9_REFDIVA_S 27 |
1468 | |
1469 | #define AR9285_AN_RF2G1 0x7820 |
1470 | #define AR9285_AN_RF2G1_ENPACAL 0x00000800 |
1471 | #define AR9285_AN_RF2G1_ENPACAL_S 11 |
1472 | #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 |
1473 | #define AR9285_AN_RF2G1_PDPADRV1_S 25 |
1474 | #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 |
1475 | #define AR9285_AN_RF2G1_PDPADRV2_S 24 |
1476 | #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 |
1477 | #define AR9285_AN_RF2G1_PDPAOUT_S 23 |
1478 | |
1479 | |
1480 | #define AR9285_AN_RF2G2 0x7824 |
1481 | #define AR9285_AN_RF2G2_OFFCAL 0x00001000 |
1482 | #define AR9285_AN_RF2G2_OFFCAL_S 12 |
1483 | |
1484 | #define AR9285_AN_RF2G3 0x7828 |
1485 | #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 |
1486 | #define AR9285_AN_RF2G3_PDVCCOMP_S 25 |
1487 | #define AR9285_AN_RF2G3_OB_0 0x00E00000 |
1488 | #define AR9285_AN_RF2G3_OB_0_S 21 |
1489 | #define AR9285_AN_RF2G3_OB_1 0x001C0000 |
1490 | #define AR9285_AN_RF2G3_OB_1_S 18 |
1491 | #define AR9285_AN_RF2G3_OB_2 0x00038000 |
1492 | #define AR9285_AN_RF2G3_OB_2_S 15 |
1493 | #define AR9285_AN_RF2G3_OB_3 0x00007000 |
1494 | #define AR9285_AN_RF2G3_OB_3_S 12 |
1495 | #define AR9285_AN_RF2G3_OB_4 0x00000E00 |
1496 | #define AR9285_AN_RF2G3_OB_4_S 9 |
1497 | |
1498 | #define AR9285_AN_RF2G3_DB1_0 0x000001C0 |
1499 | #define AR9285_AN_RF2G3_DB1_0_S 6 |
1500 | #define AR9285_AN_RF2G3_DB1_1 0x00000038 |
1501 | #define AR9285_AN_RF2G3_DB1_1_S 3 |
1502 | #define AR9285_AN_RF2G3_DB1_2 0x00000007 |
1503 | #define AR9285_AN_RF2G3_DB1_2_S 0 |
1504 | #define AR9285_AN_RF2G4 0x782C |
1505 | #define AR9285_AN_RF2G4_DB1_3 0xE0000000 |
1506 | #define AR9285_AN_RF2G4_DB1_3_S 29 |
1507 | #define AR9285_AN_RF2G4_DB1_4 0x1C000000 |
1508 | #define AR9285_AN_RF2G4_DB1_4_S 26 |
1509 | |
1510 | #define AR9285_AN_RF2G4_DB2_0 0x03800000 |
1511 | #define AR9285_AN_RF2G4_DB2_0_S 23 |
1512 | #define AR9285_AN_RF2G4_DB2_1 0x00700000 |
1513 | #define AR9285_AN_RF2G4_DB2_1_S 20 |
1514 | #define AR9285_AN_RF2G4_DB2_2 0x000E0000 |
1515 | #define AR9285_AN_RF2G4_DB2_2_S 17 |
1516 | #define AR9285_AN_RF2G4_DB2_3 0x0001C000 |
1517 | #define AR9285_AN_RF2G4_DB2_3_S 14 |
1518 | #define AR9285_AN_RF2G4_DB2_4 0x00003800 |
1519 | #define AR9285_AN_RF2G4_DB2_4_S 11 |
1520 | |
1521 | #define AR9285_RF2G5 0x7830 |
1522 | #define AR9285_RF2G5_IC50TX 0xfffff8ff |
1523 | #define AR9285_RF2G5_IC50TX_SET 0x00000400 |
1524 | #define AR9285_RF2G5_IC50TX_XE_SET 0x00000500 |
1525 | #define AR9285_RF2G5_IC50TX_CLEAR 0x00000700 |
1526 | #define AR9285_RF2G5_IC50TX_CLEAR_S 8 |
1527 | |
1528 | /* AR9271 : 0x7828, 0x782c different setting from AR9285 */ |
1529 | #define AR9271_AN_RF2G3_OB_cck 0x001C0000 |
1530 | #define AR9271_AN_RF2G3_OB_cck_S 18 |
1531 | #define AR9271_AN_RF2G3_OB_psk 0x00038000 |
1532 | #define AR9271_AN_RF2G3_OB_psk_S 15 |
1533 | #define AR9271_AN_RF2G3_OB_qam 0x00007000 |
1534 | #define AR9271_AN_RF2G3_OB_qam_S 12 |
1535 | |
1536 | #define AR9271_AN_RF2G3_DB_1 0x00E00000 |
1537 | #define AR9271_AN_RF2G3_DB_1_S 21 |
1538 | |
1539 | #define AR9271_AN_RF2G3_CCOMP 0xFFF |
1540 | #define AR9271_AN_RF2G3_CCOMP_S 0 |
1541 | |
1542 | #define AR9271_AN_RF2G4_DB_2 0xE0000000 |
1543 | #define AR9271_AN_RF2G4_DB_2_S 29 |
1544 | |
1545 | #define AR9285_AN_RF2G6 0x7834 |
1546 | #define AR9285_AN_RF2G6_CCOMP 0x00007800 |
1547 | #define AR9285_AN_RF2G6_CCOMP_S 11 |
1548 | #define AR9285_AN_RF2G6_OFFS 0x03f00000 |
1549 | #define AR9285_AN_RF2G6_OFFS_S 20 |
1550 | |
1551 | #define AR9271_AN_RF2G6_OFFS 0x07f00000 |
1552 | #define AR9271_AN_RF2G6_OFFS_S 20 |
1553 | |
1554 | #define AR9285_AN_RF2G7 0x7838 |
1555 | #define AR9285_AN_RF2G7_PWDDB 0x00000002 |
1556 | #define AR9285_AN_RF2G7_PWDDB_S 1 |
1557 | #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 |
1558 | #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 |
1559 | |
1560 | #define AR9285_AN_RF2G8 0x783C |
1561 | #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 |
1562 | #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 |
1563 | |
1564 | |
1565 | #define AR9285_AN_RF2G9 0x7840 |
1566 | #define AR9285_AN_RXTXBB1 0x7854 |
1567 | #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 |
1568 | #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 |
1569 | #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 |
1570 | #define AR9285_AN_RXTXBB1_PDV2I_S 7 |
1571 | #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 |
1572 | #define AR9285_AN_RXTXBB1_PDDACIF_S 8 |
1573 | #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 |
1574 | #define AR9285_AN_RXTXBB1_SPARE9_S 0 |
1575 | |
1576 | #define AR9285_AN_TOP2 0x7868 |
1577 | |
1578 | #define AR9285_AN_TOP3 0x786c |
1579 | #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C |
1580 | #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 |
1581 | #define AR9285_AN_TOP3_PWDDAC 0x00800000 |
1582 | #define AR9285_AN_TOP3_PWDDAC_S 23 |
1583 | |
1584 | #define AR9285_AN_TOP4 0x7870 |
1585 | #define AR9285_AN_TOP4_DEFAULT 0x10142c00 |
1586 | |
1587 | #define AR9287_AN_RF2G3_CH0 0x7808 |
1588 | #define AR9287_AN_RF2G3_CH1 0x785c |
1589 | #define AR9287_AN_RF2G3_DB1 0xE0000000 |
1590 | #define AR9287_AN_RF2G3_DB1_S 29 |
1591 | #define AR9287_AN_RF2G3_DB2 0x1C000000 |
1592 | #define AR9287_AN_RF2G3_DB2_S 26 |
1593 | #define AR9287_AN_RF2G3_OB_CCK 0x03800000 |
1594 | #define AR9287_AN_RF2G3_OB_CCK_S 23 |
1595 | #define AR9287_AN_RF2G3_OB_PSK 0x00700000 |
1596 | #define AR9287_AN_RF2G3_OB_PSK_S 20 |
1597 | #define AR9287_AN_RF2G3_OB_QAM 0x000E0000 |
1598 | #define AR9287_AN_RF2G3_OB_QAM_S 17 |
1599 | #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000 |
1600 | #define AR9287_AN_RF2G3_OB_PAL_OFF_S 14 |
1601 | |
1602 | #define AR9287_AN_TXPC0 0x7898 |
1603 | #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000 |
1604 | #define AR9287_AN_TXPC0_TXPCMODE_S 14 |
1605 | #define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0 |
1606 | #define AR9287_AN_TXPC0_TXPCMODE_TEST 1 |
1607 | #define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2 |
1608 | #define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3 |
1609 | |
1610 | #define AR9287_AN_TOP2 0x78b4 |
1611 | #define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000 |
1612 | #define AR9287_AN_TOP2_XPABIAS_LVL_S 30 |
1613 | |
1614 | /* AR9271 specific stuff */ |
1615 | #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 |
1616 | #define AR9271_RADIO_RF_RST 0x20 |
1617 | #define AR9271_GATE_MAC_CTL 0x4000 |
1618 | |
1619 | #define AR_STA_ID1_STA_AP 0x00010000 |
1620 | #define AR_STA_ID1_ADHOC 0x00020000 |
1621 | #define AR_STA_ID1_PWR_SAV 0x00040000 |
1622 | #define AR_STA_ID1_KSRCHDIS 0x00080000 |
1623 | #define AR_STA_ID1_PCF 0x00100000 |
1624 | #define AR_STA_ID1_USE_DEFANT 0x00200000 |
1625 | #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 |
1626 | #define AR_STA_ID1_AR9100_BA_FIX 0x00400000 |
1627 | #define AR_STA_ID1_RTS_USE_DEF 0x00800000 |
1628 | #define AR_STA_ID1_ACKCTS_6MB 0x01000000 |
1629 | #define AR_STA_ID1_BASE_RATE_11B 0x02000000 |
1630 | #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 |
1631 | #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 |
1632 | #define AR_STA_ID1_KSRCH_MODE 0x10000000 |
1633 | #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 |
1634 | #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 |
1635 | #define AR_STA_ID1_MCAST_KSRCH 0x80000000 |
1636 | |
1637 | #define AR_BSS_ID0 0x8008 |
1638 | #define AR_BSS_ID1 0x800C |
1639 | #define AR_BSS_ID1_U16 0x0000FFFF |
1640 | #define AR_BSS_ID1_AID 0x07FF0000 |
1641 | #define AR_BSS_ID1_AID_S 16 |
1642 | |
1643 | #define 0x8010 |
1644 | #define 0x00000FFF |
1645 | |
1646 | #define AR_TIME_OUT 0x8014 |
1647 | #define AR_TIME_OUT_ACK 0x00003FFF |
1648 | #define AR_TIME_OUT_ACK_S 0 |
1649 | #define AR_TIME_OUT_CTS 0x3FFF0000 |
1650 | #define AR_TIME_OUT_CTS_S 16 |
1651 | |
1652 | #define 0x8018 |
1653 | #define 0x000000FF |
1654 | #define 0x0000FF00 |
1655 | #define 8 |
1656 | #define 0x1F000000 |
1657 | #define 24 |
1658 | #define 0x20000000 |
1659 | |
1660 | #define AR_USEC 0x801c |
1661 | #define AR_USEC_USEC 0x0000007F |
1662 | #define AR_USEC_TX_LAT 0x007FC000 |
1663 | #define AR_USEC_TX_LAT_S 14 |
1664 | #define AR_USEC_RX_LAT 0x1F800000 |
1665 | #define AR_USEC_RX_LAT_S 23 |
1666 | #define AR_USEC_ASYNC_FIFO 0x12E00074 |
1667 | |
1668 | #define AR_RESET_TSF 0x8020 |
1669 | #define AR_RESET_TSF_ONCE 0x01000000 |
1670 | #define AR_RESET_TSF2_ONCE 0x02000000 |
1671 | |
1672 | #define AR_MAX_CFP_DUR 0x8038 |
1673 | #define AR_CFP_VAL 0x0000FFFF |
1674 | |
1675 | #define AR_RX_FILTER 0x803C |
1676 | |
1677 | #define AR_MCAST_FIL0 0x8040 |
1678 | #define AR_MCAST_FIL1 0x8044 |
1679 | |
1680 | /* |
1681 | * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes. |
1682 | * |
1683 | * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with |
1684 | * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down |
1685 | * receive. The force RX abort bit will kill any frame which is currently being |
1686 | * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS) |
1687 | * will prevent any new frames from getting started. |
1688 | */ |
1689 | #define AR_DIAG_SW 0x8048 |
1690 | #define AR_DIAG_CACHE_ACK 0x00000001 |
1691 | #define AR_DIAG_ACK_DIS 0x00000002 |
1692 | #define AR_DIAG_CTS_DIS 0x00000004 |
1693 | #define AR_DIAG_ENCRYPT_DIS 0x00000008 |
1694 | #define AR_DIAG_DECRYPT_DIS 0x00000010 |
1695 | #define AR_DIAG_RX_DIS 0x00000020 /* RX block */ |
1696 | #define AR_DIAG_LOOP_BACK 0x00000040 |
1697 | #define AR_DIAG_CORR_FCS 0x00000080 |
1698 | #define AR_DIAG_CHAN_INFO 0x00000100 |
1699 | #define AR_DIAG_SCRAM_SEED 0x0001FE00 |
1700 | #define AR_DIAG_SCRAM_SEED_S 8 |
1701 | #define AR_DIAG_FRAME_NV0 0x00020000 |
1702 | #define AR_DIAG_OBS_PT_SEL1 0x000C0000 |
1703 | #define AR_DIAG_OBS_PT_SEL1_S 18 |
1704 | #define AR_DIAG_OBS_PT_SEL2 0x08000000 |
1705 | #define AR_DIAG_OBS_PT_SEL2_S 27 |
1706 | #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ |
1707 | #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 |
1708 | #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 |
1709 | #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 |
1710 | #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 |
1711 | #define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */ |
1712 | #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 |
1713 | #define AR_DIAG_OBS_PT_SEL2 0x08000000 |
1714 | #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 |
1715 | #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 |
1716 | |
1717 | #define AR_TSF_L32 0x804c |
1718 | #define AR_TSF_U32 0x8050 |
1719 | |
1720 | #define AR_TST_ADDAC 0x8054 |
1721 | #define AR_DEF_ANTENNA 0x8058 |
1722 | |
1723 | #define AR_AES_MUTE_MASK0 0x805c |
1724 | #define AR_AES_MUTE_MASK0_FC 0x0000FFFF |
1725 | #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 |
1726 | #define AR_AES_MUTE_MASK0_QOS_S 16 |
1727 | |
1728 | #define AR_AES_MUTE_MASK1 0x8060 |
1729 | #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF |
1730 | #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 |
1731 | #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 |
1732 | |
1733 | #define AR_GATED_CLKS 0x8064 |
1734 | #define AR_GATED_CLKS_TX 0x00000002 |
1735 | #define AR_GATED_CLKS_RX 0x00000004 |
1736 | #define AR_GATED_CLKS_REG 0x00000008 |
1737 | |
1738 | #define AR_OBS_BUS_CTRL 0x8068 |
1739 | #define AR_OBS_BUS_SEL_1 0x00040000 |
1740 | #define AR_OBS_BUS_SEL_2 0x00080000 |
1741 | #define AR_OBS_BUS_SEL_3 0x000C0000 |
1742 | #define AR_OBS_BUS_SEL_4 0x08040000 |
1743 | #define AR_OBS_BUS_SEL_5 0x08080000 |
1744 | |
1745 | #define AR_OBS_BUS_1 0x806c |
1746 | #define AR_OBS_BUS_1_PCU 0x00000001 |
1747 | #define AR_OBS_BUS_1_RX_END 0x00000002 |
1748 | #define AR_OBS_BUS_1_RX_WEP 0x00000004 |
1749 | #define AR_OBS_BUS_1_RX_BEACON 0x00000008 |
1750 | #define AR_OBS_BUS_1_RX_FILTER 0x00000010 |
1751 | #define AR_OBS_BUS_1_TX_HCF 0x00000020 |
1752 | #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 |
1753 | #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 |
1754 | #define AR_OBS_BUS_1_TX_HOLD 0x00000100 |
1755 | #define AR_OBS_BUS_1_TX_FRAME 0x00000200 |
1756 | #define AR_OBS_BUS_1_RX_FRAME 0x00000400 |
1757 | #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 |
1758 | #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 |
1759 | #define AR_OBS_BUS_1_WEP_STATE_S 12 |
1760 | #define AR_OBS_BUS_1_RX_STATE 0x01F00000 |
1761 | #define AR_OBS_BUS_1_RX_STATE_S 20 |
1762 | #define AR_OBS_BUS_1_TX_STATE 0x7E000000 |
1763 | #define AR_OBS_BUS_1_TX_STATE_S 25 |
1764 | |
1765 | #define AR_LAST_TSTP 0x8080 |
1766 | #define AR_NAV 0x8084 |
1767 | #define AR_RTS_OK 0x8088 |
1768 | #define AR_RTS_FAIL 0x808c |
1769 | #define AR_ACK_FAIL 0x8090 |
1770 | #define AR_FCS_FAIL 0x8094 |
1771 | #define AR_BEACON_CNT 0x8098 |
1772 | |
1773 | #define AR_SLEEP1 0x80d4 |
1774 | #define AR_SLEEP1_ASSUME_DTIM 0x00080000 |
1775 | #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 |
1776 | #define AR_SLEEP1_CAB_TIMEOUT_S 21 |
1777 | |
1778 | #define AR_SLEEP2 0x80d8 |
1779 | #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 |
1780 | #define AR_SLEEP2_BEACON_TIMEOUT_S 21 |
1781 | |
1782 | #define AR_TPC 0x80e8 |
1783 | #define AR_TPC_ACK 0x0000003f |
1784 | #define AR_TPC_ACK_S 0 |
1785 | #define AR_TPC_CTS 0x00003f00 |
1786 | #define AR_TPC_CTS_S 8 |
1787 | #define AR_TPC_CHIRP 0x003f0000 |
1788 | #define AR_TPC_CHIRP_S 16 |
1789 | #define AR_TPC_RPT 0x3f000000 |
1790 | #define AR_TPC_RPT_S 24 |
1791 | |
1792 | #define AR_QUIET1 0x80fc |
1793 | #define AR_QUIET1_NEXT_QUIET_S 0 |
1794 | #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff |
1795 | #define AR_QUIET1_QUIET_ENABLE 0x00010000 |
1796 | #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 |
1797 | #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 |
1798 | #define AR_QUIET2 0x8100 |
1799 | #define AR_QUIET2_QUIET_PERIOD_S 0 |
1800 | #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff |
1801 | #define AR_QUIET2_QUIET_DUR_S 16 |
1802 | #define AR_QUIET2_QUIET_DUR 0xffff0000 |
1803 | |
1804 | #define AR_TSF_PARM 0x8104 |
1805 | #define AR_TSF_INCREMENT_M 0x000000ff |
1806 | #define AR_TSF_INCREMENT_S 0x00 |
1807 | |
1808 | #define AR_QOS_NO_ACK 0x8108 |
1809 | #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f |
1810 | #define AR_QOS_NO_ACK_TWO_BIT_S 0 |
1811 | #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 |
1812 | #define AR_QOS_NO_ACK_BIT_OFF_S 4 |
1813 | #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 |
1814 | #define AR_QOS_NO_ACK_BYTE_OFF_S 7 |
1815 | |
1816 | #define AR_PHY_ERR 0x810c |
1817 | |
1818 | #define AR_PHY_ERR_DCHIRP 0x00000008 |
1819 | #define AR_PHY_ERR_RADAR 0x00000020 |
1820 | #define AR_PHY_ERR_OFDM_TIMING 0x00020000 |
1821 | #define AR_PHY_ERR_CCK_TIMING 0x02000000 |
1822 | |
1823 | #define AR_RXFIFO_CFG 0x8114 |
1824 | |
1825 | |
1826 | #define AR_MIC_QOS_CONTROL 0x8118 |
1827 | #define AR_MIC_QOS_SELECT 0x811c |
1828 | |
1829 | #define AR_PCU_MISC 0x8120 |
1830 | #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 |
1831 | #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 |
1832 | #define AR_PCU_TX_ADD_TSF 0x00000008 |
1833 | #define AR_PCU_CCK_SIFS_MODE 0x00000010 |
1834 | #define AR_PCU_RX_ANT_UPDT 0x00000800 |
1835 | #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 |
1836 | #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 |
1837 | #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 |
1838 | #define AR_PCU_FORCE_QUIET_COLL 0x00040000 |
1839 | #define AR_PCU_TBTT_PROTECT 0x00200000 |
1840 | #define AR_PCU_CLEAR_VMF 0x01000000 |
1841 | #define AR_PCU_CLEAR_BA_VALID 0x04000000 |
1842 | #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 |
1843 | |
1844 | #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 |
1845 | #define AR_PCU_BT_ANT_PREVENT_RX_S 20 |
1846 | |
1847 | #define AR_FILT_OFDM 0x8124 |
1848 | #define AR_FILT_OFDM_COUNT 0x00FFFFFF |
1849 | |
1850 | #define AR_FILT_CCK 0x8128 |
1851 | #define AR_FILT_CCK_COUNT 0x00FFFFFF |
1852 | |
1853 | #define AR_PHY_ERR_1 0x812c |
1854 | #define AR_PHY_ERR_1_COUNT 0x00FFFFFF |
1855 | #define AR_PHY_ERR_MASK_1 0x8130 |
1856 | |
1857 | #define AR_PHY_ERR_2 0x8134 |
1858 | #define AR_PHY_ERR_2_COUNT 0x00FFFFFF |
1859 | #define AR_PHY_ERR_MASK_2 0x8138 |
1860 | |
1861 | #define AR_PHY_COUNTMAX (3 << 22) |
1862 | #define AR_MIBCNT_INTRMASK (3 << 22) |
1863 | |
1864 | #define AR_TSFOOR_THRESHOLD 0x813c |
1865 | #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF |
1866 | |
1867 | #define AR_PHY_ERR_EIFS_MASK 0x8144 |
1868 | |
1869 | #define AR_PHY_ERR_3 0x8168 |
1870 | #define AR_PHY_ERR_3_COUNT 0x00FFFFFF |
1871 | #define AR_PHY_ERR_MASK_3 0x816c |
1872 | |
1873 | #define AR_BT_COEX_MODE 0x8170 |
1874 | #define AR_BT_TIME_EXTEND 0x000000ff |
1875 | #define AR_BT_TIME_EXTEND_S 0 |
1876 | #define AR_BT_TXSTATE_EXTEND 0x00000100 |
1877 | #define AR_BT_TXSTATE_EXTEND_S 8 |
1878 | #define AR_BT_TX_FRAME_EXTEND 0x00000200 |
1879 | #define AR_BT_TX_FRAME_EXTEND_S 9 |
1880 | #define AR_BT_MODE 0x00000c00 |
1881 | #define AR_BT_MODE_S 10 |
1882 | #define AR_BT_QUIET 0x00001000 |
1883 | #define AR_BT_QUIET_S 12 |
1884 | #define AR_BT_QCU_THRESH 0x0001e000 |
1885 | #define AR_BT_QCU_THRESH_S 13 |
1886 | #define AR_BT_RX_CLEAR_POLARITY 0x00020000 |
1887 | #define AR_BT_RX_CLEAR_POLARITY_S 17 |
1888 | #define AR_BT_PRIORITY_TIME 0x00fc0000 |
1889 | #define AR_BT_PRIORITY_TIME_S 18 |
1890 | #define AR_BT_FIRST_SLOT_TIME 0xff000000 |
1891 | #define AR_BT_FIRST_SLOT_TIME_S 24 |
1892 | |
1893 | #define AR_BT_COEX_WEIGHT 0x8174 |
1894 | #define AR_BT_COEX_WGHT 0xff55 |
1895 | #define AR_STOMP_ALL_WLAN_WGHT 0xfcfc |
1896 | #define AR_STOMP_LOW_WLAN_WGHT 0xa8a8 |
1897 | #define AR_STOMP_NONE_WLAN_WGHT 0x0000 |
1898 | #define AR_BTCOEX_BT_WGHT 0x0000ffff |
1899 | #define AR_BTCOEX_BT_WGHT_S 0 |
1900 | #define AR_BTCOEX_WL_WGHT 0xffff0000 |
1901 | #define AR_BTCOEX_WL_WGHT_S 16 |
1902 | |
1903 | #define AR_BT_COEX_WL_WEIGHTS0 0x8174 |
1904 | #define AR_BT_COEX_WL_WEIGHTS1 0x81c4 |
1905 | #define AR_MCI_COEX_WL_WEIGHTS(_i) (0x18b0 + (_i << 2)) |
1906 | #define AR_BT_COEX_BT_WEIGHTS(_i) (0x83ac + (_i << 2)) |
1907 | |
1908 | #define AR9300_BT_WGHT 0xcccc4444 |
1909 | |
1910 | #define AR_BT_COEX_MODE2 0x817c |
1911 | #define AR_BT_BCN_MISS_THRESH 0x000000ff |
1912 | #define AR_BT_BCN_MISS_THRESH_S 0 |
1913 | #define AR_BT_BCN_MISS_CNT 0x0000ff00 |
1914 | #define AR_BT_BCN_MISS_CNT_S 8 |
1915 | #define AR_BT_HOLD_RX_CLEAR 0x00010000 |
1916 | #define AR_BT_HOLD_RX_CLEAR_S 16 |
1917 | #define AR_BT_PROTECT_BT_AFTER_WAKEUP 0x00080000 |
1918 | #define AR_BT_PROTECT_BT_AFTER_WAKEUP_S 19 |
1919 | #define AR_BT_DISABLE_BT_ANT 0x00100000 |
1920 | #define AR_BT_DISABLE_BT_ANT_S 20 |
1921 | #define AR_BT_QUIET_2_WIRE 0x00200000 |
1922 | #define AR_BT_QUIET_2_WIRE_S 21 |
1923 | #define AR_BT_WL_ACTIVE_MODE 0x00c00000 |
1924 | #define AR_BT_WL_ACTIVE_MODE_S 22 |
1925 | #define AR_BT_WL_TXRX_SEPARATE 0x01000000 |
1926 | #define AR_BT_WL_TXRX_SEPARATE_S 24 |
1927 | #define AR_BT_RS_DISCARD_EXTEND 0x02000000 |
1928 | #define AR_BT_RS_DISCARD_EXTEND_S 25 |
1929 | #define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c000000 |
1930 | #define AR_BT_TSF_BT_ACTIVE_CTRL_S 26 |
1931 | #define AR_BT_TSF_BT_PRIORITY_CTRL 0x30000000 |
1932 | #define AR_BT_TSF_BT_PRIORITY_CTRL_S 28 |
1933 | #define AR_BT_INTERRUPT_ENABLE 0x40000000 |
1934 | #define AR_BT_INTERRUPT_ENABLE_S 30 |
1935 | #define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x80000000 |
1936 | #define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 31 |
1937 | |
1938 | #define AR_TXSIFS 0x81d0 |
1939 | #define AR_TXSIFS_TIME 0x000000FF |
1940 | #define AR_TXSIFS_TX_LATENCY 0x00000F00 |
1941 | #define AR_TXSIFS_TX_LATENCY_S 8 |
1942 | #define AR_TXSIFS_ACK_SHIFT 0x00007000 |
1943 | #define AR_TXSIFS_ACK_SHIFT_S 12 |
1944 | |
1945 | #define AR_BT_COEX_MODE3 0x81d4 |
1946 | #define AR_BT_WL_ACTIVE_TIME 0x000000ff |
1947 | #define AR_BT_WL_ACTIVE_TIME_S 0 |
1948 | #define AR_BT_WL_QC_TIME 0x0000ff00 |
1949 | #define AR_BT_WL_QC_TIME_S 8 |
1950 | #define AR_BT_ALLOW_CONCURRENT_ACCESS 0x000f0000 |
1951 | #define AR_BT_ALLOW_CONCURRENT_ACCESS_S 16 |
1952 | #define AR_BT_AGC_SATURATION_CNT_ENABLE 0x00100000 |
1953 | #define AR_BT_AGC_SATURATION_CNT_ENABLE_S 20 |
1954 | |
1955 | #define AR_TXOP_X 0x81ec |
1956 | #define AR_TXOP_X_VAL 0x000000FF |
1957 | |
1958 | |
1959 | #define AR_TXOP_0_3 0x81f0 |
1960 | #define AR_TXOP_4_7 0x81f4 |
1961 | #define AR_TXOP_8_11 0x81f8 |
1962 | #define AR_TXOP_12_15 0x81fc |
1963 | |
1964 | #define AR_NEXT_NDP2_TIMER 0x8180 |
1965 | #define AR_GEN_TIMER_BANK_1_LEN 8 |
1966 | #define AR_FIRST_NDP_TIMER 7 |
1967 | #define AR_NDP2_PERIOD 0x81a0 |
1968 | #define AR_NDP2_TIMER_MODE 0x81c0 |
1969 | #define AR_GEN_TIMERS2_MODE_ENABLE_MASK 0x000000FF |
1970 | |
1971 | #define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2)) |
1972 | #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) |
1973 | #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) |
1974 | #define AR_NEXT_SWBA AR_GEN_TIMERS(2) |
1975 | #define AR_NEXT_CFP AR_GEN_TIMERS(2) |
1976 | #define AR_NEXT_HCF AR_GEN_TIMERS(3) |
1977 | #define AR_NEXT_TIM AR_GEN_TIMERS(4) |
1978 | #define AR_NEXT_DTIM AR_GEN_TIMERS(5) |
1979 | #define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) |
1980 | #define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) |
1981 | |
1982 | #define AR_BEACON_PERIOD AR_GEN_TIMERS(8) |
1983 | #define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) |
1984 | #define AR_SWBA_PERIOD AR_GEN_TIMERS(10) |
1985 | #define AR_HCF_PERIOD AR_GEN_TIMERS(11) |
1986 | #define AR_TIM_PERIOD AR_GEN_TIMERS(12) |
1987 | #define AR_DTIM_PERIOD AR_GEN_TIMERS(13) |
1988 | #define AR_QUIET_PERIOD AR_GEN_TIMERS(14) |
1989 | #define AR_NDP_PERIOD AR_GEN_TIMERS(15) |
1990 | |
1991 | #define AR_TIMER_MODE 0x8240 |
1992 | #define AR_TBTT_TIMER_EN 0x00000001 |
1993 | #define AR_DBA_TIMER_EN 0x00000002 |
1994 | #define AR_SWBA_TIMER_EN 0x00000004 |
1995 | #define AR_HCF_TIMER_EN 0x00000008 |
1996 | #define AR_TIM_TIMER_EN 0x00000010 |
1997 | #define AR_DTIM_TIMER_EN 0x00000020 |
1998 | #define AR_QUIET_TIMER_EN 0x00000040 |
1999 | #define AR_NDP_TIMER_EN 0x00000080 |
2000 | #define AR_TIMER_OVERFLOW_INDEX 0x00000700 |
2001 | #define AR_TIMER_OVERFLOW_INDEX_S 8 |
2002 | #define AR_TIMER_THRESH 0xFFFFF000 |
2003 | #define AR_TIMER_THRESH_S 12 |
2004 | |
2005 | #define AR_SLP32_MODE 0x8244 |
2006 | #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF |
2007 | #define AR_SLP32_ENA 0x00100000 |
2008 | #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 |
2009 | |
2010 | #define AR_SLP32_WAKE 0x8248 |
2011 | #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF |
2012 | |
2013 | #define AR_SLP32_INC 0x824c |
2014 | #define AR_SLP32_TST_INC 0x000FFFFF |
2015 | |
2016 | #define AR_SLP_CNT 0x8250 |
2017 | #define AR_SLP_CYCLE_CNT 0x8254 |
2018 | |
2019 | #define AR_SLP_MIB_CTRL 0x8258 |
2020 | #define AR_SLP_MIB_CLEAR 0x00000001 |
2021 | #define AR_SLP_MIB_PENDING 0x00000002 |
2022 | |
2023 | #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 |
2024 | #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 |
2025 | |
2026 | |
2027 | #define AR_2040_MODE 0x8318 |
2028 | #define AR_2040_JOINED_RX_CLEAR 0x00000001 |
2029 | |
2030 | |
2031 | #define AR_EXTRCCNT 0x8328 |
2032 | |
2033 | #define AR_SELFGEN_MASK 0x832c |
2034 | |
2035 | #define AR_PCU_TXBUF_CTRL 0x8340 |
2036 | #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF |
2037 | #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 |
2038 | #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 |
2039 | #define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE 0x500 |
2040 | |
2041 | #define AR_PCU_MISC_MODE2 0x8344 |
2042 | #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 |
2043 | #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 |
2044 | |
2045 | #define AR_PCU_MISC_MODE2_RESERVED 0x00000038 |
2046 | #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 |
2047 | #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 |
2048 | #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 |
2049 | #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 |
2050 | #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 |
2051 | #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 |
2052 | #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 |
2053 | #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 |
2054 | #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 |
2055 | |
2056 | #define AR_PCU_MISC_MODE3 0x83d0 |
2057 | |
2058 | #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 |
2059 | #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 |
2060 | #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 |
2061 | #define AR_MAC_PCU_GEN_TIMER_TSF_SEL 0x83d8 |
2062 | |
2063 | #define AR_DIRECT_CONNECT 0x83a0 |
2064 | #define AR_DC_AP_STA_EN 0x00000001 |
2065 | #define AR_DC_TSF2_ENABLE 0x00000001 |
2066 | |
2067 | #define AR_AES_MUTE_MASK0 0x805c |
2068 | #define AR_AES_MUTE_MASK0_FC 0x0000FFFF |
2069 | #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 |
2070 | #define AR_AES_MUTE_MASK0_QOS_S 16 |
2071 | |
2072 | #define AR_AES_MUTE_MASK1 0x8060 |
2073 | #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF |
2074 | #define AR_AES_MUTE_MASK1_SEQ_S 0 |
2075 | #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 |
2076 | #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 |
2077 | |
2078 | #define AR_RATE_DURATION_0 0x8700 |
2079 | #define AR_RATE_DURATION_31 0x87CC |
2080 | #define AR_RATE_DURATION_32 0x8780 |
2081 | #define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) |
2082 | |
2083 | /* WoW - Wake On Wireless */ |
2084 | |
2085 | #define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */ |
2086 | #define AR_PMCTRL_D3COLD_VAUX 0x00800000 |
2087 | #define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW |
2088 | event */ |
2089 | #define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */ |
2090 | #define AR_PMCTRL_PWR_STATE_MASK 0x0f000000 /* Power State Mask */ |
2091 | #define AR_PMCTRL_PWR_STATE_D1D3 0x0f000000 /* Activate D1 and D3 */ |
2092 | #define AR_PMCTRL_PWR_STATE_D1D3_REAL 0x0f000000 /* Activate D1 and D3 */ |
2093 | #define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */ |
2094 | #define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power mgmt */ |
2095 | |
2096 | #define AR_WOW_BEACON_TIMO_MAX 0xffffffff |
2097 | |
2098 | #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ |
2099 | #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ |
2100 | |
2101 | #define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */ |
2102 | #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search |
2103 | * based on both MAC Address and Key ID. |
2104 | * If bit is 0, then Multicast search is |
2105 | * based on MAC address only. |
2106 | * For Merlin and above only. |
2107 | */ |
2108 | #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, |
2109 | * when it is enable, AGG_WEP would takes |
2110 | * charge of the encryption interface of |
2111 | * pcu_txsm. |
2112 | */ |
2113 | |
2114 | #define AR9300_SM_BASE 0xa200 |
2115 | #define AR9002_PHY_AGC_CONTROL 0x9860 |
2116 | #define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4 |
2117 | #define AR_PHY_AGC_CONTROL(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL) |
2118 | #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ |
2119 | #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ |
2120 | #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ |
2121 | #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ |
2122 | #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ |
2123 | #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ |
2124 | #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ |
2125 | #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ |
2126 | #define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 |
2127 | #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 |
2128 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 |
2129 | |
2130 | #endif |
2131 | |