| 1 | /* |
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| 2 | * Copyright (c) 2015 Qualcomm Atheros Inc. |
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| 3 | * |
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| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
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| 5 | * purpose with or without fee is hereby granted, provided that the above |
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| 6 | * copyright notice and this permission notice appear in all copies. |
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| 7 | * |
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| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef REG_MCI_H |
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| 18 | #define REG_MCI_H |
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| 19 | |
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| 20 | #define AR_MCI_COMMAND0 0x1800 |
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| 21 | #define AR_MCI_COMMAND0_HEADER 0xFF |
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| 22 | #define AR_MCI_COMMAND0_HEADER_S 0 |
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| 23 | #define AR_MCI_COMMAND0_LEN 0x1f00 |
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| 24 | #define AR_MCI_COMMAND0_LEN_S 8 |
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| 25 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 |
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| 26 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 |
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| 27 | |
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| 28 | #define AR_MCI_COMMAND1 0x1804 |
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| 29 | |
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| 30 | #define AR_MCI_COMMAND2 0x1808 |
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| 31 | #define AR_MCI_COMMAND2_RESET_TX 0x01 |
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| 32 | #define AR_MCI_COMMAND2_RESET_TX_S 0 |
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| 33 | #define AR_MCI_COMMAND2_RESET_RX 0x02 |
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| 34 | #define AR_MCI_COMMAND2_RESET_RX_S 1 |
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| 35 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC |
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| 36 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 |
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| 37 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 |
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| 38 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 |
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| 39 | |
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| 40 | #define AR_MCI_RX_CTRL 0x180c |
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| 41 | |
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| 42 | #define AR_MCI_TX_CTRL 0x1810 |
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| 43 | /* |
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| 44 | * 0 = no division, |
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| 45 | * 1 = divide by 2, |
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| 46 | * 2 = divide by 4, |
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| 47 | * 3 = divide by 8 |
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| 48 | */ |
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| 49 | #define AR_MCI_TX_CTRL_CLK_DIV 0x03 |
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| 50 | #define AR_MCI_TX_CTRL_CLK_DIV_S 0 |
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| 51 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 |
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| 52 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 |
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| 53 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 |
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| 54 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 |
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| 55 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 |
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| 56 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 |
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| 57 | |
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| 58 | #define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814 |
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| 59 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF |
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| 60 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 |
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| 61 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 |
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| 62 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 |
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| 63 | |
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| 64 | #define AR_MCI_SCHD_TABLE_0 0x1818 |
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| 65 | #define AR_MCI_SCHD_TABLE_1 0x181c |
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| 66 | #define AR_MCI_GPM_0 0x1820 |
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| 67 | #define AR_MCI_GPM_1 0x1824 |
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| 68 | #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 |
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| 69 | #define AR_MCI_GPM_WRITE_PTR_S 16 |
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| 70 | #define AR_MCI_GPM_BUF_LEN 0x0000FFFF |
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| 71 | #define AR_MCI_GPM_BUF_LEN_S 0 |
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| 72 | |
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| 73 | #define AR_MCI_INTERRUPT_RAW 0x1828 |
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| 74 | |
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| 75 | #define AR_MCI_INTERRUPT_EN 0x182c |
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| 76 | #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 |
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| 77 | #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 |
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| 78 | #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 |
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| 79 | #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 |
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| 80 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 |
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| 81 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 |
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| 82 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 |
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| 83 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 |
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| 84 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 |
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| 85 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 |
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| 86 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 |
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| 87 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 |
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| 88 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 |
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| 89 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 |
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| 90 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 |
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| 91 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 |
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| 92 | #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 |
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| 93 | #define AR_MCI_INTERRUPT_RX_MSG_S 9 |
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| 94 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 |
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| 95 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 |
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| 96 | #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 |
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| 97 | #define AR_MCI_INTERRUPT_BT_PRI_S 11 |
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| 98 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 |
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| 99 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 |
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| 100 | #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 |
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| 101 | #define AR_MCI_INTERRUPT_BT_FREQ_S 28 |
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| 102 | #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 |
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| 103 | #define AR_MCI_INTERRUPT_BT_STOMP_S 29 |
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| 104 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 |
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| 105 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 |
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| 106 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 |
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| 107 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 |
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| 108 | |
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| 109 | #define AR_MCI_REMOTE_CPU_INT 0x1830 |
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| 110 | #define AR_MCI_REMOTE_CPU_INT_EN 0x1834 |
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| 111 | #define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838 |
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| 112 | #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c |
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| 113 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 |
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| 114 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 |
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| 115 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 |
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| 116 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 |
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| 117 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 |
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| 118 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 |
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| 119 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 |
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| 120 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 |
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| 121 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 |
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| 122 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 |
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| 123 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 |
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| 124 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 |
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| 125 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 |
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| 126 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 |
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| 127 | #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 |
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| 128 | #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 |
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| 129 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 |
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| 130 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 |
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| 131 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 |
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| 132 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 |
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| 133 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 |
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| 134 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 |
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| 135 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 |
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| 136 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 |
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| 137 | |
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| 138 | #define AR_MCI_CPU_INT 0x1840 |
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| 139 | |
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| 140 | #define AR_MCI_RX_STATUS 0x1844 |
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| 141 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 |
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| 142 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 |
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| 143 | #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 |
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| 144 | #define AR_MCI_RX_REMOTE_SLEEP_S 12 |
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| 145 | #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 |
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| 146 | #define AR_MCI_RX_MCI_CLK_REQ_S 13 |
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| 147 | |
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| 148 | #define AR_MCI_CONT_STATUS 0x1848 |
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| 149 | #define 0x000000FF |
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| 150 | #define 0 |
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| 151 | #define AR_MCI_CONT_PRIORITY 0x0000FF00 |
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| 152 | #define AR_MCI_CONT_PRIORITY_S 8 |
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| 153 | #define AR_MCI_CONT_TXRX 0x00010000 |
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| 154 | #define AR_MCI_CONT_TXRX_S 16 |
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| 155 | |
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| 156 | #define AR_MCI_BT_PRI0 0x184c |
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| 157 | #define AR_MCI_BT_PRI1 0x1850 |
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| 158 | #define AR_MCI_BT_PRI2 0x1854 |
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| 159 | #define AR_MCI_BT_PRI3 0x1858 |
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| 160 | #define AR_MCI_BT_PRI 0x185c |
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| 161 | #define AR_MCI_WL_FREQ0 0x1860 |
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| 162 | #define AR_MCI_WL_FREQ1 0x1864 |
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| 163 | #define AR_MCI_WL_FREQ2 0x1868 |
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| 164 | #define AR_MCI_GAIN 0x186c |
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| 165 | #define AR_MCI_WBTIMER1 0x1870 |
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| 166 | #define AR_MCI_WBTIMER2 0x1874 |
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| 167 | #define AR_MCI_WBTIMER3 0x1878 |
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| 168 | #define AR_MCI_WBTIMER4 0x187c |
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| 169 | #define AR_MCI_MAXGAIN 0x1880 |
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| 170 | #define AR_MCI_HW_SCHD_TBL_CTL 0x1884 |
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| 171 | #define AR_MCI_HW_SCHD_TBL_D0 0x1888 |
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| 172 | #define AR_MCI_HW_SCHD_TBL_D1 0x188c |
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| 173 | #define AR_MCI_HW_SCHD_TBL_D2 0x1890 |
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| 174 | #define AR_MCI_HW_SCHD_TBL_D3 0x1894 |
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| 175 | #define AR_MCI_TX_PAYLOAD0 0x1898 |
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| 176 | #define AR_MCI_TX_PAYLOAD1 0x189c |
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| 177 | #define AR_MCI_TX_PAYLOAD2 0x18a0 |
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| 178 | #define AR_MCI_TX_PAYLOAD3 0x18a4 |
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| 179 | #define AR_BTCOEX_WBTIMER 0x18a8 |
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| 180 | |
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| 181 | #define AR_BTCOEX_CTRL 0x18ac |
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| 182 | #define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001 |
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| 183 | #define AR_BTCOEX_CTRL_AR9462_MODE_S 0 |
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| 184 | #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 |
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| 185 | #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 |
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| 186 | #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 |
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| 187 | #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 |
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| 188 | #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 |
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| 189 | #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 |
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| 190 | #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 |
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| 191 | #define AR_BTCOEX_CTRL_PA_SHARED_S 4 |
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| 192 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 |
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| 193 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 |
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| 194 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 |
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| 195 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 |
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| 196 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 |
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| 197 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 |
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| 198 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 |
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| 199 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 |
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| 200 | #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 |
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| 201 | #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 |
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| 202 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 |
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| 203 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 |
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| 204 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 |
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| 205 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 |
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| 206 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 |
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| 207 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 |
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| 208 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 |
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| 209 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 |
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| 210 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 |
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| 211 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 |
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| 212 | #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 |
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| 213 | #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 |
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| 214 | |
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| 215 | #define AR_BTCOEX_WL_WEIGHTS0 0x18b0 |
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| 216 | #define AR_BTCOEX_WL_WEIGHTS1 0x18b4 |
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| 217 | #define AR_BTCOEX_WL_WEIGHTS2 0x18b8 |
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| 218 | #define AR_BTCOEX_WL_WEIGHTS3 0x18bc |
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| 219 | |
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| 220 | #define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) |
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| 221 | #define AR_BTCOEX_WL_LNA 0x1940 |
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| 222 | #define AR_BTCOEX_RFGAIN_CTRL 0x1944 |
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| 223 | #define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF |
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| 224 | #define AR_BTCOEX_WL_LNA_TIMEOUT_S 0 |
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| 225 | |
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| 226 | #define AR_BTCOEX_CTRL2 0x1948 |
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| 227 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 |
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| 228 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 |
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| 229 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 |
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| 230 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 |
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| 231 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 |
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| 232 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 |
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| 233 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 |
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| 234 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 |
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| 235 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 |
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| 236 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 |
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| 237 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 |
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| 238 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 |
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| 239 | |
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| 240 | #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 |
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| 241 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 |
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| 242 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 |
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| 243 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 |
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| 244 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 |
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| 245 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 |
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| 246 | #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 |
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| 247 | #define AR_GLB_WLAN_UART_INTF_EN_S 17 |
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| 248 | #define AR_GLB_DS_JTAG_DISABLE 0x00040000 |
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| 249 | #define AR_GLB_DS_JTAG_DISABLE_S 18 |
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| 250 | |
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| 251 | #define AR_BTCOEX_RC 0x194c |
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| 252 | #define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2)) |
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| 253 | #define AR_BTCOEX_DBG 0x1a50 |
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| 254 | #define AR_MCI_LAST_HW_MSG_HDR 0x1a54 |
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| 255 | #define AR_MCI_LAST_HW_MSG_BDY 0x1a58 |
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| 256 | |
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| 257 | #define AR_MCI_SCHD_TABLE_2 0x1a5c |
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| 258 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 |
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| 259 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 |
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| 260 | #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 |
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| 261 | #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 |
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| 262 | |
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| 263 | #define AR_BTCOEX_CTRL3 0x1a60 |
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| 264 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff |
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| 265 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 |
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| 266 | |
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| 267 | #define AR_GLB_SWREG_DISCONT_MODE 0x2002c |
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| 268 | #define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3 |
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| 269 | |
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| 270 | #define AR_MCI_MISC 0x1a74 |
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| 271 | #define AR_MCI_MISC_HW_FIX_EN 0x00000001 |
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| 272 | #define AR_MCI_MISC_HW_FIX_EN_S 0 |
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| 273 | |
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| 274 | #define AR_MCI_DBG_CNT_CTRL 0x1a78 |
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| 275 | #define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001 |
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| 276 | #define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0 |
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| 277 | #define AR_MCI_DBG_CNT_CTRL_BT_LINKID 0x000007f8 |
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| 278 | #define AR_MCI_DBG_CNT_CTRL_BT_LINKID_S 3 |
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| 279 | |
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| 280 | #define MCI_STAT_ALL_BT_LINKID 0xffff |
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| 281 | |
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| 282 | #define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \ |
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| 283 | AR_MCI_INTERRUPT_RX_INVALID_HDR | \ |
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| 284 | AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ |
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| 285 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ |
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| 286 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ |
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| 287 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ |
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| 288 | AR_MCI_INTERRUPT_RX_MSG | \ |
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| 289 | AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ |
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| 290 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT) |
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| 291 | |
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| 292 | #define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ |
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| 293 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ |
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| 294 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ |
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| 295 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL) |
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| 296 | |
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| 297 | #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ |
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| 298 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ |
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| 299 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ |
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| 300 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ |
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| 301 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ |
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| 302 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST) |
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| 303 | |
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| 304 | #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \ |
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| 305 | AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \ |
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| 306 | AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ |
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| 307 | AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \ |
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| 308 | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) |
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| 309 | |
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| 310 | #endif /* REG_MCI_H */ |
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| 311 | |
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