| 1 | /* |
|---|
| 2 | * Shared Atheros AR9170 Header |
|---|
| 3 | * |
|---|
| 4 | * PHY register map |
|---|
| 5 | * |
|---|
| 6 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
|---|
| 7 | * |
|---|
| 8 | * Permission to use, copy, modify, and/or distribute this software for any |
|---|
| 9 | * purpose with or without fee is hereby granted, provided that the above |
|---|
| 10 | * copyright notice and this permission notice appear in all copies. |
|---|
| 11 | * |
|---|
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
|---|
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
|---|
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
|---|
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
|---|
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
|---|
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
|---|
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
|---|
| 19 | */ |
|---|
| 20 | |
|---|
| 21 | #ifndef __CARL9170_SHARED_PHY_H |
|---|
| 22 | #define __CARL9170_SHARED_PHY_H |
|---|
| 23 | |
|---|
| 24 | #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800) |
|---|
| 25 | #define AR9170_PHY_REG(_n) (AR9170_PHY_REG_BASE + \ |
|---|
| 26 | ((_n) << 2)) |
|---|
| 27 | |
|---|
| 28 | #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000) |
|---|
| 29 | #define AR9170_PHY_TEST_AGC_CLR 0x10000000 |
|---|
| 30 | #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000 |
|---|
| 31 | |
|---|
| 32 | #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004) |
|---|
| 33 | #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001 |
|---|
| 34 | #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002 |
|---|
| 35 | #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004 |
|---|
| 36 | #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008 |
|---|
| 37 | #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010 |
|---|
| 38 | /* For 25 MHz channel spacing -- not used but supported by hw */ |
|---|
| 39 | #define AR9170_PHY_TURBO_FC_DYN2040_EXT_CH 0x00000020 |
|---|
| 40 | #define AR9170_PHY_TURBO_FC_HT_EN 0x00000040 |
|---|
| 41 | #define AR9170_PHY_TURBO_FC_SHORT_GI_40 0x00000080 |
|---|
| 42 | #define AR9170_PHY_TURBO_FC_WALSH 0x00000100 |
|---|
| 43 | #define AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 0x00000200 |
|---|
| 44 | #define AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO 0x00000800 |
|---|
| 45 | |
|---|
| 46 | #define AR9170_PHY_REG_TEST2 (AR9170_PHY_REG_BASE + 0x0008) |
|---|
| 47 | |
|---|
| 48 | #define AR9170_PHY_REG_TIMING2 (AR9170_PHY_REG_BASE + 0x0010) |
|---|
| 49 | #define AR9170_PHY_TIMING2_USE_FORCE 0x00001000 |
|---|
| 50 | #define AR9170_PHY_TIMING2_FORCE 0x00000fff |
|---|
| 51 | #define AR9170_PHY_TIMING2_FORCE_S 0 |
|---|
| 52 | |
|---|
| 53 | #define AR9170_PHY_REG_TIMING3 (AR9170_PHY_REG_BASE + 0x0014) |
|---|
| 54 | #define AR9170_PHY_TIMING3_DSC_EXP 0x0001e000 |
|---|
| 55 | #define AR9170_PHY_TIMING3_DSC_EXP_S 13 |
|---|
| 56 | #define AR9170_PHY_TIMING3_DSC_MAN 0xfffe0000 |
|---|
| 57 | #define AR9170_PHY_TIMING3_DSC_MAN_S 17 |
|---|
| 58 | |
|---|
| 59 | #define AR9170_PHY_REG_CHIP_ID (AR9170_PHY_REG_BASE + 0x0018) |
|---|
| 60 | #define AR9170_PHY_CHIP_ID_REV_0 0x80 |
|---|
| 61 | #define AR9170_PHY_CHIP_ID_REV_1 0x81 |
|---|
| 62 | #define AR9170_PHY_CHIP_ID_9160_REV_0 0xb0 |
|---|
| 63 | |
|---|
| 64 | #define AR9170_PHY_REG_ACTIVE (AR9170_PHY_REG_BASE + 0x001c) |
|---|
| 65 | #define AR9170_PHY_ACTIVE_EN 0x00000001 |
|---|
| 66 | #define AR9170_PHY_ACTIVE_DIS 0x00000000 |
|---|
| 67 | |
|---|
| 68 | #define AR9170_PHY_REG_RF_CTL2 (AR9170_PHY_REG_BASE + 0x0024) |
|---|
| 69 | #define AR9170_PHY_RF_CTL2_TX_END_DATA_START 0x000000ff |
|---|
| 70 | #define AR9170_PHY_RF_CTL2_TX_END_DATA_START_S 0 |
|---|
| 71 | #define AR9170_PHY_RF_CTL2_TX_END_PA_ON 0x0000ff00 |
|---|
| 72 | #define AR9170_PHY_RF_CTL2_TX_END_PA_ON_S 8 |
|---|
| 73 | |
|---|
| 74 | #define AR9170_PHY_REG_RF_CTL3 (AR9170_PHY_REG_BASE + 0x0028) |
|---|
| 75 | #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON 0x00ff0000 |
|---|
| 76 | #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 16 |
|---|
| 77 | |
|---|
| 78 | #define AR9170_PHY_REG_ADC_CTL (AR9170_PHY_REG_BASE + 0x002c) |
|---|
| 79 | #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 |
|---|
| 80 | #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 |
|---|
| 81 | #define AR9170_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 |
|---|
| 82 | #define AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 |
|---|
| 83 | #define AR9170_PHY_ADC_CTL_OFF_PWDADC 0x00008000 |
|---|
| 84 | #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 |
|---|
| 85 | #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S 16 |
|---|
| 86 | |
|---|
| 87 | #define AR9170_PHY_REG_ADC_SERIAL_CTL (AR9170_PHY_REG_BASE + 0x0030) |
|---|
| 88 | #define AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC 0x00000000 |
|---|
| 89 | #define AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO 0x00000001 |
|---|
| 90 | |
|---|
| 91 | #define AR9170_PHY_REG_RF_CTL4 (AR9170_PHY_REG_BASE + 0x0034) |
|---|
| 92 | #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF 0xff000000 |
|---|
| 93 | #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 |
|---|
| 94 | #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00ff0000 |
|---|
| 95 | #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 |
|---|
| 96 | #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000ff00 |
|---|
| 97 | #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 |
|---|
| 98 | #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000ff |
|---|
| 99 | #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 |
|---|
| 100 | |
|---|
| 101 | #define AR9170_PHY_REG_TSTDAC_CONST (AR9170_PHY_REG_BASE + 0x003c) |
|---|
| 102 | |
|---|
| 103 | #define AR9170_PHY_REG_SETTLING (AR9170_PHY_REG_BASE + 0x0044) |
|---|
| 104 | #define AR9170_PHY_SETTLING_SWITCH 0x00003f80 |
|---|
| 105 | #define AR9170_PHY_SETTLING_SWITCH_S 7 |
|---|
| 106 | |
|---|
| 107 | #define AR9170_PHY_REG_RXGAIN (AR9170_PHY_REG_BASE + 0x0048) |
|---|
| 108 | #define AR9170_PHY_REG_RXGAIN_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2048) |
|---|
| 109 | #define AR9170_PHY_RXGAIN_TXRX_ATTEN 0x0003f000 |
|---|
| 110 | #define AR9170_PHY_RXGAIN_TXRX_ATTEN_S 12 |
|---|
| 111 | #define AR9170_PHY_RXGAIN_TXRX_RF_MAX 0x007c0000 |
|---|
| 112 | #define AR9170_PHY_RXGAIN_TXRX_RF_MAX_S 18 |
|---|
| 113 | |
|---|
| 114 | #define AR9170_PHY_REG_DESIRED_SZ (AR9170_PHY_REG_BASE + 0x0050) |
|---|
| 115 | #define AR9170_PHY_DESIRED_SZ_ADC 0x000000ff |
|---|
| 116 | #define AR9170_PHY_DESIRED_SZ_ADC_S 0 |
|---|
| 117 | #define AR9170_PHY_DESIRED_SZ_PGA 0x0000ff00 |
|---|
| 118 | #define AR9170_PHY_DESIRED_SZ_PGA_S 8 |
|---|
| 119 | #define AR9170_PHY_DESIRED_SZ_TOT_DES 0x0ff00000 |
|---|
| 120 | #define AR9170_PHY_DESIRED_SZ_TOT_DES_S 20 |
|---|
| 121 | |
|---|
| 122 | #define AR9170_PHY_REG_FIND_SIG (AR9170_PHY_REG_BASE + 0x0058) |
|---|
| 123 | #define AR9170_PHY_FIND_SIG_FIRSTEP 0x0003f000 |
|---|
| 124 | #define AR9170_PHY_FIND_SIG_FIRSTEP_S 12 |
|---|
| 125 | #define AR9170_PHY_FIND_SIG_FIRPWR 0x03fc0000 |
|---|
| 126 | #define AR9170_PHY_FIND_SIG_FIRPWR_S 18 |
|---|
| 127 | |
|---|
| 128 | #define AR9170_PHY_REG_AGC_CTL1 (AR9170_PHY_REG_BASE + 0x005c) |
|---|
| 129 | #define AR9170_PHY_AGC_CTL1_COARSE_LOW 0x00007f80 |
|---|
| 130 | #define AR9170_PHY_AGC_CTL1_COARSE_LOW_S 7 |
|---|
| 131 | #define AR9170_PHY_AGC_CTL1_COARSE_HIGH 0x003f8000 |
|---|
| 132 | #define AR9170_PHY_AGC_CTL1_COARSE_HIGH_S 15 |
|---|
| 133 | |
|---|
| 134 | #define AR9170_PHY_REG_AGC_CONTROL (AR9170_PHY_REG_BASE + 0x0060) |
|---|
| 135 | #define AR9170_PHY_AGC_CONTROL_CAL 0x00000001 |
|---|
| 136 | #define AR9170_PHY_AGC_CONTROL_NF 0x00000002 |
|---|
| 137 | #define AR9170_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 |
|---|
| 138 | #define AR9170_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 |
|---|
| 139 | #define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 |
|---|
| 140 | |
|---|
| 141 | #define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064) |
|---|
| 142 | #define AR9170_PHY_CCA_MIN_PWR 0x0ff80000 |
|---|
| 143 | #define AR9170_PHY_CCA_MIN_PWR_S 19 |
|---|
| 144 | #define AR9170_PHY_CCA_THRESH62 0x0007f000 |
|---|
| 145 | #define AR9170_PHY_CCA_THRESH62_S 12 |
|---|
| 146 | |
|---|
| 147 | #define AR9170_PHY_REG_SFCORR (AR9170_PHY_REG_BASE + 0x0068) |
|---|
| 148 | #define AR9170_PHY_SFCORR_M2COUNT_THR 0x0000001f |
|---|
| 149 | #define AR9170_PHY_SFCORR_M2COUNT_THR_S 0 |
|---|
| 150 | #define AR9170_PHY_SFCORR_M1_THRESH 0x00fe0000 |
|---|
| 151 | #define AR9170_PHY_SFCORR_M1_THRESH_S 17 |
|---|
| 152 | #define AR9170_PHY_SFCORR_M2_THRESH 0x7f000000 |
|---|
| 153 | #define AR9170_PHY_SFCORR_M2_THRESH_S 24 |
|---|
| 154 | |
|---|
| 155 | #define AR9170_PHY_REG_SFCORR_LOW (AR9170_PHY_REG_BASE + 0x006c) |
|---|
| 156 | #define AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 |
|---|
| 157 | #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003f00 |
|---|
| 158 | #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 |
|---|
| 159 | #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001fc000 |
|---|
| 160 | #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 |
|---|
| 161 | #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0fe00000 |
|---|
| 162 | #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 |
|---|
| 163 | |
|---|
| 164 | #define AR9170_PHY_REG_SLEEP_CTR_CONTROL (AR9170_PHY_REG_BASE + 0x0070) |
|---|
| 165 | #define AR9170_PHY_REG_SLEEP_CTR_LIMIT (AR9170_PHY_REG_BASE + 0x0074) |
|---|
| 166 | #define AR9170_PHY_REG_SLEEP_SCAL (AR9170_PHY_REG_BASE + 0x0078) |
|---|
| 167 | |
|---|
| 168 | #define AR9170_PHY_REG_PLL_CTL (AR9170_PHY_REG_BASE + 0x007c) |
|---|
| 169 | #define AR9170_PHY_PLL_CTL_40 0xaa |
|---|
| 170 | #define AR9170_PHY_PLL_CTL_40_5413 0x04 |
|---|
| 171 | #define AR9170_PHY_PLL_CTL_44 0xab |
|---|
| 172 | #define AR9170_PHY_PLL_CTL_44_2133 0xeb |
|---|
| 173 | #define AR9170_PHY_PLL_CTL_40_2133 0xea |
|---|
| 174 | |
|---|
| 175 | #define AR9170_PHY_REG_BIN_MASK_1 (AR9170_PHY_REG_BASE + 0x0100) |
|---|
| 176 | #define AR9170_PHY_REG_BIN_MASK_2 (AR9170_PHY_REG_BASE + 0x0104) |
|---|
| 177 | #define AR9170_PHY_REG_BIN_MASK_3 (AR9170_PHY_REG_BASE + 0x0108) |
|---|
| 178 | #define AR9170_PHY_REG_MASK_CTL (AR9170_PHY_REG_BASE + 0x010c) |
|---|
| 179 | |
|---|
| 180 | /* analogue power on time (100ns) */ |
|---|
| 181 | #define AR9170_PHY_REG_RX_DELAY (AR9170_PHY_REG_BASE + 0x0114) |
|---|
| 182 | #define AR9170_PHY_REG_SEARCH_START_DELAY (AR9170_PHY_REG_BASE + 0x0118) |
|---|
| 183 | #define AR9170_PHY_RX_DELAY_DELAY 0x00003fff |
|---|
| 184 | |
|---|
| 185 | #define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \ |
|---|
| 186 | (0x0120 + ((_i) << 12))) |
|---|
| 187 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01f |
|---|
| 188 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 |
|---|
| 189 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7e0 |
|---|
| 190 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 |
|---|
| 191 | #define AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 |
|---|
| 192 | #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xf000 |
|---|
| 193 | #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 |
|---|
| 194 | #define AR9170_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 |
|---|
| 195 | #define 0x80000000 |
|---|
| 196 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 |
|---|
| 197 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 |
|---|
| 198 | #define AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 |
|---|
| 199 | |
|---|
| 200 | #define AR9170_PHY_REG_TIMING5 (AR9170_PHY_REG_BASE + 0x0124) |
|---|
| 201 | #define AR9170_PHY_TIMING5_CYCPWR_THR1 0x000000fe |
|---|
| 202 | #define AR9170_PHY_TIMING5_CYCPWR_THR1_S 1 |
|---|
| 203 | |
|---|
| 204 | #define AR9170_PHY_REG_POWER_TX_RATE1 (AR9170_PHY_REG_BASE + 0x0134) |
|---|
| 205 | #define AR9170_PHY_REG_POWER_TX_RATE2 (AR9170_PHY_REG_BASE + 0x0138) |
|---|
| 206 | #define AR9170_PHY_REG_POWER_TX_RATE_MAX (AR9170_PHY_REG_BASE + 0x013c) |
|---|
| 207 | #define AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 |
|---|
| 208 | |
|---|
| 209 | #define AR9170_PHY_REG_FRAME_CTL (AR9170_PHY_REG_BASE + 0x0144) |
|---|
| 210 | #define AR9170_PHY_FRAME_CTL_TX_CLIP 0x00000038 |
|---|
| 211 | #define AR9170_PHY_FRAME_CTL_TX_CLIP_S 3 |
|---|
| 212 | |
|---|
| 213 | #define AR9170_PHY_REG_SPUR_REG (AR9170_PHY_REG_BASE + 0x014c) |
|---|
| 214 | #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL (0xff << 18) |
|---|
| 215 | #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 |
|---|
| 216 | #define AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 |
|---|
| 217 | #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT (0xff << 9) |
|---|
| 218 | #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 |
|---|
| 219 | #define 0x100 |
|---|
| 220 | #define 0x7f |
|---|
| 221 | #define 0 |
|---|
| 222 | |
|---|
| 223 | #define AR9170_PHY_REG_RADAR_EXT (AR9170_PHY_REG_BASE + 0x0140) |
|---|
| 224 | #define AR9170_PHY_RADAR_EXT_ENA 0x00004000 |
|---|
| 225 | |
|---|
| 226 | #define AR9170_PHY_REG_RADAR_0 (AR9170_PHY_REG_BASE + 0x0154) |
|---|
| 227 | #define AR9170_PHY_RADAR_0_ENA 0x00000001 |
|---|
| 228 | #define AR9170_PHY_RADAR_0_FFT_ENA 0x80000000 |
|---|
| 229 | /* inband pulse threshold */ |
|---|
| 230 | #define AR9170_PHY_RADAR_0_INBAND 0x0000003e |
|---|
| 231 | #define AR9170_PHY_RADAR_0_INBAND_S 1 |
|---|
| 232 | /* pulse RSSI threshold */ |
|---|
| 233 | #define 0x00000fc0 |
|---|
| 234 | #define 6 |
|---|
| 235 | /* pulse height threshold */ |
|---|
| 236 | #define AR9170_PHY_RADAR_0_HEIGHT 0x0003f000 |
|---|
| 237 | #define AR9170_PHY_RADAR_0_HEIGHT_S 12 |
|---|
| 238 | /* radar RSSI threshold */ |
|---|
| 239 | #define 0x00fc0000 |
|---|
| 240 | #define 18 |
|---|
| 241 | /* radar firepower threshold */ |
|---|
| 242 | #define AR9170_PHY_RADAR_0_FIRPWR 0x7f000000 |
|---|
| 243 | #define AR9170_PHY_RADAR_0_FIRPWR_S 24 |
|---|
| 244 | |
|---|
| 245 | #define AR9170_PHY_REG_RADAR_1 (AR9170_PHY_REG_BASE + 0x0158) |
|---|
| 246 | #define AR9170_PHY_RADAR_1_RELPWR_ENA 0x00800000 |
|---|
| 247 | #define AR9170_PHY_RADAR_1_USE_FIR128 0x00400000 |
|---|
| 248 | #define AR9170_PHY_RADAR_1_RELPWR_THRESH 0x003f0000 |
|---|
| 249 | #define AR9170_PHY_RADAR_1_RELPWR_THRESH_S 16 |
|---|
| 250 | #define AR9170_PHY_RADAR_1_BLOCK_CHECK 0x00008000 |
|---|
| 251 | #define 0x00004000 |
|---|
| 252 | #define AR9170_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 |
|---|
| 253 | #define AR9170_PHY_RADAR_1_RELSTEP_THRESH 0x00001f00 |
|---|
| 254 | #define AR9170_PHY_RADAR_1_RELSTEP_THRESH_S 8 |
|---|
| 255 | #define AR9170_PHY_RADAR_1_MAXLEN 0x000000ff |
|---|
| 256 | #define AR9170_PHY_RADAR_1_MAXLEN_S 0 |
|---|
| 257 | |
|---|
| 258 | #define AR9170_PHY_REG_SWITCH_CHAIN_0 (AR9170_PHY_REG_BASE + 0x0160) |
|---|
| 259 | #define AR9170_PHY_REG_SWITCH_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2160) |
|---|
| 260 | |
|---|
| 261 | #define AR9170_PHY_REG_SWITCH_COM (AR9170_PHY_REG_BASE + 0x0164) |
|---|
| 262 | |
|---|
| 263 | #define AR9170_PHY_REG_CCA_THRESHOLD (AR9170_PHY_REG_BASE + 0x0168) |
|---|
| 264 | |
|---|
| 265 | #define AR9170_PHY_REG_SIGMA_DELTA (AR9170_PHY_REG_BASE + 0x016c) |
|---|
| 266 | #define AR9170_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 |
|---|
| 267 | #define AR9170_PHY_SIGMA_DELTA_ADC_SEL_S 0 |
|---|
| 268 | #define AR9170_PHY_SIGMA_DELTA_FILT2 0x000000f8 |
|---|
| 269 | #define AR9170_PHY_SIGMA_DELTA_FILT2_S 3 |
|---|
| 270 | #define AR9170_PHY_SIGMA_DELTA_FILT1 0x00001f00 |
|---|
| 271 | #define AR9170_PHY_SIGMA_DELTA_FILT1_S 8 |
|---|
| 272 | #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 |
|---|
| 273 | #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S 13 |
|---|
| 274 | |
|---|
| 275 | #define AR9170_PHY_REG_RESTART (AR9170_PHY_REG_BASE + 0x0170) |
|---|
| 276 | #define AR9170_PHY_RESTART_DIV_GC 0x001c0000 |
|---|
| 277 | #define AR9170_PHY_RESTART_DIV_GC_S 18 |
|---|
| 278 | |
|---|
| 279 | #define AR9170_PHY_REG_RFBUS_REQ (AR9170_PHY_REG_BASE + 0x017c) |
|---|
| 280 | #define AR9170_PHY_RFBUS_REQ_EN 0x00000001 |
|---|
| 281 | |
|---|
| 282 | #define AR9170_PHY_REG_TIMING7 (AR9170_PHY_REG_BASE + 0x0180) |
|---|
| 283 | #define AR9170_PHY_REG_TIMING8 (AR9170_PHY_REG_BASE + 0x0184) |
|---|
| 284 | #define AR9170_PHY_TIMING8_PILOT_MASK_2 0x000fffff |
|---|
| 285 | #define AR9170_PHY_TIMING8_PILOT_MASK_2_S 0 |
|---|
| 286 | |
|---|
| 287 | #define AR9170_PHY_REG_BIN_MASK2_1 (AR9170_PHY_REG_BASE + 0x0188) |
|---|
| 288 | #define AR9170_PHY_REG_BIN_MASK2_2 (AR9170_PHY_REG_BASE + 0x018c) |
|---|
| 289 | #define AR9170_PHY_REG_BIN_MASK2_3 (AR9170_PHY_REG_BASE + 0x0190) |
|---|
| 290 | #define AR9170_PHY_REG_BIN_MASK2_4 (AR9170_PHY_REG_BASE + 0x0194) |
|---|
| 291 | #define AR9170_PHY_BIN_MASK2_4_MASK_4 0x00003fff |
|---|
| 292 | #define AR9170_PHY_BIN_MASK2_4_MASK_4_S 0 |
|---|
| 293 | |
|---|
| 294 | #define AR9170_PHY_REG_TIMING9 (AR9170_PHY_REG_BASE + 0x0198) |
|---|
| 295 | #define AR9170_PHY_REG_TIMING10 (AR9170_PHY_REG_BASE + 0x019c) |
|---|
| 296 | #define AR9170_PHY_TIMING10_PILOT_MASK_2 0x000fffff |
|---|
| 297 | #define AR9170_PHY_TIMING10_PILOT_MASK_2_S 0 |
|---|
| 298 | |
|---|
| 299 | #define AR9170_PHY_REG_TIMING11 (AR9170_PHY_REG_BASE + 0x01a0) |
|---|
| 300 | #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE 0x000fffff |
|---|
| 301 | #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 |
|---|
| 302 | #define AR9170_PHY_TIMING11_SPUR_FREQ_SD 0x3ff00000 |
|---|
| 303 | #define AR9170_PHY_TIMING11_SPUR_FREQ_SD_S 20 |
|---|
| 304 | #define AR9170_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 |
|---|
| 305 | #define AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 |
|---|
| 306 | |
|---|
| 307 | #define AR9170_PHY_REG_RX_CHAINMASK (AR9170_PHY_REG_BASE + 0x01a4) |
|---|
| 308 | #define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \ |
|---|
| 309 | 0x01b4 + ((_i) << 12)) |
|---|
| 310 | #define AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 |
|---|
| 311 | #define AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 |
|---|
| 312 | |
|---|
| 313 | #define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL (AR9170_PHY_REG_BASE + 0x01ac) |
|---|
| 314 | #define AR9170_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 |
|---|
| 315 | #define AR9170_PHY_9285_ANT_DIV_CTL 0x01000000 |
|---|
| 316 | #define AR9170_PHY_9285_ANT_DIV_CTL_S 24 |
|---|
| 317 | #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 |
|---|
| 318 | #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 |
|---|
| 319 | #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 |
|---|
| 320 | #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 |
|---|
| 321 | #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 |
|---|
| 322 | #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 |
|---|
| 323 | #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 |
|---|
| 324 | #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 |
|---|
| 325 | #define AR9170_PHY_9285_ANT_DIV_LNA1 2 |
|---|
| 326 | #define AR9170_PHY_9285_ANT_DIV_LNA2 1 |
|---|
| 327 | #define AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 |
|---|
| 328 | #define AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 |
|---|
| 329 | #define AR9170_PHY_9285_ANT_DIV_GAINTB_0 0 |
|---|
| 330 | #define AR9170_PHY_9285_ANT_DIV_GAINTB_1 1 |
|---|
| 331 | |
|---|
| 332 | #define AR9170_PHY_REG_EXT_CCA0 (AR9170_PHY_REG_BASE + 0x01b8) |
|---|
| 333 | #define AR9170_PHY_REG_EXT_CCA0_THRESH62 0x000000ff |
|---|
| 334 | #define AR9170_PHY_REG_EXT_CCA0_THRESH62_S 0 |
|---|
| 335 | |
|---|
| 336 | #define AR9170_PHY_REG_EXT_CCA (AR9170_PHY_REG_BASE + 0x01bc) |
|---|
| 337 | #define AR9170_PHY_EXT_CCA_CYCPWR_THR1 0x0000fe00 |
|---|
| 338 | #define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9 |
|---|
| 339 | #define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000 |
|---|
| 340 | #define AR9170_PHY_EXT_CCA_THRESH62_S 16 |
|---|
| 341 | #define AR9170_PHY_EXT_CCA_MIN_PWR 0xff800000 |
|---|
| 342 | #define AR9170_PHY_EXT_CCA_MIN_PWR_S 23 |
|---|
| 343 | |
|---|
| 344 | #define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0) |
|---|
| 345 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f |
|---|
| 346 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH_S 0 |
|---|
| 347 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH 0x00003f80 |
|---|
| 348 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH_S 7 |
|---|
| 349 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001fc000 |
|---|
| 350 | #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 |
|---|
| 351 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0fe00000 |
|---|
| 352 | #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 |
|---|
| 353 | #define AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 |
|---|
| 354 | |
|---|
| 355 | #define AR9170_PHY_REG_HALFGI (AR9170_PHY_REG_BASE + 0x01d0) |
|---|
| 356 | #define AR9170_PHY_HALFGI_DSC_MAN 0x0007fff0 |
|---|
| 357 | #define AR9170_PHY_HALFGI_DSC_MAN_S 4 |
|---|
| 358 | #define AR9170_PHY_HALFGI_DSC_EXP 0x0000000f |
|---|
| 359 | #define AR9170_PHY_HALFGI_DSC_EXP_S 0 |
|---|
| 360 | |
|---|
| 361 | #define AR9170_PHY_REG_CHANNEL_MASK_01_30 (AR9170_PHY_REG_BASE + 0x01d4) |
|---|
| 362 | #define AR9170_PHY_REG_CHANNEL_MASK_31_60 (AR9170_PHY_REG_BASE + 0x01d8) |
|---|
| 363 | |
|---|
| 364 | #define AR9170_PHY_REG_CHAN_INFO_MEMORY (AR9170_PHY_REG_BASE + 0x01dc) |
|---|
| 365 | #define AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 |
|---|
| 366 | |
|---|
| 367 | #define AR9170_PHY_REG_HEAVY_CLIP_ENABLE (AR9170_PHY_REG_BASE + 0x01e0) |
|---|
| 368 | #define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS (AR9170_PHY_REG_BASE + 0x01ec) |
|---|
| 369 | #define AR9170_PHY_RIFS_INIT_DELAY 0x03ff0000 |
|---|
| 370 | |
|---|
| 371 | #define AR9170_PHY_REG_CALMODE (AR9170_PHY_REG_BASE + 0x01f0) |
|---|
| 372 | #define AR9170_PHY_CALMODE_IQ 0x00000000 |
|---|
| 373 | #define AR9170_PHY_CALMODE_ADC_GAIN 0x00000001 |
|---|
| 374 | #define AR9170_PHY_CALMODE_ADC_DC_PER 0x00000002 |
|---|
| 375 | #define AR9170_PHY_CALMODE_ADC_DC_INIT 0x00000003 |
|---|
| 376 | |
|---|
| 377 | #define AR9170_PHY_REG_REFCLKDLY (AR9170_PHY_REG_BASE + 0x01f4) |
|---|
| 378 | #define AR9170_PHY_REG_REFCLKPD (AR9170_PHY_REG_BASE + 0x01f8) |
|---|
| 379 | |
|---|
| 380 | |
|---|
| 381 | #define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \ |
|---|
| 382 | 0x0410 + ((_i) << 12)) |
|---|
| 383 | #define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \ |
|---|
| 384 | 0x0414 \ + ((_i) << 12)) |
|---|
| 385 | #define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \ |
|---|
| 386 | 0x0418 + ((_i) << 12)) |
|---|
| 387 | #define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + \ |
|---|
| 388 | 0x041c + ((_i) << 12)) |
|---|
| 389 | |
|---|
| 390 | #define (AR9170_PHY_REG_BASE + 0x041c) |
|---|
| 391 | |
|---|
| 392 | #define AR9170_PHY_REG_RFBUS_GRANT (AR9170_PHY_REG_BASE + 0x0420) |
|---|
| 393 | #define AR9170_PHY_RFBUS_GRANT_EN 0x00000001 |
|---|
| 394 | |
|---|
| 395 | #define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF (AR9170_PHY_REG_BASE + 0x04f4) |
|---|
| 396 | #define AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 |
|---|
| 397 | |
|---|
| 398 | #define AR9170_PHY_REG_CHAN_INFO_GAIN (AR9170_PHY_REG_BASE + 0x04fc) |
|---|
| 399 | |
|---|
| 400 | #define AR9170_PHY_REG_MODE (AR9170_PHY_REG_BASE + 0x0a00) |
|---|
| 401 | #define AR9170_PHY_MODE_ASYNCFIFO 0x80 |
|---|
| 402 | #define AR9170_PHY_MODE_AR2133 0x08 |
|---|
| 403 | #define AR9170_PHY_MODE_AR5111 0x00 |
|---|
| 404 | #define AR9170_PHY_MODE_AR5112 0x08 |
|---|
| 405 | #define AR9170_PHY_MODE_DYNAMIC 0x04 |
|---|
| 406 | #define AR9170_PHY_MODE_RF2GHZ 0x02 |
|---|
| 407 | #define AR9170_PHY_MODE_RF5GHZ 0x00 |
|---|
| 408 | #define AR9170_PHY_MODE_CCK 0x01 |
|---|
| 409 | #define AR9170_PHY_MODE_OFDM 0x00 |
|---|
| 410 | #define AR9170_PHY_MODE_DYN_CCK_DISABLE 0x100 |
|---|
| 411 | |
|---|
| 412 | #define AR9170_PHY_REG_CCK_TX_CTRL (AR9170_PHY_REG_BASE + 0x0a04) |
|---|
| 413 | #define AR9170_PHY_CCK_TX_CTRL_JAPAN 0x00000010 |
|---|
| 414 | #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000c |
|---|
| 415 | #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 |
|---|
| 416 | |
|---|
| 417 | #define AR9170_PHY_REG_CCK_DETECT (AR9170_PHY_REG_BASE + 0x0a08) |
|---|
| 418 | #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003f |
|---|
| 419 | #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 |
|---|
| 420 | /* [12:6] settling time for antenna switch */ |
|---|
| 421 | #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001fc0 |
|---|
| 422 | #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 |
|---|
| 423 | #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 |
|---|
| 424 | #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 |
|---|
| 425 | |
|---|
| 426 | #define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c) |
|---|
| 427 | #define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c) |
|---|
| 428 | #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000 |
|---|
| 429 | #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 |
|---|
| 430 | #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00 |
|---|
| 431 | #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 |
|---|
| 432 | #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001f |
|---|
| 433 | #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 |
|---|
| 434 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003e0000 |
|---|
| 435 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 |
|---|
| 436 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001f000 |
|---|
| 437 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 |
|---|
| 438 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000fc0 |
|---|
| 439 | #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 |
|---|
| 440 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003f |
|---|
| 441 | #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 |
|---|
| 442 | |
|---|
| 443 | #define AR9170_PHY_REG_CCK_RXCTRL4 (AR9170_PHY_REG_BASE + 0x0a1c) |
|---|
| 444 | #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01f80000 |
|---|
| 445 | #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 |
|---|
| 446 | |
|---|
| 447 | #define AR9170_PHY_REG_DAG_CTRLCCK (AR9170_PHY_REG_BASE + 0x0a28) |
|---|
| 448 | #define 0x00000200 |
|---|
| 449 | #define 0x0001fc00 |
|---|
| 450 | #define 10 |
|---|
| 451 | |
|---|
| 452 | #define AR9170_PHY_REG_FORCE_CLKEN_CCK (AR9170_PHY_REG_BASE + 0x0a2c) |
|---|
| 453 | #define AR9170_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 |
|---|
| 454 | |
|---|
| 455 | #define AR9170_PHY_REG_POWER_TX_RATE3 (AR9170_PHY_REG_BASE + 0x0a34) |
|---|
| 456 | #define AR9170_PHY_REG_POWER_TX_RATE4 (AR9170_PHY_REG_BASE + 0x0a38) |
|---|
| 457 | |
|---|
| 458 | #define AR9170_PHY_REG_SCRM_SEQ_XR (AR9170_PHY_REG_BASE + 0x0a3c) |
|---|
| 459 | #define (AR9170_PHY_REG_BASE + 0x0a40) |
|---|
| 460 | #define AR9170_PHY_REG_CHIRP_DETECTED_XR (AR9170_PHY_REG_BASE + 0x0a44) |
|---|
| 461 | #define AR9170_PHY_REG_BLUETOOTH (AR9170_PHY_REG_BASE + 0x0a54) |
|---|
| 462 | |
|---|
| 463 | #define AR9170_PHY_REG_TPCRG1 (AR9170_PHY_REG_BASE + 0x0a58) |
|---|
| 464 | #define AR9170_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 |
|---|
| 465 | #define AR9170_PHY_TPCRG1_NUM_PD_GAIN_S 14 |
|---|
| 466 | #define AR9170_PHY_TPCRG1_PD_GAIN_1 0x00030000 |
|---|
| 467 | #define AR9170_PHY_TPCRG1_PD_GAIN_1_S 16 |
|---|
| 468 | #define AR9170_PHY_TPCRG1_PD_GAIN_2 0x000c0000 |
|---|
| 469 | #define AR9170_PHY_TPCRG1_PD_GAIN_2_S 18 |
|---|
| 470 | #define AR9170_PHY_TPCRG1_PD_GAIN_3 0x00300000 |
|---|
| 471 | #define AR9170_PHY_TPCRG1_PD_GAIN_3_S 20 |
|---|
| 472 | #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 |
|---|
| 473 | #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S 22 |
|---|
| 474 | |
|---|
| 475 | #define AR9170_PHY_REG_TX_PWRCTRL4 (AR9170_PHY_REG_BASE + 0x0a64) |
|---|
| 476 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 |
|---|
| 477 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 |
|---|
| 478 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001fe |
|---|
| 479 | #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 |
|---|
| 480 | |
|---|
| 481 | #define AR9170_PHY_REG_ANALOG_SWAP (AR9170_PHY_REG_BASE + 0x0a68) |
|---|
| 482 | #define AR9170_PHY_ANALOG_SWAP_AB 0x0001 |
|---|
| 483 | #define AR9170_PHY_ANALOG_SWAP_ALT_CHAIN 0x00000040 |
|---|
| 484 | |
|---|
| 485 | #define AR9170_PHY_REG_TPCRG5 (AR9170_PHY_REG_BASE + 0x0a6c) |
|---|
| 486 | #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000f |
|---|
| 487 | #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 |
|---|
| 488 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003f0 |
|---|
| 489 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 |
|---|
| 490 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000fc00 |
|---|
| 491 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 |
|---|
| 492 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003f0000 |
|---|
| 493 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 |
|---|
| 494 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0fc00000 |
|---|
| 495 | #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 |
|---|
| 496 | |
|---|
| 497 | #define AR9170_PHY_REG_TX_PWRCTRL6_0 (AR9170_PHY_REG_BASE + 0x0a70) |
|---|
| 498 | #define AR9170_PHY_REG_TX_PWRCTRL6_1 (AR9170_PHY_REG_BASE + 0x1a70) |
|---|
| 499 | #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 |
|---|
| 500 | #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 |
|---|
| 501 | |
|---|
| 502 | #define AR9170_PHY_REG_TX_PWRCTRL7 (AR9170_PHY_REG_BASE + 0x0a74) |
|---|
| 503 | #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01f80000 |
|---|
| 504 | #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 |
|---|
| 505 | |
|---|
| 506 | #define AR9170_PHY_REG_TX_PWRCTRL9 (AR9170_PHY_REG_BASE + 0x0a7c) |
|---|
| 507 | #define AR9170_PHY_TX_DESIRED_SCALE_CCK 0x00007c00 |
|---|
| 508 | #define AR9170_PHY_TX_DESIRED_SCALE_CCK_S 10 |
|---|
| 509 | #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 |
|---|
| 510 | #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 |
|---|
| 511 | |
|---|
| 512 | #define AR9170_PHY_REG_TX_GAIN_TBL1 (AR9170_PHY_REG_BASE + 0x0b00) |
|---|
| 513 | #define AR9170_PHY_TX_GAIN 0x0007f000 |
|---|
| 514 | #define AR9170_PHY_TX_GAIN_S 12 |
|---|
| 515 | |
|---|
| 516 | /* Carrier leak calibration control, do it after AGC calibration */ |
|---|
| 517 | #define AR9170_PHY_REG_CL_CAL_CTL (AR9170_PHY_REG_BASE + 0x0b58) |
|---|
| 518 | #define AR9170_PHY_CL_CAL_ENABLE 0x00000002 |
|---|
| 519 | #define AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE 0x00000001 |
|---|
| 520 | |
|---|
| 521 | #define AR9170_PHY_REG_POWER_TX_RATE5 (AR9170_PHY_REG_BASE + 0x0b8c) |
|---|
| 522 | #define AR9170_PHY_REG_POWER_TX_RATE6 (AR9170_PHY_REG_BASE + 0x0b90) |
|---|
| 523 | |
|---|
| 524 | #define AR9170_PHY_REG_CH0_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x0b98) |
|---|
| 525 | #define AR9170_PHY_REG_CH1_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x1b98) |
|---|
| 526 | #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP 0x0000fc00 |
|---|
| 527 | #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S 10 |
|---|
| 528 | |
|---|
| 529 | #define AR9170_PHY_REG_CAL_CHAINMASK (AR9170_PHY_REG_BASE + 0x0b9c) |
|---|
| 530 | #define AR9170_PHY_REG_VIT_MASK2_M_46_61 (AR9170_PHY_REG_BASE + 0x0ba0) |
|---|
| 531 | #define AR9170_PHY_REG_MASK2_M_31_45 (AR9170_PHY_REG_BASE + 0x0ba4) |
|---|
| 532 | #define AR9170_PHY_REG_MASK2_M_16_30 (AR9170_PHY_REG_BASE + 0x0ba8) |
|---|
| 533 | #define AR9170_PHY_REG_MASK2_M_00_15 (AR9170_PHY_REG_BASE + 0x0bac) |
|---|
| 534 | #define AR9170_PHY_REG_PILOT_MASK_01_30 (AR9170_PHY_REG_BASE + 0x0bb0) |
|---|
| 535 | #define AR9170_PHY_REG_PILOT_MASK_31_60 (AR9170_PHY_REG_BASE + 0x0bb4) |
|---|
| 536 | #define AR9170_PHY_REG_MASK2_P_15_01 (AR9170_PHY_REG_BASE + 0x0bb8) |
|---|
| 537 | #define AR9170_PHY_REG_MASK2_P_30_16 (AR9170_PHY_REG_BASE + 0x0bbc) |
|---|
| 538 | #define AR9170_PHY_REG_MASK2_P_45_31 (AR9170_PHY_REG_BASE + 0x0bc0) |
|---|
| 539 | #define AR9170_PHY_REG_MASK2_P_61_45 (AR9170_PHY_REG_BASE + 0x0bc4) |
|---|
| 540 | #define AR9170_PHY_REG_POWER_TX_SUB (AR9170_PHY_REG_BASE + 0x0bc8) |
|---|
| 541 | #define AR9170_PHY_REG_POWER_TX_RATE7 (AR9170_PHY_REG_BASE + 0x0bcc) |
|---|
| 542 | #define AR9170_PHY_REG_POWER_TX_RATE8 (AR9170_PHY_REG_BASE + 0x0bd0) |
|---|
| 543 | #define AR9170_PHY_REG_POWER_TX_RATE9 (AR9170_PHY_REG_BASE + 0x0bd4) |
|---|
| 544 | #define AR9170_PHY_REG_XPA_CFG (AR9170_PHY_REG_BASE + 0x0bd8) |
|---|
| 545 | #define AR9170_PHY_FORCE_XPA_CFG 0x000000001 |
|---|
| 546 | #define AR9170_PHY_FORCE_XPA_CFG_S 0 |
|---|
| 547 | |
|---|
| 548 | #define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064) |
|---|
| 549 | #define AR9170_PHY_CH1_CCA_MIN_PWR 0x0ff80000 |
|---|
| 550 | #define AR9170_PHY_CH1_CCA_MIN_PWR_S 19 |
|---|
| 551 | |
|---|
| 552 | #define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064) |
|---|
| 553 | #define AR9170_PHY_CH2_CCA_MIN_PWR 0x0ff80000 |
|---|
| 554 | #define AR9170_PHY_CH2_CCA_MIN_PWR_S 19 |
|---|
| 555 | |
|---|
| 556 | #define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc) |
|---|
| 557 | #define AR9170_PHY_CH1_EXT_CCA_MIN_PWR 0xff800000 |
|---|
| 558 | #define AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S 23 |
|---|
| 559 | |
|---|
| 560 | #define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc) |
|---|
| 561 | #define AR9170_PHY_CH2_EXT_CCA_MIN_PWR 0xff800000 |
|---|
| 562 | #define AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S 23 |
|---|
| 563 | |
|---|
| 564 | #endif /* __CARL9170_SHARED_PHY_H */ |
|---|
| 565 | |
|---|
