| 1 | /* |
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| 2 | * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> |
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| 3 | * |
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| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
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| 5 | * purpose with or without fee is hereby granted, provided that the above |
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| 6 | * copyright notice and this permission notice appear in all copies. |
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| 7 | * |
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| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
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| 11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
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| 13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
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| 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef _DXE_H_ |
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| 18 | #define _DXE_H_ |
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| 19 | |
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| 20 | #include "wcn36xx.h" |
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| 21 | |
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| 22 | /* |
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| 23 | TX_LOW = DMA0 |
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| 24 | TX_HIGH = DMA4 |
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| 25 | RX_LOW = DMA1 |
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| 26 | RX_HIGH = DMA3 |
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| 27 | H2H_TEST_RX_TX = DMA2 |
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| 28 | */ |
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| 29 | |
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| 30 | /* DXE registers */ |
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| 31 | #define WCN36XX_DXE_MEM_REG 0 |
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| 32 | |
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| 33 | #define WCN36XX_CCU_DXE_INT_SELECT_RIVA 0x310 |
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| 34 | #define WCN36XX_CCU_DXE_INT_SELECT_PRONTO 0x10dc |
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| 35 | |
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| 36 | /* Descriptor valid */ |
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| 37 | #define WCN36xx_DXE_CTRL_VLD BIT(0) |
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| 38 | /* End of packet */ |
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| 39 | #define WCN36xx_DXE_CTRL_EOP BIT(3) |
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| 40 | /* BD handling bit */ |
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| 41 | #define WCN36xx_DXE_CTRL_BDH BIT(4) |
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| 42 | /* Source is a queue */ |
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| 43 | #define WCN36xx_DXE_CTRL_SIQ BIT(5) |
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| 44 | /* Destination is a queue */ |
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| 45 | #define WCN36xx_DXE_CTRL_DIQ BIT(6) |
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| 46 | /* Pointer address is a queue */ |
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| 47 | #define WCN36xx_DXE_CTRL_PIQ BIT(7) |
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| 48 | /* Release PDU when done */ |
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| 49 | #define WCN36xx_DXE_CTRL_PDU_REL BIT(8) |
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| 50 | /* STOP channel processing */ |
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| 51 | #define WCN36xx_DXE_CTRL_STOP BIT(16) |
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| 52 | /* INT on descriptor done */ |
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| 53 | #define WCN36xx_DXE_CTRL_INT BIT(17) |
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| 54 | /* Endian byte swap enable */ |
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| 55 | #define WCN36xx_DXE_CTRL_SWAP BIT(20) |
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| 56 | /* Master endianness */ |
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| 57 | #define WCN36xx_DXE_CTRL_ENDIANNESS BIT(21) |
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| 58 | |
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| 59 | /* Transfer type */ |
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| 60 | #define WCN36xx_DXE_CTRL_XTYPE_SHIFT 1 |
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| 61 | #define WCN36xx_DXE_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CTRL_XTYPE_SHIFT) |
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| 62 | #define WCN36xx_DXE_CTRL_XTYPE_SET(x) ((x) << WCN36xx_DXE_CTRL_XTYPE_SHIFT) |
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| 63 | |
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| 64 | /* BMU Threshold select */ |
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| 65 | #define WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT 9 |
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| 66 | #define WCN36xx_DXE_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT) |
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| 67 | #define WCN36xx_DXE_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT) |
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| 68 | |
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| 69 | /* Priority */ |
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| 70 | #define WCN36xx_DXE_CTRL_PRIO_SHIFT 13 |
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| 71 | #define WCN36xx_DXE_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CTRL_PRIO_SHIFT) |
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| 72 | #define WCN36xx_DXE_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CTRL_PRIO_SHIFT) |
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| 73 | |
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| 74 | /* BD Template index */ |
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| 75 | #define WCN36xx_DXE_CTRL_BDT_IDX_SHIFT 18 |
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| 76 | #define WCN36xx_DXE_CTRL_BDT_IDX_MASK GENMASK(19, WCN36xx_DXE_CTRL_BDT_IDX_SHIFT) |
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| 77 | #define WCN36xx_DXE_CTRL_BDT_IDX_SET(x) ((x) << WCN36xx_DXE_CTRL_BDT_IDX_SHIFT) |
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| 78 | |
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| 79 | /* Transfer types: */ |
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| 80 | /* Host to host */ |
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| 81 | #define WCN36xx_DXE_XTYPE_H2H (0) |
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| 82 | /* Host to BMU */ |
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| 83 | #define WCN36xx_DXE_XTYPE_H2B (2) |
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| 84 | /* BMU to host */ |
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| 85 | #define WCN36xx_DXE_XTYPE_B2H (3) |
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| 86 | |
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| 87 | #define WCN36XX_DXE_CTRL_TX_L (WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 88 | WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | \ |
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| 89 | WCN36xx_DXE_CTRL_PRIO_SET(4) | WCN36xx_DXE_CTRL_INT | \ |
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| 90 | WCN36xx_DXE_CTRL_SWAP | WCN36xx_DXE_CTRL_ENDIANNESS) |
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| 91 | |
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| 92 | #define WCN36XX_DXE_CTRL_TX_H (WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 93 | WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | \ |
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| 94 | WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_INT | \ |
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| 95 | WCN36xx_DXE_CTRL_SWAP | WCN36xx_DXE_CTRL_ENDIANNESS) |
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| 96 | |
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| 97 | #define WCN36XX_DXE_CTRL_RX_L (WCN36xx_DXE_CTRL_VLD | \ |
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| 98 | WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ |
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| 99 | WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_SIQ | \ |
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| 100 | WCN36xx_DXE_CTRL_PDU_REL | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(6) | \ |
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| 101 | WCN36xx_DXE_CTRL_PRIO_SET(5) | WCN36xx_DXE_CTRL_INT | \ |
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| 102 | WCN36xx_DXE_CTRL_SWAP) |
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| 103 | |
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| 104 | #define WCN36XX_DXE_CTRL_RX_H (WCN36xx_DXE_CTRL_VLD | \ |
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| 105 | WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ |
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| 106 | WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_SIQ | \ |
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| 107 | WCN36xx_DXE_CTRL_PDU_REL | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(8) | \ |
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| 108 | WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_INT | \ |
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| 109 | WCN36xx_DXE_CTRL_SWAP) |
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| 110 | |
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| 111 | #define WCN36XX_DXE_CTRL_TX_H_BD (WCN36xx_DXE_CTRL_VLD | \ |
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| 112 | WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 113 | WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | \ |
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| 114 | WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_SWAP | \ |
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| 115 | WCN36xx_DXE_CTRL_ENDIANNESS) |
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| 116 | |
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| 117 | #define WCN36XX_DXE_CTRL_TX_H_SKB (WCN36xx_DXE_CTRL_VLD | \ |
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| 118 | WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 119 | WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_DIQ | \ |
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| 120 | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | WCN36xx_DXE_CTRL_PRIO_SET(6) | \ |
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| 121 | WCN36xx_DXE_CTRL_INT | WCN36xx_DXE_CTRL_SWAP | \ |
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| 122 | WCN36xx_DXE_CTRL_ENDIANNESS) |
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| 123 | |
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| 124 | #define WCN36XX_DXE_CTRL_TX_L_BD (WCN36xx_DXE_CTRL_VLD | \ |
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| 125 | WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 126 | WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | \ |
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| 127 | WCN36xx_DXE_CTRL_PRIO_SET(4) | WCN36xx_DXE_CTRL_SWAP | \ |
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| 128 | WCN36xx_DXE_CTRL_ENDIANNESS) |
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| 129 | |
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| 130 | #define WCN36XX_DXE_CTRL_TX_L_SKB (WCN36xx_DXE_CTRL_VLD | \ |
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| 131 | WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 132 | WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_DIQ | \ |
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| 133 | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | WCN36xx_DXE_CTRL_PRIO_SET(4) | \ |
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| 134 | WCN36xx_DXE_CTRL_INT | WCN36xx_DXE_CTRL_SWAP | \ |
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| 135 | WCN36xx_DXE_CTRL_ENDIANNESS) |
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| 136 | |
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| 137 | /* TODO This must calculated properly but not hardcoded */ |
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| 138 | #define WCN36XX_DXE_WQ_TX_L(wcn) ((wcn)->is_pronto_v3 ? 0x6 : 0x17) |
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| 139 | #define WCN36XX_DXE_WQ_TX_H(wcn) ((wcn)->is_pronto_v3 ? 0x6 : 0x17) |
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| 140 | #define WCN36XX_DXE_WQ_RX_L 0xB |
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| 141 | #define WCN36XX_DXE_WQ_RX_H 0x4 |
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| 142 | |
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| 143 | /* Channel enable or restart */ |
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| 144 | #define WCN36xx_DXE_CH_CTRL_EN BIT(0) |
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| 145 | /* End of packet bit */ |
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| 146 | #define WCN36xx_DXE_CH_CTRL_EOP BIT(3) |
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| 147 | /* BD Handling bit */ |
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| 148 | #define WCN36xx_DXE_CH_CTRL_BDH BIT(4) |
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| 149 | /* Source is queue */ |
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| 150 | #define WCN36xx_DXE_CH_CTRL_SIQ BIT(5) |
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| 151 | /* Destination is queue */ |
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| 152 | #define WCN36xx_DXE_CH_CTRL_DIQ BIT(6) |
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| 153 | /* Pointer descriptor is queue */ |
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| 154 | #define WCN36xx_DXE_CH_CTRL_PIQ BIT(7) |
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| 155 | /* Relase PDU when done */ |
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| 156 | #define WCN36xx_DXE_CH_CTRL_PDU_REL BIT(8) |
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| 157 | /* Stop channel processing */ |
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| 158 | #define WCN36xx_DXE_CH_CTRL_STOP BIT(16) |
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| 159 | /* Enable external descriptor interrupt */ |
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| 160 | #define WCN36xx_DXE_CH_CTRL_INE_ED BIT(17) |
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| 161 | /* Enable channel interrupt on errors */ |
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| 162 | #define WCN36xx_DXE_CH_CTRL_INE_ERR BIT(18) |
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| 163 | /* Enable Channel interrupt when done */ |
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| 164 | #define WCN36xx_DXE_CH_CTRL_INE_DONE BIT(19) |
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| 165 | /* External descriptor enable */ |
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| 166 | #define WCN36xx_DXE_CH_CTRL_EDEN BIT(20) |
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| 167 | /* Wait for valid bit */ |
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| 168 | #define WCN36xx_DXE_CH_CTRL_EDVEN BIT(21) |
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| 169 | /* Endianness is little endian*/ |
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| 170 | #define WCN36xx_DXE_CH_CTRL_ENDIANNESS BIT(26) |
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| 171 | /* Abort transfer */ |
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| 172 | #define WCN36xx_DXE_CH_CTRL_ABORT BIT(27) |
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| 173 | /* Long descriptor format */ |
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| 174 | #define WCN36xx_DXE_CH_CTRL_DFMT BIT(28) |
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| 175 | /* Endian byte swap enable */ |
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| 176 | #define WCN36xx_DXE_CH_CTRL_SWAP BIT(31) |
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| 177 | |
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| 178 | /* Transfer type */ |
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| 179 | #define WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT 1 |
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| 180 | #define WCN36xx_DXE_CH_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT) |
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| 181 | #define WCN36xx_DXE_CH_CTRL_XTYPE_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT) |
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| 182 | |
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| 183 | /* Channel BMU Threshold select */ |
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| 184 | #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT 9 |
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| 185 | #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT) |
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| 186 | #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT) |
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| 187 | |
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| 188 | /* Channel Priority */ |
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| 189 | #define WCN36xx_DXE_CH_CTRL_PRIO_SHIFT 13 |
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| 190 | #define WCN36xx_DXE_CH_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CH_CTRL_PRIO_SHIFT) |
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| 191 | #define WCN36xx_DXE_CH_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_PRIO_SHIFT) |
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| 192 | |
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| 193 | /* Counter select */ |
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| 194 | #define WCN36xx_DXE_CH_CTRL_SEL_SHIFT 22 |
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| 195 | #define WCN36xx_DXE_CH_CTRL_SEL_MASK GENMASK(25, WCN36xx_DXE_CH_CTRL_SEL_SHIFT) |
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| 196 | #define WCN36xx_DXE_CH_CTRL_SEL_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_SEL_SHIFT) |
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| 197 | |
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| 198 | /* Channel BD template index */ |
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| 199 | #define WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT 29 |
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| 200 | #define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK GENMASK(30, WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT) |
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| 201 | #define WCN36xx_DXE_CH_CTRL_BDT_IDX_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT) |
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| 202 | |
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| 203 | /* DXE default control register values */ |
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| 204 | #define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L (WCN36xx_DXE_CH_CTRL_EN | \ |
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| 205 | WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ |
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| 206 | WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \ |
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| 207 | WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(6) | \ |
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| 208 | WCN36xx_DXE_CH_CTRL_PRIO_SET(5) | WCN36xx_DXE_CH_CTRL_INE_ED | \ |
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| 209 | WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ |
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| 210 | WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ |
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| 211 | WCN36xx_DXE_CH_CTRL_SEL_SET(1) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ |
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| 212 | WCN36xx_DXE_CH_CTRL_SWAP) |
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| 213 | |
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| 214 | #define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H (WCN36xx_DXE_CH_CTRL_EN | \ |
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| 215 | WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ |
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| 216 | WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \ |
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| 217 | WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(8) | \ |
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| 218 | WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \ |
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| 219 | WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ |
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| 220 | WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ |
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| 221 | WCN36xx_DXE_CH_CTRL_SEL_SET(3) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ |
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| 222 | WCN36xx_DXE_CH_CTRL_SWAP) |
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| 223 | |
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| 224 | #define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H (WCN36xx_DXE_CH_CTRL_EN | \ |
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| 225 | WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 226 | WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \ |
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| 227 | WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(7) | \ |
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| 228 | WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \ |
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| 229 | WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ |
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| 230 | WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ |
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| 231 | WCN36xx_DXE_CH_CTRL_SEL_SET(4) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ |
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| 232 | WCN36xx_DXE_CH_CTRL_SWAP) |
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| 233 | |
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| 234 | #define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L (WCN36xx_DXE_CH_CTRL_EN | \ |
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| 235 | WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ |
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| 236 | WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \ |
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| 237 | WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(5) | \ |
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| 238 | WCN36xx_DXE_CH_CTRL_PRIO_SET(4) | WCN36xx_DXE_CH_CTRL_INE_ED | \ |
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| 239 | WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ |
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| 240 | WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ |
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| 241 | WCN36xx_DXE_CH_CTRL_SEL_SET(0) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ |
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| 242 | WCN36xx_DXE_CH_CTRL_SWAP) |
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| 243 | |
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| 244 | /* Common DXE registers */ |
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| 245 | #define WCN36XX_DXE_MEM_CSR (WCN36XX_DXE_MEM_REG + 0x00) |
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| 246 | #define WCN36XX_DXE_REG_CSR_RESET (WCN36XX_DXE_MEM_REG + 0x00) |
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| 247 | #define WCN36XX_DXE_ENCH_ADDR (WCN36XX_DXE_MEM_REG + 0x04) |
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| 248 | #define WCN36XX_DXE_REG_CH_EN (WCN36XX_DXE_MEM_REG + 0x08) |
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| 249 | #define WCN36XX_DXE_REG_CH_DONE (WCN36XX_DXE_MEM_REG + 0x0C) |
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| 250 | #define WCN36XX_DXE_REG_CH_ERR (WCN36XX_DXE_MEM_REG + 0x10) |
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| 251 | #define WCN36XX_DXE_INT_MASK_REG (WCN36XX_DXE_MEM_REG + 0x18) |
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| 252 | #define WCN36XX_DXE_INT_SRC_RAW_REG (WCN36XX_DXE_MEM_REG + 0x20) |
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| 253 | /* #define WCN36XX_DXE_INT_CH6_MASK 0x00000040 */ |
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| 254 | /* #define WCN36XX_DXE_INT_CH5_MASK 0x00000020 */ |
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| 255 | #define WCN36XX_DXE_INT_CH4_MASK 0x00000010 |
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| 256 | #define WCN36XX_DXE_INT_CH3_MASK 0x00000008 |
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| 257 | /* #define WCN36XX_DXE_INT_CH2_MASK 0x00000004 */ |
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| 258 | #define WCN36XX_DXE_INT_CH1_MASK 0x00000002 |
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| 259 | #define WCN36XX_DXE_INT_CH0_MASK 0x00000001 |
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| 260 | #define WCN36XX_DXE_0_INT_CLR (WCN36XX_DXE_MEM_REG + 0x30) |
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| 261 | #define WCN36XX_DXE_0_INT_ED_CLR (WCN36XX_DXE_MEM_REG + 0x34) |
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| 262 | #define WCN36XX_DXE_0_INT_DONE_CLR (WCN36XX_DXE_MEM_REG + 0x38) |
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| 263 | #define WCN36XX_DXE_0_INT_ERR_CLR (WCN36XX_DXE_MEM_REG + 0x3C) |
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| 264 | |
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| 265 | #define WCN36XX_CH_STAT_INT_DONE_MASK 0x00008000 |
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| 266 | #define WCN36XX_CH_STAT_INT_ERR_MASK 0x00004000 |
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| 267 | #define WCN36XX_CH_STAT_INT_ED_MASK 0x00002000 |
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| 268 | |
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| 269 | #define WCN36XX_DXE_0_CH0_STATUS (WCN36XX_DXE_MEM_REG + 0x404) |
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| 270 | #define WCN36XX_DXE_0_CH1_STATUS (WCN36XX_DXE_MEM_REG + 0x444) |
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| 271 | #define WCN36XX_DXE_0_CH2_STATUS (WCN36XX_DXE_MEM_REG + 0x484) |
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| 272 | #define WCN36XX_DXE_0_CH3_STATUS (WCN36XX_DXE_MEM_REG + 0x4C4) |
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| 273 | #define WCN36XX_DXE_0_CH4_STATUS (WCN36XX_DXE_MEM_REG + 0x504) |
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| 274 | |
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| 275 | #define WCN36XX_DXE_REG_RESET 0x5c89 |
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| 276 | |
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| 277 | /* Temporary BMU Workqueue 4 */ |
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| 278 | #define WCN36XX_DXE_BMU_WQ_RX_LOW 0xB |
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| 279 | #define WCN36XX_DXE_BMU_WQ_RX_HIGH 0x4 |
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| 280 | /* DMA channel offset */ |
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| 281 | #define WCN36XX_DXE_TX_LOW_OFFSET 0x400 |
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| 282 | #define WCN36XX_DXE_TX_HIGH_OFFSET 0x500 |
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| 283 | #define WCN36XX_DXE_RX_LOW_OFFSET 0x440 |
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| 284 | #define WCN36XX_DXE_RX_HIGH_OFFSET 0x4C0 |
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| 285 | |
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| 286 | /* Address of the next DXE descriptor */ |
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| 287 | #define WCN36XX_DXE_CH_NEXT_DESC_ADDR 0x001C |
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| 288 | #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \ |
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| 289 | WCN36XX_DXE_TX_LOW_OFFSET + \ |
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| 290 | WCN36XX_DXE_CH_NEXT_DESC_ADDR) |
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| 291 | #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \ |
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| 292 | WCN36XX_DXE_TX_HIGH_OFFSET + \ |
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| 293 | WCN36XX_DXE_CH_NEXT_DESC_ADDR) |
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| 294 | #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ |
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| 295 | WCN36XX_DXE_RX_LOW_OFFSET + \ |
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| 296 | WCN36XX_DXE_CH_NEXT_DESC_ADDR) |
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| 297 | #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ |
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| 298 | WCN36XX_DXE_RX_HIGH_OFFSET + \ |
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| 299 | WCN36XX_DXE_CH_NEXT_DESC_ADDR) |
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| 300 | |
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| 301 | /* DXE Descriptor source address */ |
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| 302 | #define WCN36XX_DXE_CH_SRC_ADDR 0x000C |
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| 303 | #define WCN36XX_DXE_CH_SRC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ |
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| 304 | WCN36XX_DXE_RX_LOW_OFFSET + \ |
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| 305 | WCN36XX_DXE_CH_SRC_ADDR) |
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| 306 | #define WCN36XX_DXE_CH_SRC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ |
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| 307 | WCN36XX_DXE_RX_HIGH_OFFSET + \ |
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| 308 | WCN36XX_DXE_CH_SRC_ADDR) |
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| 309 | |
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| 310 | /* DXE Descriptor address destination address */ |
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| 311 | #define WCN36XX_DXE_CH_DEST_ADDR 0x0014 |
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| 312 | #define WCN36XX_DXE_CH_DEST_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \ |
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| 313 | WCN36XX_DXE_TX_LOW_OFFSET + \ |
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| 314 | WCN36XX_DXE_CH_DEST_ADDR) |
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| 315 | #define WCN36XX_DXE_CH_DEST_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \ |
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| 316 | WCN36XX_DXE_TX_HIGH_OFFSET + \ |
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| 317 | WCN36XX_DXE_CH_DEST_ADDR) |
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| 318 | #define WCN36XX_DXE_CH_DEST_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ |
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| 319 | WCN36XX_DXE_RX_LOW_OFFSET + \ |
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| 320 | WCN36XX_DXE_CH_DEST_ADDR) |
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| 321 | #define WCN36XX_DXE_CH_DEST_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ |
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| 322 | WCN36XX_DXE_RX_HIGH_OFFSET + \ |
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| 323 | WCN36XX_DXE_CH_DEST_ADDR) |
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| 324 | |
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| 325 | /* Interrupt status */ |
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| 326 | #define WCN36XX_DXE_CH_STATUS_REG_ADDR 0x0004 |
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| 327 | #define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \ |
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| 328 | WCN36XX_DXE_TX_LOW_OFFSET + \ |
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| 329 | WCN36XX_DXE_CH_STATUS_REG_ADDR) |
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| 330 | #define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \ |
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| 331 | WCN36XX_DXE_TX_HIGH_OFFSET + \ |
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| 332 | WCN36XX_DXE_CH_STATUS_REG_ADDR) |
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| 333 | #define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ |
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| 334 | WCN36XX_DXE_RX_LOW_OFFSET + \ |
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| 335 | WCN36XX_DXE_CH_STATUS_REG_ADDR) |
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| 336 | #define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ |
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| 337 | WCN36XX_DXE_RX_HIGH_OFFSET + \ |
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| 338 | WCN36XX_DXE_CH_STATUS_REG_ADDR) |
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| 339 | |
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| 340 | |
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| 341 | /* DXE default control register */ |
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| 342 | #define WCN36XX_DXE_REG_CTL_RX_L (WCN36XX_DXE_MEM_REG + \ |
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| 343 | WCN36XX_DXE_RX_LOW_OFFSET) |
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| 344 | #define WCN36XX_DXE_REG_CTL_RX_H (WCN36XX_DXE_MEM_REG + \ |
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| 345 | WCN36XX_DXE_RX_HIGH_OFFSET) |
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| 346 | #define WCN36XX_DXE_REG_CTL_TX_H (WCN36XX_DXE_MEM_REG + \ |
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| 347 | WCN36XX_DXE_TX_HIGH_OFFSET) |
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| 348 | #define WCN36XX_DXE_REG_CTL_TX_L (WCN36XX_DXE_MEM_REG + \ |
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| 349 | WCN36XX_DXE_TX_LOW_OFFSET) |
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| 350 | |
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| 351 | #define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400 |
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| 352 | #define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY 0x00000200 |
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| 353 | |
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| 354 | |
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| 355 | /* Interrupt control channel mask */ |
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| 356 | #define WCN36XX_INT_MASK_CHAN_TX_L 0x00000001 |
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| 357 | #define WCN36XX_INT_MASK_CHAN_RX_L 0x00000002 |
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| 358 | #define WCN36XX_INT_MASK_CHAN_RX_H 0x00000008 |
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| 359 | #define WCN36XX_INT_MASK_CHAN_TX_H 0x00000010 |
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| 360 | |
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| 361 | #define WCN36XX_BD_CHUNK_SIZE 128 |
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| 362 | |
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| 363 | #define WCN36XX_PKT_SIZE 0xF20 |
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| 364 | enum wcn36xx_dxe_ch_type { |
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| 365 | WCN36XX_DXE_CH_TX_L, |
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| 366 | WCN36XX_DXE_CH_TX_H, |
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| 367 | WCN36XX_DXE_CH_RX_L, |
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| 368 | WCN36XX_DXE_CH_RX_H |
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| 369 | }; |
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| 370 | |
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| 371 | /* amount of descriptors per channel */ |
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| 372 | enum wcn36xx_dxe_ch_desc_num { |
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| 373 | WCN36XX_DXE_CH_DESC_NUMB_TX_L = 128, |
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| 374 | WCN36XX_DXE_CH_DESC_NUMB_TX_H = 10, |
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| 375 | WCN36XX_DXE_CH_DESC_NUMB_RX_L = 512, |
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| 376 | WCN36XX_DXE_CH_DESC_NUMB_RX_H = 40 |
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| 377 | }; |
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| 378 | |
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| 379 | /** |
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| 380 | * struct wcn36xx_dxe_desc - describes descriptor of one DXE buffer |
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| 381 | * |
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| 382 | * @ctrl: is a union that consists of following bits: |
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| 383 | * union { |
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| 384 | * u32 valid :1; //0 = DMA stop, 1 = DMA continue with this |
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| 385 | * //descriptor |
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| 386 | * u32 transfer_type :2; //0 = Host to Host space |
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| 387 | * u32 eop :1; //End of Packet |
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| 388 | * u32 bd_handling :1; //if transferType = Host to BMU, then 0 |
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| 389 | * // means first 128 bytes contain BD, and 1 |
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| 390 | * // means create new empty BD |
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| 391 | * u32 siq :1; // SIQ |
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| 392 | * u32 diq :1; // DIQ |
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| 393 | * u32 pdu_rel :1; //0 = don't release BD and PDUs when done, |
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| 394 | * // 1 = release them |
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| 395 | * u32 bthld_sel :4; //BMU Threshold Select |
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| 396 | * u32 prio :3; //Specifies the priority level to use for |
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| 397 | * // the transfer |
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| 398 | * u32 stop_channel :1; //1 = DMA stops processing further, channel |
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| 399 | * //requires re-enabling after this |
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| 400 | * u32 intr :1; //Interrupt on Descriptor Done |
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| 401 | * u32 rsvd :1; //reserved |
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| 402 | * u32 size :14;//14 bits used - ignored for BMU transfers, |
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| 403 | * //only used for host to host transfers? |
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| 404 | * } ctrl; |
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| 405 | */ |
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| 406 | struct wcn36xx_dxe_desc { |
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| 407 | u32 ctrl; |
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| 408 | u32 fr_len; |
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| 409 | |
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| 410 | u32 src_addr_l; |
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| 411 | u32 dst_addr_l; |
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| 412 | u32 phy_next_l; |
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| 413 | u32 src_addr_h; |
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| 414 | u32 dst_addr_h; |
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| 415 | u32 phy_next_h; |
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| 416 | } __packed; |
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| 417 | |
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| 418 | /* DXE Control block */ |
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| 419 | struct wcn36xx_dxe_ctl { |
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| 420 | struct wcn36xx_dxe_ctl *next; |
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| 421 | struct wcn36xx_dxe_desc *desc; |
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| 422 | unsigned int desc_phy_addr; |
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| 423 | int ctl_blk_order; |
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| 424 | struct sk_buff *skb; |
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| 425 | void *bd_cpu_addr; |
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| 426 | dma_addr_t bd_phy_addr; |
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| 427 | }; |
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| 428 | |
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| 429 | struct wcn36xx_dxe_ch { |
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| 430 | spinlock_t lock; /* protects head/tail ptrs */ |
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| 431 | enum wcn36xx_dxe_ch_type ch_type; |
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| 432 | void *cpu_addr; |
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| 433 | dma_addr_t dma_addr; |
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| 434 | enum wcn36xx_dxe_ch_desc_num desc_num; |
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| 435 | /* DXE control block ring */ |
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| 436 | struct wcn36xx_dxe_ctl *head_blk_ctl; |
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| 437 | struct wcn36xx_dxe_ctl *tail_blk_ctl; |
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| 438 | |
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| 439 | /* DXE channel specific configs */ |
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| 440 | u32 dxe_wq; |
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| 441 | u32 ctrl_bd; |
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| 442 | u32 ctrl_skb; |
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| 443 | u32 reg_ctrl; |
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| 444 | u32 def_ctrl; |
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| 445 | }; |
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| 446 | |
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| 447 | /* Memory Pool for BD headers */ |
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| 448 | struct wcn36xx_dxe_mem_pool { |
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| 449 | int chunk_size; |
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| 450 | void *virt_addr; |
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| 451 | dma_addr_t phy_addr; |
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| 452 | }; |
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| 453 | |
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| 454 | struct wcn36xx_tx_bd; |
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| 455 | struct wcn36xx_vif; |
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| 456 | int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn); |
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| 457 | void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn); |
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| 458 | void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn); |
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| 459 | int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn); |
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| 460 | void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn); |
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| 461 | int wcn36xx_dxe_init(struct wcn36xx *wcn); |
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| 462 | void wcn36xx_dxe_deinit(struct wcn36xx *wcn); |
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| 463 | int wcn36xx_dxe_init_channels(struct wcn36xx *wcn); |
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| 464 | int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn, |
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| 465 | struct wcn36xx_vif *vif_priv, |
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| 466 | struct wcn36xx_tx_bd *bd, |
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| 467 | struct sk_buff *skb, |
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| 468 | bool is_low); |
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| 469 | int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn); |
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| 470 | void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status); |
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| 471 | #endif /* _DXE_H_ */ |
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| 472 | |
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