1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef B43_H_ |
3 | #define B43_H_ |
4 | |
5 | #include <linux/kernel.h> |
6 | #include <linux/spinlock.h> |
7 | #include <linux/interrupt.h> |
8 | #include <linux/hw_random.h> |
9 | #include <linux/bcma/bcma.h> |
10 | #include <linux/ssb/ssb.h> |
11 | #include <linux/completion.h> |
12 | #include <net/mac80211.h> |
13 | |
14 | #include "debugfs.h" |
15 | #include "leds.h" |
16 | #include "rfkill.h" |
17 | #include "bus.h" |
18 | #include "lo.h" |
19 | #include "phy_common.h" |
20 | |
21 | |
22 | #ifdef CONFIG_B43_DEBUG |
23 | # define B43_DEBUG 1 |
24 | #else |
25 | # define B43_DEBUG 0 |
26 | #endif |
27 | |
28 | /* MMIO offsets */ |
29 | #define B43_MMIO_DMA0_REASON 0x20 |
30 | #define B43_MMIO_DMA0_IRQ_MASK 0x24 |
31 | #define B43_MMIO_DMA1_REASON 0x28 |
32 | #define B43_MMIO_DMA1_IRQ_MASK 0x2C |
33 | #define B43_MMIO_DMA2_REASON 0x30 |
34 | #define B43_MMIO_DMA2_IRQ_MASK 0x34 |
35 | #define B43_MMIO_DMA3_REASON 0x38 |
36 | #define B43_MMIO_DMA3_IRQ_MASK 0x3C |
37 | #define B43_MMIO_DMA4_REASON 0x40 |
38 | #define B43_MMIO_DMA4_IRQ_MASK 0x44 |
39 | #define B43_MMIO_DMA5_REASON 0x48 |
40 | #define B43_MMIO_DMA5_IRQ_MASK 0x4C |
41 | #define B43_MMIO_MACCTL 0x120 /* MAC control */ |
42 | #define B43_MMIO_MACCMD 0x124 /* MAC command */ |
43 | #define B43_MMIO_GEN_IRQ_REASON 0x128 |
44 | #define B43_MMIO_GEN_IRQ_MASK 0x12C |
45 | #define B43_MMIO_RAM_CONTROL 0x130 |
46 | #define B43_MMIO_RAM_DATA 0x134 |
47 | #define B43_MMIO_PS_STATUS 0x140 |
48 | #define B43_MMIO_RADIO_HWENABLED_HI 0x158 |
49 | #define B43_MMIO_MAC_HW_CAP 0x15C /* MAC capabilities (corerev >= 13) */ |
50 | #define B43_MMIO_SHM_CONTROL 0x160 |
51 | #define B43_MMIO_SHM_DATA 0x164 |
52 | #define B43_MMIO_SHM_DATA_UNALIGNED 0x166 |
53 | #define B43_MMIO_XMITSTAT_0 0x170 |
54 | #define B43_MMIO_XMITSTAT_1 0x174 |
55 | #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ |
56 | #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ |
57 | #define B43_MMIO_TSF_CFP_REP 0x188 |
58 | #define B43_MMIO_TSF_CFP_START 0x18C |
59 | #define B43_MMIO_TSF_CFP_MAXDUR 0x190 |
60 | |
61 | /* 32-bit DMA */ |
62 | #define B43_MMIO_DMA32_BASE0 0x200 |
63 | #define B43_MMIO_DMA32_BASE1 0x220 |
64 | #define B43_MMIO_DMA32_BASE2 0x240 |
65 | #define B43_MMIO_DMA32_BASE3 0x260 |
66 | #define B43_MMIO_DMA32_BASE4 0x280 |
67 | #define B43_MMIO_DMA32_BASE5 0x2A0 |
68 | /* 64-bit DMA */ |
69 | #define B43_MMIO_DMA64_BASE0 0x200 |
70 | #define B43_MMIO_DMA64_BASE1 0x240 |
71 | #define B43_MMIO_DMA64_BASE2 0x280 |
72 | #define B43_MMIO_DMA64_BASE3 0x2C0 |
73 | #define B43_MMIO_DMA64_BASE4 0x300 |
74 | #define B43_MMIO_DMA64_BASE5 0x340 |
75 | |
76 | /* PIO on core rev < 11 */ |
77 | #define B43_MMIO_PIO_BASE0 0x300 |
78 | #define B43_MMIO_PIO_BASE1 0x310 |
79 | #define B43_MMIO_PIO_BASE2 0x320 |
80 | #define B43_MMIO_PIO_BASE3 0x330 |
81 | #define B43_MMIO_PIO_BASE4 0x340 |
82 | #define B43_MMIO_PIO_BASE5 0x350 |
83 | #define B43_MMIO_PIO_BASE6 0x360 |
84 | #define B43_MMIO_PIO_BASE7 0x370 |
85 | /* PIO on core rev >= 11 */ |
86 | #define B43_MMIO_PIO11_BASE0 0x200 |
87 | #define B43_MMIO_PIO11_BASE1 0x240 |
88 | #define B43_MMIO_PIO11_BASE2 0x280 |
89 | #define B43_MMIO_PIO11_BASE3 0x2C0 |
90 | #define B43_MMIO_PIO11_BASE4 0x300 |
91 | #define B43_MMIO_PIO11_BASE5 0x340 |
92 | |
93 | #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */ |
94 | #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */ |
95 | #define B43_MMIO_PHY_VER 0x3E0 |
96 | #define B43_MMIO_PHY_RADIO 0x3E2 |
97 | #define B43_MMIO_PHY0 0x3E6 |
98 | #define B43_MMIO_ANTENNA 0x3E8 |
99 | #define B43_MMIO_CHANNEL 0x3F0 |
100 | #define B43_MMIO_CHANNEL_EXT 0x3F4 |
101 | #define B43_MMIO_RADIO_CONTROL 0x3F6 |
102 | #define B43_MMIO_RADIO_DATA_HIGH 0x3F8 |
103 | #define B43_MMIO_RADIO_DATA_LOW 0x3FA |
104 | #define B43_MMIO_PHY_CONTROL 0x3FC |
105 | #define B43_MMIO_PHY_DATA 0x3FE |
106 | #define B43_MMIO_MACFILTER_CONTROL 0x420 |
107 | #define B43_MMIO_MACFILTER_DATA 0x422 |
108 | #define B43_MMIO_RCMTA_COUNT 0x43C |
109 | #define B43_MMIO_PSM_PHY_HDR 0x492 |
110 | #define B43_MMIO_RADIO_HWENABLED_LO 0x49A |
111 | #define B43_MMIO_GPIO_CONTROL 0x49C |
112 | #define B43_MMIO_GPIO_MASK 0x49E |
113 | #define B43_MMIO_TXE0_CTL 0x500 |
114 | #define B43_MMIO_TXE0_AUX 0x502 |
115 | #define B43_MMIO_TXE0_TS_LOC 0x504 |
116 | #define B43_MMIO_TXE0_TIME_OUT 0x506 |
117 | #define B43_MMIO_TXE0_WM_0 0x508 |
118 | #define B43_MMIO_TXE0_WM_1 0x50A |
119 | #define B43_MMIO_TXE0_PHYCTL 0x50C |
120 | #define B43_MMIO_TXE0_STATUS 0x50E |
121 | #define B43_MMIO_TXE0_MMPLCP0 0x510 |
122 | #define B43_MMIO_TXE0_MMPLCP1 0x512 |
123 | #define B43_MMIO_TXE0_PHYCTL1 0x514 |
124 | #define B43_MMIO_XMTFIFODEF 0x520 |
125 | #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */ |
126 | #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */ |
127 | #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */ |
128 | #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */ |
129 | #define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */ |
130 | #define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */ |
131 | #define B43_MMIO_XMTFIFOCMD 0x540 |
132 | #define B43_MMIO_XMTFIFOFLUSH 0x542 |
133 | #define B43_MMIO_XMTFIFOTHRESH 0x544 |
134 | #define B43_MMIO_XMTFIFORDY 0x546 |
135 | #define B43_MMIO_XMTFIFOPRIRDY 0x548 |
136 | #define B43_MMIO_XMTFIFORQPRI 0x54A |
137 | #define B43_MMIO_XMTTPLATETXPTR 0x54C |
138 | #define B43_MMIO_XMTTPLATEPTR 0x550 |
139 | #define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */ |
140 | #define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */ |
141 | #define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */ |
142 | #define B43_MMIO_XMTTPLATEDATALO 0x560 |
143 | #define B43_MMIO_XMTTPLATEDATAHI 0x562 |
144 | #define B43_MMIO_XMTSEL 0x568 |
145 | #define B43_MMIO_XMTTXCNT 0x56A |
146 | #define B43_MMIO_XMTTXSHMADDR 0x56C |
147 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 |
148 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 |
149 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 |
150 | #define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E |
151 | #define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630 |
152 | #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */ |
153 | #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */ |
154 | #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ |
155 | #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ |
156 | #define B43_MMIO_RNG 0x65A |
157 | #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ |
158 | #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ |
159 | #define B43_MMIO_IFSSTAT 0x690 |
160 | #define B43_MMIO_IFSMEDBUSYCTL 0x692 |
161 | #define B43_MMIO_IFTXDUR 0x694 |
162 | #define B43_MMIO_IFSCTL_USE_EDCF 0x0004 |
163 | #define B43_MMIO_POWERUP_DELAY 0x6A8 |
164 | #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */ |
165 | #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */ |
166 | #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */ |
167 | #define B43_MMIO_WEPCTL 0x7C0 |
168 | |
169 | /* SPROM boardflags_lo values */ |
170 | #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ |
171 | #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ |
172 | #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ |
173 | #define 0x0008 /* software calculates nrssi slope. */ |
174 | #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ |
175 | #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ |
176 | #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ |
177 | #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */ |
178 | #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */ |
179 | #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ |
180 | #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */ |
181 | #define B43_BFL_FEM 0x0800 /* supports the Front End Module */ |
182 | #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */ |
183 | #define B43_BFL_HGPA 0x2000 /* had high gain PA */ |
184 | #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ |
185 | #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ |
186 | |
187 | /* SPROM boardflags_hi values */ |
188 | #define B43_BFH_NOPA 0x0001 /* has no PA */ |
189 | #define 0x0002 /* RSSI uses positive slope (not TSSI) */ |
190 | #define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */ |
191 | #define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared |
192 | * with bluetooth */ |
193 | #define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ |
194 | #define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */ |
195 | #define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna |
196 | * with bluetooth */ |
197 | #define B43_BFH_NOCBUCK 0x0080 |
198 | #define B43_BFH_PALDO 0x0200 |
199 | #define B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */ |
200 | |
201 | /* SPROM boardflags2_lo values */ |
202 | #define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ |
203 | #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ |
204 | #define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ |
205 | #define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ |
206 | #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ |
207 | #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ |
208 | #define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ |
209 | #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ |
210 | #define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ |
211 | #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ |
212 | #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ |
213 | #define B43_BFL2_SINGLEANT_CCK 0x1000 |
214 | #define B43_BFL2_2G_SPUR_WAR 0x2000 |
215 | |
216 | /* SPROM boardflags2_hi values */ |
217 | #define B43_BFH2_GPLL_WAR2 0x0001 |
218 | #define B43_BFH2_IPALVLSHIFT_3P3 0x0002 |
219 | #define B43_BFH2_INTERNDET_TXIQCAL 0x0004 |
220 | #define B43_BFH2_XTALBUFOUTEN 0x0008 |
221 | |
222 | /* GPIO register offset, in both ChipCommon and PCI core. */ |
223 | #define B43_GPIO_CONTROL 0x6c |
224 | |
225 | /* SHM Routing */ |
226 | enum { |
227 | B43_SHM_UCODE, /* Microcode memory */ |
228 | B43_SHM_SHARED, /* Shared memory */ |
229 | B43_SHM_SCRATCH, /* Scratch memory */ |
230 | B43_SHM_HW, /* Internal hardware register */ |
231 | B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */ |
232 | }; |
233 | /* SHM Routing modifiers */ |
234 | #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */ |
235 | #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */ |
236 | #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \ |
237 | B43_SHM_AUTOINC_W) |
238 | |
239 | /* Misc SHM_SHARED offsets */ |
240 | #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */ |
241 | #define B43_SHM_SH_PCTLWDPOS 0x0008 |
242 | #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */ |
243 | #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */ |
244 | #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */ |
245 | #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */ |
246 | #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */ |
247 | #define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */ |
248 | #define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */ |
249 | #define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */ |
250 | #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */ |
251 | #define B43_SHM_SH_RADAR 0x0066 /* Radar register */ |
252 | #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */ |
253 | #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */ |
254 | #define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */ |
255 | #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ |
256 | #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */ |
257 | #define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */ |
258 | #define B43_SHM_SH_MACHW_L 0x00C0 /* Location where the ucode expects the MAC capabilities */ |
259 | #define B43_SHM_SH_MACHW_H 0x00C2 /* Location where the ucode expects the MAC capabilities */ |
260 | #define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */ |
261 | #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ |
262 | /* TSSI information */ |
263 | #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */ |
264 | #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */ |
265 | #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */ |
266 | #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */ |
267 | /* SHM_SHARED TX FIFO variables */ |
268 | #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */ |
269 | #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */ |
270 | #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */ |
271 | #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */ |
272 | /* SHM_SHARED background noise */ |
273 | #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */ |
274 | #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */ |
275 | #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */ |
276 | /* SHM_SHARED crypto engine */ |
277 | #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */ |
278 | #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */ |
279 | #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */ |
280 | #define B43_SHM_SH_TKIPTSCTTAK 0x0318 |
281 | #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */ |
282 | #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */ |
283 | /* SHM_SHARED WME variables */ |
284 | #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */ |
285 | #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */ |
286 | #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */ |
287 | /* SHM_SHARED powersave mode related */ |
288 | #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */ |
289 | #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */ |
290 | #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */ |
291 | /* SHM_SHARED beacon/AP variables */ |
292 | #define B43_SHM_SH_BT_BASE0 0x0068 /* Beacon template base 0 */ |
293 | #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ |
294 | #define B43_SHM_SH_BT_BASE1 0x0468 /* Beacon template base 1 */ |
295 | #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ |
296 | #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ |
297 | #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */ |
298 | #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */ |
299 | #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */ |
300 | #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */ |
301 | #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */ |
302 | #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */ |
303 | #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */ |
304 | #define B43_SHM_SH_BCN_LI 0x00B6 /* beacon listen interval */ |
305 | /* SHM_SHARED ACK/CTS control */ |
306 | #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */ |
307 | /* SHM_SHARED probe response variables */ |
308 | #define 0x0160 /* Probe Response SSID */ |
309 | #define 0x0048 /* Probe Response SSID length */ |
310 | #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */ |
311 | #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */ |
312 | #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */ |
313 | /* SHM_SHARED rate tables */ |
314 | #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */ |
315 | #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */ |
316 | #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */ |
317 | #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */ |
318 | /* SHM_SHARED microcode soft registers */ |
319 | #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */ |
320 | #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */ |
321 | #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */ |
322 | #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */ |
323 | #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */ |
324 | #define B43_SHM_SH_UCODESTAT_INVALID 0 |
325 | #define B43_SHM_SH_UCODESTAT_INIT 1 |
326 | #define B43_SHM_SH_UCODESTAT_ACTIVE 2 |
327 | #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */ |
328 | #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */ |
329 | #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */ |
330 | #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */ |
331 | #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */ |
332 | /* SHM_SHARED tx iq workarounds */ |
333 | #define B43_SHM_SH_NPHY_TXIQW0 0x0700 |
334 | #define B43_SHM_SH_NPHY_TXIQW1 0x0702 |
335 | #define B43_SHM_SH_NPHY_TXIQW2 0x0704 |
336 | #define B43_SHM_SH_NPHY_TXIQW3 0x0706 |
337 | /* SHM_SHARED tx pwr ctrl */ |
338 | #define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708 |
339 | #define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E |
340 | |
341 | /* SHM_SCRATCH offsets */ |
342 | #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */ |
343 | #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */ |
344 | #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */ |
345 | #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */ |
346 | #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */ |
347 | #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */ |
348 | #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */ |
349 | #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */ |
350 | #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */ |
351 | #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */ |
352 | |
353 | /* Hardware Radio Enable masks */ |
354 | #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) |
355 | #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) |
356 | |
357 | /* HostFlags. See b43_hf_read/write() */ |
358 | #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */ |
359 | #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */ |
360 | #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */ |
361 | #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */ |
362 | #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */ |
363 | #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */ |
364 | #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */ |
365 | #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */ |
366 | #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */ |
367 | #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */ |
368 | #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */ |
369 | #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */ |
370 | #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */ |
371 | #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */ |
372 | #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */ |
373 | #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */ |
374 | #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */ |
375 | #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */ |
376 | #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */ |
377 | #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */ |
378 | #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */ |
379 | #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */ |
380 | #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */ |
381 | #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */ |
382 | #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */ |
383 | #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */ |
384 | #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */ |
385 | #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */ |
386 | #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */ |
387 | #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */ |
388 | #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */ |
389 | #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */ |
390 | #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */ |
391 | #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */ |
392 | #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */ |
393 | |
394 | /* Firmware capabilities field in SHM (Opensource firmware only) */ |
395 | #define B43_FWCAPA_HWCRYPTO 0x0001 |
396 | #define B43_FWCAPA_QOS 0x0002 |
397 | |
398 | /* MacFilter offsets. */ |
399 | #define B43_MACFILTER_SELF 0x0000 |
400 | #define B43_MACFILTER_BSSID 0x0003 |
401 | |
402 | /* PowerControl */ |
403 | #define B43_PCTL_IN 0xB0 |
404 | #define B43_PCTL_OUT 0xB4 |
405 | #define B43_PCTL_OUTENABLE 0xB8 |
406 | #define B43_PCTL_XTAL_POWERUP 0x40 |
407 | #define B43_PCTL_PLL_POWERDOWN 0x80 |
408 | |
409 | /* PowerControl Clock Modes */ |
410 | #define B43_PCTL_CLK_FAST 0x00 |
411 | #define B43_PCTL_CLK_SLOW 0x01 |
412 | #define B43_PCTL_CLK_DYNAMIC 0x02 |
413 | |
414 | #define B43_PCTL_FORCE_SLOW 0x0800 |
415 | #define B43_PCTL_FORCE_PLL 0x1000 |
416 | #define B43_PCTL_DYN_XTAL 0x2000 |
417 | |
418 | /* PHYVersioning */ |
419 | #define B43_PHYTYPE_A 0x00 |
420 | #define B43_PHYTYPE_B 0x01 |
421 | #define B43_PHYTYPE_G 0x02 |
422 | #define B43_PHYTYPE_N 0x04 |
423 | #define B43_PHYTYPE_LP 0x05 |
424 | #define B43_PHYTYPE_SSLPN 0x06 |
425 | #define B43_PHYTYPE_HT 0x07 |
426 | #define B43_PHYTYPE_LCN 0x08 |
427 | #define B43_PHYTYPE_LCNXN 0x09 |
428 | #define B43_PHYTYPE_LCN40 0x0a |
429 | #define B43_PHYTYPE_AC 0x0b |
430 | |
431 | /* PHYRegisters */ |
432 | #define B43_PHY_ILT_A_CTRL 0x0072 |
433 | #define B43_PHY_ILT_A_DATA1 0x0073 |
434 | #define B43_PHY_ILT_A_DATA2 0x0074 |
435 | #define B43_PHY_G_LO_CONTROL 0x0810 |
436 | #define B43_PHY_ILT_G_CTRL 0x0472 |
437 | #define B43_PHY_ILT_G_DATA1 0x0473 |
438 | #define B43_PHY_ILT_G_DATA2 0x0474 |
439 | #define B43_PHY_A_PCTL 0x007B |
440 | #define B43_PHY_G_PCTL 0x0029 |
441 | #define B43_PHY_A_CRS 0x0029 |
442 | #define B43_PHY_RADIO_BITFIELD 0x0401 |
443 | #define B43_PHY_G_CRS 0x0429 |
444 | #define 0x0803 |
445 | #define 0x0804 |
446 | |
447 | /* RadioRegisters */ |
448 | #define B43_RADIOCTL_ID 0x01 |
449 | |
450 | /* MAC Control bitfield */ |
451 | #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */ |
452 | #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */ |
453 | #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */ |
454 | #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */ |
455 | #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */ |
456 | #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */ |
457 | #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */ |
458 | #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */ |
459 | #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */ |
460 | #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */ |
461 | #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */ |
462 | #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */ |
463 | #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */ |
464 | #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */ |
465 | #define B43_MACCTL_PHY_LOCK 0x00200000 |
466 | #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */ |
467 | #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */ |
468 | #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */ |
469 | #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */ |
470 | #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */ |
471 | #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */ |
472 | #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */ |
473 | #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */ |
474 | #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */ |
475 | #define B43_MACCTL_GMODE 0x80000000 /* G Mode */ |
476 | |
477 | /* MAC Command bitfield */ |
478 | #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */ |
479 | #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */ |
480 | #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */ |
481 | #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */ |
482 | #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */ |
483 | |
484 | /* B43_MMIO_PSM_PHY_HDR bits */ |
485 | #define B43_PSM_HDR_MAC_PHY_RESET 0x00000001 |
486 | #define B43_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002 |
487 | #define B43_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004 |
488 | |
489 | /* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */ |
490 | #define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100 |
491 | #define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200 |
492 | #define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000 |
493 | #define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000 |
494 | |
495 | /* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */ |
496 | #define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */ |
497 | #define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */ |
498 | #define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */ |
499 | #define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */ |
500 | #define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */ |
501 | #define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ |
502 | #define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */ |
503 | #define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */ |
504 | #define B43_BCMA_IOCTL_PHY_BW_80MHZ 0x000000C0 /* 80 MHz bandwidth */ |
505 | #define B43_BCMA_IOCTL_DAC 0x00000300 /* Highspeed DAC mode control field */ |
506 | #define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */ |
507 | |
508 | /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */ |
509 | #define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */ |
510 | #define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */ |
511 | #define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */ |
512 | #define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */ |
513 | |
514 | /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ |
515 | #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ |
516 | #define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */ |
517 | #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ |
518 | #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */ |
519 | #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */ |
520 | #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ |
521 | #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ |
522 | #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ |
523 | #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */ |
524 | |
525 | /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */ |
526 | #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */ |
527 | #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */ |
528 | #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */ |
529 | #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */ |
530 | |
531 | /* Generic-Interrupt reasons. */ |
532 | #define B43_IRQ_MAC_SUSPENDED 0x00000001 |
533 | #define B43_IRQ_BEACON 0x00000002 |
534 | #define B43_IRQ_TBTT_INDI 0x00000004 |
535 | #define B43_IRQ_BEACON_TX_OK 0x00000008 |
536 | #define B43_IRQ_BEACON_CANCEL 0x00000010 |
537 | #define B43_IRQ_ATIM_END 0x00000020 |
538 | #define B43_IRQ_PMQ 0x00000040 |
539 | #define B43_IRQ_PIO_WORKAROUND 0x00000100 |
540 | #define B43_IRQ_MAC_TXERR 0x00000200 |
541 | #define B43_IRQ_PHY_TXERR 0x00000800 |
542 | #define B43_IRQ_PMEVENT 0x00001000 |
543 | #define B43_IRQ_TIMER0 0x00002000 |
544 | #define B43_IRQ_TIMER1 0x00004000 |
545 | #define B43_IRQ_DMA 0x00008000 |
546 | #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000 |
547 | #define B43_IRQ_CCA_MEASURE_OK 0x00020000 |
548 | #define B43_IRQ_NOISESAMPLE_OK 0x00040000 |
549 | #define B43_IRQ_UCODE_DEBUG 0x08000000 |
550 | #define B43_IRQ_RFKILL 0x10000000 |
551 | #define B43_IRQ_TX_OK 0x20000000 |
552 | #define B43_IRQ_PHY_G_CHANGED 0x40000000 |
553 | #define B43_IRQ_TIMEOUT 0x80000000 |
554 | |
555 | #define B43_IRQ_ALL 0xFFFFFFFF |
556 | #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \ |
557 | B43_IRQ_ATIM_END | \ |
558 | B43_IRQ_PMQ | \ |
559 | B43_IRQ_MAC_TXERR | \ |
560 | B43_IRQ_PHY_TXERR | \ |
561 | B43_IRQ_DMA | \ |
562 | B43_IRQ_TXFIFO_FLUSH_OK | \ |
563 | B43_IRQ_NOISESAMPLE_OK | \ |
564 | B43_IRQ_UCODE_DEBUG | \ |
565 | B43_IRQ_RFKILL | \ |
566 | B43_IRQ_TX_OK) |
567 | |
568 | /* The firmware register to fetch the debug-IRQ reason from. */ |
569 | #define B43_DEBUGIRQ_REASON_REG 63 |
570 | /* Debug-IRQ reasons. */ |
571 | #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */ |
572 | #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */ |
573 | #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */ |
574 | #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */ |
575 | #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */ |
576 | |
577 | /* The firmware register that contains the "marker" line. */ |
578 | #define B43_MARKER_ID_REG 2 |
579 | #define B43_MARKER_LINE_REG 3 |
580 | |
581 | /* The firmware register to fetch the panic reason from. */ |
582 | #define B43_FWPANIC_REASON_REG 3 |
583 | /* Firmware panic reason codes */ |
584 | #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */ |
585 | #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */ |
586 | |
587 | /* The firmware register that contains the watchdog counter. */ |
588 | #define B43_WATCHDOG_REG 1 |
589 | |
590 | /* Device specific rate values. |
591 | * The actual values defined here are (rate_in_mbps * 2). |
592 | * Some code depends on this. Don't change it. */ |
593 | #define B43_CCK_RATE_1MB 0x02 |
594 | #define B43_CCK_RATE_2MB 0x04 |
595 | #define B43_CCK_RATE_5MB 0x0B |
596 | #define B43_CCK_RATE_11MB 0x16 |
597 | #define B43_OFDM_RATE_6MB 0x0C |
598 | #define B43_OFDM_RATE_9MB 0x12 |
599 | #define B43_OFDM_RATE_12MB 0x18 |
600 | #define B43_OFDM_RATE_18MB 0x24 |
601 | #define B43_OFDM_RATE_24MB 0x30 |
602 | #define B43_OFDM_RATE_36MB 0x48 |
603 | #define B43_OFDM_RATE_48MB 0x60 |
604 | #define B43_OFDM_RATE_54MB 0x6C |
605 | /* Convert a b43 rate value to a rate in 100kbps */ |
606 | #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2) |
607 | |
608 | #define B43_DEFAULT_SHORT_RETRY_LIMIT 7 |
609 | #define B43_DEFAULT_LONG_RETRY_LIMIT 4 |
610 | |
611 | #define B43_PHY_TX_BADNESS_LIMIT 1000 |
612 | |
613 | /* Max size of a security key */ |
614 | #define B43_SEC_KEYSIZE 16 |
615 | /* Max number of group keys */ |
616 | #define B43_NR_GROUP_KEYS 4 |
617 | /* Max number of pairwise keys */ |
618 | #define B43_NR_PAIRWISE_KEYS 50 |
619 | /* Security algorithms. */ |
620 | enum { |
621 | B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ |
622 | B43_SEC_ALGO_WEP40, |
623 | B43_SEC_ALGO_TKIP, |
624 | B43_SEC_ALGO_AES, |
625 | B43_SEC_ALGO_WEP104, |
626 | B43_SEC_ALGO_AES_LEGACY, |
627 | }; |
628 | |
629 | struct b43_dmaring; |
630 | |
631 | /* The firmware file header */ |
632 | #define B43_FW_TYPE_UCODE 'u' |
633 | #define B43_FW_TYPE_PCM 'p' |
634 | #define B43_FW_TYPE_IV 'i' |
635 | struct { |
636 | /* File type */ |
637 | u8 ; |
638 | /* File format version */ |
639 | u8 ; |
640 | u8 [2]; |
641 | /* Size of the data. For ucode and PCM this is in bytes. |
642 | * For IV this is number-of-ivs. */ |
643 | __be32 ; |
644 | } __packed; |
645 | |
646 | /* Initial Value file format */ |
647 | #define B43_IV_OFFSET_MASK 0x7FFF |
648 | #define B43_IV_32BIT 0x8000 |
649 | struct b43_iv { |
650 | __be16 offset_size; |
651 | union { |
652 | __be16 d16; |
653 | __be32 d32; |
654 | } __packed data; |
655 | } __packed; |
656 | |
657 | |
658 | /* Data structures for DMA transmission, per 80211 core. */ |
659 | struct b43_dma { |
660 | struct b43_dmaring *tx_ring_AC_BK; /* Background */ |
661 | struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */ |
662 | struct b43_dmaring *tx_ring_AC_VI; /* Video */ |
663 | struct b43_dmaring *tx_ring_AC_VO; /* Voice */ |
664 | struct b43_dmaring *tx_ring_mcast; /* Multicast */ |
665 | |
666 | struct b43_dmaring *rx_ring; |
667 | |
668 | u32 translation; /* Routing bits */ |
669 | bool translation_in_low; /* Should translation bit go into low addr? */ |
670 | bool parity; /* Check for parity */ |
671 | }; |
672 | |
673 | struct b43_pio_txqueue; |
674 | struct b43_pio_rxqueue; |
675 | |
676 | /* Data structures for PIO transmission, per 80211 core. */ |
677 | struct b43_pio { |
678 | struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */ |
679 | struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */ |
680 | struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */ |
681 | struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */ |
682 | struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */ |
683 | |
684 | struct b43_pio_rxqueue *rx_queue; |
685 | }; |
686 | |
687 | /* Context information for a noise calculation (Link Quality). */ |
688 | struct b43_noise_calculation { |
689 | bool calculation_running; |
690 | u8 nr_samples; |
691 | s8 samples[8][4]; |
692 | }; |
693 | |
694 | struct b43_stats { |
695 | u8 link_noise; |
696 | }; |
697 | |
698 | struct b43_key { |
699 | /* If keyconf is NULL, this key is disabled. |
700 | * keyconf is a cookie. Don't derefenrence it outside of the set_key |
701 | * path, because b43 doesn't own it. */ |
702 | struct ieee80211_key_conf *keyconf; |
703 | u8 algorithm; |
704 | }; |
705 | |
706 | /* SHM offsets to the QOS data structures for the 4 different queues. */ |
707 | #define B43_QOS_QUEUE_NUM 4 |
708 | #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \ |
709 | (B43_NR_QOSPARAMS * sizeof(u16) * (queue))) |
710 | #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0) |
711 | #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1) |
712 | #define B43_QOS_VIDEO B43_QOS_PARAMS(2) |
713 | #define B43_QOS_VOICE B43_QOS_PARAMS(3) |
714 | |
715 | /* QOS parameter hardware data structure offsets. */ |
716 | #define B43_NR_QOSPARAMS 16 |
717 | enum { |
718 | B43_QOSPARAM_TXOP = 0, |
719 | B43_QOSPARAM_CWMIN, |
720 | B43_QOSPARAM_CWMAX, |
721 | B43_QOSPARAM_CWCUR, |
722 | B43_QOSPARAM_AIFS, |
723 | B43_QOSPARAM_BSLOTS, |
724 | B43_QOSPARAM_REGGAP, |
725 | B43_QOSPARAM_STATUS, |
726 | }; |
727 | |
728 | /* QOS parameters for a queue. */ |
729 | struct b43_qos_params { |
730 | /* The QOS parameters */ |
731 | struct ieee80211_tx_queue_params p; |
732 | }; |
733 | |
734 | struct b43_wl; |
735 | |
736 | /* The type of the firmware file. */ |
737 | enum b43_firmware_file_type { |
738 | B43_FWTYPE_PROPRIETARY, |
739 | B43_FWTYPE_OPENSOURCE, |
740 | B43_NR_FWTYPES, |
741 | }; |
742 | |
743 | /* Context data for fetching firmware. */ |
744 | struct b43_request_fw_context { |
745 | /* The device we are requesting the fw for. */ |
746 | struct b43_wldev *dev; |
747 | /* a pointer to the firmware object */ |
748 | const struct firmware *blob; |
749 | /* The type of firmware to request. */ |
750 | enum b43_firmware_file_type req_type; |
751 | /* Error messages for each firmware type. */ |
752 | char errors[B43_NR_FWTYPES][128]; |
753 | /* Temporary buffer for storing the firmware name. */ |
754 | char fwname[64]; |
755 | /* A fatal error occurred while requesting. Firmware request |
756 | * can not continue, as any other request will also fail. */ |
757 | int fatal_failure; |
758 | }; |
759 | |
760 | /* In-memory representation of a cached microcode file. */ |
761 | struct b43_firmware_file { |
762 | const char *filename; |
763 | const struct firmware *data; |
764 | /* Type of the firmware file name. Note that this does only indicate |
765 | * the type by the firmware name. NOT the file contents. |
766 | * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource |
767 | * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware |
768 | * binary code, not just the filename. |
769 | */ |
770 | enum b43_firmware_file_type type; |
771 | }; |
772 | |
773 | enum b43_firmware_hdr_format { |
774 | B43_FW_HDR_598, |
775 | B43_FW_HDR_410, |
776 | B43_FW_HDR_351, |
777 | }; |
778 | |
779 | /* Pointers to the firmware data and meta information about it. */ |
780 | struct b43_firmware { |
781 | /* Microcode */ |
782 | struct b43_firmware_file ucode; |
783 | /* PCM code */ |
784 | struct b43_firmware_file pcm; |
785 | /* Initial MMIO values for the firmware */ |
786 | struct b43_firmware_file initvals; |
787 | /* Initial MMIO values for the firmware, band-specific */ |
788 | struct b43_firmware_file initvals_band; |
789 | |
790 | /* Firmware revision */ |
791 | u16 rev; |
792 | /* Firmware patchlevel */ |
793 | u16 patch; |
794 | |
795 | /* Format of header used by firmware */ |
796 | enum b43_firmware_hdr_format hdr_format; |
797 | |
798 | /* Set to true, if we are using an opensource firmware. |
799 | * Use this to check for proprietary vs opensource. */ |
800 | bool opensource; |
801 | /* Set to true, if the core needs a PCM firmware, but |
802 | * we failed to load one. This is always false for |
803 | * core rev > 10, as these don't need PCM firmware. */ |
804 | bool pcm_request_failed; |
805 | }; |
806 | |
807 | enum b43_band { |
808 | B43_BAND_2G = 0, |
809 | B43_BAND_5G_LO = 1, |
810 | B43_BAND_5G_MI = 2, |
811 | B43_BAND_5G_HI = 3, |
812 | }; |
813 | |
814 | /* Device (802.11 core) initialization status. */ |
815 | enum { |
816 | B43_STAT_UNINIT = 0, /* Uninitialized. */ |
817 | B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */ |
818 | B43_STAT_STARTED = 2, /* Up and running. */ |
819 | }; |
820 | #define b43_status(wldev) atomic_read(&(wldev)->__init_status) |
821 | #define b43_set_status(wldev, stat) do { \ |
822 | atomic_set(&(wldev)->__init_status, (stat)); \ |
823 | smp_wmb(); \ |
824 | } while (0) |
825 | |
826 | /* Data structure for one wireless device (802.11 core) */ |
827 | struct b43_wldev { |
828 | struct b43_bus_dev *dev; |
829 | struct b43_wl *wl; |
830 | /* a completion event structure needed if this call is asynchronous */ |
831 | struct completion fw_load_complete; |
832 | |
833 | /* The device initialization status. |
834 | * Use b43_status() to query. */ |
835 | atomic_t __init_status; |
836 | |
837 | bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */ |
838 | bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */ |
839 | bool radio_hw_enable; /* saved state of radio hardware enabled state */ |
840 | bool qos_enabled; /* TRUE, if QoS is used. */ |
841 | bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */ |
842 | bool use_pio; /* TRUE if next init should use PIO */ |
843 | |
844 | /* PHY/Radio device. */ |
845 | struct b43_phy phy; |
846 | |
847 | union { |
848 | /* DMA engines. */ |
849 | struct b43_dma dma; |
850 | /* PIO engines. */ |
851 | struct b43_pio pio; |
852 | }; |
853 | /* Use b43_using_pio_transfers() to check whether we are using |
854 | * DMA or PIO data transfers. */ |
855 | bool __using_pio_transfers; |
856 | |
857 | /* Various statistics about the physical device. */ |
858 | struct b43_stats stats; |
859 | |
860 | /* Reason code of the last interrupt. */ |
861 | u32 irq_reason; |
862 | u32 dma_reason[6]; |
863 | /* The currently active generic-interrupt mask. */ |
864 | u32 irq_mask; |
865 | |
866 | /* Link Quality calculation context. */ |
867 | struct b43_noise_calculation noisecalc; |
868 | /* if > 0 MAC is suspended. if == 0 MAC is enabled. */ |
869 | int mac_suspended; |
870 | |
871 | /* Periodic tasks */ |
872 | struct delayed_work periodic_work; |
873 | unsigned int periodic_state; |
874 | |
875 | struct work_struct restart_work; |
876 | |
877 | /* encryption/decryption */ |
878 | u16 ktp; /* Key table pointer */ |
879 | struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS]; |
880 | |
881 | /* Firmware data */ |
882 | struct b43_firmware fw; |
883 | |
884 | /* Devicelist in struct b43_wl (all 802.11 cores) */ |
885 | struct list_head list; |
886 | |
887 | /* Debugging stuff follows. */ |
888 | #ifdef CONFIG_B43_DEBUG |
889 | struct b43_dfsentry *dfsentry; |
890 | unsigned int irq_count; |
891 | unsigned int irq_bit_count[32]; |
892 | unsigned int tx_count; |
893 | unsigned int rx_count; |
894 | #endif |
895 | }; |
896 | |
897 | /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */ |
898 | struct b43_wl { |
899 | /* Pointer to the active wireless device on this chip */ |
900 | struct b43_wldev *current_dev; |
901 | /* Pointer to the ieee80211 hardware data structure */ |
902 | struct ieee80211_hw *hw; |
903 | |
904 | /* Global driver mutex. Every operation must run with this mutex locked. */ |
905 | struct mutex mutex; |
906 | /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ |
907 | * handler, only. This basically is just the IRQ mask register. */ |
908 | spinlock_t hardirq_lock; |
909 | |
910 | /* Set this if we call ieee80211_register_hw() and check if we call |
911 | * ieee80211_unregister_hw(). */ |
912 | bool hw_registered; |
913 | |
914 | /* We can only have one operating interface (802.11 core) |
915 | * at a time. General information about this interface follows. |
916 | */ |
917 | |
918 | struct ieee80211_vif *vif; |
919 | /* The MAC address of the operating interface. */ |
920 | u8 mac_addr[ETH_ALEN]; |
921 | /* Current BSSID */ |
922 | u8 bssid[ETH_ALEN]; |
923 | /* Interface type. (NL80211_IFTYPE_XXX) */ |
924 | int if_type; |
925 | /* Is the card operating in AP, STA or IBSS mode? */ |
926 | bool operating; |
927 | /* filter flags */ |
928 | unsigned int filter_flags; |
929 | /* Stats about the wireless interface */ |
930 | struct ieee80211_low_level_stats ieee_stats; |
931 | |
932 | #ifdef CONFIG_B43_HWRNG |
933 | struct hwrng rng; |
934 | bool rng_initialized; |
935 | char rng_name[30 + 1]; |
936 | #endif /* CONFIG_B43_HWRNG */ |
937 | |
938 | bool radiotap_enabled; |
939 | bool radio_enabled; |
940 | |
941 | /* The beacon we are currently using (AP or IBSS mode). */ |
942 | struct sk_buff *current_beacon; |
943 | bool beacon0_uploaded; |
944 | bool beacon1_uploaded; |
945 | bool beacon_templates_virgin; /* Never wrote the templates? */ |
946 | struct work_struct beacon_update_trigger; |
947 | spinlock_t beacon_lock; |
948 | |
949 | /* The current QOS parameters for the 4 queues. */ |
950 | struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM]; |
951 | |
952 | /* Work for adjustment of the transmission power. |
953 | * This is scheduled when we determine that the actual TX output |
954 | * power doesn't match what we want. */ |
955 | struct work_struct txpower_adjust_work; |
956 | |
957 | /* Packet transmit work */ |
958 | struct work_struct tx_work; |
959 | |
960 | /* Queue of packets to be transmitted. */ |
961 | struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM]; |
962 | |
963 | /* Flag that implement the queues stopping. */ |
964 | bool tx_queue_stopped[B43_QOS_QUEUE_NUM]; |
965 | |
966 | /* firmware loading work */ |
967 | struct work_struct firmware_load; |
968 | |
969 | /* The device LEDs. */ |
970 | struct b43_leds leds; |
971 | |
972 | /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */ |
973 | u8 pio_scratchspace[118] __attribute__((__aligned__(8))); |
974 | u8 pio_tailspace[4] __attribute__((__aligned__(8))); |
975 | }; |
976 | |
977 | static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw) |
978 | { |
979 | return hw->priv; |
980 | } |
981 | |
982 | static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev) |
983 | { |
984 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); |
985 | return ssb_get_drvdata(dev: ssb_dev); |
986 | } |
987 | |
988 | /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */ |
989 | static inline int b43_is_mode(struct b43_wl *wl, int type) |
990 | { |
991 | return (wl->operating && wl->if_type == type); |
992 | } |
993 | |
994 | /** |
995 | * b43_current_band - Returns the currently used band. |
996 | * Returns one of NL80211_BAND_2GHZ and NL80211_BAND_5GHZ. |
997 | */ |
998 | static inline enum nl80211_band b43_current_band(struct b43_wl *wl) |
999 | { |
1000 | return wl->hw->conf.chandef.chan->band; |
1001 | } |
1002 | |
1003 | static inline int b43_bus_may_powerdown(struct b43_wldev *wldev) |
1004 | { |
1005 | return wldev->dev->bus_may_powerdown(wldev->dev); |
1006 | } |
1007 | static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl) |
1008 | { |
1009 | return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl); |
1010 | } |
1011 | static inline int b43_device_is_enabled(struct b43_wldev *wldev) |
1012 | { |
1013 | return wldev->dev->device_is_enabled(wldev->dev); |
1014 | } |
1015 | static inline void b43_device_enable(struct b43_wldev *wldev, |
1016 | u32 core_specific_flags) |
1017 | { |
1018 | wldev->dev->device_enable(wldev->dev, core_specific_flags); |
1019 | } |
1020 | static inline void b43_device_disable(struct b43_wldev *wldev, |
1021 | u32 core_specific_flags) |
1022 | { |
1023 | wldev->dev->device_disable(wldev->dev, core_specific_flags); |
1024 | } |
1025 | |
1026 | static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) |
1027 | { |
1028 | return dev->dev->read16(dev->dev, offset); |
1029 | } |
1030 | |
1031 | static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value) |
1032 | { |
1033 | dev->dev->write16(dev->dev, offset, value); |
1034 | } |
1035 | |
1036 | /* To optimize this check for flush_writes on BCM47XX_BCMA only. */ |
1037 | static inline void b43_write16f(struct b43_wldev *dev, u16 offset, u16 value) |
1038 | { |
1039 | b43_write16(dev, offset, value); |
1040 | #if defined(CONFIG_BCM47XX_BCMA) |
1041 | if (dev->dev->flush_writes) |
1042 | b43_read16(dev, offset); |
1043 | #endif |
1044 | } |
1045 | |
1046 | static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask, |
1047 | u16 set) |
1048 | { |
1049 | b43_write16(dev, offset, value: (b43_read16(dev, offset) & mask) | set); |
1050 | } |
1051 | |
1052 | static inline u32 b43_read32(struct b43_wldev *dev, u16 offset) |
1053 | { |
1054 | return dev->dev->read32(dev->dev, offset); |
1055 | } |
1056 | |
1057 | static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value) |
1058 | { |
1059 | dev->dev->write32(dev->dev, offset, value); |
1060 | } |
1061 | |
1062 | static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask, |
1063 | u32 set) |
1064 | { |
1065 | b43_write32(dev, offset, value: (b43_read32(dev, offset) & mask) | set); |
1066 | } |
1067 | |
1068 | static inline void b43_block_read(struct b43_wldev *dev, void *buffer, |
1069 | size_t count, u16 offset, u8 reg_width) |
1070 | { |
1071 | dev->dev->block_read(dev->dev, buffer, count, offset, reg_width); |
1072 | } |
1073 | |
1074 | static inline void b43_block_write(struct b43_wldev *dev, const void *buffer, |
1075 | size_t count, u16 offset, u8 reg_width) |
1076 | { |
1077 | dev->dev->block_write(dev->dev, buffer, count, offset, reg_width); |
1078 | } |
1079 | |
1080 | static inline bool b43_using_pio_transfers(struct b43_wldev *dev) |
1081 | { |
1082 | return dev->__using_pio_transfers; |
1083 | } |
1084 | |
1085 | static inline void b43_wake_queue(struct b43_wldev *dev, int queue_prio) |
1086 | { |
1087 | if (dev->qos_enabled) |
1088 | ieee80211_wake_queue(hw: dev->wl->hw, queue: queue_prio); |
1089 | else |
1090 | ieee80211_wake_queue(hw: dev->wl->hw, queue: 0); |
1091 | } |
1092 | |
1093 | static inline void b43_stop_queue(struct b43_wldev *dev, int queue_prio) |
1094 | { |
1095 | if (dev->qos_enabled) |
1096 | ieee80211_stop_queue(hw: dev->wl->hw, queue: queue_prio); |
1097 | else |
1098 | ieee80211_stop_queue(hw: dev->wl->hw, queue: 0); |
1099 | } |
1100 | |
1101 | /* Message printing */ |
1102 | __printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...); |
1103 | __printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...); |
1104 | __printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...); |
1105 | __printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...); |
1106 | |
1107 | |
1108 | /* A WARN_ON variant that vanishes when b43 debugging is disabled. |
1109 | * This _also_ evaluates the arg with debugging disabled. */ |
1110 | #if B43_DEBUG |
1111 | # define B43_WARN_ON(x) WARN_ON(x) |
1112 | #else |
1113 | static inline bool __b43_warn_on_dummy(bool x) { return x; } |
1114 | # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x))) |
1115 | #endif |
1116 | |
1117 | /* Convert an integer to a Q5.2 value */ |
1118 | #define INT_TO_Q52(i) ((i) << 2) |
1119 | /* Convert a Q5.2 value to an integer (precision loss!) */ |
1120 | #define Q52_TO_INT(q52) ((q52) >> 2) |
1121 | /* Macros for printing a value in Q5.2 format */ |
1122 | #define Q52_FMT "%u.%u" |
1123 | #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4) |
1124 | |
1125 | #endif /* B43_H_ */ |
1126 | |