1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef B43_PHY_HT_H_ |
3 | #define B43_PHY_HT_H_ |
4 | |
5 | #include "phy_common.h" |
6 | |
7 | |
8 | #define B43_PHY_HT_BBCFG 0x001 /* BB config */ |
9 | #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ |
10 | #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ |
11 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
12 | #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ |
13 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
14 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ |
15 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ |
16 | #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */ |
17 | #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */ |
18 | #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */ |
19 | #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */ |
20 | #define B43_PHY_HT_IQLOCAL_CMDGCTL 0x0C2 /* I/Q LO cal command G control */ |
21 | #define B43_PHY_HT_SAMP_CMD 0x0C3 /* Sample command */ |
22 | #define B43_PHY_HT_SAMP_CMD_STOP 0x0002 /* Stop */ |
23 | #define B43_PHY_HT_SAMP_LOOP_CNT 0x0C4 /* Sample loop count */ |
24 | #define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ |
25 | #define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ |
26 | #define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ |
27 | #define B43_PHY_HT_EST_PWR_C1 0x118 |
28 | #define B43_PHY_HT_EST_PWR_C2 0x119 |
29 | #define B43_PHY_HT_EST_PWR_C3 0x11A |
30 | #define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */ |
31 | #define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */ |
32 | #define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */ |
33 | #define B43_PHY_HT_BW1 0x1CE |
34 | #define B43_PHY_HT_BW2 0x1CF |
35 | #define B43_PHY_HT_BW3 0x1D0 |
36 | #define B43_PHY_HT_BW4 0x1D1 |
37 | #define B43_PHY_HT_BW5 0x1D2 |
38 | #define B43_PHY_HT_BW6 0x1D3 |
39 | #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */ |
40 | #define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */ |
41 | #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */ |
42 | #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */ |
43 | #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */ |
44 | #define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */ |
45 | #define B43_PHY_HT_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ |
46 | #define B43_PHY_HT_TXPCTL_N_TSSID_SHIFT 0 |
47 | #define B43_PHY_HT_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ |
48 | #define B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT 8 |
49 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI 0x1E9 /* TX power control idle TSSI */ |
50 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1 0x003F |
51 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT 0 |
52 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2 0x3F00 |
53 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT 8 |
54 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF 0x8000 /* Raw TSSI offset bin format */ |
55 | #define B43_PHY_HT_TXPCTL_TARG_PWR 0x1EA /* TX power control target power */ |
56 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C1 0x00FF /* Power 0 */ |
57 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0 |
58 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */ |
59 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8 |
60 | #define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED |
61 | #define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE |
62 | #define B43_PHY_HT_TXPCTL_CMD_C2 0x222 |
63 | #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F |
64 | #define 0x219 |
65 | #define 0x21A |
66 | #define 0x21B |
67 | |
68 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) |
69 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) |
70 | #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) |
71 | |
72 | #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) |
73 | #define B43_PHY_HT_RF_SEQ_MODE_CA_OVER 0x0001 /* Core active override */ |
74 | #define B43_PHY_HT_RF_SEQ_MODE_TR_OVER 0x0002 /* Trigger override */ |
75 | #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) |
76 | #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ |
77 | #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ |
78 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ |
79 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ |
80 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ |
81 | #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ |
82 | #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) |
83 | /* Values for the status are the same as for the trigger */ |
84 | |
85 | #define B43_PHY_HT_RF_CTL_CMD 0x810 |
86 | #define B43_PHY_HT_RF_CTL_CMD_FORCE 0x0001 |
87 | #define B43_PHY_HT_RF_CTL_CMD_CHIP0_PU 0x0002 |
88 | |
89 | #define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c) |
90 | #define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c) |
91 | #define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c) |
92 | |
93 | #define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110) |
94 | #define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111) |
95 | #define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114) |
96 | #define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115) |
97 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) |
98 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) |
99 | |
100 | #define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164) |
101 | #define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F |
102 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI2 B43_PHY_EXTG(0x165) /* TX power control idle TSSI */ |
103 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3 0x003F |
104 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT 0 |
105 | #define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */ |
106 | #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF |
107 | #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0 |
108 | #define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169) |
109 | |
110 | #define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) |
111 | #define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ |
112 | #define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */ |
113 | #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) |
114 | |
115 | |
116 | /* Values for PHY registers used on channel switching */ |
117 | struct b43_phy_ht_channeltab_e_phy { |
118 | u16 bw1; |
119 | u16 bw2; |
120 | u16 bw3; |
121 | u16 bw4; |
122 | u16 bw5; |
123 | u16 bw6; |
124 | }; |
125 | |
126 | |
127 | struct b43_phy_ht { |
128 | u16 rf_ctl_int_save[3]; |
129 | |
130 | bool tx_pwr_ctl; |
131 | u8 tx_pwr_idx[3]; |
132 | |
133 | s32 bb_mult_save[3]; |
134 | |
135 | u8 idle_tssi[3]; |
136 | }; |
137 | |
138 | |
139 | struct b43_phy_operations; |
140 | extern const struct b43_phy_operations b43_phyops_ht; |
141 | |
142 | #endif /* B43_PHY_HT_H_ */ |
143 | |