| 1 | /****************************************************************************** |
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| 2 | * |
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| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
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| 4 | * redistributing this file, you may do so under either license. |
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| 5 | * |
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| 6 | * GPL LICENSE SUMMARY |
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| 7 | * |
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| 8 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
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| 9 | * |
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| 10 | * This program is free software; you can redistribute it and/or modify |
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| 11 | * it under the terms of version 2 of the GNU General Public License as |
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| 12 | * published by the Free Software Foundation. |
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| 13 | * |
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| 14 | * This program is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with this program; if not, write to the Free Software |
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| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
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| 22 | * USA |
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| 23 | * |
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| 24 | * The full GNU General Public License is included in this distribution |
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| 25 | * in the file called LICENSE.GPL. |
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| 26 | * |
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| 27 | * Contact Information: |
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| 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
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| 29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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| 30 | * |
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| 31 | * BSD LICENSE |
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| 32 | * |
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| 33 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
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| 34 | * All rights reserved. |
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| 35 | * |
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| 36 | * Redistribution and use in source and binary forms, with or without |
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| 37 | * modification, are permitted provided that the following conditions |
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| 38 | * are met: |
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| 39 | * |
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| 40 | * * Redistributions of source code must retain the above copyright |
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| 41 | * notice, this list of conditions and the following disclaimer. |
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| 42 | * * Redistributions in binary form must reproduce the above copyright |
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| 43 | * notice, this list of conditions and the following disclaimer in |
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| 44 | * the documentation and/or other materials provided with the |
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| 45 | * distribution. |
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| 46 | * * Neither the name Intel Corporation nor the names of its |
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| 47 | * contributors may be used to endorse or promote products derived |
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| 48 | * from this software without specific prior written permission. |
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| 49 | * |
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| 50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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| 53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| 54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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| 56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 61 | *****************************************************************************/ |
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| 62 | |
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| 63 | #ifndef __il_prph_h__ |
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| 64 | #define __il_prph_h__ |
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| 65 | |
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| 66 | /* |
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| 67 | * Registers in this file are internal, not PCI bus memory mapped. |
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| 68 | * Driver accesses these via HBUS_TARG_PRPH_* registers. |
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| 69 | */ |
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| 70 | #define PRPH_BASE (0x00000) |
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| 71 | #define PRPH_END (0xFFFFF) |
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| 72 | |
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| 73 | /* APMG (power management) constants */ |
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| 74 | #define APMG_BASE (PRPH_BASE + 0x3000) |
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| 75 | #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) |
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| 76 | #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) |
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| 77 | #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) |
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| 78 | #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) |
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| 79 | #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) |
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| 80 | #define APMG_RFKILL_REG (APMG_BASE + 0x0014) |
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| 81 | #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) |
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| 82 | #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) |
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| 83 | #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) |
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| 84 | #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) |
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| 85 | |
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| 86 | #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) |
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| 87 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
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| 88 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) |
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| 89 | |
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| 90 | #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
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| 91 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) |
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| 92 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) |
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| 93 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) |
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| 94 | #define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */ |
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| 95 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) |
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| 96 | #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ |
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| 97 | #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) |
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| 98 | |
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| 99 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
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| 100 | |
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| 101 | /** |
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| 102 | * BSM (Bootstrap State Machine) |
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| 103 | * |
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| 104 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program |
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| 105 | * in special SRAM that does not power down when the embedded control |
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| 106 | * processor is sleeping (e.g. for periodic power-saving shutdowns of radio). |
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| 107 | * |
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| 108 | * When powering back up after sleeps (or during initial uCode load), the BSM |
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| 109 | * internally loads the short bootstrap program from the special SRAM into the |
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| 110 | * embedded processor's instruction SRAM, and starts the processor so it runs |
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| 111 | * the bootstrap program. |
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| 112 | * |
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| 113 | * This bootstrap program loads (via PCI busmaster DMA) instructions and data |
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| 114 | * images for a uCode program from host DRAM locations. The host driver |
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| 115 | * indicates DRAM locations and sizes for instruction and data images via the |
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| 116 | * four BSM_DRAM_* registers. Once the bootstrap program loads the new program, |
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| 117 | * the new program starts automatically. |
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| 118 | * |
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| 119 | * The uCode used for open-source drivers includes two programs: |
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| 120 | * |
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| 121 | * 1) Initialization -- performs hardware calibration and sets up some |
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| 122 | * internal data, then notifies host via "initialize alive" notification |
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| 123 | * (struct il_init_alive_resp) that it has completed all of its work. |
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| 124 | * After signal from host, it then loads and starts the runtime program. |
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| 125 | * The initialization program must be used when initially setting up the |
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| 126 | * NIC after loading the driver. |
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| 127 | * |
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| 128 | * 2) Runtime/Protocol -- performs all normal runtime operations. This |
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| 129 | * notifies host via "alive" notification (struct il_alive_resp) that it |
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| 130 | * is ready to be used. |
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| 131 | * |
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| 132 | * When initializing the NIC, the host driver does the following procedure: |
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| 133 | * |
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| 134 | * 1) Load bootstrap program (instructions only, no data image for bootstrap) |
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| 135 | * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND |
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| 136 | * |
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| 137 | * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction |
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| 138 | * images in host DRAM. |
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| 139 | * |
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| 140 | * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked: |
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| 141 | * BSM_WR_MEM_SRC_REG = 0 |
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| 142 | * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND |
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| 143 | * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image |
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| 144 | * |
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| 145 | * 4) Load bootstrap into instruction SRAM: |
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| 146 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START |
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| 147 | * |
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| 148 | * 5) Wait for load completion: |
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| 149 | * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0 |
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| 150 | * |
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| 151 | * 6) Enable future boot loads whenever NIC's power management triggers it: |
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| 152 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN |
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| 153 | * |
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| 154 | * 7) Start the NIC by removing all reset bits: |
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| 155 | * CSR_RESET = 0 |
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| 156 | * |
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| 157 | * The bootstrap uCode (already in instruction SRAM) loads initialization |
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| 158 | * uCode. Initialization uCode performs data initialization, sends |
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| 159 | * "initialize alive" notification to host, and waits for a signal from |
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| 160 | * host to load runtime code. |
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| 161 | * |
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| 162 | * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction |
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| 163 | * images in host DRAM. The last register loaded must be the instruction |
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| 164 | * byte count register ("1" in MSbit tells initialization uCode to load |
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| 165 | * the runtime uCode): |
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| 166 | * BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD |
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| 167 | * |
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| 168 | * 5) Wait for "alive" notification, then issue normal runtime commands. |
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| 169 | * |
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| 170 | * Data caching during power-downs: |
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| 171 | * |
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| 172 | * Just before the embedded controller powers down (e.g for automatic |
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| 173 | * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA) |
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| 174 | * a current snapshot of the embedded processor's data SRAM into host DRAM. |
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| 175 | * This caches the data while the embedded processor's memory is powered down. |
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| 176 | * Location and size are controlled by BSM_DRAM_DATA_* registers. |
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| 177 | * |
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| 178 | * NOTE: Instruction SRAM does not need to be saved, since that doesn't |
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| 179 | * change during operation; the original image (from uCode distribution |
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| 180 | * file) can be used for reload. |
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| 181 | * |
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| 182 | * When powering back up, the BSM loads the bootstrap program. Bootstrap looks |
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| 183 | * at the BSM_DRAM_* registers, which now point to the runtime instruction |
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| 184 | * image and the cached (modified) runtime data (*not* the initialization |
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| 185 | * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the |
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| 186 | * uCode from where it left off before the power-down. |
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| 187 | * |
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| 188 | * NOTE: Initialization uCode does *not* run as part of the save/restore |
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| 189 | * procedure. |
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| 190 | * |
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| 191 | * This save/restore method is mostly for autonomous power management during |
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| 192 | * normal operation (result of C_POWER_TBL). Platform suspend/resume and |
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| 193 | * RFKILL should use complete restarts (with total re-initialization) of uCode, |
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| 194 | * allowing total shutdown (including BSM memory). |
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| 195 | * |
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| 196 | * Note that, during normal operation, the host DRAM that held the initial |
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| 197 | * startup data for the runtime code is now being used as a backup data cache |
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| 198 | * for modified data! If you need to completely re-initialize the NIC, make |
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| 199 | * sure that you use the runtime data image from the uCode distribution file, |
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| 200 | * not the modified/saved runtime data. You may want to store a separate |
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| 201 | * "clean" runtime data image in DRAM to avoid disk reads of distribution file. |
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| 202 | */ |
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| 203 | |
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| 204 | /* BSM bit fields */ |
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| 205 | #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */ |
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| 206 | #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup */ |
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| 207 | #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */ |
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| 208 | |
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| 209 | /* BSM addresses */ |
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| 210 | #define BSM_BASE (PRPH_BASE + 0x3400) |
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| 211 | #define BSM_END (PRPH_BASE + 0x3800) |
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| 212 | |
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| 213 | #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ |
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| 214 | #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ |
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| 215 | #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ |
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| 216 | #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ |
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| 217 | #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ |
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| 218 | |
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| 219 | /* |
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| 220 | * Pointers and size regs for bootstrap load and data SRAM save/restore. |
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| 221 | * NOTE: 3945 pointers use bits 31:0 of DRAM address. |
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| 222 | * 4965 pointers use bits 35:4 of DRAM address. |
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| 223 | */ |
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| 224 | #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) |
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| 225 | #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) |
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| 226 | #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) |
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| 227 | #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) |
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| 228 | |
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| 229 | /* |
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| 230 | * BSM special memory, stays powered on during power-save sleeps. |
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| 231 | * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1) |
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| 232 | */ |
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| 233 | #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) |
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| 234 | #define BSM_SRAM_SIZE (1024) /* bytes */ |
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| 235 | |
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| 236 | /* 3945 Tx scheduler registers */ |
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| 237 | #define ALM_SCD_BASE (PRPH_BASE + 0x2E00) |
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| 238 | #define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000) |
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| 239 | #define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004) |
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| 240 | #define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010) |
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| 241 | #define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014) |
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| 242 | #define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020) |
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| 243 | #define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) |
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| 244 | #define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) |
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| 245 | |
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| 246 | /** |
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| 247 | * Tx Scheduler |
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| 248 | * |
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| 249 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
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| 250 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
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| 251 | * host DRAM. It steers each frame's Tx command (which contains the frame |
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| 252 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the |
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| 253 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, |
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| 254 | * but one DMA channel may take input from several queues. |
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| 255 | * |
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| 256 | * Tx DMA FIFOs have dedicated purposes. For 4965, they are used as follows |
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| 257 | * (cf. default_queue_to_tx_fifo in 4965.c): |
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| 258 | * |
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| 259 | * 0 -- EDCA BK (background) frames, lowest priority |
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| 260 | * 1 -- EDCA BE (best effort) frames, normal priority |
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| 261 | * 2 -- EDCA VI (video) frames, higher priority |
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| 262 | * 3 -- EDCA VO (voice) and management frames, highest priority |
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| 263 | * 4 -- Commands (e.g. RXON, etc.) |
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| 264 | * 5 -- unused (HCCA) |
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| 265 | * 6 -- unused (HCCA) |
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| 266 | * 7 -- not used by driver (device-internal only) |
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| 267 | * |
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| 268 | * |
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| 269 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. |
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| 270 | * In addition, driver can map the remaining queues to Tx DMA/FIFO |
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| 271 | * channels 0-3 to support 11n aggregation via EDCA DMA channels. |
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| 272 | * |
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| 273 | * The driver sets up each queue to work in one of two modes: |
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| 274 | * |
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| 275 | * 1) Scheduler-Ack, in which the scheduler automatically supports a |
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| 276 | * block-ack (BA) win of up to 64 TFDs. In this mode, each queue |
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| 277 | * contains TFDs for a unique combination of Recipient Address (RA) |
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| 278 | * and Traffic Identifier (TID), that is, traffic of a given |
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| 279 | * Quality-Of-Service (QOS) priority, destined for a single station. |
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| 280 | * |
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| 281 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of |
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| 282 | * each frame within the BA win, including whether it's been transmitted, |
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| 283 | * and whether it's been acknowledged by the receiving station. The device |
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| 284 | * automatically processes block-acks received from the receiving STA, |
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| 285 | * and reschedules un-acked frames to be retransmitted (successful |
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| 286 | * Tx completion may end up being out-of-order). |
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| 287 | * |
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| 288 | * The driver must maintain the queue's Byte Count table in host DRAM |
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| 289 | * (struct il4965_sched_queue_byte_cnt_tbl) for this mode. |
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| 290 | * This mode does not support fragmentation. |
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| 291 | * |
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| 292 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. |
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| 293 | * The device may automatically retry Tx, but will retry only one frame |
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| 294 | * at a time, until receiving ACK from receiving station, or reaching |
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| 295 | * retry limit and giving up. |
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| 296 | * |
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| 297 | * The command queue (#4/#9) must use this mode! |
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| 298 | * This mode does not require use of the Byte Count table in host DRAM. |
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| 299 | * |
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| 300 | * Driver controls scheduler operation via 3 means: |
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| 301 | * 1) Scheduler registers |
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| 302 | * 2) Shared scheduler data base in internal 4956 SRAM |
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| 303 | * 3) Shared data in host DRAM |
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| 304 | * |
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| 305 | * Initialization: |
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| 306 | * |
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| 307 | * When loading, driver should allocate memory for: |
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| 308 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. |
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| 309 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory |
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| 310 | * (1024 bytes for each queue). |
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| 311 | * |
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| 312 | * After receiving "Alive" response from uCode, driver must initialize |
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| 313 | * the scheduler (especially for queue #4/#9, the command queue, otherwise |
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| 314 | * the driver can't issue commands!): |
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| 315 | */ |
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| 316 | |
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| 317 | /** |
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| 318 | * Max Tx win size is the max number of contiguous TFDs that the scheduler |
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| 319 | * can keep track of at one time when creating block-ack chains of frames. |
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| 320 | * Note that "64" matches the number of ack bits in a block-ack packet. |
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| 321 | * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize |
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| 322 | * IL49_SCD_CONTEXT_QUEUE_OFFSET(x) values. |
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| 323 | */ |
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| 324 | #define SCD_WIN_SIZE 64 |
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| 325 | #define SCD_FRAME_LIMIT 64 |
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| 326 | |
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| 327 | /* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */ |
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| 328 | #define IL49_SCD_START_OFFSET 0xa02c00 |
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| 329 | |
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| 330 | /* |
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| 331 | * 4965 tells driver SRAM address for internal scheduler structs via this reg. |
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| 332 | * Value is valid only after "Alive" response from uCode. |
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| 333 | */ |
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| 334 | #define IL49_SCD_SRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x0) |
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| 335 | |
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| 336 | /* |
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| 337 | * Driver may need to update queue-empty bits after changing queue's |
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| 338 | * write and read pointers (idxes) during (re-)initialization (i.e. when |
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| 339 | * scheduler is not tracking what's happening). |
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| 340 | * Bit fields: |
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| 341 | * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit |
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| 342 | * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty |
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| 343 | * NOTE: This register is not used by Linux driver. |
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| 344 | */ |
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| 345 | #define IL49_SCD_EMPTY_BITS (IL49_SCD_START_OFFSET + 0x4) |
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| 346 | |
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| 347 | /* |
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| 348 | * Physical base address of array of byte count (BC) circular buffers (CBs). |
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| 349 | * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. |
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| 350 | * This register points to BC CB for queue 0, must be on 1024-byte boundary. |
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| 351 | * Others are spaced by 1024 bytes. |
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| 352 | * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. |
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| 353 | * (Index into a queue's BC CB) = (idx into queue's TFD CB) = (SSN & 0xff). |
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| 354 | * Bit fields: |
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| 355 | * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. |
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| 356 | */ |
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| 357 | #define IL49_SCD_DRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x10) |
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| 358 | |
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| 359 | /* |
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| 360 | * Enables any/all Tx DMA/FIFO channels. |
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| 361 | * Scheduler generates requests for only the active channels. |
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| 362 | * Set this to 0xff to enable all 8 channels (normal usage). |
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| 363 | * Bit fields: |
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| 364 | * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 |
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| 365 | */ |
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| 366 | #define IL49_SCD_TXFACT (IL49_SCD_START_OFFSET + 0x1c) |
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| 367 | /* |
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| 368 | * Queue (x) Write Pointers (idxes, really!), one for each Tx queue. |
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| 369 | * Initialized and updated by driver as new TFDs are added to queue. |
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| 370 | * NOTE: If using Block Ack, idx must correspond to frame's |
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| 371 | * Start Sequence Number; idx = (SSN & 0xff) |
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| 372 | * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? |
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| 373 | */ |
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| 374 | #define IL49_SCD_QUEUE_WRPTR(x) (IL49_SCD_START_OFFSET + 0x24 + (x) * 4) |
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| 375 | |
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| 376 | /* |
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| 377 | * Queue (x) Read Pointers (idxes, really!), one for each Tx queue. |
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| 378 | * For FIFO mode, idx indicates next frame to transmit. |
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| 379 | * For Scheduler-ACK mode, idx indicates first frame in Tx win. |
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| 380 | * Initialized by driver, updated by scheduler. |
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| 381 | */ |
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| 382 | #define IL49_SCD_QUEUE_RDPTR(x) (IL49_SCD_START_OFFSET + 0x64 + (x) * 4) |
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| 383 | |
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| 384 | /* |
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| 385 | * Select which queues work in chain mode (1) vs. not (0). |
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| 386 | * Use chain mode to build chains of aggregated frames. |
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| 387 | * Bit fields: |
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| 388 | * 31-16: Reserved |
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| 389 | * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time |
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| 390 | * NOTE: If driver sets up queue for chain mode, it should be also set up |
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| 391 | * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). |
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| 392 | */ |
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| 393 | #define IL49_SCD_QUEUECHAIN_SEL (IL49_SCD_START_OFFSET + 0xd0) |
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| 394 | |
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| 395 | /* |
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| 396 | * Select which queues interrupt driver when scheduler increments |
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| 397 | * a queue's read pointer (idx). |
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| 398 | * Bit fields: |
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| 399 | * 31-16: Reserved |
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| 400 | * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled |
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| 401 | * NOTE: This functionality is apparently a no-op; driver relies on interrupts |
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| 402 | * from Rx queue to read Tx command responses and update Tx queues. |
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| 403 | */ |
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| 404 | #define IL49_SCD_INTERRUPT_MASK (IL49_SCD_START_OFFSET + 0xe4) |
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| 405 | |
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| 406 | /* |
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| 407 | * Queue search status registers. One for each queue. |
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| 408 | * Sets up queue mode and assigns queue to Tx DMA channel. |
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| 409 | * Bit fields: |
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| 410 | * 19-10: Write mask/enable bits for bits 0-9 |
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| 411 | * 9: Driver should init to "0" |
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| 412 | * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). |
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| 413 | * Driver should init to "1" for aggregation mode, or "0" otherwise. |
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| 414 | * 7-6: Driver should init to "0" |
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| 415 | * 5: Window Size Left; indicates whether scheduler can request |
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| 416 | * another TFD, based on win size, etc. Driver should init |
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| 417 | * this bit to "1" for aggregation mode, or "0" for non-agg. |
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| 418 | * 4-1: Tx FIFO to use (range 0-7). |
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| 419 | * 0: Queue is active (1), not active (0). |
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| 420 | * Other bits should be written as "0" |
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| 421 | * |
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| 422 | * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled |
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| 423 | * via SCD_QUEUECHAIN_SEL. |
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| 424 | */ |
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| 425 | #define IL49_SCD_QUEUE_STATUS_BITS(x)\ |
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| 426 | (IL49_SCD_START_OFFSET + 0x104 + (x) * 4) |
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| 427 | |
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| 428 | /* Bit field positions */ |
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| 429 | #define IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0) |
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| 430 | #define IL49_SCD_QUEUE_STTS_REG_POS_TXF (1) |
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| 431 | #define IL49_SCD_QUEUE_STTS_REG_POS_WSL (5) |
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| 432 | #define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) |
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| 433 | |
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| 434 | /* Write masks */ |
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| 435 | #define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) |
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| 436 | #define IL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00) |
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| 437 | |
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| 438 | /** |
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| 439 | * 4965 internal SRAM structures for scheduler, shared with driver ... |
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| 440 | * |
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| 441 | * Driver should clear and initialize the following areas after receiving |
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| 442 | * "Alive" response from 4965 uCode, i.e. after initial |
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| 443 | * uCode load, or after a uCode load done for error recovery: |
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| 444 | * |
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| 445 | * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) |
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| 446 | * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) |
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| 447 | * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) |
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| 448 | * |
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| 449 | * Driver accesses SRAM via HBUS_TARG_MEM_* registers. |
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| 450 | * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. |
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| 451 | * All OFFSET values must be added to this base address. |
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| 452 | */ |
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| 453 | |
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| 454 | /* |
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| 455 | * Queue context. One 8-byte entry for each of 16 queues. |
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| 456 | * |
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| 457 | * Driver should clear this entire area (size 0x80) to 0 after receiving |
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| 458 | * "Alive" notification from uCode. Additionally, driver should init |
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| 459 | * each queue's entry as follows: |
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| 460 | * |
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| 461 | * LS Dword bit fields: |
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| 462 | * 0-06: Max Tx win size for Scheduler-ACK. Driver should init to 64. |
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| 463 | * |
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| 464 | * MS Dword bit fields: |
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| 465 | * 16-22: Frame limit. Driver should init to 10 (0xa). |
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| 466 | * |
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| 467 | * Driver should init all other bits to 0. |
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| 468 | * |
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| 469 | * Init must be done after driver receives "Alive" response from 4965 uCode, |
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| 470 | * and when setting up queue for aggregation. |
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| 471 | */ |
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| 472 | #define IL49_SCD_CONTEXT_DATA_OFFSET 0x380 |
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| 473 | #define IL49_SCD_CONTEXT_QUEUE_OFFSET(x) \ |
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| 474 | (IL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) |
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| 475 | |
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| 476 | #define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) |
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| 477 | #define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) |
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| 478 | #define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
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| 479 | #define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) |
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| 480 | |
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| 481 | /* |
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| 482 | * Tx Status Bitmap |
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| 483 | * |
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| 484 | * Driver should clear this entire area (size 0x100) to 0 after receiving |
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| 485 | * "Alive" notification from uCode. Area is used only by device itself; |
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| 486 | * no other support (besides clearing) is required from driver. |
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| 487 | */ |
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| 488 | #define IL49_SCD_TX_STTS_BITMAP_OFFSET 0x400 |
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| 489 | |
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| 490 | /* |
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| 491 | * RAxTID to queue translation mapping. |
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| 492 | * |
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| 493 | * When queue is in Scheduler-ACK mode, frames placed in a that queue must be |
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| 494 | * for only one combination of receiver address (RA) and traffic ID (TID), i.e. |
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| 495 | * one QOS priority level destined for one station (for this wireless link, |
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| 496 | * not final destination). The SCD_TRANSLATE_TBL area provides 16 16-bit |
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| 497 | * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK |
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| 498 | * mode, the device ignores the mapping value. |
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| 499 | * |
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| 500 | * Bit fields, for each 16-bit map: |
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| 501 | * 15-9: Reserved, set to 0 |
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| 502 | * 8-4: Index into device's station table for recipient station |
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| 503 | * 3-0: Traffic ID (tid), range 0-15 |
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| 504 | * |
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| 505 | * Driver should clear this entire area (size 32 bytes) to 0 after receiving |
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| 506 | * "Alive" notification from uCode. To update a 16-bit map value, driver |
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| 507 | * must read a dword-aligned value from device SRAM, replace the 16-bit map |
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| 508 | * value of interest, and write the dword value back into device SRAM. |
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| 509 | */ |
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| 510 | #define IL49_SCD_TRANSLATE_TBL_OFFSET 0x500 |
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| 511 | |
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| 512 | /* Find translation table dword to read/write for given queue */ |
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| 513 | #define IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ |
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| 514 | ((IL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) |
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| 515 | |
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| 516 | #define IL_SCD_TXFIFO_POS_TID (0) |
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| 517 | #define IL_SCD_TXFIFO_POS_RA (4) |
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| 518 | #define IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) |
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| 519 | |
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| 520 | /*********************** END TX SCHEDULER *************************************/ |
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| 521 | |
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| 522 | #endif /* __il_prph_h__ */ |
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| 523 | |
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