1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* |
3 | * Copyright (C) 2018, 2020-2023 Intel Corporation |
4 | */ |
5 | #ifndef __iwl_context_info_file_gen3_h__ |
6 | #define __iwl_context_info_file_gen3_h__ |
7 | |
8 | #include "iwl-context-info.h" |
9 | |
10 | #define CSR_CTXT_INFO_BOOT_CTRL 0x0 |
11 | #define CSR_CTXT_INFO_ADDR 0x118 |
12 | #define CSR_IML_DATA_ADDR 0x120 |
13 | #define CSR_IML_SIZE_ADDR 0x128 |
14 | #define CSR_IML_RESP_ADDR 0x12c |
15 | |
16 | #define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2 |
17 | |
18 | /* Set bit for enabling automatic function boot */ |
19 | #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) |
20 | /* Set bit for initiating function boot */ |
21 | #define CSR_AUTO_FUNC_INIT BIT(7) |
22 | |
23 | /** |
24 | * enum iwl_prph_scratch_mtr_format - tfd size configuration |
25 | * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd |
26 | * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd |
27 | * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd |
28 | * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd |
29 | */ |
30 | enum iwl_prph_scratch_mtr_format { |
31 | IWL_PRPH_MTR_FORMAT_16B = 0x0, |
32 | IWL_PRPH_MTR_FORMAT_32B = 0x40000, |
33 | IWL_PRPH_MTR_FORMAT_64B = 0x80000, |
34 | IWL_PRPH_MTR_FORMAT_256B = 0xC0000, |
35 | }; |
36 | |
37 | /** |
38 | * enum iwl_prph_scratch_flags - PRPH scratch control flags |
39 | * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug |
40 | * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf |
41 | * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated |
42 | * in hwm config. |
43 | * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM |
44 | * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for |
45 | * multicomm. |
46 | * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW |
47 | * @IWL_PRPH_SCRATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) |
48 | * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for |
49 | * completion descriptor, 1 for responses (legacy) |
50 | * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. |
51 | * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, |
52 | * 3: 256 bit. |
53 | * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored |
54 | * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K |
55 | * appropriately; use the below values for this. |
56 | * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size |
57 | * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size |
58 | * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size |
59 | */ |
60 | enum iwl_prph_scratch_flags { |
61 | IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), |
62 | IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), |
63 | IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), |
64 | IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), |
65 | IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), |
66 | IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), |
67 | IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), |
68 | IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), |
69 | IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), |
70 | IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, |
71 | IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, |
72 | IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, |
73 | IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, |
74 | }; |
75 | |
76 | /* |
77 | * struct iwl_prph_scratch_version - version structure |
78 | * @mac_id: SKU and revision id |
79 | * @version: prph scratch information version id |
80 | * @size: the size of the context information in DWs |
81 | * @reserved: reserved |
82 | */ |
83 | struct iwl_prph_scratch_version { |
84 | __le16 mac_id; |
85 | __le16 version; |
86 | __le16 size; |
87 | __le16 reserved; |
88 | } __packed; /* PERIPH_SCRATCH_VERSION_S */ |
89 | |
90 | /* |
91 | * struct iwl_prph_scratch_control - control structure |
92 | * @control_flags: context information flags see &enum iwl_prph_scratch_flags |
93 | * @reserved: reserved |
94 | */ |
95 | struct iwl_prph_scratch_control { |
96 | __le32 control_flags; |
97 | __le32 reserved; |
98 | } __packed; /* PERIPH_SCRATCH_CONTROL_S */ |
99 | |
100 | /* |
101 | * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch |
102 | * @pnvm_base_addr: PNVM start address |
103 | * @pnvm_size: the size of the PNVM image in bytes |
104 | * @reserved: reserved |
105 | */ |
106 | struct iwl_prph_scratch_pnvm_cfg { |
107 | __le64 pnvm_base_addr; |
108 | __le32 pnvm_size; |
109 | __le32 reserved; |
110 | } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ |
111 | |
112 | /** |
113 | * struct iwl_prph_scrath_mem_desc_addr_array |
114 | * @mem_descs: array of dram addresses. |
115 | * Each address is the beggining of a pnvm payload. |
116 | */ |
117 | struct iwl_prph_scrath_mem_desc_addr_array { |
118 | __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX]; |
119 | } __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */ |
120 | /* |
121 | * struct iwl_prph_scratch_hwm_cfg - hwm config |
122 | * @hwm_base_addr: hwm start address |
123 | * @hwm_size: hwm size in DWs |
124 | * @debug_token_config: debug preset |
125 | */ |
126 | struct iwl_prph_scratch_hwm_cfg { |
127 | __le64 hwm_base_addr; |
128 | __le32 hwm_size; |
129 | __le32 debug_token_config; |
130 | } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ |
131 | |
132 | /* |
133 | * struct iwl_prph_scratch_rbd_cfg - RBDs configuration |
134 | * @free_rbd_addr: default queue free RB CB base address |
135 | * @reserved: reserved |
136 | */ |
137 | struct iwl_prph_scratch_rbd_cfg { |
138 | __le64 free_rbd_addr; |
139 | __le32 reserved; |
140 | } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ |
141 | |
142 | /* |
143 | * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table |
144 | * @base_addr: reduce power table address |
145 | * @size: the size of the entire power table image |
146 | */ |
147 | struct iwl_prph_scratch_uefi_cfg { |
148 | __le64 base_addr; |
149 | __le32 size; |
150 | __le32 reserved; |
151 | } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ |
152 | |
153 | /* |
154 | * struct iwl_prph_scratch_step_cfg - prph scratch step configuration |
155 | * @mbx_addr_0: [0:7] revision, |
156 | * [8:15] cnvi_to_cnvr length, |
157 | * [16:23] cnvr_to_cnvi channel length, |
158 | * [24:31] radio1 reserved |
159 | * @mbx_addr_1: [0:7] radio2 reserved |
160 | */ |
161 | |
162 | struct iwl_prph_scratch_step_cfg { |
163 | __le32 mbx_addr_0; |
164 | __le32 mbx_addr_1; |
165 | } __packed; |
166 | |
167 | /* |
168 | * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config |
169 | * @version: version information of context info and HW |
170 | * @control: control flags of FH configurations |
171 | * @pnvm_cfg: ror configuration |
172 | * @hwm_cfg: hwm configuration |
173 | * @rbd_cfg: default RX queue configuration |
174 | * @step_cfg: step configuration |
175 | */ |
176 | struct iwl_prph_scratch_ctrl_cfg { |
177 | struct iwl_prph_scratch_version version; |
178 | struct iwl_prph_scratch_control control; |
179 | struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; |
180 | struct iwl_prph_scratch_hwm_cfg hwm_cfg; |
181 | struct iwl_prph_scratch_rbd_cfg rbd_cfg; |
182 | struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; |
183 | struct iwl_prph_scratch_step_cfg step_cfg; |
184 | } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ |
185 | |
186 | /* |
187 | * struct iwl_prph_scratch - peripheral scratch mapping |
188 | * @ctrl_cfg: control and configuration of prph scratch |
189 | * @dram: firmware images addresses in DRAM |
190 | * @fseq_override: FSEQ override parameters |
191 | * @step_analog_params: STEP analog calibration values |
192 | * @reserved: reserved |
193 | */ |
194 | struct iwl_prph_scratch { |
195 | struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; |
196 | __le32 fseq_override; |
197 | __le32 step_analog_params; |
198 | __le32 reserved[8]; |
199 | struct iwl_context_info_dram dram; |
200 | } __packed; /* PERIPH_SCRATCH_S */ |
201 | |
202 | /* |
203 | * struct iwl_prph_info - peripheral information |
204 | * @boot_stage_mirror: reflects the value in the Boot Stage CSR register |
205 | * @ipc_status_mirror: reflects the value in the IPC Status CSR register |
206 | * @sleep_notif: indicates the peripheral sleep status |
207 | * @reserved: reserved |
208 | */ |
209 | struct iwl_prph_info { |
210 | __le32 boot_stage_mirror; |
211 | __le32 ipc_status_mirror; |
212 | __le32 sleep_notif; |
213 | __le32 reserved; |
214 | } __packed; /* PERIPH_INFO_S */ |
215 | |
216 | /* |
217 | * struct iwl_context_info_gen3 - device INIT configuration |
218 | * @version: version of the context information |
219 | * @size: size of context information in DWs |
220 | * @config: context in which the peripheral would execute - a subset of |
221 | * capability csr register published by the peripheral |
222 | * @prph_info_base_addr: the peripheral information structure start address |
223 | * @cr_head_idx_arr_base_addr: the completion ring head index array |
224 | * start address |
225 | * @tr_tail_idx_arr_base_addr: the transfer ring tail index array |
226 | * start address |
227 | * @cr_tail_idx_arr_base_addr: the completion ring tail index array |
228 | * start address |
229 | * @tr_head_idx_arr_base_addr: the transfer ring head index array |
230 | * start address |
231 | * @cr_idx_arr_size: number of entries in the completion ring index array |
232 | * @tr_idx_arr_size: number of entries in the transfer ring index array |
233 | * @mtr_base_addr: the message transfer ring start address |
234 | * @mcr_base_addr: the message completion ring start address |
235 | * @mtr_size: number of entries which the message transfer ring can hold |
236 | * @mcr_size: number of entries which the message completion ring can hold |
237 | * @mtr_doorbell_vec: the doorbell vector associated with the message |
238 | * transfer ring |
239 | * @mcr_doorbell_vec: the doorbell vector associated with the message |
240 | * completion ring |
241 | * @mtr_msi_vec: the MSI which shall be generated by the peripheral after |
242 | * completing a transfer descriptor in the message transfer ring |
243 | * @mcr_msi_vec: the MSI which shall be generated by the peripheral after |
244 | * completing a completion descriptor in the message completion ring |
245 | * @mtr_opt_header_size: the size of the optional header in the transfer |
246 | * descriptor associated with the message transfer ring in DWs |
247 | * @mtr_opt_footer_size: the size of the optional footer in the transfer |
248 | * descriptor associated with the message transfer ring in DWs |
249 | * @mcr_opt_header_size: the size of the optional header in the completion |
250 | * descriptor associated with the message completion ring in DWs |
251 | * @mcr_opt_footer_size: the size of the optional footer in the completion |
252 | * descriptor associated with the message completion ring in DWs |
253 | * @msg_rings_ctrl_flags: message rings control flags |
254 | * @prph_info_msi_vec: the MSI which shall be generated by the peripheral |
255 | * after updating the Peripheral Information structure |
256 | * @prph_scratch_base_addr: the peripheral scratch structure start address |
257 | * @prph_scratch_size: the size of the peripheral scratch structure in DWs |
258 | * @reserved: reserved |
259 | */ |
260 | struct iwl_context_info_gen3 { |
261 | __le16 version; |
262 | __le16 size; |
263 | __le32 config; |
264 | __le64 prph_info_base_addr; |
265 | __le64 cr_head_idx_arr_base_addr; |
266 | __le64 tr_tail_idx_arr_base_addr; |
267 | __le64 cr_tail_idx_arr_base_addr; |
268 | __le64 tr_head_idx_arr_base_addr; |
269 | __le16 cr_idx_arr_size; |
270 | __le16 tr_idx_arr_size; |
271 | __le64 mtr_base_addr; |
272 | __le64 mcr_base_addr; |
273 | __le16 mtr_size; |
274 | __le16 mcr_size; |
275 | __le16 mtr_doorbell_vec; |
276 | __le16 mcr_doorbell_vec; |
277 | __le16 mtr_msi_vec; |
278 | __le16 mcr_msi_vec; |
279 | u8 ; |
280 | u8 ; |
281 | u8 ; |
282 | u8 ; |
283 | __le16 msg_rings_ctrl_flags; |
284 | __le16 prph_info_msi_vec; |
285 | __le64 prph_scratch_base_addr; |
286 | __le32 prph_scratch_size; |
287 | __le32 reserved; |
288 | } __packed; /* IPC_CONTEXT_INFO_S */ |
289 | |
290 | int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, |
291 | const struct fw_img *fw); |
292 | void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive); |
293 | |
294 | int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, |
295 | const struct iwl_pnvm_image *pnvm_payloads, |
296 | const struct iwl_ucode_capabilities *capa); |
297 | void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, |
298 | const struct iwl_ucode_capabilities *capa); |
299 | int |
300 | iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans, |
301 | const struct iwl_pnvm_image *payloads, |
302 | const struct iwl_ucode_capabilities *capa); |
303 | void |
304 | iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, |
305 | const struct iwl_ucode_capabilities *capa); |
306 | int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans, |
307 | u32 mbx_addr_0_step, u32 mbx_addr_1_step); |
308 | #endif /* __iwl_context_info_file_gen3_h__ */ |
309 | |