1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* |
3 | * Copyright (C) 2018-2021 Intel Corporation |
4 | */ |
5 | #ifndef __iwl_io_h__ |
6 | #define __iwl_io_h__ |
7 | |
8 | #include "iwl-devtrace.h" |
9 | #include "iwl-trans.h" |
10 | |
11 | void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val); |
12 | void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val); |
13 | void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val); |
14 | u32 iwl_read32(struct iwl_trans *trans, u32 ofs); |
15 | |
16 | static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask) |
17 | { |
18 | iwl_trans_set_bits_mask(trans, reg, mask, value: mask); |
19 | } |
20 | |
21 | static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask) |
22 | { |
23 | iwl_trans_set_bits_mask(trans, reg, mask, value: 0); |
24 | } |
25 | |
26 | int iwl_poll_bit(struct iwl_trans *trans, u32 addr, |
27 | u32 bits, u32 mask, int timeout); |
28 | int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask, |
29 | int timeout); |
30 | |
31 | u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg); |
32 | void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value); |
33 | void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value); |
34 | |
35 | |
36 | u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs); |
37 | u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs); |
38 | void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val); |
39 | void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val); |
40 | void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, |
41 | u32 val, u32 delay_ms); |
42 | static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val) |
43 | { |
44 | iwl_write_prph_delay(trans, ofs, val, delay_ms: 0); |
45 | } |
46 | |
47 | int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr, |
48 | u32 bits, u32 mask, int timeout); |
49 | void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); |
50 | void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs, |
51 | u32 bits, u32 mask); |
52 | void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); |
53 | void iwl_force_nmi(struct iwl_trans *trans); |
54 | |
55 | int iwl_finish_nic_init(struct iwl_trans *trans); |
56 | |
57 | /* Error handling */ |
58 | int iwl_dump_fh(struct iwl_trans *trans, char **buf); |
59 | |
60 | /* |
61 | * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from |
62 | * device family AX200. So peripheries used in families above and below AX200 |
63 | * should go through iwl_..._umac_..._prph. |
64 | */ |
65 | static inline u32 iwl_umac_prph(struct iwl_trans *trans, u32 ofs) |
66 | { |
67 | return ofs + trans->trans_cfg->umac_prph_offset; |
68 | } |
69 | |
70 | static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs) |
71 | { |
72 | return iwl_read_prph_no_grab(trans, ofs: ofs + |
73 | trans->trans_cfg->umac_prph_offset); |
74 | } |
75 | |
76 | static inline u32 iwl_read_umac_prph(struct iwl_trans *trans, u32 ofs) |
77 | { |
78 | return iwl_read_prph(trans, ofs: ofs + trans->trans_cfg->umac_prph_offset); |
79 | } |
80 | |
81 | static inline void iwl_write_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs, |
82 | u32 val) |
83 | { |
84 | iwl_write_prph_no_grab(trans, ofs: ofs + trans->trans_cfg->umac_prph_offset, |
85 | val); |
86 | } |
87 | |
88 | static inline void iwl_write_umac_prph(struct iwl_trans *trans, u32 ofs, |
89 | u32 val) |
90 | { |
91 | iwl_write_prph(trans, ofs: ofs + trans->trans_cfg->umac_prph_offset, val); |
92 | } |
93 | |
94 | static inline int iwl_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr, |
95 | u32 bits, u32 mask, int timeout) |
96 | { |
97 | return iwl_poll_prph_bit(trans, addr: addr + |
98 | trans->trans_cfg->umac_prph_offset, |
99 | bits, mask, timeout); |
100 | } |
101 | |
102 | #endif |
103 | |