1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * RTL8XXXU mac80211 USB driver - 8188e specific subdriver |
4 | * |
5 | * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@gmail.com> |
6 | * |
7 | * Portions, notably calibration code: |
8 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
9 | * |
10 | * This driver was written as a replacement for the vendor provided |
11 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in |
12 | * their programming interface, I have started adding support for |
13 | * additional 8xxx chips like the 8192cu, 8188cus, etc. |
14 | */ |
15 | |
16 | #include <linux/init.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/sched.h> |
19 | #include <linux/errno.h> |
20 | #include <linux/slab.h> |
21 | #include <linux/module.h> |
22 | #include <linux/spinlock.h> |
23 | #include <linux/list.h> |
24 | #include <linux/usb.h> |
25 | #include <linux/netdevice.h> |
26 | #include <linux/etherdevice.h> |
27 | #include <linux/ethtool.h> |
28 | #include <linux/wireless.h> |
29 | #include <linux/firmware.h> |
30 | #include <linux/moduleparam.h> |
31 | #include <net/mac80211.h> |
32 | #include "rtl8xxxu.h" |
33 | #include "rtl8xxxu_regs.h" |
34 | |
35 | static const struct rtl8xxxu_reg8val rtl8188e_mac_init_table[] = { |
36 | {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f}, |
37 | {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x01}, |
38 | {0x432, 0x02}, {0x433, 0x04}, {0x434, 0x05}, {0x435, 0x06}, |
39 | {0x436, 0x07}, {0x437, 0x08}, {0x438, 0x00}, {0x439, 0x00}, |
40 | {0x43a, 0x01}, {0x43b, 0x02}, {0x43c, 0x04}, {0x43d, 0x05}, |
41 | {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, |
42 | {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, |
43 | {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, |
44 | {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x480, 0x08}, |
45 | {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, |
46 | {0x4ce, 0x01}, {0x4d3, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, |
47 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, |
48 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, |
49 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, |
50 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, |
51 | {0x516, 0x0a}, {0x525, 0x4f}, {0x550, 0x10}, {0x551, 0x10}, |
52 | {0x559, 0x02}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, |
53 | {0x609, 0x2a}, {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, |
54 | {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, |
55 | {0x627, 0xff}, {0x63c, 0x08}, {0x63d, 0x08}, {0x63e, 0x0c}, |
56 | {0x63f, 0x0c}, {0x640, 0x40}, {0x652, 0x20}, {0x66e, 0x05}, |
57 | {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, |
58 | {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, |
59 | {0xffff, 0xff}, |
60 | }; |
61 | |
62 | static const struct rtl8xxxu_reg32val rtl8188eu_phy_init_table[] = { |
63 | {0x800, 0x80040000}, {0x804, 0x00000003}, |
64 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
65 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, |
66 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
67 | {0x820, 0x01000100}, {0x824, 0x00390204}, |
68 | {0x828, 0x00000000}, {0x82c, 0x00000000}, |
69 | {0x830, 0x00000000}, {0x834, 0x00000000}, |
70 | {0x838, 0x00000000}, {0x83c, 0x00000000}, |
71 | {0x840, 0x00010000}, {0x844, 0x00000000}, |
72 | {0x848, 0x00000000}, {0x84c, 0x00000000}, |
73 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
74 | {0x858, 0x569a11a9}, {0x85c, 0x01000014}, |
75 | {0x860, 0x66f60110}, {0x864, 0x061f0649}, |
76 | {0x868, 0x00000000}, {0x86c, 0x27272700}, |
77 | {0x870, 0x07000760}, {0x874, 0x25004000}, |
78 | {0x878, 0x00000808}, {0x87c, 0x00000000}, |
79 | {0x880, 0xb0000c1c}, {0x884, 0x00000001}, |
80 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, |
81 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
82 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
83 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
84 | {0x908, 0x00000000}, {0x90c, 0x81121111}, |
85 | {0x910, 0x00000002}, {0x914, 0x00000201}, |
86 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, |
87 | {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, |
88 | {0xa10, 0x9500bb7e}, {0xa14, 0x1114d028}, |
89 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
90 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
91 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
92 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
93 | {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, |
94 | {0xa80, 0x218075b1}, {0xb2c, 0x80000000}, |
95 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, |
96 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
97 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
98 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
99 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
100 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
101 | {0xc30, 0x69e9ac47}, {0xc34, 0x469652af}, |
102 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
103 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
104 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
105 | {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, |
106 | {0xc58, 0x00013169}, {0xc5c, 0x00250492}, |
107 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, |
108 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
109 | {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, |
110 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, |
111 | {0xc80, 0x390000e4}, {0xc84, 0x21f60000}, |
112 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, |
113 | {0xc90, 0x00091521}, {0xc94, 0x00000000}, |
114 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, |
115 | {0xca0, 0x00000000}, {0xca4, 0x000300a0}, |
116 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
117 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
118 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
119 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
120 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
121 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
122 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
123 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
124 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
125 | {0xd00, 0x00000740}, {0xd04, 0x00020401}, |
126 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
127 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, |
128 | {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, |
129 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
130 | {0xd38, 0x00000000}, {0xd3c, 0x00127353}, |
131 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
132 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
133 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
134 | {0xd58, 0x00000282}, {0xd5c, 0x30032064}, |
135 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
136 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
137 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
138 | {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, |
139 | {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, |
140 | {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, |
141 | {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, |
142 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
143 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
144 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
145 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
146 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
147 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
148 | {0xe5c, 0x28160d05}, {0xe60, 0x00000048}, |
149 | {0xe68, 0x001b25a4}, {0xe6c, 0x00c00014}, |
150 | {0xe70, 0x00c00014}, {0xe74, 0x01000014}, |
151 | {0xe78, 0x01000014}, {0xe7c, 0x01000014}, |
152 | {0xe80, 0x01000014}, {0xe84, 0x00c00014}, |
153 | {0xe88, 0x01000014}, {0xe8c, 0x00c00014}, |
154 | {0xed0, 0x00c00014}, {0xed4, 0x00c00014}, |
155 | {0xed8, 0x00c00014}, {0xedc, 0x00000014}, |
156 | {0xee0, 0x00000014}, {0xee8, 0x21555448}, |
157 | {0xeec, 0x01c00014}, {0xf14, 0x00000003}, |
158 | {0xf4c, 0x00000000}, {0xf00, 0x00000300}, |
159 | {0xffff, 0xffffffff}, |
160 | }; |
161 | |
162 | static const struct rtl8xxxu_reg32val rtl8188e_agc_table[] = { |
163 | {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, |
164 | {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, |
165 | {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, |
166 | {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, |
167 | {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, |
168 | {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, |
169 | {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, |
170 | {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, |
171 | {0xc78, 0xf0100001}, {0xc78, 0xef110001}, |
172 | {0xc78, 0xee120001}, {0xc78, 0xed130001}, |
173 | {0xc78, 0xec140001}, {0xc78, 0xeb150001}, |
174 | {0xc78, 0xea160001}, {0xc78, 0xe9170001}, |
175 | {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, |
176 | {0xc78, 0xe61a0001}, {0xc78, 0xe51b0001}, |
177 | {0xc78, 0xe41c0001}, {0xc78, 0xe31d0001}, |
178 | {0xc78, 0xe21e0001}, {0xc78, 0xe11f0001}, |
179 | {0xc78, 0x8a200001}, {0xc78, 0x89210001}, |
180 | {0xc78, 0x88220001}, {0xc78, 0x87230001}, |
181 | {0xc78, 0x86240001}, {0xc78, 0x85250001}, |
182 | {0xc78, 0x84260001}, {0xc78, 0x83270001}, |
183 | {0xc78, 0x82280001}, {0xc78, 0x6b290001}, |
184 | {0xc78, 0x6a2a0001}, {0xc78, 0x692b0001}, |
185 | {0xc78, 0x682c0001}, {0xc78, 0x672d0001}, |
186 | {0xc78, 0x662e0001}, {0xc78, 0x652f0001}, |
187 | {0xc78, 0x64300001}, {0xc78, 0x63310001}, |
188 | {0xc78, 0x62320001}, {0xc78, 0x61330001}, |
189 | {0xc78, 0x46340001}, {0xc78, 0x45350001}, |
190 | {0xc78, 0x44360001}, {0xc78, 0x43370001}, |
191 | {0xc78, 0x42380001}, {0xc78, 0x41390001}, |
192 | {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, |
193 | {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, |
194 | {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, |
195 | {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, |
196 | {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, |
197 | {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, |
198 | {0xc78, 0xfb460001}, {0xc78, 0xfb470001}, |
199 | {0xc78, 0xfb480001}, {0xc78, 0xfa490001}, |
200 | {0xc78, 0xf94a0001}, {0xc78, 0xf84b0001}, |
201 | {0xc78, 0xf74c0001}, {0xc78, 0xf64d0001}, |
202 | {0xc78, 0xf54e0001}, {0xc78, 0xf44f0001}, |
203 | {0xc78, 0xf3500001}, {0xc78, 0xf2510001}, |
204 | {0xc78, 0xf1520001}, {0xc78, 0xf0530001}, |
205 | {0xc78, 0xef540001}, {0xc78, 0xee550001}, |
206 | {0xc78, 0xed560001}, {0xc78, 0xec570001}, |
207 | {0xc78, 0xeb580001}, {0xc78, 0xea590001}, |
208 | {0xc78, 0xe95a0001}, {0xc78, 0xe85b0001}, |
209 | {0xc78, 0xe75c0001}, {0xc78, 0xe65d0001}, |
210 | {0xc78, 0xe55e0001}, {0xc78, 0xe45f0001}, |
211 | {0xc78, 0xe3600001}, {0xc78, 0xe2610001}, |
212 | {0xc78, 0xc3620001}, {0xc78, 0xc2630001}, |
213 | {0xc78, 0xc1640001}, {0xc78, 0x8b650001}, |
214 | {0xc78, 0x8a660001}, {0xc78, 0x89670001}, |
215 | {0xc78, 0x88680001}, {0xc78, 0x87690001}, |
216 | {0xc78, 0x866a0001}, {0xc78, 0x856b0001}, |
217 | {0xc78, 0x846c0001}, {0xc78, 0x676d0001}, |
218 | {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, |
219 | {0xc78, 0x64700001}, {0xc78, 0x63710001}, |
220 | {0xc78, 0x62720001}, {0xc78, 0x61730001}, |
221 | {0xc78, 0x60740001}, {0xc78, 0x46750001}, |
222 | {0xc78, 0x45760001}, {0xc78, 0x44770001}, |
223 | {0xc78, 0x43780001}, {0xc78, 0x42790001}, |
224 | {0xc78, 0x417a0001}, {0xc78, 0x407b0001}, |
225 | {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, |
226 | {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, |
227 | {0xc50, 0x69553422}, {0xc50, 0x69553420}, |
228 | {0xffff, 0xffffffff} |
229 | }; |
230 | |
231 | static const struct rtl8xxxu_rfregval rtl8188eu_radioa_init_table[] = { |
232 | {0x00, 0x00030000}, {0x08, 0x00084000}, |
233 | {0x18, 0x00000407}, {0x19, 0x00000012}, |
234 | {0x1e, 0x00080009}, {0x1f, 0x00000880}, |
235 | {0x2f, 0x0001a060}, {0x3f, 0x00000000}, |
236 | {0x42, 0x000060c0}, {0x57, 0x000d0000}, |
237 | {0x58, 0x000be180}, {0x67, 0x00001552}, |
238 | {0x83, 0x00000000}, {0xb0, 0x000ff8fc}, |
239 | {0xb1, 0x00054400}, {0xb2, 0x000ccc19}, |
240 | {0xb4, 0x00043003}, {0xb6, 0x0004953e}, |
241 | {0xb7, 0x0001c718}, {0xb8, 0x000060ff}, |
242 | {0xb9, 0x00080001}, {0xba, 0x00040000}, |
243 | {0xbb, 0x00000400}, {0xbf, 0x000c0000}, |
244 | {0xc2, 0x00002400}, {0xc3, 0x00000009}, |
245 | {0xc4, 0x00040c91}, {0xc5, 0x00099999}, |
246 | {0xc6, 0x000000a3}, {0xc7, 0x00088820}, |
247 | {0xc8, 0x00076c06}, {0xc9, 0x00000000}, |
248 | {0xca, 0x00080000}, {0xdf, 0x00000180}, |
249 | {0xef, 0x000001a0}, {0x51, 0x0006b27d}, |
250 | {0x52, 0x0007e49d}, /* Set to 0x0007e4dd for SDIO */ |
251 | {0x53, 0x00000073}, {0x56, 0x00051ff3}, |
252 | {0x35, 0x00000086}, {0x35, 0x00000186}, |
253 | {0x35, 0x00000286}, {0x36, 0x00001c25}, |
254 | {0x36, 0x00009c25}, {0x36, 0x00011c25}, |
255 | {0x36, 0x00019c25}, {0xb6, 0x00048538}, |
256 | {0x18, 0x00000c07}, {0x5a, 0x0004bd00}, |
257 | {0x19, 0x000739d0}, {0x34, 0x0000adf3}, |
258 | {0x34, 0x00009df0}, {0x34, 0x00008ded}, |
259 | {0x34, 0x00007dea}, {0x34, 0x00006de7}, |
260 | {0x34, 0x000054ee}, {0x34, 0x000044eb}, |
261 | {0x34, 0x000034e8}, {0x34, 0x0000246b}, |
262 | {0x34, 0x00001468}, {0x34, 0x0000006d}, |
263 | {0x00, 0x00030159}, {0x84, 0x00068200}, |
264 | {0x86, 0x000000ce}, {0x87, 0x00048a00}, |
265 | {0x8e, 0x00065540}, {0x8f, 0x00088000}, |
266 | {0xef, 0x000020a0}, {0x3b, 0x000f02b0}, |
267 | {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, |
268 | {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, |
269 | {0x3b, 0x000a0080}, {0x3b, 0x00090080}, |
270 | {0x3b, 0x0008f780}, {0x3b, 0x000722b0}, |
271 | {0x3b, 0x0006f7b0}, {0x3b, 0x00054fb0}, |
272 | {0x3b, 0x0004f060}, {0x3b, 0x00030090}, |
273 | {0x3b, 0x00020080}, {0x3b, 0x00010080}, |
274 | {0x3b, 0x0000f780}, {0xef, 0x000000a0}, |
275 | {0x00, 0x00010159}, {0x18, 0x0000f407}, |
276 | {0xFE, 0x00000000}, {0xFE, 0x00000000}, |
277 | {0x1F, 0x00080003}, {0xFE, 0x00000000}, |
278 | {0xFE, 0x00000000}, {0x1E, 0x00000001}, |
279 | {0x1F, 0x00080000}, {0x00, 0x00033e60}, |
280 | {0xff, 0xffffffff} |
281 | }; |
282 | |
283 | #define PERENTRY 23 |
284 | #define RETRYSIZE 5 |
285 | #define RATESIZE 28 |
286 | #define TX_RPT2_ITEM_SIZE 8 |
287 | |
288 | static const u8 retry_penalty[PERENTRY][RETRYSIZE + 1] = { |
289 | {5, 4, 3, 2, 0, 3}, /* 92 , idx=0 */ |
290 | {6, 5, 4, 3, 0, 4}, /* 86 , idx=1 */ |
291 | {6, 5, 4, 2, 0, 4}, /* 81 , idx=2 */ |
292 | {8, 7, 6, 4, 0, 6}, /* 75 , idx=3 */ |
293 | {10, 9, 8, 6, 0, 8}, /* 71 , idx=4 */ |
294 | {10, 9, 8, 4, 0, 8}, /* 66 , idx=5 */ |
295 | {10, 9, 8, 2, 0, 8}, /* 62 , idx=6 */ |
296 | {10, 9, 8, 0, 0, 8}, /* 59 , idx=7 */ |
297 | {18, 17, 16, 8, 0, 16}, /* 53 , idx=8 */ |
298 | {26, 25, 24, 16, 0, 24}, /* 50 , idx=9 */ |
299 | {34, 33, 32, 24, 0, 32}, /* 47 , idx=0x0a */ |
300 | {34, 31, 28, 20, 0, 32}, /* 43 , idx=0x0b */ |
301 | {34, 31, 27, 18, 0, 32}, /* 40 , idx=0x0c */ |
302 | {34, 31, 26, 16, 0, 32}, /* 37 , idx=0x0d */ |
303 | {34, 30, 22, 16, 0, 32}, /* 32 , idx=0x0e */ |
304 | {34, 30, 24, 16, 0, 32}, /* 26 , idx=0x0f */ |
305 | {49, 46, 40, 16, 0, 48}, /* 20 , idx=0x10 */ |
306 | {49, 45, 32, 0, 0, 48}, /* 17 , idx=0x11 */ |
307 | {49, 45, 22, 18, 0, 48}, /* 15 , idx=0x12 */ |
308 | {49, 40, 24, 16, 0, 48}, /* 12 , idx=0x13 */ |
309 | {49, 32, 18, 12, 0, 48}, /* 9 , idx=0x14 */ |
310 | {49, 22, 18, 14, 0, 48}, /* 6 , idx=0x15 */ |
311 | {49, 16, 16, 0, 0, 48} /* 3, idx=0x16 */ |
312 | }; |
313 | |
314 | static const u8 pt_penalty[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32}; |
315 | |
316 | static const u8 retry_penalty_idx_normal[2][RATESIZE] = { |
317 | { /* RSSI>TH */ |
318 | 4, 4, 4, 5, |
319 | 4, 4, 5, 7, 7, 7, 8, 0x0a, |
320 | 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, |
321 | 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f |
322 | }, |
323 | { /* RSSI<TH */ |
324 | 0x0a, 0x0a, 0x0b, 0x0c, |
325 | 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13, |
326 | 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x13, |
327 | 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13 |
328 | } |
329 | }; |
330 | |
331 | static const u8 retry_penalty_idx_cut_i[2][RATESIZE] = { |
332 | { /* RSSI>TH */ |
333 | 4, 4, 4, 5, |
334 | 4, 4, 5, 7, 7, 7, 8, 0x0a, |
335 | 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, |
336 | 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f |
337 | }, |
338 | { /* RSSI<TH */ |
339 | 0x0a, 0x0a, 0x0b, 0x0c, |
340 | 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13, |
341 | 0x06, 0x07, 0x08, 0x0d, 0x0e, 0x11, 0x11, 0x11, |
342 | 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13 |
343 | } |
344 | }; |
345 | |
346 | static const u8 retry_penalty_up_idx_normal[RATESIZE] = { |
347 | 0x0c, 0x0d, 0x0d, 0x0f, |
348 | 0x0d, 0x0e, 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, |
349 | 0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15, |
350 | 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15 |
351 | }; |
352 | |
353 | static const u8 retry_penalty_up_idx_cut_i[RATESIZE] = { |
354 | 0x0c, 0x0d, 0x0d, 0x0f, |
355 | 0x0d, 0x0e, 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, |
356 | 0x0b, 0x0b, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12, |
357 | 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15 |
358 | }; |
359 | |
360 | static const u8 [RATESIZE] = { |
361 | 0, 0, 0, 0, |
362 | 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, |
363 | 0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a, |
364 | 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c |
365 | }; |
366 | |
367 | static const u16 n_threshold_high[RATESIZE] = { |
368 | 4, 4, 8, 16, |
369 | 24, 36, 48, 72, 96, 144, 192, 216, |
370 | 60, 80, 100, 160, 240, 400, 600, 800, |
371 | 300, 320, 480, 720, 1000, 1200, 1600, 2000 |
372 | }; |
373 | |
374 | static const u16 n_threshold_low[RATESIZE] = { |
375 | 2, 2, 4, 8, |
376 | 12, 18, 24, 36, 48, 72, 96, 108, |
377 | 30, 40, 50, 80, 120, 200, 300, 400, |
378 | 150, 160, 240, 360, 500, 600, 800, 1000 |
379 | }; |
380 | |
381 | static const u8 dropping_necessary[RATESIZE] = { |
382 | 1, 1, 1, 1, |
383 | 1, 2, 3, 4, 5, 6, 7, 8, |
384 | 1, 2, 3, 4, 5, 6, 7, 8, |
385 | 5, 6, 7, 8, 9, 10, 11, 12 |
386 | }; |
387 | |
388 | static const u8 pending_for_rate_up_fail[5] = {2, 10, 24, 40, 60}; |
389 | |
390 | static const u16 dynamic_tx_rpt_timing[6] = { |
391 | 0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c /* 200ms-1200ms */ |
392 | }; |
393 | |
394 | enum rtl8188e_tx_rpt_timing { |
395 | DEFAULT_TIMING = 0, |
396 | INCREASE_TIMING, |
397 | DECREASE_TIMING |
398 | }; |
399 | |
400 | static int rtl8188eu_identify_chip(struct rtl8xxxu_priv *priv) |
401 | { |
402 | struct device *dev = &priv->udev->dev; |
403 | u32 sys_cfg, vendor; |
404 | int ret = 0; |
405 | |
406 | strscpy(priv->chip_name, "8188EU" , sizeof(priv->chip_name)); |
407 | priv->rtl_chip = RTL8188E; |
408 | priv->rf_paths = 1; |
409 | priv->rx_paths = 1; |
410 | priv->tx_paths = 1; |
411 | priv->has_wifi = 1; |
412 | |
413 | sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); |
414 | priv->chip_cut = u32_get_bits(v: sys_cfg, SYS_CFG_CHIP_VERSION_MASK); |
415 | if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { |
416 | dev_info(dev, "Unsupported test chip\n" ); |
417 | return -EOPNOTSUPP; |
418 | } |
419 | |
420 | /* |
421 | * TODO: At a glance, I cut requires a different firmware, |
422 | * different initialisation tables, and no software rate |
423 | * control. The vendor driver is not configured to handle |
424 | * I cut chips by default. Are there any in the wild? |
425 | */ |
426 | if (priv->chip_cut == 8) { |
427 | dev_info(dev, "RTL8188EU cut I is not supported. Please complain about it at linux-wireless@vger.kernel.org.\n" ); |
428 | return -EOPNOTSUPP; |
429 | } |
430 | |
431 | vendor = sys_cfg & SYS_CFG_VENDOR_ID; |
432 | rtl8xxxu_identify_vendor_1bit(priv, vendor); |
433 | |
434 | ret = rtl8xxxu_config_endpoints_no_sie(priv); |
435 | |
436 | return ret; |
437 | } |
438 | |
439 | static void rtl8188eu_config_channel(struct ieee80211_hw *hw) |
440 | { |
441 | struct rtl8xxxu_priv *priv = hw->priv; |
442 | u32 val32, rsr; |
443 | u8 opmode; |
444 | int sec_ch_above, channel; |
445 | int i; |
446 | |
447 | opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); |
448 | rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
449 | channel = hw->conf.chandef.chan->hw_value; |
450 | |
451 | switch (hw->conf.chandef.width) { |
452 | case NL80211_CHAN_WIDTH_20_NOHT: |
453 | case NL80211_CHAN_WIDTH_20: |
454 | opmode |= BW_OPMODE_20MHZ; |
455 | rtl8xxxu_write8(priv, REG_BW_OPMODE, val: opmode); |
456 | |
457 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
458 | val32 &= ~FPGA_RF_MODE; |
459 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32); |
460 | |
461 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
462 | val32 &= ~FPGA_RF_MODE; |
463 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val: val32); |
464 | break; |
465 | case NL80211_CHAN_WIDTH_40: |
466 | if (hw->conf.chandef.center_freq1 > |
467 | hw->conf.chandef.chan->center_freq) { |
468 | sec_ch_above = 1; |
469 | channel += 2; |
470 | } else { |
471 | sec_ch_above = 0; |
472 | channel -= 2; |
473 | } |
474 | |
475 | opmode &= ~BW_OPMODE_20MHZ; |
476 | rtl8xxxu_write8(priv, REG_BW_OPMODE, val: opmode); |
477 | rsr &= ~RSR_RSC_BANDWIDTH_40M; |
478 | if (sec_ch_above) |
479 | rsr |= RSR_RSC_LOWER_SUB_CHANNEL; |
480 | else |
481 | rsr |= RSR_RSC_UPPER_SUB_CHANNEL; |
482 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val: rsr); |
483 | |
484 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
485 | val32 |= FPGA_RF_MODE; |
486 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32); |
487 | |
488 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
489 | val32 |= FPGA_RF_MODE; |
490 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val: val32); |
491 | |
492 | /* |
493 | * Set Control channel to upper or lower. These settings |
494 | * are required only for 40MHz |
495 | */ |
496 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); |
497 | val32 &= ~CCK0_SIDEBAND; |
498 | if (!sec_ch_above) |
499 | val32 |= CCK0_SIDEBAND; |
500 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val: val32); |
501 | |
502 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); |
503 | val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ |
504 | if (sec_ch_above) |
505 | val32 |= OFDM_LSTF_PRIME_CH_LOW; |
506 | else |
507 | val32 |= OFDM_LSTF_PRIME_CH_HIGH; |
508 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val: val32); |
509 | |
510 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); |
511 | val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); |
512 | if (sec_ch_above) |
513 | val32 |= FPGA0_PS_UPPER_CHANNEL; |
514 | else |
515 | val32 |= FPGA0_PS_LOWER_CHANNEL; |
516 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val: val32); |
517 | break; |
518 | |
519 | default: |
520 | break; |
521 | } |
522 | |
523 | for (i = RF_A; i < priv->rf_paths; i++) { |
524 | val32 = rtl8xxxu_read_rfreg(priv, path: i, RF6052_REG_MODE_AG); |
525 | u32p_replace_bits(p: &val32, val: channel, MODE_AG_CHANNEL_MASK); |
526 | rtl8xxxu_write_rfreg(priv, path: i, RF6052_REG_MODE_AG, data: val32); |
527 | } |
528 | |
529 | for (i = RF_A; i < priv->rf_paths; i++) { |
530 | val32 = rtl8xxxu_read_rfreg(priv, path: i, RF6052_REG_MODE_AG); |
531 | val32 &= ~MODE_AG_BW_MASK; |
532 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) |
533 | val32 |= MODE_AG_BW_40MHZ_8723B; |
534 | else |
535 | val32 |= MODE_AG_BW_20MHZ_8723B; |
536 | rtl8xxxu_write_rfreg(priv, path: i, RF6052_REG_MODE_AG, data: val32); |
537 | } |
538 | } |
539 | |
540 | static void rtl8188eu_init_aggregation(struct rtl8xxxu_priv *priv) |
541 | { |
542 | u8 agg_ctrl, usb_spec; |
543 | |
544 | usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); |
545 | usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; |
546 | rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val: usb_spec); |
547 | |
548 | agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); |
549 | agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; |
550 | rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, val: agg_ctrl); |
551 | } |
552 | |
553 | static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv) |
554 | { |
555 | struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu; |
556 | |
557 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
558 | return -EINVAL; |
559 | |
560 | ether_addr_copy(dst: priv->mac_addr, src: efuse->mac_addr); |
561 | |
562 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
563 | sizeof(efuse->tx_power_index_A.cck_base)); |
564 | |
565 | memcpy(priv->ht40_1s_tx_power_index_A, |
566 | efuse->tx_power_index_A.ht40_base, |
567 | sizeof(efuse->tx_power_index_A.ht40_base)); |
568 | |
569 | priv->default_crystal_cap = efuse->xtal_k & 0x3f; |
570 | |
571 | return 0; |
572 | } |
573 | |
574 | static void rtl8188eu_reset_8051(struct rtl8xxxu_priv *priv) |
575 | { |
576 | u16 sys_func; |
577 | |
578 | sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
579 | sys_func &= ~SYS_FUNC_CPU_ENABLE; |
580 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val: sys_func); |
581 | |
582 | sys_func |= SYS_FUNC_CPU_ENABLE; |
583 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val: sys_func); |
584 | } |
585 | |
586 | static int rtl8188eu_load_firmware(struct rtl8xxxu_priv *priv) |
587 | { |
588 | const char *fw_name; |
589 | int ret; |
590 | |
591 | fw_name = "rtlwifi/rtl8188eufw.bin" ; |
592 | |
593 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
594 | |
595 | return ret; |
596 | } |
597 | |
598 | static void rtl8188eu_init_phy_bb(struct rtl8xxxu_priv *priv) |
599 | { |
600 | u8 val8; |
601 | u16 val16; |
602 | |
603 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
604 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; |
605 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val: val16); |
606 | |
607 | /* |
608 | * Per vendor driver, run power sequence before init of RF |
609 | */ |
610 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
611 | rtl8xxxu_write8(priv, REG_RF_CTRL, val: val8); |
612 | |
613 | val8 = SYS_FUNC_USBA | SYS_FUNC_USBD | |
614 | SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; |
615 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val: val8); |
616 | |
617 | rtl8xxxu_init_phy_regs(priv, array: rtl8188eu_phy_init_table); |
618 | rtl8xxxu_init_phy_regs(priv, array: rtl8188e_agc_table); |
619 | } |
620 | |
621 | static int rtl8188eu_init_phy_rf(struct rtl8xxxu_priv *priv) |
622 | { |
623 | return rtl8xxxu_init_phy_rf(priv, table: rtl8188eu_radioa_init_table, path: RF_A); |
624 | } |
625 | |
626 | static int rtl8188eu_iqk_path_a(struct rtl8xxxu_priv *priv) |
627 | { |
628 | u32 reg_eac, reg_e94, reg_e9c; |
629 | int result = 0; |
630 | |
631 | /* Path A IQK setting */ |
632 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x10008c1c); |
633 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x30008c1c); |
634 | |
635 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: 0x8214032a); |
636 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: 0x28160000); |
637 | |
638 | /* LO calibration setting */ |
639 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x00462911); |
640 | |
641 | /* One shot, path A LOK & IQK */ |
642 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf9000000); |
643 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8000000); |
644 | |
645 | mdelay(10); |
646 | |
647 | /* Check failed */ |
648 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
649 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
650 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
651 | |
652 | if (!(reg_eac & BIT(28)) && |
653 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
654 | ((reg_e9c & 0x03ff0000) != 0x00420000)) |
655 | result |= 0x01; |
656 | |
657 | return result; |
658 | } |
659 | |
660 | static int rtl8188eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) |
661 | { |
662 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; |
663 | int result = 0; |
664 | |
665 | /* Leave IQK mode */ |
666 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
667 | u32p_replace_bits(p: &val32, val: 0, field: 0xffffff00); |
668 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32); |
669 | |
670 | /* Enable path A PA in TX IQK mode */ |
671 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT, data: 0x800a0); |
672 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RCK_OS, data: 0x30000); |
673 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G1, data: 0x0000f); |
674 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G2, data: 0xf117b); |
675 | |
676 | /* Enter IQK mode */ |
677 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
678 | u32p_replace_bits(p: &val32, val: 0x808000, field: 0xffffff00); |
679 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32); |
680 | |
681 | /* TX IQK setting */ |
682 | rtl8xxxu_write32(priv, REG_TX_IQK, val: 0x01007c00); |
683 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x81004800); |
684 | |
685 | /* path-A IQK setting */ |
686 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x10008c1c); |
687 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x30008c1c); |
688 | |
689 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: 0x82160804); |
690 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: 0x28160000); |
691 | |
692 | /* LO calibration setting */ |
693 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x0046a911); |
694 | |
695 | /* One shot, path A LOK & IQK */ |
696 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf9000000); |
697 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8000000); |
698 | |
699 | mdelay(10); |
700 | |
701 | /* Check failed */ |
702 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
703 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
704 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
705 | |
706 | if (!(reg_eac & BIT(28)) && |
707 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
708 | ((reg_e9c & 0x03ff0000) != 0x00420000)) |
709 | result |= 0x01; |
710 | else |
711 | goto out; |
712 | |
713 | val32 = 0x80007c00 | |
714 | (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); |
715 | rtl8xxxu_write32(priv, REG_TX_IQK, val: val32); |
716 | |
717 | /* Modify RX IQK mode table */ |
718 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
719 | u32p_replace_bits(p: &val32, val: 0, field: 0xffffff00); |
720 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32); |
721 | |
722 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT, data: 0x800a0); |
723 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RCK_OS, data: 0x30000); |
724 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G1, data: 0x0000f); |
725 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G2, data: 0xf7ffa); |
726 | |
727 | /* Enter IQK mode */ |
728 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
729 | u32p_replace_bits(p: &val32, val: 0x808000, field: 0xffffff00); |
730 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32); |
731 | |
732 | /* IQK setting */ |
733 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x01004800); |
734 | |
735 | /* Path A IQK setting */ |
736 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x30008c1c); |
737 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x10008c1c); |
738 | |
739 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: 0x82160c05); |
740 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: 0x28160c05); |
741 | |
742 | /* LO calibration setting */ |
743 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x0046a911); |
744 | |
745 | /* One shot, path A LOK & IQK */ |
746 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf9000000); |
747 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8000000); |
748 | |
749 | mdelay(10); |
750 | |
751 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
752 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
753 | |
754 | if (!(reg_eac & BIT(27)) && |
755 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
756 | ((reg_eac & 0x03ff0000) != 0x00360000)) |
757 | result |= 0x02; |
758 | else |
759 | dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n" , |
760 | __func__); |
761 | |
762 | out: |
763 | return result; |
764 | } |
765 | |
766 | static void rtl8188eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
767 | int result[][8], int t) |
768 | { |
769 | struct device *dev = &priv->udev->dev; |
770 | u32 i, val32; |
771 | int path_a_ok; |
772 | int retry = 2; |
773 | static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
774 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
775 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
776 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
777 | REG_TX_OFDM_BBON, REG_TX_TO_RX, |
778 | REG_TX_TO_TX, REG_RX_CCK, |
779 | REG_RX_OFDM, REG_RX_WAIT_RIFS, |
780 | REG_RX_TO_RX, REG_STANDBY, |
781 | REG_SLEEP, REG_PMPD_ANAEN |
782 | }; |
783 | static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
784 | REG_TXPAUSE, REG_BEACON_CTRL, |
785 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
786 | }; |
787 | static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
788 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
789 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
790 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
791 | REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING |
792 | }; |
793 | |
794 | /* |
795 | * Note: IQ calibration must be performed after loading |
796 | * PHY_REG.txt , and radio_a, radio_b.txt |
797 | */ |
798 | |
799 | if (t == 0) { |
800 | /* Save ADDA parameters, turn Path A ADDA on */ |
801 | rtl8xxxu_save_regs(priv, regs: adda_regs, backup: priv->adda_backup, |
802 | RTL8XXXU_ADDA_REGS); |
803 | rtl8xxxu_save_mac_regs(priv, reg: iqk_mac_regs, backup: priv->mac_backup); |
804 | rtl8xxxu_save_regs(priv, regs: iqk_bb_regs, |
805 | backup: priv->bb_backup, RTL8XXXU_BB_REGS); |
806 | } |
807 | |
808 | rtl8xxxu_path_adda_on(priv, regs: adda_regs, path_a_on: true); |
809 | |
810 | if (t == 0) { |
811 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); |
812 | priv->pi_enabled = u32_get_bits(v: val32, FPGA0_HSSI_PARM1_PI); |
813 | } |
814 | |
815 | if (!priv->pi_enabled) { |
816 | /* Switch BB to PI mode to do IQ Calibration. */ |
817 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000100); |
818 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val: 0x01000100); |
819 | } |
820 | |
821 | /* MAC settings */ |
822 | rtl8xxxu_mac_calibration(priv, regs: iqk_mac_regs, backup: priv->mac_backup); |
823 | |
824 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); |
825 | u32p_replace_bits(p: &val32, val: 0xf, field: 0x0f000000); |
826 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val: val32); |
827 | |
828 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x03a05600); |
829 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000800e4); |
830 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x22204000); |
831 | |
832 | if (!priv->no_pape) { |
833 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); |
834 | val32 |= (FPGA0_RF_PAPE | |
835 | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); |
836 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val: val32); |
837 | } |
838 | |
839 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); |
840 | val32 &= ~BIT(10); |
841 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val: val32); |
842 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); |
843 | val32 &= ~BIT(10); |
844 | rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val: val32); |
845 | |
846 | /* Page B init */ |
847 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, val: 0x0f600000); |
848 | |
849 | /* IQ calibration setting */ |
850 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
851 | u32p_replace_bits(p: &val32, val: 0x808000, field: 0xffffff00); |
852 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32); |
853 | rtl8xxxu_write32(priv, REG_TX_IQK, val: 0x01007c00); |
854 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x81004800); |
855 | |
856 | for (i = 0; i < retry; i++) { |
857 | path_a_ok = rtl8188eu_iqk_path_a(priv); |
858 | if (path_a_ok == 0x01) { |
859 | val32 = rtl8xxxu_read32(priv, |
860 | REG_TX_POWER_BEFORE_IQK_A); |
861 | result[t][0] = (val32 >> 16) & 0x3ff; |
862 | val32 = rtl8xxxu_read32(priv, |
863 | REG_TX_POWER_AFTER_IQK_A); |
864 | result[t][1] = (val32 >> 16) & 0x3ff; |
865 | break; |
866 | } |
867 | } |
868 | |
869 | if (!path_a_ok) |
870 | dev_dbg(dev, "%s: Path A TX IQK failed!\n" , __func__); |
871 | |
872 | for (i = 0; i < retry; i++) { |
873 | path_a_ok = rtl8188eu_rx_iqk_path_a(priv); |
874 | if (path_a_ok == 0x03) { |
875 | val32 = rtl8xxxu_read32(priv, |
876 | REG_RX_POWER_BEFORE_IQK_A_2); |
877 | result[t][2] = (val32 >> 16) & 0x3ff; |
878 | val32 = rtl8xxxu_read32(priv, |
879 | REG_RX_POWER_AFTER_IQK_A_2); |
880 | result[t][3] = (val32 >> 16) & 0x3ff; |
881 | |
882 | break; |
883 | } |
884 | } |
885 | |
886 | if (!path_a_ok) |
887 | dev_dbg(dev, "%s: Path A RX IQK failed!\n" , __func__); |
888 | |
889 | /* Back to BB mode, load original value */ |
890 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
891 | u32p_replace_bits(p: &val32, val: 0, field: 0xffffff00); |
892 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32); |
893 | |
894 | if (t == 0) |
895 | return; |
896 | |
897 | if (!priv->pi_enabled) { |
898 | /* Switch back BB to SI mode after finishing IQ Calibration */ |
899 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000000); |
900 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val: 0x01000000); |
901 | } |
902 | |
903 | /* Reload ADDA power saving parameters */ |
904 | rtl8xxxu_restore_regs(priv, regs: adda_regs, backup: priv->adda_backup, |
905 | RTL8XXXU_ADDA_REGS); |
906 | |
907 | /* Reload MAC parameters */ |
908 | rtl8xxxu_restore_mac_regs(priv, reg: iqk_mac_regs, backup: priv->mac_backup); |
909 | |
910 | /* Reload BB parameters */ |
911 | rtl8xxxu_restore_regs(priv, regs: iqk_bb_regs, |
912 | backup: priv->bb_backup, RTL8XXXU_BB_REGS); |
913 | |
914 | /* Restore RX initial gain */ |
915 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, val: 0x00032ed3); |
916 | |
917 | /* Load 0xe30 IQC default value */ |
918 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x01008c00); |
919 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x01008c00); |
920 | } |
921 | |
922 | static void rtl8188eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
923 | { |
924 | struct device *dev = &priv->udev->dev; |
925 | int result[4][8]; /* last is final result */ |
926 | int i, candidate; |
927 | bool path_a_ok; |
928 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
929 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
930 | bool simu; |
931 | |
932 | memset(result, 0, sizeof(result)); |
933 | result[3][0] = 0x100; |
934 | result[3][2] = 0x100; |
935 | result[3][4] = 0x100; |
936 | result[3][6] = 0x100; |
937 | |
938 | candidate = -1; |
939 | |
940 | path_a_ok = false; |
941 | |
942 | for (i = 0; i < 3; i++) { |
943 | rtl8188eu_phy_iqcalibrate(priv, result, t: i); |
944 | |
945 | if (i == 1) { |
946 | simu = rtl8xxxu_simularity_compare(priv, |
947 | result, c1: 0, c2: 1); |
948 | if (simu) { |
949 | candidate = 0; |
950 | break; |
951 | } |
952 | } |
953 | |
954 | if (i == 2) { |
955 | simu = rtl8xxxu_simularity_compare(priv, |
956 | result, c1: 0, c2: 2); |
957 | if (simu) { |
958 | candidate = 0; |
959 | break; |
960 | } |
961 | |
962 | simu = rtl8xxxu_simularity_compare(priv, |
963 | result, c1: 1, c2: 2); |
964 | if (simu) |
965 | candidate = 1; |
966 | else |
967 | candidate = 3; |
968 | } |
969 | } |
970 | |
971 | if (candidate >= 0) { |
972 | reg_e94 = result[candidate][0]; |
973 | priv->rege94 = reg_e94; |
974 | reg_e9c = result[candidate][1]; |
975 | priv->rege9c = reg_e9c; |
976 | reg_ea4 = result[candidate][2]; |
977 | reg_eac = result[candidate][3]; |
978 | reg_eb4 = result[candidate][4]; |
979 | priv->regeb4 = reg_eb4; |
980 | reg_ebc = result[candidate][5]; |
981 | priv->regebc = reg_ebc; |
982 | reg_ec4 = result[candidate][6]; |
983 | reg_ecc = result[candidate][7]; |
984 | dev_dbg(dev, "%s: candidate is %x\n" , __func__, candidate); |
985 | dev_dbg(dev, |
986 | "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n" , |
987 | __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, |
988 | reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
989 | path_a_ok = true; |
990 | } else { |
991 | reg_e94 = 0x100; |
992 | reg_eb4 = 0x100; |
993 | priv->rege94 = 0x100; |
994 | priv->regeb4 = 0x100; |
995 | reg_e9c = 0x0; |
996 | reg_ebc = 0x0; |
997 | priv->rege9c = 0x0; |
998 | priv->regebc = 0x0; |
999 | } |
1000 | |
1001 | if (reg_e94 && candidate >= 0) |
1002 | rtl8xxxu_fill_iqk_matrix_a(priv, iqk_ok: path_a_ok, result, |
1003 | candidate, tx_only: (reg_ea4 == 0)); |
1004 | |
1005 | rtl8xxxu_save_regs(priv, regs: rtl8xxxu_iqk_phy_iq_bb_reg, |
1006 | backup: priv->bb_recovery_backup, RTL8XXXU_BB_REGS); |
1007 | } |
1008 | |
1009 | static void rtl8188e_disabled_to_emu(struct rtl8xxxu_priv *priv) |
1010 | { |
1011 | u16 val16; |
1012 | |
1013 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
1014 | val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); |
1015 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val: val16); |
1016 | } |
1017 | |
1018 | static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv) |
1019 | { |
1020 | u8 val8; |
1021 | u32 val32; |
1022 | u16 val16; |
1023 | int count, ret = 0; |
1024 | |
1025 | /* wait till 0x04[17] = 1 power ready*/ |
1026 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
1027 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1028 | if (val32 & BIT(17)) |
1029 | break; |
1030 | |
1031 | udelay(10); |
1032 | } |
1033 | |
1034 | if (!count) { |
1035 | ret = -EBUSY; |
1036 | goto exit; |
1037 | } |
1038 | |
1039 | /* reset baseband */ |
1040 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
1041 | val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); |
1042 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val: val8); |
1043 | |
1044 | /*0x24[23] = 2b'01 schmit trigger */ |
1045 | val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); |
1046 | val32 |= BIT(23); |
1047 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val: val32); |
1048 | |
1049 | /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ |
1050 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
1051 | val16 &= ~APS_FSMCO_HW_POWERDOWN; |
1052 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val: val16); |
1053 | |
1054 | /*0x04[12:11] = 2b'00 disable WL suspend*/ |
1055 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
1056 | val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); |
1057 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val: val16); |
1058 | |
1059 | /* set, then poll until 0 */ |
1060 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1061 | val32 |= APS_FSMCO_MAC_ENABLE; |
1062 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val: val32); |
1063 | |
1064 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
1065 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1066 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { |
1067 | ret = 0; |
1068 | break; |
1069 | } |
1070 | udelay(10); |
1071 | } |
1072 | |
1073 | if (!count) { |
1074 | ret = -EBUSY; |
1075 | goto exit; |
1076 | } |
1077 | |
1078 | /* LDO normal mode*/ |
1079 | val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); |
1080 | val8 &= ~BIT(4); |
1081 | rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val: val8); |
1082 | |
1083 | exit: |
1084 | return ret; |
1085 | } |
1086 | |
1087 | static int rtl8188eu_active_to_emu(struct rtl8xxxu_priv *priv) |
1088 | { |
1089 | u8 val8; |
1090 | |
1091 | /* Turn off RF */ |
1092 | val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); |
1093 | val8 &= ~RF_ENABLE; |
1094 | rtl8xxxu_write8(priv, REG_RF_CTRL, val: val8); |
1095 | |
1096 | /* LDO Sleep mode */ |
1097 | val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); |
1098 | val8 |= BIT(4); |
1099 | rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val: val8); |
1100 | |
1101 | return 0; |
1102 | } |
1103 | |
1104 | static int rtl8188eu_emu_to_disabled(struct rtl8xxxu_priv *priv) |
1105 | { |
1106 | u32 val32; |
1107 | u16 val16; |
1108 | u8 val8; |
1109 | |
1110 | val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); |
1111 | val32 |= BIT(23); |
1112 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val: val32); |
1113 | |
1114 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
1115 | val16 &= ~APS_FSMCO_PCIE; |
1116 | val16 |= APS_FSMCO_HW_SUSPEND; |
1117 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val: val16); |
1118 | |
1119 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, val: 0x00); |
1120 | |
1121 | val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG + 1); |
1122 | val8 &= ~BIT(4); |
1123 | rtl8xxxu_write8(priv, REG_GPIO_MUXCFG + 1, val: val8); |
1124 | |
1125 | /* Set USB suspend enable local register 0xfe10[4]=1 */ |
1126 | val8 = rtl8xxxu_read8(priv, addr: 0xfe10); |
1127 | val8 |= BIT(4); |
1128 | rtl8xxxu_write8(priv, addr: 0xfe10, val: val8); |
1129 | |
1130 | return 0; |
1131 | } |
1132 | |
1133 | static int rtl8188eu_active_to_lps(struct rtl8xxxu_priv *priv) |
1134 | { |
1135 | struct device *dev = &priv->udev->dev; |
1136 | u8 val8; |
1137 | u16 val16; |
1138 | u32 val32; |
1139 | int retry, retval; |
1140 | |
1141 | rtl8xxxu_write8(priv, REG_TXPAUSE, val: 0x7f); |
1142 | |
1143 | retry = 100; |
1144 | retval = -EBUSY; |
1145 | /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ |
1146 | do { |
1147 | val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); |
1148 | if (!val32) { |
1149 | retval = 0; |
1150 | break; |
1151 | } |
1152 | } while (retry--); |
1153 | |
1154 | if (!retry) { |
1155 | dev_warn(dev, "Failed to flush TX queue\n" ); |
1156 | retval = -EBUSY; |
1157 | goto out; |
1158 | } |
1159 | |
1160 | /* Disable CCK and OFDM, clock gated */ |
1161 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
1162 | val8 &= ~SYS_FUNC_BBRSTB; |
1163 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val: val8); |
1164 | |
1165 | udelay(2); |
1166 | |
1167 | /* Reset MAC TRX */ |
1168 | val16 = rtl8xxxu_read16(priv, REG_CR); |
1169 | val16 |= 0xff; |
1170 | val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); |
1171 | rtl8xxxu_write16(priv, REG_CR, val: val16); |
1172 | |
1173 | val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); |
1174 | val8 |= DUAL_TSF_TX_OK; |
1175 | rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val: val8); |
1176 | |
1177 | out: |
1178 | return retval; |
1179 | } |
1180 | |
1181 | static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv) |
1182 | { |
1183 | u16 val16; |
1184 | int ret; |
1185 | |
1186 | rtl8188e_disabled_to_emu(priv); |
1187 | |
1188 | ret = rtl8188e_emu_to_active(priv); |
1189 | if (ret) |
1190 | goto exit; |
1191 | |
1192 | /* |
1193 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
1194 | * Set CR bit10 to enable 32k calibration. |
1195 | * We do not set CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE here |
1196 | * due to a hardware bug in the 88E, requiring those to be |
1197 | * set after REG_TRXFF_BNDY is set. If not the RXFF bundary |
1198 | * will get set to a larger buffer size than the real buffer |
1199 | * size. |
1200 | */ |
1201 | val16 = (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
1202 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
1203 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
1204 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); |
1205 | rtl8xxxu_write16(priv, REG_CR, val: val16); |
1206 | |
1207 | exit: |
1208 | return ret; |
1209 | } |
1210 | |
1211 | static void rtl8188eu_power_off(struct rtl8xxxu_priv *priv) |
1212 | { |
1213 | u8 val8; |
1214 | u16 val16; |
1215 | |
1216 | rtl8xxxu_flush_fifo(priv); |
1217 | |
1218 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); |
1219 | val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; |
1220 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val: val8); |
1221 | |
1222 | /* Turn off RF */ |
1223 | rtl8xxxu_write8(priv, REG_RF_CTRL, val: 0x00); |
1224 | |
1225 | rtl8188eu_active_to_lps(priv); |
1226 | |
1227 | /* Reset Firmware if running in RAM */ |
1228 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) |
1229 | rtl8xxxu_firmware_self_reset(priv); |
1230 | |
1231 | /* Reset MCU */ |
1232 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
1233 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
1234 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val: val16); |
1235 | |
1236 | /* Reset MCU ready status */ |
1237 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val: 0x00); |
1238 | |
1239 | /* 32K_CTRL looks to be very 8188e specific */ |
1240 | val8 = rtl8xxxu_read8(priv, REG_32K_CTRL); |
1241 | val8 &= ~BIT(0); |
1242 | rtl8xxxu_write8(priv, REG_32K_CTRL, val: val8); |
1243 | |
1244 | rtl8188eu_active_to_emu(priv); |
1245 | rtl8188eu_emu_to_disabled(priv); |
1246 | |
1247 | /* Reset MCU IO Wrapper */ |
1248 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
1249 | val8 &= ~BIT(3); |
1250 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val: val8); |
1251 | |
1252 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
1253 | val8 |= BIT(3); |
1254 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val: val8); |
1255 | |
1256 | /* Vendor driver refers to GPIO_IN */ |
1257 | val8 = rtl8xxxu_read8(priv, REG_GPIO_PIN_CTRL); |
1258 | /* Vendor driver refers to GPIO_OUT */ |
1259 | rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 1, val: val8); |
1260 | rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 2, val: 0xff); |
1261 | |
1262 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL); |
1263 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL, val: val8 << 4); |
1264 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL + 1); |
1265 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val: val8 | 0x0f); |
1266 | |
1267 | /* |
1268 | * Set LNA, TRSW, EX_PA Pin to output mode |
1269 | * Referred to as REG_BB_PAD_CTRL in 8188eu vendor driver |
1270 | */ |
1271 | rtl8xxxu_write32(priv, REG_PAD_CTRL1, val: 0x00080808); |
1272 | |
1273 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val: 0x00); |
1274 | |
1275 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val: 0x00000000); |
1276 | } |
1277 | |
1278 | static void rtl8188e_enable_rf(struct rtl8xxxu_priv *priv) |
1279 | { |
1280 | u32 val32; |
1281 | |
1282 | rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); |
1283 | |
1284 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
1285 | val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); |
1286 | val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; |
1287 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: val32); |
1288 | |
1289 | rtl8xxxu_write8(priv, REG_TXPAUSE, val: 0x00); |
1290 | } |
1291 | |
1292 | static void rtl8188e_disable_rf(struct rtl8xxxu_priv *priv) |
1293 | { |
1294 | u32 val32; |
1295 | |
1296 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
1297 | val32 &= ~OFDM_RF_PATH_TX_MASK; |
1298 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: val32); |
1299 | |
1300 | /* Power down RF module */ |
1301 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_AC, data: 0); |
1302 | |
1303 | rtl8188eu_active_to_emu(priv); |
1304 | } |
1305 | |
1306 | static void rtl8188e_usb_quirks(struct rtl8xxxu_priv *priv) |
1307 | { |
1308 | u16 val16; |
1309 | |
1310 | /* |
1311 | * Technically this is not a USB quirk, but a chip quirk. |
1312 | * This has to be done after REG_TRXFF_BNDY is set, see |
1313 | * rtl8188eu_power_on() for details. |
1314 | */ |
1315 | val16 = rtl8xxxu_read16(priv, REG_CR); |
1316 | val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); |
1317 | rtl8xxxu_write16(priv, REG_CR, val: val16); |
1318 | |
1319 | rtl8xxxu_gen2_usb_quirks(priv); |
1320 | |
1321 | /* Pre-TX enable WEP/TKIP security */ |
1322 | rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8188E + 3, val: 0x01); |
1323 | } |
1324 | |
1325 | static s8 (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) |
1326 | { |
1327 | /* only use lna 0/1/2/3/7 */ |
1328 | static const s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41}; |
1329 | /* only use lna 3/7 */ |
1330 | static const s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; |
1331 | |
1332 | u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; |
1333 | s8 rx_pwr_all = 0x00; |
1334 | u8 vga_idx, lna_idx; |
1335 | s8 lna_gain = 0; |
1336 | |
1337 | lna_idx = u8_get_bits(v: cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); |
1338 | vga_idx = u8_get_bits(v: cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); |
1339 | |
1340 | if (priv->chip_cut >= 8) /* cut I */ /* SMIC */ |
1341 | lna_gain = lna_gain_table_0[lna_idx]; |
1342 | else /* TSMC */ |
1343 | lna_gain = lna_gain_table_1[lna_idx]; |
1344 | |
1345 | rx_pwr_all = lna_gain - (2 * vga_idx); |
1346 | |
1347 | return rx_pwr_all; |
1348 | } |
1349 | |
1350 | static int rtl8188eu_led_brightness_set(struct led_classdev *led_cdev, |
1351 | enum led_brightness brightness) |
1352 | { |
1353 | struct rtl8xxxu_priv *priv = container_of(led_cdev, |
1354 | struct rtl8xxxu_priv, |
1355 | led_cdev); |
1356 | u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); |
1357 | |
1358 | if (brightness == LED_OFF) { |
1359 | ledcfg &= ~LEDCFG2_HW_LED_CONTROL; |
1360 | ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; |
1361 | } else if (brightness == LED_ON) { |
1362 | ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); |
1363 | ledcfg |= LEDCFG2_SW_LED_CONTROL; |
1364 | } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { |
1365 | ledcfg &= ~LEDCFG2_SW_LED_DISABLE; |
1366 | ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; |
1367 | } |
1368 | |
1369 | rtl8xxxu_write8(priv, REG_LEDCFG2, val: ledcfg); |
1370 | |
1371 | return 0; |
1372 | } |
1373 | |
1374 | static void rtl8188e_set_tx_rpt_timing(struct rtl8xxxu_ra_info *ra, u8 timing) |
1375 | { |
1376 | u8 idx; |
1377 | |
1378 | for (idx = 0; idx < 5; idx++) |
1379 | if (dynamic_tx_rpt_timing[idx] == ra->rpt_time) |
1380 | break; |
1381 | |
1382 | if (timing == DEFAULT_TIMING) { |
1383 | idx = 0; /* 200ms */ |
1384 | } else if (timing == INCREASE_TIMING) { |
1385 | if (idx < 5) |
1386 | idx++; |
1387 | } else if (timing == DECREASE_TIMING) { |
1388 | if (idx > 0) |
1389 | idx--; |
1390 | } |
1391 | |
1392 | ra->rpt_time = dynamic_tx_rpt_timing[idx]; |
1393 | } |
1394 | |
1395 | static void rtl8188e_rate_down(struct rtl8xxxu_ra_info *ra) |
1396 | { |
1397 | u8 rate_id = ra->pre_rate; |
1398 | u8 lowest_rate = ra->lowest_rate; |
1399 | u8 highest_rate = ra->highest_rate; |
1400 | s8 i; |
1401 | |
1402 | if (rate_id > highest_rate) { |
1403 | rate_id = highest_rate; |
1404 | } else if (ra->rate_sgi) { |
1405 | ra->rate_sgi = 0; |
1406 | } else if (rate_id > lowest_rate) { |
1407 | if (rate_id > 0) { |
1408 | for (i = rate_id - 1; i >= lowest_rate; i--) { |
1409 | if (ra->ra_use_rate & BIT(i)) { |
1410 | rate_id = i; |
1411 | goto rate_down_finish; |
1412 | } |
1413 | } |
1414 | } |
1415 | } else if (rate_id <= lowest_rate) { |
1416 | rate_id = lowest_rate; |
1417 | } |
1418 | |
1419 | rate_down_finish: |
1420 | if (ra->ra_waiting_counter == 1) { |
1421 | ra->ra_waiting_counter++; |
1422 | ra->ra_pending_counter++; |
1423 | } else if (ra->ra_waiting_counter > 1) { |
1424 | ra->ra_waiting_counter = 0; |
1425 | ra->ra_pending_counter = 0; |
1426 | } |
1427 | |
1428 | if (ra->ra_pending_counter >= 4) |
1429 | ra->ra_pending_counter = 4; |
1430 | |
1431 | ra->ra_drop_after_down = 1; |
1432 | |
1433 | ra->decision_rate = rate_id; |
1434 | |
1435 | rtl8188e_set_tx_rpt_timing(ra, timing: DECREASE_TIMING); |
1436 | } |
1437 | |
1438 | static void rtl8188e_rate_up(struct rtl8xxxu_ra_info *ra) |
1439 | { |
1440 | u8 rate_id = ra->pre_rate; |
1441 | u8 highest_rate = ra->highest_rate; |
1442 | u8 i; |
1443 | |
1444 | if (ra->ra_waiting_counter == 1) { |
1445 | ra->ra_waiting_counter = 0; |
1446 | ra->ra_pending_counter = 0; |
1447 | } else if (ra->ra_waiting_counter > 1) { |
1448 | ra->pre_rssi_sta_ra = ra->rssi_sta_ra; |
1449 | goto rate_up_finish; |
1450 | } |
1451 | |
1452 | rtl8188e_set_tx_rpt_timing(ra, timing: DEFAULT_TIMING); |
1453 | |
1454 | if (rate_id < highest_rate) { |
1455 | for (i = rate_id + 1; i <= highest_rate; i++) { |
1456 | if (ra->ra_use_rate & BIT(i)) { |
1457 | rate_id = i; |
1458 | goto rate_up_finish; |
1459 | } |
1460 | } |
1461 | } else if (rate_id == highest_rate) { |
1462 | if (ra->sgi_enable && !ra->rate_sgi) |
1463 | ra->rate_sgi = 1; |
1464 | else if (!ra->sgi_enable) |
1465 | ra->rate_sgi = 0; |
1466 | } else { /* rate_id > ra->highest_rate */ |
1467 | rate_id = highest_rate; |
1468 | } |
1469 | |
1470 | rate_up_finish: |
1471 | if (ra->ra_waiting_counter == (4 + pending_for_rate_up_fail[ra->ra_pending_counter])) |
1472 | ra->ra_waiting_counter = 0; |
1473 | else |
1474 | ra->ra_waiting_counter++; |
1475 | |
1476 | ra->decision_rate = rate_id; |
1477 | } |
1478 | |
1479 | static void rtl8188e_reset_ra_counter(struct rtl8xxxu_ra_info *ra) |
1480 | { |
1481 | u8 rate_id = ra->decision_rate; |
1482 | |
1483 | ra->nsc_up = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; |
1484 | ra->nsc_down = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; |
1485 | } |
1486 | |
1487 | static void rtl8188e_rate_decision(struct rtl8xxxu_ra_info *ra) |
1488 | { |
1489 | struct rtl8xxxu_priv *priv = container_of(ra, struct rtl8xxxu_priv, ra_info); |
1490 | const u8 *retry_penalty_idx_0; |
1491 | const u8 *retry_penalty_idx_1; |
1492 | const u8 *retry_penalty_up_idx; |
1493 | u8 rate_id, penalty_id1, penalty_id2; |
1494 | int i; |
1495 | |
1496 | if (ra->total == 0) |
1497 | return; |
1498 | |
1499 | if (ra->ra_drop_after_down) { |
1500 | ra->ra_drop_after_down--; |
1501 | |
1502 | rtl8188e_reset_ra_counter(ra); |
1503 | |
1504 | return; |
1505 | } |
1506 | |
1507 | if (priv->chip_cut == 8) { /* cut I */ |
1508 | retry_penalty_idx_0 = retry_penalty_idx_cut_i[0]; |
1509 | retry_penalty_idx_1 = retry_penalty_idx_cut_i[1]; |
1510 | retry_penalty_up_idx = retry_penalty_up_idx_cut_i; |
1511 | } else { |
1512 | retry_penalty_idx_0 = retry_penalty_idx_normal[0]; |
1513 | retry_penalty_idx_1 = retry_penalty_idx_normal[1]; |
1514 | retry_penalty_up_idx = retry_penalty_up_idx_normal; |
1515 | } |
1516 | |
1517 | if (ra->rssi_sta_ra < (ra->pre_rssi_sta_ra - 3) || |
1518 | ra->rssi_sta_ra > (ra->pre_rssi_sta_ra + 3)) { |
1519 | ra->pre_rssi_sta_ra = ra->rssi_sta_ra; |
1520 | ra->ra_waiting_counter = 0; |
1521 | ra->ra_pending_counter = 0; |
1522 | } |
1523 | |
1524 | /* Start RA decision */ |
1525 | if (ra->pre_rate > ra->highest_rate) |
1526 | rate_id = ra->highest_rate; |
1527 | else |
1528 | rate_id = ra->pre_rate; |
1529 | |
1530 | /* rate down */ |
1531 | if (ra->rssi_sta_ra > rssi_threshold[rate_id]) |
1532 | penalty_id1 = retry_penalty_idx_0[rate_id]; |
1533 | else |
1534 | penalty_id1 = retry_penalty_idx_1[rate_id]; |
1535 | |
1536 | for (i = 0; i < 5; i++) |
1537 | ra->nsc_down += ra->retry[i] * retry_penalty[penalty_id1][i]; |
1538 | |
1539 | if (ra->nsc_down > (ra->total * retry_penalty[penalty_id1][5])) |
1540 | ra->nsc_down -= ra->total * retry_penalty[penalty_id1][5]; |
1541 | else |
1542 | ra->nsc_down = 0; |
1543 | |
1544 | /* rate up */ |
1545 | penalty_id2 = retry_penalty_up_idx[rate_id]; |
1546 | |
1547 | for (i = 0; i < 5; i++) |
1548 | ra->nsc_up += ra->retry[i] * retry_penalty[penalty_id2][i]; |
1549 | |
1550 | if (ra->nsc_up > (ra->total * retry_penalty[penalty_id2][5])) |
1551 | ra->nsc_up -= ra->total * retry_penalty[penalty_id2][5]; |
1552 | else |
1553 | ra->nsc_up = 0; |
1554 | |
1555 | if (ra->nsc_down < n_threshold_low[rate_id] || |
1556 | ra->drop > dropping_necessary[rate_id]) { |
1557 | rtl8188e_rate_down(ra); |
1558 | |
1559 | rtl8xxxu_update_ra_report(rarpt: &priv->ra_report, rate: ra->decision_rate, |
1560 | sgi: ra->rate_sgi, bw: priv->ra_report.txrate.bw); |
1561 | } else if (ra->nsc_up > n_threshold_high[rate_id]) { |
1562 | rtl8188e_rate_up(ra); |
1563 | |
1564 | rtl8xxxu_update_ra_report(rarpt: &priv->ra_report, rate: ra->decision_rate, |
1565 | sgi: ra->rate_sgi, bw: priv->ra_report.txrate.bw); |
1566 | } |
1567 | |
1568 | if (ra->decision_rate == ra->pre_rate) |
1569 | ra->dynamic_tx_rpt_timing_counter++; |
1570 | else |
1571 | ra->dynamic_tx_rpt_timing_counter = 0; |
1572 | |
1573 | if (ra->dynamic_tx_rpt_timing_counter >= 4) { |
1574 | /* Rate didn't change 4 times, extend RPT timing */ |
1575 | rtl8188e_set_tx_rpt_timing(ra, timing: INCREASE_TIMING); |
1576 | ra->dynamic_tx_rpt_timing_counter = 0; |
1577 | } |
1578 | |
1579 | ra->pre_rate = ra->decision_rate; |
1580 | |
1581 | rtl8188e_reset_ra_counter(ra); |
1582 | } |
1583 | |
1584 | static void rtl8188e_power_training_try_state(struct rtl8xxxu_ra_info *ra) |
1585 | { |
1586 | ra->pt_try_state = 0; |
1587 | switch (ra->pt_mode_ss) { |
1588 | case 3: |
1589 | if (ra->decision_rate >= DESC_RATE_MCS13) |
1590 | ra->pt_try_state = 1; |
1591 | break; |
1592 | case 2: |
1593 | if (ra->decision_rate >= DESC_RATE_MCS5) |
1594 | ra->pt_try_state = 1; |
1595 | break; |
1596 | case 1: |
1597 | if (ra->decision_rate >= DESC_RATE_48M) |
1598 | ra->pt_try_state = 1; |
1599 | break; |
1600 | case 0: |
1601 | if (ra->decision_rate >= DESC_RATE_11M) |
1602 | ra->pt_try_state = 1; |
1603 | break; |
1604 | default: |
1605 | break; |
1606 | } |
1607 | |
1608 | if (ra->rssi_sta_ra < 48) { |
1609 | ra->pt_stage = 0; |
1610 | } else if (ra->pt_try_state == 1) { |
1611 | if ((ra->pt_stop_count >= 10) || |
1612 | (ra->pt_pre_rssi > ra->rssi_sta_ra + 5) || |
1613 | (ra->pt_pre_rssi < ra->rssi_sta_ra - 5) || |
1614 | (ra->decision_rate != ra->pt_pre_rate)) { |
1615 | if (ra->pt_stage == 0) |
1616 | ra->pt_stage = 1; |
1617 | else if (ra->pt_stage == 1) |
1618 | ra->pt_stage = 3; |
1619 | else |
1620 | ra->pt_stage = 5; |
1621 | |
1622 | ra->pt_pre_rssi = ra->rssi_sta_ra; |
1623 | ra->pt_stop_count = 0; |
1624 | } else { |
1625 | ra->ra_stage = 0; |
1626 | ra->pt_stop_count++; |
1627 | } |
1628 | } else { |
1629 | ra->pt_stage = 0; |
1630 | ra->ra_stage = 0; |
1631 | } |
1632 | |
1633 | ra->pt_pre_rate = ra->decision_rate; |
1634 | |
1635 | /* TODO: implement the "false alarm" statistics for this */ |
1636 | /* Disable power training when noisy environment */ |
1637 | /* if (p_dm_odm->is_disable_power_training) { */ |
1638 | if (1) { |
1639 | ra->pt_stage = 0; |
1640 | ra->ra_stage = 0; |
1641 | ra->pt_stop_count = 0; |
1642 | } |
1643 | } |
1644 | |
1645 | static void rtl8188e_power_training_decision(struct rtl8xxxu_ra_info *ra) |
1646 | { |
1647 | u8 temp_stage; |
1648 | u32 numsc; |
1649 | u32 num_total; |
1650 | u8 stage_id; |
1651 | u8 j; |
1652 | |
1653 | numsc = 0; |
1654 | num_total = ra->total * pt_penalty[5]; |
1655 | for (j = 0; j <= 4; j++) { |
1656 | numsc += ra->retry[j] * pt_penalty[j]; |
1657 | |
1658 | if (numsc > num_total) |
1659 | break; |
1660 | } |
1661 | |
1662 | j >>= 1; |
1663 | temp_stage = (ra->pt_stage + 1) >> 1; |
1664 | if (temp_stage > j) |
1665 | stage_id = temp_stage - j; |
1666 | else |
1667 | stage_id = 0; |
1668 | |
1669 | ra->pt_smooth_factor = (ra->pt_smooth_factor >> 1) + |
1670 | (ra->pt_smooth_factor >> 2) + |
1671 | stage_id * 16 + 2; |
1672 | if (ra->pt_smooth_factor > 192) |
1673 | ra->pt_smooth_factor = 192; |
1674 | stage_id = ra->pt_smooth_factor >> 6; |
1675 | temp_stage = stage_id * 2; |
1676 | if (temp_stage != 0) |
1677 | temp_stage--; |
1678 | if (ra->drop > 3) |
1679 | temp_stage = 0; |
1680 | ra->pt_stage = temp_stage; |
1681 | } |
1682 | |
1683 | void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb) |
1684 | { |
1685 | u32 *_rx_desc = (u32 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); |
1686 | struct rtl8xxxu_rxdesc16 *rx_desc = (struct rtl8xxxu_rxdesc16 *)_rx_desc; |
1687 | struct device *dev = &priv->udev->dev; |
1688 | struct rtl8xxxu_ra_info *ra = &priv->ra_info; |
1689 | u32 tx_rpt_len = rx_desc->pktlen & 0x3ff; |
1690 | u32 items = tx_rpt_len / TX_RPT2_ITEM_SIZE; |
1691 | u64 macid_valid = ((u64)_rx_desc[5] << 32) | _rx_desc[4]; |
1692 | u32 macid; |
1693 | u8 *rpt = skb->data; |
1694 | bool valid; |
1695 | u16 min_rpt_time = 0x927c; |
1696 | |
1697 | dev_dbg(dev, "%s: len: %d items: %d\n" , __func__, tx_rpt_len, items); |
1698 | |
1699 | /* We only use macid 0, so only the first item is relevant. |
1700 | * AP mode will use more of them if it's ever implemented. |
1701 | */ |
1702 | if (!priv->vifs[0] || priv->vifs[0]->type == NL80211_IFTYPE_STATION) |
1703 | items = 1; |
1704 | |
1705 | for (macid = 0; macid < items; macid++) { |
1706 | valid = false; |
1707 | |
1708 | if (macid < 64) |
1709 | valid = macid_valid & BIT(macid); |
1710 | |
1711 | if (valid) { |
1712 | ra->retry[0] = le16_to_cpu(*(__le16 *)rpt); |
1713 | ra->retry[1] = rpt[2]; |
1714 | ra->retry[2] = rpt[3]; |
1715 | ra->retry[3] = rpt[4]; |
1716 | ra->retry[4] = rpt[5]; |
1717 | ra->drop = rpt[6]; |
1718 | ra->total = ra->retry[0] + ra->retry[1] + ra->retry[2] + |
1719 | ra->retry[3] + ra->retry[4] + ra->drop; |
1720 | |
1721 | if (ra->total > 0) { |
1722 | if (ra->ra_stage < 5) |
1723 | rtl8188e_rate_decision(ra); |
1724 | else if (ra->ra_stage == 5) |
1725 | rtl8188e_power_training_try_state(ra); |
1726 | else /* ra->ra_stage == 6 */ |
1727 | rtl8188e_power_training_decision(ra); |
1728 | |
1729 | if (ra->ra_stage <= 5) |
1730 | ra->ra_stage++; |
1731 | else |
1732 | ra->ra_stage = 0; |
1733 | } |
1734 | } else if (macid == 0) { |
1735 | dev_warn(dev, "%s: TX report item 0 not valid\n" , __func__); |
1736 | } |
1737 | |
1738 | dev_dbg(dev, "%s: valid: %d retry: %d %d %d %d %d drop: %d\n" , |
1739 | __func__, valid, |
1740 | ra->retry[0], ra->retry[1], ra->retry[2], |
1741 | ra->retry[3], ra->retry[4], ra->drop); |
1742 | |
1743 | if (min_rpt_time > ra->rpt_time) |
1744 | min_rpt_time = ra->rpt_time; |
1745 | |
1746 | rpt += TX_RPT2_ITEM_SIZE; |
1747 | } |
1748 | |
1749 | if (min_rpt_time != ra->pre_min_rpt_time) { |
1750 | rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, val: min_rpt_time); |
1751 | ra->pre_min_rpt_time = min_rpt_time; |
1752 | } |
1753 | } |
1754 | |
1755 | static void rtl8188e_arfb_refresh(struct rtl8xxxu_ra_info *ra) |
1756 | { |
1757 | s8 i; |
1758 | |
1759 | ra->ra_use_rate = ra->rate_mask; |
1760 | |
1761 | /* Highest rate */ |
1762 | if (ra->ra_use_rate) { |
1763 | for (i = RATESIZE; i >= 0; i--) { |
1764 | if (ra->ra_use_rate & BIT(i)) { |
1765 | ra->highest_rate = i; |
1766 | break; |
1767 | } |
1768 | } |
1769 | } else { |
1770 | ra->highest_rate = 0; |
1771 | } |
1772 | |
1773 | /* Lowest rate */ |
1774 | if (ra->ra_use_rate) { |
1775 | for (i = 0; i < RATESIZE; i++) { |
1776 | if (ra->ra_use_rate & BIT(i)) { |
1777 | ra->lowest_rate = i; |
1778 | break; |
1779 | } |
1780 | } |
1781 | } else { |
1782 | ra->lowest_rate = 0; |
1783 | } |
1784 | |
1785 | if (ra->highest_rate > DESC_RATE_MCS7) |
1786 | ra->pt_mode_ss = 3; |
1787 | else if (ra->highest_rate > DESC_RATE_54M) |
1788 | ra->pt_mode_ss = 2; |
1789 | else if (ra->highest_rate > DESC_RATE_11M) |
1790 | ra->pt_mode_ss = 1; |
1791 | else |
1792 | ra->pt_mode_ss = 0; |
1793 | } |
1794 | |
1795 | static void |
1796 | rtl8188e_update_rate_mask(struct rtl8xxxu_priv *priv, |
1797 | u32 ramask, u8 rateid, int sgi, int txbw_40mhz, |
1798 | u8 macid) |
1799 | { |
1800 | struct rtl8xxxu_ra_info *ra = &priv->ra_info; |
1801 | |
1802 | ra->rate_id = rateid; |
1803 | ra->rate_mask = ramask; |
1804 | ra->sgi_enable = sgi; |
1805 | |
1806 | rtl8188e_arfb_refresh(ra); |
1807 | } |
1808 | |
1809 | static void (struct rtl8xxxu_priv *priv, u8 macid, u8 ) |
1810 | { |
1811 | priv->ra_info.rssi_sta_ra = rssi; |
1812 | } |
1813 | |
1814 | void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra) |
1815 | { |
1816 | ra->decision_rate = DESC_RATE_MCS7; |
1817 | ra->pre_rate = DESC_RATE_MCS7; |
1818 | ra->highest_rate = DESC_RATE_MCS7; |
1819 | ra->lowest_rate = 0; |
1820 | ra->rate_id = 0; |
1821 | ra->rate_mask = 0xfffff; |
1822 | ra->rssi_sta_ra = 0; |
1823 | ra->pre_rssi_sta_ra = 0; |
1824 | ra->sgi_enable = 0; |
1825 | ra->ra_use_rate = 0xfffff; |
1826 | ra->nsc_down = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; |
1827 | ra->nsc_up = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; |
1828 | ra->rate_sgi = 0; |
1829 | ra->rpt_time = 0x927c; |
1830 | ra->drop = 0; |
1831 | ra->retry[0] = 0; |
1832 | ra->retry[1] = 0; |
1833 | ra->retry[2] = 0; |
1834 | ra->retry[3] = 0; |
1835 | ra->retry[4] = 0; |
1836 | ra->total = 0; |
1837 | ra->ra_waiting_counter = 0; |
1838 | ra->ra_pending_counter = 0; |
1839 | ra->ra_drop_after_down = 0; |
1840 | |
1841 | ra->pt_try_state = 0; |
1842 | ra->pt_stage = 5; |
1843 | ra->pt_smooth_factor = 192; |
1844 | ra->pt_stop_count = 0; |
1845 | ra->pt_pre_rate = 0; |
1846 | ra->pt_pre_rssi = 0; |
1847 | ra->pt_mode_ss = 0; |
1848 | ra->ra_stage = 0; |
1849 | } |
1850 | |
1851 | struct rtl8xxxu_fileops rtl8188eu_fops = { |
1852 | .identify_chip = rtl8188eu_identify_chip, |
1853 | .parse_efuse = rtl8188eu_parse_efuse, |
1854 | .load_firmware = rtl8188eu_load_firmware, |
1855 | .power_on = rtl8188eu_power_on, |
1856 | .power_off = rtl8188eu_power_off, |
1857 | .read_efuse = rtl8xxxu_read_efuse, |
1858 | .reset_8051 = rtl8188eu_reset_8051, |
1859 | .llt_init = rtl8xxxu_init_llt_table, |
1860 | .init_phy_bb = rtl8188eu_init_phy_bb, |
1861 | .init_phy_rf = rtl8188eu_init_phy_rf, |
1862 | .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, |
1863 | .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate, |
1864 | .config_channel = rtl8188eu_config_channel, |
1865 | .parse_rx_desc = rtl8xxxu_parse_rxdesc16, |
1866 | .parse_phystats = rtl8723au_rx_parse_phystats, |
1867 | .init_aggregation = rtl8188eu_init_aggregation, |
1868 | .enable_rf = rtl8188e_enable_rf, |
1869 | .disable_rf = rtl8188e_disable_rf, |
1870 | .usb_quirks = rtl8188e_usb_quirks, |
1871 | .set_tx_power = rtl8188f_set_tx_power, |
1872 | .update_rate_mask = rtl8188e_update_rate_mask, |
1873 | .report_connect = rtl8xxxu_gen2_report_connect, |
1874 | .report_rssi = rtl8188e_ra_set_rssi, |
1875 | .fill_txdesc = rtl8xxxu_fill_txdesc_v3, |
1876 | .set_crystal_cap = rtl8188f_set_crystal_cap, |
1877 | .cck_rssi = rtl8188e_cck_rssi, |
1878 | .led_classdev_brightness_set = rtl8188eu_led_brightness_set, |
1879 | .writeN_block_size = 128, |
1880 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), |
1881 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), |
1882 | .has_tx_report = 1, |
1883 | .init_reg_pkt_life_time = 1, |
1884 | .gen2_thermal_meter = 1, |
1885 | .max_sec_cam_num = 32, |
1886 | .adda_1t_init = 0x0b1b25a0, |
1887 | .adda_1t_path_on = 0x0bdb25a0, |
1888 | /* |
1889 | * Use 9K for 8188e normal chip |
1890 | * Max RX buffer = 10K - max(TxReportSize(64*8), WOLPattern(16*24)) |
1891 | */ |
1892 | .trxff_boundary = 0x25ff, |
1893 | .pbp_rx = PBP_PAGE_SIZE_128, |
1894 | .pbp_tx = PBP_PAGE_SIZE_128, |
1895 | .mactable = rtl8188e_mac_init_table, |
1896 | .total_page_num = TX_TOTAL_PAGE_NUM_8188E, |
1897 | .page_num_hi = TX_PAGE_NUM_HI_PQ_8188E, |
1898 | .page_num_lo = TX_PAGE_NUM_LO_PQ_8188E, |
1899 | .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188E, |
1900 | .last_llt_entry = 175, |
1901 | }; |
1902 | |