rtl8xxxu_8188f.c source code [linux/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c]

1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* RTL8XXXU mac80211 USB driver - 8188f specific subdriver
4	*
5	* Copyright (c) 2022 Bitterblue Smith <rtl8821cerfe2@gmail.com>
6	*
7	* Portions copied from existing rtl8xxxu code:
8	* Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
9	*
10	* Portions, notably calibration code:
11	* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
12	*/
13
14	#include <linux/init.h>
15	#include <linux/kernel.h>
16	#include <linux/sched.h>
17	#include <linux/errno.h>
18	#include <linux/slab.h>
19	#include <linux/module.h>
20	#include <linux/spinlock.h>
21	#include <linux/list.h>
22	#include <linux/usb.h>
23	#include <linux/netdevice.h>
24	#include <linux/etherdevice.h>
25	#include <linux/ethtool.h>
26	#include <linux/wireless.h>
27	#include <linux/firmware.h>
28	#include <linux/moduleparam.h>
29	#include <net/mac80211.h>
30	#include "rtl8xxxu.h"
31	#include "rtl8xxxu_regs.h"
32
33	static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = {
34	{`0x024`, `0xDF`}, {`0x025`, `0x07`}, {`0x02B`, `0x1C`}, {`0x283`, `0x20`},
35	{`0x421`, `0x0F`}, {`0x428`, `0x0A`}, {`0x429`, `0x10`}, {`0x430`, `0x00`},
36	{`0x431`, `0x00`}, {`0x432`, `0x00`}, {`0x433`, `0x01`}, {`0x434`, `0x04`},
37	{`0x435`, `0x05`}, {`0x436`, `0x07`}, {`0x437`, `0x08`}, {`0x43C`, `0x04`},
38	{`0x43D`, `0x05`}, {`0x43E`, `0x07`}, {`0x43F`, `0x08`}, {`0x440`, `0x5D`},
39	{`0x441`, `0x01`}, {`0x442`, `0x00`}, {`0x444`, `0x10`}, {`0x445`, `0x00`},
40	{`0x446`, `0x00`}, {`0x447`, `0x00`}, {`0x448`, `0x00`}, {`0x449`, `0xF0`},
41	{`0x44A`, `0x0F`}, {`0x44B`, `0x3E`}, {`0x44C`, `0x10`}, {`0x44D`, `0x00`},
42	{`0x44E`, `0x00`}, {`0x44F`, `0x00`}, {`0x450`, `0x00`}, {`0x451`, `0xF0`},
43	{`0x452`, `0x0F`}, {`0x453`, `0x00`}, {`0x456`, `0x5E`}, {`0x460`, `0x44`},
44	{`0x461`, `0x44`}, {`0x4BC`, `0xC0`}, {`0x4C8`, `0xFF`}, {`0x4C9`, `0x08`},
45	{`0x4CC`, `0xFF`}, {`0x4CD`, `0xFF`}, {`0x4CE`, `0x01`}, {`0x500`, `0x26`},
46	{`0x501`, `0xA2`}, {`0x502`, `0x2F`}, {`0x503`, `0x00`}, {`0x504`, `0x28`},
47	{`0x505`, `0xA3`}, {`0x506`, `0x5E`}, {`0x507`, `0x00`}, {`0x508`, `0x2B`},
48	{`0x509`, `0xA4`}, {`0x50A`, `0x5E`}, {`0x50B`, `0x00`}, {`0x50C`, `0x4F`},
49	{`0x50D`, `0xA4`}, {`0x50E`, `0x00`}, {`0x50F`, `0x00`}, {`0x512`, `0x1C`},
50	{`0x514`, `0x0A`}, {`0x516`, `0x0A`}, {`0x525`, `0x4F`}, {`0x550`, `0x10`},
51	{`0x551`, `0x10`}, {`0x559`, `0x02`}, {`0x55C`, `0x28`}, {`0x55D`, `0xFF`},
52	{`0x605`, `0x30`}, {`0x608`, `0x0E`}, {`0x609`, `0x2A`}, {`0x620`, `0xFF`},
53	{`0x621`, `0xFF`}, {`0x622`, `0xFF`}, {`0x623`, `0xFF`}, {`0x624`, `0xFF`},
54	{`0x625`, `0xFF`}, {`0x626`, `0xFF`}, {`0x627`, `0xFF`}, {`0x638`, `0x28`},
55	{`0x63C`, `0x0A`}, {`0x63D`, `0x0A`}, {`0x63E`, `0x0E`}, {`0x63F`, `0x0E`},
56	{`0x640`, `0x40`}, {`0x642`, `0x40`}, {`0x643`, `0x00`}, {`0x652`, `0xC8`},
57	{`0x66E`, `0x05`}, {`0x700`, `0x21`}, {`0x701`, `0x43`}, {`0x702`, `0x65`},
58	{`0x703`, `0x87`}, {`0x708`, `0x21`}, {`0x709`, `0x43`}, {`0x70A`, `0x65`},
59	{`0x70B`, `0x87`},
60	{`0xffff`, `0xff`},
61	};
62
63	static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = {
64	{`0x800`, `0x80045700`}, {`0x804`, `0x00000001`},
65	{`0x808`, `0x0000FC00`}, {`0x80C`, `0x0000000A`},
66	{`0x810`, `0x10001331`}, {`0x814`, `0x020C3D10`},
67	{`0x818`, `0x00200385`}, {`0x81C`, `0x00000000`},
68	{`0x820`, `0x01000100`}, {`0x824`, `0x00390204`},
69	{`0x828`, `0x00000000`}, {`0x82C`, `0x00000000`},
70	{`0x830`, `0x00000000`}, {`0x834`, `0x00000000`},
71	{`0x838`, `0x00000000`}, {`0x83C`, `0x00000000`},
72	{`0x840`, `0x00010000`}, {`0x844`, `0x00000000`},
73	{`0x848`, `0x00000000`}, {`0x84C`, `0x00000000`},
74	{`0x850`, `0x00030000`}, {`0x854`, `0x00000000`},
75	{`0x858`, `0x569A569A`}, {`0x85C`, `0x569A569A`},
76	{`0x860`, `0x00000130`}, {`0x864`, `0x00000000`},
77	{`0x868`, `0x00000000`}, {`0x86C`, `0x27272700`},
78	{`0x870`, `0x00000000`}, {`0x874`, `0x25004000`},
79	{`0x878`, `0x00000808`}, {`0x87C`, `0x004F0201`},
80	{`0x880`, `0xB0000B1E`}, {`0x884`, `0x00000007`},
81	{`0x888`, `0x00000000`}, {`0x88C`, `0xCCC000C0`},
82	{`0x890`, `0x00000800`}, {`0x894`, `0xFFFFFFFE`},
83	{`0x898`, `0x40302010`}, {`0x89C`, `0x00706050`},
84	{`0x900`, `0x00000000`}, {`0x904`, `0x00000023`},
85	{`0x908`, `0x00000000`}, {`0x90C`, `0x81121111`},
86	{`0x910`, `0x00000002`}, {`0x914`, `0x00000201`},
87	{`0x948`, `0x99000000`}, {`0x94C`, `0x00000010`},
88	{`0x950`, `0x20003000`}, {`0x954`, `0x4A880000`},
89	{`0x958`, `0x4BC5D87A`}, {`0x95C`, `0x04EB9B79`},
90	{`0x96C`, `0x00000003`}, {`0xA00`, `0x00D047C8`},
91	{`0xA04`, `0x80FF800C`}, {`0xA08`, `0x8C898300`},
92	{`0xA0C`, `0x2E7F120F`}, {`0xA10`, `0x9500BB78`},
93	{`0xA14`, `0x1114D028`}, {`0xA18`, `0x00881117`},
94	{`0xA1C`, `0x89140F00`}, {`0xA20`, `0xD1D80000`},
95	{`0xA24`, `0x5A7DA0BD`}, {`0xA28`, `0x0000223B`},
96	{`0xA2C`, `0x00D30000`}, {`0xA70`, `0x101FBF00`},
97	{`0xA74`, `0x00000007`}, {`0xA78`, `0x00000900`},
98	{`0xA7C`, `0x225B0606`}, {`0xA80`, `0x218075B1`},
99	{`0xA84`, `0x00120000`}, {`0xA88`, `0x040C0000`},
100	{`0xA8C`, `0x12345678`}, {`0xA90`, `0xABCDEF00`},
101	{`0xA94`, `0x001B1B89`}, {`0xA98`, `0x05100000`},
102	{`0xA9C`, `0x3F000000`}, {`0xAA0`, `0x00000000`},
103	{`0xB2C`, `0x00000000`}, {`0xC00`, `0x48071D40`},
104	{`0xC04`, `0x03A05611`}, {`0xC08`, `0x000000E4`},
105	{`0xC0C`, `0x6C6C6C6C`}, {`0xC10`, `0x18800000`},
106	{`0xC14`, `0x40000100`}, {`0xC18`, `0x08800000`},
107	{`0xC1C`, `0x40000100`}, {`0xC20`, `0x00000000`},
108	{`0xC24`, `0x00000000`}, {`0xC28`, `0x00000000`},
109	{`0xC2C`, `0x00000000`}, {`0xC30`, `0x69E9CC4A`},
110	{`0xC34`, `0x31000040`}, {`0xC38`, `0x21688080`},
111	{`0xC3C`, `0x00001714`}, {`0xC40`, `0x1F78403F`},
112	{`0xC44`, `0x00010036`}, {`0xC48`, `0xEC020107`},
113	{`0xC4C`, `0x007F037F`}, {`0xC50`, `0x69553420`},
114	{`0xC54`, `0x43BC0094`}, {`0xC58`, `0x00013169`},
115	{`0xC5C`, `0x00250492`}, {`0xC60`, `0x00000000`},
116	{`0xC64`, `0x7112848B`}, {`0xC68`, `0x47C07BFF`},
117	{`0xC6C`, `0x00000036`}, {`0xC70`, `0x2C7F000D`},
118	{`0xC74`, `0x020600DB`}, {`0xC78`, `0x0000001F`},
119	{`0xC7C`, `0x00B91612`}, {`0xC80`, `0x390000E4`},
120	{`0xC84`, `0x11F60000`},
121	{`0xC88`, `0x40000100`}, {`0xC8C`, `0x20200000`},
122	{`0xC90`, `0x00091521`}, {`0xC94`, `0x00000000`},
123	{`0xC98`, `0x00121820`}, {`0xC9C`, `0x00007F7F`},
124	{`0xCA0`, `0x00000000`}, {`0xCA4`, `0x000300A0`},
125	{`0xCA8`, `0x00000000`}, {`0xCAC`, `0x00000000`},
126	{`0xCB0`, `0x00000000`}, {`0xCB4`, `0x00000000`},
127	{`0xCB8`, `0x00000000`}, {`0xCBC`, `0x28000000`},
128	{`0xCC0`, `0x00000000`}, {`0xCC4`, `0x00000000`},
129	{`0xCC8`, `0x00000000`}, {`0xCCC`, `0x00000000`},
130	{`0xCD0`, `0x00000000`}, {`0xCD4`, `0x00000000`},
131	{`0xCD8`, `0x64B22427`}, {`0xCDC`, `0x00766932`},
132	{`0xCE0`, `0x00222222`}, {`0xCE4`, `0x10000000`},
133	{`0xCE8`, `0x37644302`}, {`0xCEC`, `0x2F97D40C`},
134	{`0xD00`, `0x04030740`}, {`0xD04`, `0x40020401`},
135	{`0xD08`, `0x0000907F`}, {`0xD0C`, `0x20010201`},
136	{`0xD10`, `0xA0633333`}, {`0xD14`, `0x3333BC53`},
137	{`0xD18`, `0x7A8F5B6F`}, {`0xD2C`, `0xCB979975`},
138	{`0xD30`, `0x00000000`}, {`0xD34`, `0x80608000`},
139	{`0xD38`, `0x98000000`}, {`0xD3C`, `0x40127353`},
140	{`0xD40`, `0x00000000`}, {`0xD44`, `0x00000000`},
141	{`0xD48`, `0x00000000`}, {`0xD4C`, `0x00000000`},
142	{`0xD50`, `0x6437140A`}, {`0xD54`, `0x00000000`},
143	{`0xD58`, `0x00000282`}, {`0xD5C`, `0x30032064`},
144	{`0xD60`, `0x4653DE68`}, {`0xD64`, `0x04518A3C`},
145	{`0xD68`, `0x00002101`}, {`0xD6C`, `0x2A201C16`},
146	{`0xD70`, `0x1812362E`}, {`0xD74`, `0x322C2220`},
147	{`0xD78`, `0x000E3C24`}, {`0xE00`, `0x2D2D2D2D`},
148	{`0xE04`, `0x2D2D2D2D`}, {`0xE08`, `0x0390272D`},
149	{`0xE10`, `0x2D2D2D2D`}, {`0xE14`, `0x2D2D2D2D`},
150	{`0xE18`, `0x2D2D2D2D`}, {`0xE1C`, `0x2D2D2D2D`},
151	{`0xE28`, `0x00000000`}, {`0xE30`, `0x1000DC1F`},
152	{`0xE34`, `0x10008C1F`}, {`0xE38`, `0x02140102`},
153	{`0xE3C`, `0x681604C2`}, {`0xE40`, `0x01007C00`},
154	{`0xE44`, `0x01004800`}, {`0xE48`, `0xFB000000`},
155	{`0xE4C`, `0x000028D1`}, {`0xE50`, `0x1000DC1F`},
156	{`0xE54`, `0x10008C1F`}, {`0xE58`, `0x02140102`},
157	{`0xE5C`, `0x28160D05`}, {`0xE60`, `0x00000008`},
158	{`0xE60`, `0x021400A0`}, {`0xE64`, `0x281600A0`},
159	{`0xE6C`, `0x01C00010`}, {`0xE70`, `0x01C00010`},
160	{`0xE74`, `0x02000010`}, {`0xE78`, `0x02000010`},
161	{`0xE7C`, `0x02000010`}, {`0xE80`, `0x02000010`},
162	{`0xE84`, `0x01C00010`}, {`0xE88`, `0x02000010`},
163	{`0xE8C`, `0x01C00010`}, {`0xED0`, `0x01C00010`},
164	{`0xED4`, `0x01C00010`}, {`0xED8`, `0x01C00010`},
165	{`0xEDC`, `0x00000010`}, {`0xEE0`, `0x00000010`},
166	{`0xEEC`, `0x03C00010`}, {`0xF14`, `0x00000003`},
167	{`0xF4C`, `0x00000000`}, {`0xF00`, `0x00000300`},
168	{`0xffff`, `0xffffffff`},
169	};
170
171	static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = {
172	{`0xC78`, `0xFC000001`}, {`0xC78`, `0xFB010001`},
173	{`0xC78`, `0xFA020001`}, {`0xC78`, `0xF9030001`},
174	{`0xC78`, `0xF8040001`}, {`0xC78`, `0xF7050001`},
175	{`0xC78`, `0xF6060001`}, {`0xC78`, `0xF5070001`},
176	{`0xC78`, `0xF4080001`}, {`0xC78`, `0xF3090001`},
177	{`0xC78`, `0xF20A0001`}, {`0xC78`, `0xF10B0001`},
178	{`0xC78`, `0xF00C0001`}, {`0xC78`, `0xEF0D0001`},
179	{`0xC78`, `0xEE0E0001`}, {`0xC78`, `0xED0F0001`},
180	{`0xC78`, `0xEC100001`}, {`0xC78`, `0xEB110001`},
181	{`0xC78`, `0xEA120001`}, {`0xC78`, `0xE9130001`},
182	{`0xC78`, `0xE8140001`}, {`0xC78`, `0xE7150001`},
183	{`0xC78`, `0xE6160001`}, {`0xC78`, `0xE5170001`},
184	{`0xC78`, `0xE4180001`}, {`0xC78`, `0xE3190001`},
185	{`0xC78`, `0xE21A0001`}, {`0xC78`, `0xE11B0001`},
186	{`0xC78`, `0xE01C0001`}, {`0xC78`, `0xC21D0001`},
187	{`0xC78`, `0xC11E0001`}, {`0xC78`, `0xC01F0001`},
188	{`0xC78`, `0xA5200001`}, {`0xC78`, `0xA4210001`},
189	{`0xC78`, `0xA3220001`}, {`0xC78`, `0xA2230001`},
190	{`0xC78`, `0xA1240001`}, {`0xC78`, `0xA0250001`},
191	{`0xC78`, `0x65260001`}, {`0xC78`, `0x64270001`},
192	{`0xC78`, `0x63280001`}, {`0xC78`, `0x62290001`},
193	{`0xC78`, `0x612A0001`}, {`0xC78`, `0x442B0001`},
194	{`0xC78`, `0x432C0001`}, {`0xC78`, `0x422D0001`},
195	{`0xC78`, `0x412E0001`}, {`0xC78`, `0x402F0001`},
196	{`0xC78`, `0x21300001`}, {`0xC78`, `0x20310001`},
197	{`0xC78`, `0x05320001`}, {`0xC78`, `0x04330001`},
198	{`0xC78`, `0x03340001`}, {`0xC78`, `0x02350001`},
199	{`0xC78`, `0x01360001`}, {`0xC78`, `0x00370001`},
200	{`0xC78`, `0x00380001`}, {`0xC78`, `0x00390001`},
201	{`0xC78`, `0x003A0001`}, {`0xC78`, `0x003B0001`},
202	{`0xC78`, `0x003C0001`}, {`0xC78`, `0x003D0001`},
203	{`0xC78`, `0x003E0001`}, {`0xC78`, `0x003F0001`},
204	{`0xC50`, `0x69553422`}, {`0xC50`, `0x69553420`},
205	{`0xffff`, `0xffffffff`}
206	};
207
208	static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = {
209	{`0x00`, `0x00030000`}, {`0x08`, `0x00008400`},
210	{`0x18`, `0x00000407`}, {`0x19`, `0x00000012`},
211	{`0x1B`, `0x00001C6C`},
212	{`0x1E`, `0x00080009`}, {`0x1F`, `0x00000880`},
213	{`0x2F`, `0x0001A060`}, {`0x3F`, `0x00028000`},
214	{`0x42`, `0x000060C0`}, {`0x57`, `0x000D0000`},
215	{`0x58`, `0x000C0160`}, {`0x67`, `0x00001552`},
216	{`0x83`, `0x00000000`}, {`0xB0`, `0x000FF9F0`},
217	{`0xB1`, `0x00022218`}, {`0xB2`, `0x00034C00`},
218	{`0xB4`, `0x0004484B`}, {`0xB5`, `0x0000112A`},
219	{`0xB6`, `0x0000053E`}, {`0xB7`, `0x00010408`},
220	{`0xB8`, `0x00010200`}, {`0xB9`, `0x00080001`},
221	{`0xBA`, `0x00040001`}, {`0xBB`, `0x00000400`},
222	{`0xBF`, `0x000C0000`}, {`0xC2`, `0x00002400`},
223	{`0xC3`, `0x00000009`}, {`0xC4`, `0x00040C91`},
224	{`0xC5`, `0x00099999`}, {`0xC6`, `0x000000A3`},
225	{`0xC7`, `0x0008F820`}, {`0xC8`, `0x00076C06`},
226	{`0xC9`, `0x00000000`}, {`0xCA`, `0x00080000`},
227	{`0xDF`, `0x00000180`}, {`0xEF`, `0x000001A0`},
228	{`0x51`, `0x000E8333`}, {`0x52`, `0x000FAC2C`},
229	{`0x53`, `0x00000103`}, {`0x56`, `0x000517F0`},
230	{`0x35`, `0x00000099`}, {`0x35`, `0x00000199`},
231	{`0x35`, `0x00000299`}, {`0x36`, `0x00000064`},
232	{`0x36`, `0x00008064`}, {`0x36`, `0x00010064`},
233	{`0x36`, `0x00018064`}, {`0x18`, `0x00000C07`},
234	{`0x5A`, `0x00048000`}, {`0x19`, `0x000739D0`},
235	{`0x34`, `0x0000ADD6`}, {`0x34`, `0x00009DD3`},
236	{`0x34`, `0x00008CF4`}, {`0x34`, `0x00007CF1`},
237	{`0x34`, `0x00006CEE`}, {`0x34`, `0x00005CEB`},
238	{`0x34`, `0x00004CCE`}, {`0x34`, `0x00003CCB`},
239	{`0x34`, `0x00002CC8`}, {`0x34`, `0x00001C4B`},
240	{`0x34`, `0x00000C48`},
241	{`0x00`, `0x00030159`}, {`0x84`, `0x00048000`},
242	{`0x86`, `0x0000002A`}, {`0x87`, `0x00000025`},
243	{`0x8E`, `0x00065540`}, {`0x8F`, `0x00088000`},
244	{`0xEF`, `0x000020A0`}, {`0x3B`, `0x000F0F00`},
245	{`0x3B`, `0x000E0B00`}, {`0x3B`, `0x000D0900`},
246	{`0x3B`, `0x000C0700`}, {`0x3B`, `0x000B0600`},
247	{`0x3B`, `0x000A0400`}, {`0x3B`, `0x00090200`},
248	{`0x3B`, `0x00080000`}, {`0x3B`, `0x0007BF00`},
249	{`0x3B`, `0x00060B00`}, {`0x3B`, `0x0005C900`},
250	{`0x3B`, `0x00040700`}, {`0x3B`, `0x00030600`},
251	{`0x3B`, `0x0002D500`}, {`0x3B`, `0x00010200`},
252	{`0x3B`, `0x0000E000`}, {`0xEF`, `0x000000A0`},
253	{`0xEF`, `0x00000010`}, {`0x3B`, `0x0000C0A8`},
254	{`0x3B`, `0x00010400`}, {`0xEF`, `0x00000000`},
255	{`0xEF`, `0x00080000`}, {`0x30`, `0x00010000`},
256	{`0x31`, `0x0000000F`}, {`0x32`, `0x00007EFE`},
257	{`0xEF`, `0x00000000`}, {`0x00`, `0x00010159`},
258	{`0x18`, `0x0000FC07`}, {`0xFE`, `0x00000000`},
259	{`0xFE`, `0x00000000`}, {`0x1F`, `0x00080003`},
260	{`0xFE`, `0x00000000`}, {`0xFE`, `0x00000000`},
261	{`0x1E`, `0x00000001`}, {`0x1F`, `0x00080000`},
262	{`0x00`, `0x00033D95`},
263	{`0xff`, `0xffffffff`}
264	};
265
266	static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = {
267	{`0x00`, `0x00030000`}, {`0x08`, `0x00008400`},
268	{`0x18`, `0x00000407`}, {`0x19`, `0x00000012`},
269	{`0x1B`, `0x00001C6C`},
270	{`0x1E`, `0x00080009`}, {`0x1F`, `0x00000880`},
271	{`0x2F`, `0x0001A060`}, {`0x3F`, `0x00028000`},
272	{`0x42`, `0x000060C0`}, {`0x57`, `0x000D0000`},
273	{`0x58`, `0x000C0160`}, {`0x67`, `0x00001552`},
274	{`0x83`, `0x00000000`}, {`0xB0`, `0x000FF9F0`},
275	{`0xB1`, `0x00022218`}, {`0xB2`, `0x00034C00`},
276	{`0xB4`, `0x0004484B`}, {`0xB5`, `0x0000112A`},
277	{`0xB6`, `0x0000053E`}, {`0xB7`, `0x00010408`},
278	{`0xB8`, `0x00010200`}, {`0xB9`, `0x00080001`},
279	{`0xBA`, `0x00040001`}, {`0xBB`, `0x00000400`},
280	{`0xBF`, `0x000C0000`}, {`0xC2`, `0x00002400`},
281	{`0xC3`, `0x00000009`}, {`0xC4`, `0x00040C91`},
282	{`0xC5`, `0x00099999`}, {`0xC6`, `0x000000A3`},
283	{`0xC7`, `0x0008F820`}, {`0xC8`, `0x00076C06`},
284	{`0xC9`, `0x00000000`}, {`0xCA`, `0x00080000`},
285	{`0xDF`, `0x00000180`}, {`0xEF`, `0x000001A0`},
286	{`0x51`, `0x000E8231`}, {`0x52`, `0x000FAC2C`},
287	{`0x53`, `0x00000141`}, {`0x56`, `0x000517F0`},
288	{`0x35`, `0x00000090`}, {`0x35`, `0x00000190`},
289	{`0x35`, `0x00000290`}, {`0x36`, `0x00001064`},
290	{`0x36`, `0x00009064`}, {`0x36`, `0x00011064`},
291	{`0x36`, `0x00019064`}, {`0x18`, `0x00000C07`},
292	{`0x5A`, `0x00048000`}, {`0x19`, `0x000739D0`},
293	{`0x34`, `0x0000ADD2`}, {`0x34`, `0x00009DD0`},
294	{`0x34`, `0x00008CF3`}, {`0x34`, `0x00007CF0`},
295	{`0x34`, `0x00006CED`}, {`0x34`, `0x00005CD2`},
296	{`0x34`, `0x00004CCF`}, {`0x34`, `0x00003CCC`},
297	{`0x34`, `0x00002CC9`}, {`0x34`, `0x00001C4C`},
298	{`0x34`, `0x00000C49`},
299	{`0x00`, `0x00030159`}, {`0x84`, `0x00048000`},
300	{`0x86`, `0x0000002A`}, {`0x87`, `0x00000025`},
301	{`0x8E`, `0x00065540`}, {`0x8F`, `0x00088000`},
302	{`0xEF`, `0x000020A0`}, {`0x3B`, `0x000F0F00`},
303	{`0x3B`, `0x000E0B00`}, {`0x3B`, `0x000D0900`},
304	{`0x3B`, `0x000C0700`}, {`0x3B`, `0x000B0600`},
305	{`0x3B`, `0x000A0400`}, {`0x3B`, `0x00090200`},
306	{`0x3B`, `0x00080000`}, {`0x3B`, `0x0007BF00`},
307	{`0x3B`, `0x00060B00`}, {`0x3B`, `0x0005C900`},
308	{`0x3B`, `0x00040700`}, {`0x3B`, `0x00030600`},
309	{`0x3B`, `0x0002D500`}, {`0x3B`, `0x00010200`},
310	{`0x3B`, `0x0000E000`}, {`0xEF`, `0x000000A0`},
311	{`0xEF`, `0x00000010`}, {`0x3B`, `0x0000C0A8`},
312	{`0x3B`, `0x00010400`}, {`0xEF`, `0x00000000`},
313	{`0xEF`, `0x00080000`}, {`0x30`, `0x00010000`},
314	{`0x31`, `0x0000000F`}, {`0x32`, `0x00007EFE`},
315	{`0xEF`, `0x00000000`}, {`0x00`, `0x00010159`},
316	{`0x18`, `0x0000FC07`}, {`0xFE`, `0x00000000`},
317	{`0xFE`, `0x00000000`}, {`0x1F`, `0x00080003`},
318	{`0xFE`, `0x00000000`}, {`0xFE`, `0x00000000`},
319	{`0x1E`, `0x00000001`}, {`0x1F`, `0x00080000`},
320	{`0x00`, `0x00033D95`},
321	{`0xff`, `0xffffffff`}
322	};
323
324	static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv)
325	{
326	struct device *dev = &priv->udev->dev;
327	u32 sys_cfg, vendor;
328	int ret = `0`;
329
330	strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name));
331	priv->rtl_chip = RTL8188F;
332	priv->rf_paths = `1`;
333	priv->rx_paths = `1`;
334	priv->tx_paths = `1`;
335	priv->has_wifi = `1`;
336
337	sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
338	priv->chip_cut = u32_get_bits(v: sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
339	if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
340	dev_info(dev, "Unsupported test chip\n");
341	ret = -ENOTSUPP;
342	goto out;
343	}
344
345	vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK;
346	rtl8xxxu_identify_vendor_2bits(priv, vendor);
347
348	ret = rtl8xxxu_config_endpoints_no_sie(priv);
349
350	out:
351	return ret;
352	}
353
354	void rtl8188f_channel_to_group(int channel, int group, int* *cck_group)
355	{
356	if (channel < `3`)
357	*group = `0`;
358	else if (channel < `6`)
359	*group = `1`;
360	else if (channel < `9`)
361	*group = `2`;
362	else if (channel < `12`)
363	*group = `3`;
364	else
365	*group = `4`;
366
367	if (channel == `14`)
368	*cck_group = `5`;
369	else
370	cck_group = group;
371	}
372
373	void
374	rtl8188f_set_tx_power(struct rtl8xxxu_priv priv, int* channel, bool ht40)
375	{
376	u32 val32, ofdm, mcs;
377	u8 cck, ofdmbase, mcsbase;
378	int group, cck_group;
379
380	rtl8188f_channel_to_group(channel, group: &group, cck_group: &cck_group);
381
382	cck = priv->cck_tx_power_index_A[cck_group];
383
384	val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
385	val32 &= `0xffff00ff`;
386	val32 \|= (cck << `8`);
387	rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val: val32);
388
389	val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
390	val32 &= `0xff`;
391	val32 \|= ((cck << `8`) \| (cck << `16`) \| (cck << `24`));
392	rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val: val32);
393
394	ofdmbase = priv->ht40_1s_tx_power_index_A[group];
395	ofdmbase += priv->ofdm_tx_power_diff[`0`].a;
396	ofdm = ofdmbase \| ofdmbase << `8` \| ofdmbase << `16` \| ofdmbase << `24`;
397
398	rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, val: ofdm);
399	rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, val: ofdm);
400
401	mcsbase = priv->ht40_1s_tx_power_index_A[group];
402	if (ht40)
403	/ This diff is always 0 - not used in 8188FU. /
404	mcsbase += priv->ht40_tx_power_diff[`0`].a;
405	else
406	mcsbase += priv->ht20_tx_power_diff[`0`].a;
407	mcs = mcsbase \| mcsbase << `8` \| mcsbase << `16` \| mcsbase << `24`;
408
409	rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, val: mcs);
410	rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, val: mcs);
411	rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, val: mcs);
412	rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, val: mcs);
413	}
414
415	/ A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. /
416	static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel)
417	{
418	static const u32 frequencies[`14` + `1`] = {
419	[`5`] = `0xFCCD`,
420	[`6`] = `0xFC4D`,
421	[`7`] = `0xFFCD`,
422	[`8`] = `0xFF4D`,
423	[`11`] = `0xFDCD`,
424	[`13`] = `0xFCCD`,
425	[`14`] = `0xFF9A`
426	};
427
428	static const u32 reg_d40[`14` + `1`] = {
429	[`5`] = `0x06000000`,
430	[`6`] = `0x00000600`,
431	[`13`] = `0x06000000`
432	};
433
434	static const u32 reg_d44[`14` + `1`] = {
435	[`11`] = `0x04000000`
436	};
437
438	static const u32 reg_d4c[`14` + `1`] = {
439	[`7`] = `0x06000000`,
440	[`8`] = `0x00000380`,
441	[`14`] = `0x00180000`
442	};
443
444	const u8 threshold = `0x16`;
445	bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = `0`, sw_ctrl_s1 = `0`;
446	u32 val32, initial_gain, reg948;
447
448	val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH);
449	val32 \|= GENMASK(`28`, `24`);
450	rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val: val32);
451
452	/ enable notch filter /
453	val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH);
454	val32 \|= BIT(`9`);
455	rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val: val32);
456
457	if (channel <= `14` && frequencies[channel] > `0`) {
458	reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
459	hw_ctrl = reg948 & BIT(`6`);
460	sw_ctrl = !hw_ctrl;
461
462	if (hw_ctrl) {
463	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
464	val32 &= GENMASK(`5`, `3`);
465	hw_ctrl_s1 = val32 == BIT(`3`);
466	} else if (sw_ctrl) {
467	sw_ctrl_s1 = !(reg948 & BIT(`9`));
468	}
469
470	if (hw_ctrl_s1 \|\| sw_ctrl_s1) {
471	initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
472
473	/ Disable CCK block /
474	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
475	val32 &= ~FPGA_RF_MODE_CCK;
476	rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32);
477
478	val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK;
479	val32 \|= `0x30`;
480	rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val: val32);
481
482	/ disable 3-wire /
483	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: `0xccf000c0`);
484
485	/ Setup PSD /
486	rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, val: frequencies[channel]);
487
488	/ Start PSD /
489	rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, val: `0x400000` \| frequencies[channel]);
490
491	msleep(msecs: `30`);
492
493	do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold;
494
495	/ turn off PSD /
496	rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, val: frequencies[channel]);
497
498	/ enable 3-wire /
499	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: `0xccc000c0`);
500
501	/ Enable CCK block /
502	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
503	val32 \|= FPGA_RF_MODE_CCK;
504	rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32);
505
506	rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val: initial_gain);
507
508	if (do_notch) {
509	rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, val: reg_d40[channel]);
510	rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, val: reg_d44[channel]);
511	rtl8xxxu_write32(priv, addr: `0xd48`, val: `0x0`);
512	rtl8xxxu_write32(priv, addr: `0xd4c`, val: reg_d4c[channel]);
513
514	/ enable CSI mask /
515	val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
516	val32 \|= BIT(`28`);
517	rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val: val32);
518
519	return;
520	}
521	}
522	}
523
524	/ disable CSI mask function /
525	val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
526	val32 &= ~BIT(`28`);
527	rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val: val32);
528	}
529
530	static void rtl8188fu_config_channel(struct ieee80211_hw *hw)
531	{
532	struct rtl8xxxu_priv *priv = hw->priv;
533	u32 val32;
534	u8 channel, subchannel;
535	bool sec_ch_above;
536
537	channel = (u8)hw->conf.chandef.chan->hw_value;
538
539	/ Set channel /
540	val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG);
541	val32 &= ~MODE_AG_CHANNEL_MASK;
542	val32 \|= channel;
543	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG, data: val32);
544
545	/ Spur calibration /
546	rtl8188f_spur_calibration(priv, channel);
547
548	/ Set bandwidth mode /
549	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
550	val32 &= ~FPGA_RF_MODE;
551	val32 \|= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40;
552	rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32);
553
554	val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
555	val32 &= ~FPGA_RF_MODE;
556	val32 \|= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40;
557	rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val: val32);
558
559	/ RXADC CLK /
560	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
561	val32 \|= GENMASK(`10`, `8`);
562	rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32);
563
564	/ TXDAC CLK /
565	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
566	val32 \|= BIT(`14`) \| BIT(`12`);
567	val32 &= ~BIT(`13`);
568	rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val: val32);
569
570	/ small BW /
571	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
572	val32 &= ~GENMASK(`31`, `30`);
573	rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val: val32);
574
575	/ adc buffer clk /
576	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
577	val32 &= ~BIT(`29`);
578	val32 \|= BIT(`28`);
579	rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val: val32);
580
581	/ adc buffer clk /
582	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE);
583	val32 &= ~BIT(`29`);
584	val32 \|= BIT(`28`);
585	rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val: val32);
586
587	val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
588	val32 &= ~BIT(`19`);
589	rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val: val32);
590
591	val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
592	val32 &= ~GENMASK(`23`, `20`);
593	val32 \|= BIT(`21`);
594	if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 \|\|
595	hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT)
596	val32 \|= BIT(`20`);
597	else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
598	val32 \|= BIT(`22`);
599	rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val: val32);
600
601	if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) {
602	if (hw->conf.chandef.center_freq1 >
603	hw->conf.chandef.chan->center_freq) {
604	sec_ch_above = `1`;
605	channel += `2`;
606	} else {
607	sec_ch_above = `0`;
608	channel -= `2`;
609	}
610
611	/ Set Control channel to upper or lower. /
612	val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
613	val32 &= ~CCK0_SIDEBAND;
614	if (!sec_ch_above)
615	val32 \|= CCK0_SIDEBAND;
616	rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val: val32);
617
618	val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL);
619	val32 &= ~GENMASK(`3`, `0`);
620	if (sec_ch_above)
621	subchannel = `2`;
622	else
623	subchannel = `1`;
624	val32 \|= subchannel;
625	rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val: val32);
626
627	val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
628	val32 &= ~RSR_RSC_BANDWIDTH_40M;
629	rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val: val32);
630	}
631
632	/ RF TRX_BW /
633	val32 = channel;
634	if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 \|\|
635	hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT)
636	val32 \|= MODE_AG_BW_20MHZ_8723B;
637	else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
638	val32 \|= MODE_AG_BW_40MHZ_8723B;
639	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG, data: val32);
640
641	/ FILTER BW&RC Corner (ACPR) /
642	if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 \|\|
643	hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT)
644	val32 = `0x00065`;
645	else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
646	val32 = `0x00025`;
647	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RXG_MIX_SWBW, data: val32);
648
649	if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 \|\|
650	hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT)
651	val32 = `0x0`;
652	else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
653	val32 = `0x01000`;
654	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RX_BB2, data: val32);
655
656	/ RC Corner /
657	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x00140`);
658	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RX_G2, data: `0x01c6c`);
659	}
660
661	static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv)
662	{
663	u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = `6`;
664	u32 agg_rx, val32;
665
666	/ TX aggregation /
667	val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F);
668	val32 &= ~(`0xf` << `4`);
669	val32 \|= usb_tx_agg_desc_num << `4`;
670	rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val: val32);
671	rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, val: usb_tx_agg_desc_num << `1`);
672
673	/ RX aggregation /
674	agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
675	agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
676
677	agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
678	agg_rx &= ~RXDMA_USB_AGG_ENABLE;
679	agg_rx &= ~`0xFF0F`; / reset agg size and timeout /
680
681	rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
682	rxdma_mode &= ~BIT(`1`);
683
684	rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, val: agg_ctrl);
685	rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, val: agg_rx);
686	rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val: rxdma_mode);
687	}
688
689	static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv)
690	{
691	u32 val32;
692
693	/ Time duration for NHM unit: 4us, 0xc350=200ms /
694	rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + `2`, val: `0xc350`);
695	rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + `2`, val: `0xffff`);
696	rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, val: `0xffffff50`);
697	rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, val: `0xffffffff`);
698
699	/ TH8 /
700	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
701	val32 \|= `0xff`;
702	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
703
704	/ Enable CCK /
705	val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
706	val32 &= ~(BIT(`8`) \| BIT(`9`) \| BIT(`10`));
707	val32 \|= BIT(`8`);
708	rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val: val32);
709
710	/ Max power amongst all RX antennas /
711	val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
712	val32 \|= BIT(`7`);
713	rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val: val32);
714	}
715
716	static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv)
717	{
718	struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu;
719
720	if (efuse->rtl_id != cpu_to_le16(`0x8129`))
721	return -EINVAL;
722
723	ether_addr_copy(dst: priv->mac_addr, src: efuse->mac_addr);
724
725	memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
726	sizeof(efuse->tx_power_index_A.cck_base));
727
728	memcpy(priv->ht40_1s_tx_power_index_A,
729	efuse->tx_power_index_A.ht40_base,
730	sizeof(efuse->tx_power_index_A.ht40_base));
731
732	priv->ofdm_tx_power_diff[`0`].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
733	priv->ht20_tx_power_diff[`0`].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
734
735	priv->default_crystal_cap = efuse->xtal_k & `0x3f`;
736
737	return `0`;
738	}
739
740	static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv)
741	{
742	const char *fw_name;
743	int ret;
744
745	fw_name = "rtlwifi/rtl8188fufw.bin";
746
747	ret = rtl8xxxu_load_firmware(priv, fw_name);
748
749	return ret;
750	}
751
752	static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv)
753	{
754	u8 val8;
755	u16 val16;
756
757	/ Enable BB and RF /
758	val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
759	val16 \|= SYS_FUNC_BB_GLB_RSTN \| SYS_FUNC_BBRSTB \| SYS_FUNC_DIO_RF;
760	rtl8xxxu_write16(priv, REG_SYS_FUNC, val: val16);
761
762	/*
763	* Per vendor driver, run power sequence before init of RF
764	*/
765	val8 = RF_ENABLE \| RF_RSTB \| RF_SDMRSTB;
766	rtl8xxxu_write8(priv, REG_RF_CTRL, val: val8);
767
768	usleep_range(min: `10`, max: `20`);
769
770	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_IQADJ_G1, data: `0x780`);
771
772	val8 = SYS_FUNC_BB_GLB_RSTN \| SYS_FUNC_BBRSTB \| SYS_FUNC_USBA \| SYS_FUNC_USBD;
773	rtl8xxxu_write8(priv, REG_SYS_FUNC, val: val8);
774
775	rtl8xxxu_init_phy_regs(priv, array: rtl8188fu_phy_init_table);
776	rtl8xxxu_init_phy_regs(priv, array: rtl8188f_agc_table);
777	}
778
779	static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv)
780	{
781	int ret;
782
783	if (priv->chip_cut == `1`)
784	ret = rtl8xxxu_init_phy_rf(priv, table: rtl8188fu_cut_b_radioa_init_table, path: RF_A);
785	else
786	ret = rtl8xxxu_init_phy_rf(priv, table: rtl8188fu_radioa_init_table, path: RF_A);
787
788	return ret;
789	}
790
791	void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
792	{
793	u32 val32;
794	u32 rf_amode, lstf;
795	int i;
796
797	/ Check continuous TX and Packet TX /
798	lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
799
800	if (lstf & OFDM_LSTF_MASK) {
801	/ Disable all continuous TX /
802	val32 = lstf & ~OFDM_LSTF_MASK;
803	rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val: val32);
804	} else {
805	/ Deal with Packet TX case /
806	/ block all queues /
807	rtl8xxxu_write8(priv, REG_TXPAUSE, val: `0xff`);
808	}
809
810	/ Read original RF mode Path A /
811	rf_amode = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG);
812
813	/ Start LC calibration /
814	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG, data: rf_amode \| `0x08000`);
815
816	for (i = `0`; i < `100`; i++) {
817	if ((rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG) & `0x08000`) == `0`)
818	break;
819	msleep(msecs: `10`);
820	}
821
822	if (i == `100`)
823	dev_warn(&priv->udev->dev, "LC calibration timed out.\n");
824
825	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG, data: rf_amode);
826
827	/ Restore original parameters /
828	if (lstf & OFDM_LSTF_MASK)
829	rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val: lstf);
830	else / Deal with Packet TX case /
831	rtl8xxxu_write8(priv, REG_TXPAUSE, val: `0x00`);
832	}
833
834	static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv priv, u32 lok_result)
835	{
836	u32 reg_eac, reg_e94, reg_e9c, val32;
837	int result = `0`;
838
839	/*
840	* Leave IQK mode
841	*/
842	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
843	val32 &= `0x000000ff`;
844	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
845
846	/*
847	* Enable path A PA in TX IQK mode
848	*/
849	val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT);
850	val32 \|= `0x80000`;
851	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT, data: val32);
852	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RCK_OS, data: `0x20000`);
853	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G1, data: `0x0000f`);
854	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G2, data: `0x07ff7`);
855
856	/ PA,PAD gain adjust /
857	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x980`);
858	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_PAD_TXG, data: `0x5102a`);
859
860	/ enter IQK mode /
861	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
862	val32 &= `0x000000ff`;
863	val32 \|= `0x80800000`;
864	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
865
866	/ path-A IQK setting /
867	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: `0x18008c1c`);
868	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: `0x38008c1c`);
869
870	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: `0x821403ff`);
871	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: `0x28160000`);
872
873	/ LO calibration setting /
874	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: `0x00462911`);
875
876	/ One shot, path A LOK & IQK /
877	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: `0xf9000000`);
878	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: `0xf8000000`);
879
880	mdelay(`25`);
881
882	/*
883	* Leave IQK mode
884	*/
885	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
886	val32 &= `0x000000ff`;
887	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
888
889	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x180`);
890
891	/ save LOK result /
892	*lok_result = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_TXM_IDAC);
893
894	/ Check failed /
895	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
896	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
897	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
898
899	if (!(reg_eac & BIT(`28`)) &&
900	((reg_e94 & `0x03ff0000`) != `0x01420000`) &&
901	((reg_e9c & `0x03ff0000`) != `0x00420000`))
902	result \|= `0x01`;
903
904	return result;
905	}
906
907	static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
908	{
909	u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
910	int result = `0`;
911
912	/*
913	* Leave IQK mode
914	*/
915	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
916	val32 &= `0x000000ff`;
917	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
918
919	/*
920	* Enable path A PA in TX IQK mode
921	*/
922	val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT);
923	val32 \|= `0x80000`;
924	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT, data: val32);
925	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RCK_OS, data: `0x30000`);
926	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G1, data: `0x0000f`);
927	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G2, data: `0xf1173`);
928
929	/ PA,PAD gain adjust /
930	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x980`);
931	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_PAD_TXG, data: `0x5102a`);
932
933	/*
934	* Enter IQK mode
935	*/
936	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
937	val32 &= `0x000000ff`;
938	val32 \|= `0x80800000`;
939	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
940
941	/*
942	* Tx IQK setting
943	*/
944	rtl8xxxu_write32(priv, REG_TX_IQK, val: `0x01007c00`);
945	rtl8xxxu_write32(priv, REG_RX_IQK, val: `0x01004800`);
946
947	/ path-A IQK setting /
948	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: `0x10008c1c`);
949	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: `0x30008c1c`);
950
951	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: `0x82160fff`);
952	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: `0x28160000`);
953
954	/ LO calibration setting /
955	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: `0x00462911`);
956
957	/ One shot, path A LOK & IQK /
958	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: `0xf9000000`);
959	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: `0xf8000000`);
960
961	mdelay(`25`);
962
963	/*
964	* Leave IQK mode
965	*/
966	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
967	val32 &= `0x000000ff`;
968	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
969
970	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x180`);
971
972	/ Check failed /
973	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
974	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
975	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
976
977	if (!(reg_eac & BIT(`28`)) &&
978	((reg_e94 & `0x03ff0000`) != `0x01420000`) &&
979	((reg_e9c & `0x03ff0000`) != `0x00420000`))
980	result \|= `0x01`;
981	else / If TX not OK, ignore RX /
982	goto out;
983
984	val32 = `0x80007c00` \| (reg_e94 & `0x3ff0000`) \|
985	((reg_e9c & `0x3ff0000`) >> `16`);
986	rtl8xxxu_write32(priv, REG_TX_IQK, val: val32);
987
988	/*
989	* Modify RX IQK mode table
990	*/
991	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
992	val32 &= `0x000000ff`;
993	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
994
995	val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT);
996	val32 \|= `0x80000`;
997	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_WE_LUT, data: val32);
998	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_RCK_OS, data: `0x30000`);
999	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G1, data: `0x0000f`);
1000	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXPA_G2, data: `0xf7ff2`);
1001
1002	/*
1003	* PA, PAD setting
1004	*/
1005	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x980`);
1006	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_PAD_TXG, data: `0x51000`);
1007
1008	/*
1009	* Enter IQK mode
1010	*/
1011	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1012	val32 &= `0x000000ff`;
1013	val32 \|= `0x80800000`;
1014	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
1015
1016	/*
1017	* RX IQK setting
1018	*/
1019	rtl8xxxu_write32(priv, REG_RX_IQK, val: `0x01004800`);
1020
1021	/ path-A IQK setting /
1022	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: `0x30008c1c`);
1023	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: `0x10008c1c`);
1024
1025	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: `0x82160000`);
1026	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: `0x281613ff`);
1027
1028	/ LO calibration setting /
1029	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: `0x0046a911`);
1030
1031	/ One shot, path A LOK & IQK /
1032	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: `0xf9000000`);
1033	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: `0xf8000000`);
1034
1035	mdelay(`25`);
1036
1037	/*
1038	* Leave IQK mode
1039	*/
1040	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1041	val32 &= `0x000000ff`;
1042	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
1043
1044	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: `0x180`);
1045
1046	/ reload LOK value /
1047	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_TXM_IDAC, data: lok_result);
1048
1049	/ Check failed /
1050	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1051	reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
1052
1053	if (!(reg_eac & BIT(`27`)) &&
1054	((reg_ea4 & `0x03ff0000`) != `0x01320000`) &&
1055	((reg_eac & `0x03ff0000`) != `0x00360000`))
1056	result \|= `0x02`;
1057
1058	out:
1059	return result;
1060	}
1061
1062	static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1063	int result[][`8`], int t)
1064	{
1065	struct device *dev = &priv->udev->dev;
1066	u32 i, val32, rx_initial_gain, lok_result;
1067	u32 path_sel_bb, path_sel_rf;
1068	int path_a_ok;
1069	int retry = `2`;
1070	static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1071	REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1072	REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1073	REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1074	REG_TX_OFDM_BBON, REG_TX_TO_RX,
1075	REG_TX_TO_TX, REG_RX_CCK,
1076	REG_RX_OFDM, REG_RX_WAIT_RIFS,
1077	REG_RX_TO_RX, REG_STANDBY,
1078	REG_SLEEP, REG_PMPD_ANAEN
1079	};
1080	static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1081	REG_TXPAUSE, REG_BEACON_CTRL,
1082	REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1083	};
1084	static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1085	REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1086	REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1087	REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1088	REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
1089	};
1090
1091	/*
1092	* Note: IQ calibration must be performed after loading
1093	* PHY_REG.txt , and radio_a, radio_b.txt
1094	*/
1095
1096	rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1097
1098	if (t == `0`) {
1099	/ Save ADDA parameters, turn Path A ADDA on /
1100	rtl8xxxu_save_regs(priv, regs: adda_regs, backup: priv->adda_backup,
1101	RTL8XXXU_ADDA_REGS);
1102	rtl8xxxu_save_mac_regs(priv, reg: iqk_mac_regs, backup: priv->mac_backup);
1103	rtl8xxxu_save_regs(priv, regs: iqk_bb_regs,
1104	backup: priv->bb_backup, RTL8XXXU_BB_REGS);
1105	}
1106
1107	rtl8xxxu_path_adda_on(priv, regs: adda_regs, path_a_on: true);
1108
1109	if (t == `0`) {
1110	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
1111	priv->pi_enabled = u32_get_bits(v: val32, FPGA0_HSSI_PARM1_PI);
1112	}
1113
1114	/ save RF path /
1115	path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1116	path_sel_rf = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_S0S1);
1117
1118	/ BB setting /
1119	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: `0x03a05600`);
1120	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: `0x000800e4`);
1121	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: `0x25204000`);
1122
1123	/ MAC settings /
1124	val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL);
1125	val32 \|= `0x00ff0000`;
1126	rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val: val32);
1127
1128	/ IQ calibration setting /
1129	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1130	val32 &= `0xff`;
1131	val32 \|= `0x80800000`;
1132	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
1133	rtl8xxxu_write32(priv, REG_TX_IQK, val: `0x01007c00`);
1134	rtl8xxxu_write32(priv, REG_RX_IQK, val: `0x01004800`);
1135
1136	for (i = `0`; i < retry; i++) {
1137	path_a_ok = rtl8188fu_iqk_path_a(priv, lok_result: &lok_result);
1138	if (path_a_ok == `0x01`) {
1139	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1140	val32 &= `0xff`;
1141	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
1142
1143	val32 = rtl8xxxu_read32(priv,
1144	REG_TX_POWER_BEFORE_IQK_A);
1145	result[t][`0`] = (val32 >> `16`) & `0x3ff`;
1146
1147	val32 = rtl8xxxu_read32(priv,
1148	REG_TX_POWER_AFTER_IQK_A);
1149	result[t][`1`] = (val32 >> `16`) & `0x3ff`;
1150	break;
1151	}
1152	}
1153
1154	for (i = `0`; i < retry; i++) {
1155	path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result);
1156	if (path_a_ok == `0x03`) {
1157	val32 = rtl8xxxu_read32(priv,
1158	REG_RX_POWER_BEFORE_IQK_A_2);
1159	result[t][`2`] = (val32 >> `16`) & `0x3ff`;
1160
1161	val32 = rtl8xxxu_read32(priv,
1162	REG_RX_POWER_AFTER_IQK_A_2);
1163	result[t][`3`] = (val32 >> `16`) & `0x3ff`;
1164	break;
1165	}
1166	}
1167
1168	if (!path_a_ok)
1169	dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
1170
1171	/ Back to BB mode, load original value /
1172	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1173	val32 &= `0xff`;
1174	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val: val32);
1175
1176	if (t == `0`)
1177	return;
1178
1179	if (!priv->pi_enabled) {
1180	/*
1181	* Switch back BB to SI mode after finishing
1182	* IQ Calibration
1183	*/
1184	val32 = `0x01000000`;
1185	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: val32);
1186	rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val: val32);
1187	}
1188
1189	/ Reload ADDA power saving parameters /
1190	rtl8xxxu_restore_regs(priv, regs: adda_regs, backup: priv->adda_backup,
1191	RTL8XXXU_ADDA_REGS);
1192
1193	/ Reload MAC parameters /
1194	rtl8xxxu_restore_mac_regs(priv, reg: iqk_mac_regs, backup: priv->mac_backup);
1195
1196	/ Reload BB parameters /
1197	rtl8xxxu_restore_regs(priv, regs: iqk_bb_regs,
1198	backup: priv->bb_backup, RTL8XXXU_BB_REGS);
1199
1200	/ Reload RF path /
1201	rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, val: path_sel_bb);
1202	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_S0S1, data: path_sel_rf);
1203
1204	/ Restore RX initial gain /
1205	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1206	val32 &= `0xffffff00`;
1207	val32 \|= `0x50`;
1208	rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val: val32);
1209	val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1210	val32 &= `0xffffff00`;
1211	val32 \|= rx_initial_gain & `0xff`;
1212	rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val: val32);
1213
1214	/ Load 0xe30 IQC default value /
1215	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: `0x01008c00`);
1216	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: `0x01008c00`);
1217	}
1218
1219	static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1220	{
1221	struct device *dev = &priv->udev->dev;
1222	int result[`4`][`8`]; / last is final result /
1223	int i, candidate;
1224	bool path_a_ok;
1225	u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1226	u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1227	s32 reg_tmp = `0`;
1228	bool simu;
1229	u32 path_sel_bb, path_sel_rf;
1230
1231	/ Save RF path /
1232	path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1233	path_sel_rf = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_S0S1);
1234
1235	memset(result, `0`, sizeof(result));
1236	candidate = -`1`;
1237
1238	path_a_ok = false;
1239
1240	for (i = `0`; i < `3`; i++) {
1241	rtl8188fu_phy_iqcalibrate(priv, result, t: i);
1242
1243	if (i == `1`) {
1244	simu = rtl8xxxu_gen2_simularity_compare(priv, result, c1: `0`, c2: `1`);
1245	if (simu) {
1246	candidate = `0`;
1247	break;
1248	}
1249	}
1250
1251	if (i == `2`) {
1252	simu = rtl8xxxu_gen2_simularity_compare(priv, result, c1: `0`, c2: `2`);
1253	if (simu) {
1254	candidate = `0`;
1255	break;
1256	}
1257
1258	simu = rtl8xxxu_gen2_simularity_compare(priv, result, c1: `1`, c2: `2`);
1259	if (simu) {
1260	candidate = `1`;
1261	} else {
1262	for (i = `0`; i < `8`; i++)
1263	reg_tmp += result[`3`][i];
1264
1265	if (reg_tmp)
1266	candidate = `3`;
1267	else
1268	candidate = -`1`;
1269	}
1270	}
1271	}
1272
1273	for (i = `0`; i < `4`; i++) {
1274	reg_e94 = result[i][`0`];
1275	reg_e9c = result[i][`1`];
1276	reg_ea4 = result[i][`2`];
1277	reg_eac = result[i][`3`];
1278	reg_eb4 = result[i][`4`];
1279	reg_ebc = result[i][`5`];
1280	reg_ec4 = result[i][`6`];
1281	reg_ecc = result[i][`7`];
1282	}
1283
1284	if (candidate >= `0`) {
1285	reg_e94 = result[candidate][`0`];
1286	priv->rege94 = reg_e94;
1287	reg_e9c = result[candidate][`1`];
1288	priv->rege9c = reg_e9c;
1289	reg_ea4 = result[candidate][`2`];
1290	reg_eac = result[candidate][`3`];
1291	reg_eb4 = result[candidate][`4`];
1292	priv->regeb4 = reg_eb4;
1293	reg_ebc = result[candidate][`5`];
1294	priv->regebc = reg_ebc;
1295	reg_ec4 = result[candidate][`6`];
1296	reg_ecc = result[candidate][`7`];
1297	dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1298	dev_dbg(dev,
1299	"%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1300	__func__, reg_e94, reg_e9c,
1301	reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1302	path_a_ok = true;
1303	} else {
1304	reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = `0x100`;
1305	reg_e9c = reg_ebc = priv->rege9c = priv->regebc = `0x0`;
1306	}
1307
1308	if (reg_e94 && candidate >= `0`)
1309	rtl8xxxu_fill_iqk_matrix_a(priv, iqk_ok: path_a_ok, result,
1310	candidate, tx_only: (reg_ea4 == `0`));
1311
1312	rtl8xxxu_save_regs(priv, regs: rtl8xxxu_iqk_phy_iq_bb_reg,
1313	backup: priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1314
1315	rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, val: path_sel_bb);
1316	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_S0S1, data: path_sel_rf);
1317	}
1318
1319	static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv)
1320	{
1321	u16 val8;
1322
1323	/ 0x04[12:11] = 2b'01enable WL suspend /
1324	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1325	val8 &= ~((APS_FSMCO_PCIE \| APS_FSMCO_HW_SUSPEND) >> `8`);
1326	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1327
1328	/ 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode /
1329	val8 = rtl8xxxu_read8(priv, addr: `0xc4`);
1330	val8 &= ~BIT(`4`);
1331	rtl8xxxu_write8(priv, addr: `0xc4`, val: val8);
1332	}
1333
1334	static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv)
1335	{
1336	u8 val8;
1337	u32 val32;
1338	int count, ret = `0`;
1339
1340	/ Disable SW LPS /
1341	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1342	val8 &= ~(APS_FSMCO_SW_LPS >> `8`);
1343	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1344
1345	/ wait till 0x04[17] = 1 power ready /
1346	for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1347	val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1348	if (val32 & BIT(`17`))
1349	break;
1350
1351	udelay(`10`);
1352	}
1353
1354	if (!count) {
1355	ret = -EBUSY;
1356	goto exit;
1357	}
1358
1359	/ Disable HWPDN /
1360	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1361	val8 &= ~(APS_FSMCO_HW_POWERDOWN >> `8`);
1362	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1363
1364	/ Disable WL suspend /
1365	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1366	val8 &= ~(APS_FSMCO_HW_SUSPEND >> `8`);
1367	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1368
1369	/ set, then poll until 0 /
1370	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1371	val8 \|= APS_FSMCO_MAC_ENABLE >> `8`;
1372	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1373
1374	for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1375	val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1376	if ((val32 & APS_FSMCO_MAC_ENABLE) == `0`) {
1377	ret = `0`;
1378	break;
1379	}
1380	udelay(`10`);
1381	}
1382
1383	if (!count) {
1384	ret = -EBUSY;
1385	goto exit;
1386	}
1387
1388	/ 0x27<=35 to reduce RF noise /
1389	val8 = rtl8xxxu_write8(priv, addr: `0x27`, val: `0x35`);
1390	exit:
1391	return ret;
1392	}
1393
1394	static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv)
1395	{
1396	u8 val8;
1397	u32 val32;
1398	int count, ret = `0`;
1399
1400	/ Turn off RF /
1401	rtl8xxxu_write8(priv, REG_RF_CTRL, val: `0`);
1402
1403	/ 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] /
1404	val8 = rtl8xxxu_read8(priv, addr: `0x4e`);
1405	val8 &= ~BIT(`7`);
1406	rtl8xxxu_write8(priv, addr: `0x4e`, val: val8);
1407
1408	/ 0x27 <= 34, xtal_qsel = 0 to xtal bring up /
1409	rtl8xxxu_write8(priv, addr: `0x27`, val: `0x34`);
1410
1411	/ 0x04[9] = 1 turn off MAC by HW state machine /
1412	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1413	val8 \|= APS_FSMCO_MAC_OFF >> `8`;
1414	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1415
1416	for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1417	val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1418	if ((val32 & APS_FSMCO_MAC_OFF) == `0`) {
1419	ret = `0`;
1420	break;
1421	}
1422	udelay(`10`);
1423	}
1424
1425	if (!count) {
1426	ret = -EBUSY;
1427	goto exit;
1428	}
1429
1430	exit:
1431	return ret;
1432	}
1433
1434	static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv)
1435	{
1436	u8 val8;
1437
1438	/ 0x04[12:11] = 2b'01 enable WL suspend /
1439	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + `1`);
1440	val8 &= ~((APS_FSMCO_PCIE \| APS_FSMCO_HW_SUSPEND) >> `8`);
1441	val8 \|= APS_FSMCO_HW_SUSPEND >> `8`;
1442	rtl8xxxu_write8(priv, REG_APS_FSMCO + `1`, val: val8);
1443
1444	/ 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode /
1445	val8 = rtl8xxxu_read8(priv, addr: `0xc4`);
1446	val8 \|= BIT(`4`);
1447	rtl8xxxu_write8(priv, addr: `0xc4`, val: val8);
1448
1449	return `0`;
1450	}
1451
1452	static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv)
1453	{
1454	struct device *dev = &priv->udev->dev;
1455	u8 val8;
1456	u16 val16;
1457	u32 val32;
1458	int retry, retval;
1459
1460	/ set RPWM IMR /
1461	val8 = rtl8xxxu_read8(priv, REG_FTIMR + `1`);
1462	val8 \|= IMR0_CPWM >> `8`;
1463	rtl8xxxu_write8(priv, REG_FTIMR + `1`, val: val8);
1464
1465	/ Tx Pause /
1466	rtl8xxxu_write8(priv, REG_TXPAUSE, val: `0xff`);
1467
1468	retry = `100`;
1469	retval = -EBUSY;
1470
1471	/*
1472	* Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending.
1473	*/
1474	do {
1475	val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1476	if (!val32) {
1477	retval = `0`;
1478	break;
1479	}
1480	} while (retry--);
1481
1482	if (!retry) {
1483	dev_warn(dev, "Failed to flush TX queue\n");
1484	retval = -EBUSY;
1485	goto out;
1486	}
1487
1488	/ Disable CCK and OFDM, clock gated /
1489	val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1490	val8 &= ~SYS_FUNC_BBRSTB;
1491	rtl8xxxu_write8(priv, REG_SYS_FUNC, val: val8);
1492
1493	udelay(`2`);
1494
1495	/ Whole BB is reset /
1496	val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1497	val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1498	rtl8xxxu_write8(priv, REG_SYS_FUNC, val: val8);
1499
1500	/ Reset MAC TRX /
1501	val16 = rtl8xxxu_read16(priv, REG_CR);
1502	val16 \|= `0x3f`;
1503	val16 &= ~(CR_MAC_TX_ENABLE \| CR_MAC_RX_ENABLE \| CR_SECURITY_ENABLE);
1504	rtl8xxxu_write16(priv, REG_CR, val: val16);
1505
1506	/ Respond TxOK to scheduler /
1507	val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1508	val8 \|= DUAL_TSF_TX_OK;
1509	rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val: val8);
1510
1511	out:
1512	return retval;
1513	}
1514
1515	static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv)
1516	{
1517	u16 val16;
1518	int ret;
1519
1520	rtl8188f_disabled_to_emu(priv);
1521
1522	ret = rtl8188f_emu_to_active(priv);
1523	if (ret)
1524	goto exit;
1525
1526	rtl8xxxu_write8(priv, REG_CR, val: `0`);
1527
1528	val16 = rtl8xxxu_read16(priv, REG_CR);
1529
1530	val16 \|= (CR_HCI_TXDMA_ENABLE \| CR_HCI_RXDMA_ENABLE \|
1531	CR_TXDMA_ENABLE \| CR_RXDMA_ENABLE \|
1532	CR_PROTOCOL_ENABLE \| CR_SCHEDULE_ENABLE \|
1533	CR_SECURITY_ENABLE \| CR_CALTIMER_ENABLE);
1534	rtl8xxxu_write16(priv, REG_CR, val: val16);
1535
1536	exit:
1537	return ret;
1538	}
1539
1540	static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv)
1541	{
1542	u8 val8;
1543	u16 val16;
1544
1545	rtl8xxxu_flush_fifo(priv);
1546
1547	val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG);
1548	val16 &= ~BIT(`12`);
1549	rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val: val16);
1550
1551	rtl8xxxu_write32(priv, REG_HISR0, val: `0xFFFFFFFF`);
1552	rtl8xxxu_write32(priv, REG_HISR1, val: `0xFFFFFFFF`);
1553
1554	/ Stop Tx Report Timer. 0x4EC[Bit1]=b'0 /
1555	val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1556	val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1557	rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val: val8);
1558
1559	/ Turn off RF /
1560	rtl8xxxu_write8(priv, REG_RF_CTRL, val: `0x00`);
1561
1562	/ Reset Firmware if running in RAM /
1563	if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1564	rtl8xxxu_firmware_self_reset(priv);
1565
1566	rtl8188fu_active_to_lps(priv);
1567
1568	/ Reset MCU /
1569	val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1570	val16 &= ~SYS_FUNC_CPU_ENABLE;
1571	rtl8xxxu_write16(priv, REG_SYS_FUNC, val: val16);
1572
1573	/ Reset MCU ready status /
1574	rtl8xxxu_write8(priv, REG_MCU_FW_DL, val: `0x00`);
1575
1576	rtl8188fu_active_to_emu(priv);
1577	rtl8188fu_emu_to_disabled(priv);
1578	}
1579
1580	#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee
1581	#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f
1582
1583	static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv)
1584	{
1585	u32 val32;
1586	u8 pg_pwrtrim = `0xff`, val8;
1587	s8 bb_gain;
1588
1589	/ Somehow this is not found in the efuse we read earlier. /
1590	rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, data: &pg_pwrtrim);
1591
1592	if (pg_pwrtrim != `0xff`) {
1593	bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK;
1594
1595	if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK)
1596	bb_gain = `0`;
1597	else if (bb_gain & `1`)
1598	bb_gain = bb_gain >> `1`;
1599	else
1600	bb_gain = -(bb_gain >> `1`);
1601
1602	val8 = abs(bb_gain);
1603	if (bb_gain > `0`)
1604	val8 \|= BIT(`5`);
1605
1606	val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_UNKNOWN_55);
1607	val32 &= ~`0xfc000`;
1608	val32 \|= val8 << `14`;
1609	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_UNKNOWN_55, data: val32);
1610	}
1611
1612	rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE \| RF_RSTB \| RF_SDMRSTB);
1613
1614	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1615	val32 &= ~(OFDM_RF_PATH_RX_MASK \| OFDM_RF_PATH_TX_MASK);
1616	val32 \|= OFDM_RF_PATH_RX_A \| OFDM_RF_PATH_TX_A;
1617	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: val32);
1618
1619	rtl8xxxu_write8(priv, REG_TXPAUSE, val: `0x00`);
1620	}
1621
1622	static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv)
1623	{
1624	u32 val32;
1625
1626	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1627	val32 &= ~OFDM_RF_PATH_TX_MASK;
1628	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: val32);
1629
1630	/ Power down RF module /
1631	rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_AC, data: `0`);
1632	}
1633
1634	static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv)
1635	{
1636	u16 val16;
1637	u32 val32;
1638
1639	val16 = rtl8xxxu_read16(priv, REG_CR);
1640	val16 \|= (CR_MAC_TX_ENABLE \| CR_MAC_RX_ENABLE);
1641	rtl8xxxu_write16(priv, REG_CR, val: val16);
1642
1643	val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
1644	val32 \|= TXDMA_OFFSET_DROP_DATA_EN;
1645	rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val: val32);
1646	}
1647
1648	#define XTAL1 GENMASK(22, 17)
1649	#define XTAL0 GENMASK(16, 11)
1650
1651	void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap)
1652	{
1653	struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
1654	u32 val32;
1655
1656	if (crystal_cap == cfo->crystal_cap)
1657	return;
1658
1659	val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
1660
1661	dev_dbg(&priv->udev->dev,
1662	"%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n",
1663	__func__,
1664	cfo->crystal_cap,
1665	FIELD_GET(XTAL1, val32),
1666	FIELD_GET(XTAL0, val32),
1667	crystal_cap);
1668
1669	val32 &= ~(XTAL1 \| XTAL0);
1670	val32 \|= FIELD_PREP(XTAL1, crystal_cap) \|
1671	FIELD_PREP(XTAL0, crystal_cap);
1672	rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val: val32);
1673
1674	cfo->crystal_cap = crystal_cap;
1675	}
1676
1677	static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv priv, struct* rtl8723au_phy_stats *phy_stats)
1678	{
1679	u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
1680	s8 rx_pwr_all = `0x00`;
1681	u8 vga_idx, lna_idx;
1682
1683	lna_idx = u8_get_bits(v: cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);
1684	vga_idx = u8_get_bits(v: cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);
1685
1686	switch (lna_idx) {
1687	case `7`:
1688	if (vga_idx <= `27`)
1689	rx_pwr_all = -`100` + `2` * (`27` - vga_idx);
1690	else
1691	rx_pwr_all = -`100`;
1692	break;
1693	case `5`:
1694	rx_pwr_all = -`74` + `2` * (`21` - vga_idx);
1695	break;
1696	case `3`:
1697	rx_pwr_all = -`60` + `2` * (`20` - vga_idx);
1698	break;
1699	case `1`:
1700	rx_pwr_all = -`44` + `2` * (`19` - vga_idx);
1701	break;
1702	default:
1703	break;
1704	}
1705
1706	return rx_pwr_all;
1707	}
1708
1709	struct rtl8xxxu_fileops rtl8188fu_fops = {
1710	.identify_chip = rtl8188fu_identify_chip,
1711	.parse_efuse = rtl8188fu_parse_efuse,
1712	.load_firmware = rtl8188fu_load_firmware,
1713	.power_on = rtl8188fu_power_on,
1714	.power_off = rtl8188fu_power_off,
1715	.read_efuse = rtl8xxxu_read_efuse,
1716	.reset_8051 = rtl8xxxu_reset_8051,
1717	.llt_init = rtl8xxxu_auto_llt_table,
1718	.init_phy_bb = rtl8188fu_init_phy_bb,
1719	.init_phy_rf = rtl8188fu_init_phy_rf,
1720	.phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
1721	.phy_lc_calibrate = rtl8188f_phy_lc_calibrate,
1722	.phy_iq_calibrate = rtl8188fu_phy_iq_calibrate,
1723	.config_channel = rtl8188fu_config_channel,
1724	.parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1725	.parse_phystats = rtl8723au_rx_parse_phystats,
1726	.init_aggregation = rtl8188fu_init_aggregation,
1727	.init_statistics = rtl8188fu_init_statistics,
1728	.init_burst = rtl8xxxu_init_burst,
1729	.enable_rf = rtl8188f_enable_rf,
1730	.disable_rf = rtl8188f_disable_rf,
1731	.usb_quirks = rtl8188f_usb_quirks,
1732	.set_tx_power = rtl8188f_set_tx_power,
1733	.update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1734	.report_connect = rtl8xxxu_gen2_report_connect,
1735	.report_rssi = rtl8xxxu_gen2_report_rssi,
1736	.fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1737	.set_crystal_cap = rtl8188f_set_crystal_cap,
1738	.cck_rssi = rtl8188f_cck_rssi,
1739	.writeN_block_size = `128`,
1740	.rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1741	.tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1742	.has_s0s1 = `1`,
1743	.has_tx_report = `1`,
1744	.gen2_thermal_meter = `1`,
1745	.needs_full_init = `1`,
1746	.init_reg_rxfltmap = `1`,
1747	.init_reg_pkt_life_time = `1`,
1748	.init_reg_hmtfr = `1`,
1749	.ampdu_max_time = `0x70`,
1750	.ustime_tsf_edca = `0x28`,
1751	.max_aggr_num = `0x0c14`,
1752	.supports_ap = `1`,
1753	.max_macid_num = `16`,
1754	.max_sec_cam_num = `16`,
1755	.supports_concurrent = `1`,
1756	.adda_1t_init = `0x03c00014`,
1757	.adda_1t_path_on = `0x03c00014`,
1758	.trxff_boundary = `0x3f7f`,
1759	.pbp_rx = PBP_PAGE_SIZE_256,
1760	.pbp_tx = PBP_PAGE_SIZE_256,
1761	.mactable = rtl8188f_mac_init_table,
1762	.total_page_num = TX_TOTAL_PAGE_NUM_8188F,
1763	.page_num_hi = TX_PAGE_NUM_HI_PQ_8188F,
1764	.page_num_lo = TX_PAGE_NUM_LO_PQ_8188F,
1765	.page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F,
1766	};
1767

source code of linux/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c