1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * RTL8XXXU mac80211 USB driver - 8192fu specific subdriver |
4 | * |
5 | * Copyright (c) 2023 Bitterblue Smith <rtl8821cerfe2@gmail.com> |
6 | * |
7 | * Portions copied from existing rtl8xxxu code: |
8 | * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> |
9 | * |
10 | * Portions, notably calibration code: |
11 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
12 | */ |
13 | |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> |
16 | #include <linux/sched.h> |
17 | #include <linux/errno.h> |
18 | #include <linux/slab.h> |
19 | #include <linux/module.h> |
20 | #include <linux/spinlock.h> |
21 | #include <linux/list.h> |
22 | #include <linux/usb.h> |
23 | #include <linux/netdevice.h> |
24 | #include <linux/etherdevice.h> |
25 | #include <linux/ethtool.h> |
26 | #include <linux/wireless.h> |
27 | #include <linux/firmware.h> |
28 | #include <linux/moduleparam.h> |
29 | #include <net/mac80211.h> |
30 | #include "rtl8xxxu.h" |
31 | #include "rtl8xxxu_regs.h" |
32 | |
33 | static const struct rtl8xxxu_reg8val rtl8192f_mac_init_table[] = { |
34 | {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10}, |
35 | {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, |
36 | {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, |
37 | {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08}, |
38 | {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, |
39 | {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00}, |
40 | {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10}, |
41 | {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00}, |
42 | {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20}, |
43 | {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e}, |
44 | {0x4a0, 0x00}, {0x4a1, 0x00}, {0x4a2, 0x00}, {0x4a3, 0x00}, |
45 | {0x4a4, 0x15}, {0x4a5, 0xf0}, {0x4a6, 0x01}, {0x4a7, 0x0e}, |
46 | {0x4a8, 0xe0}, {0x4a9, 0x00}, {0x4aa, 0x00}, {0x4ab, 0x00}, |
47 | {0x2448, 0x06}, {0x244a, 0x06}, {0x244c, 0x06}, {0x244e, 0x06}, |
48 | {0x4c7, 0x80}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4ca, 0x3c}, |
49 | {0x4cb, 0x3c}, {0x4cc, 0xff}, {0x4cd, 0xff}, {0x4ce, 0x01}, |
50 | {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, {0x503, 0x00}, |
51 | {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, {0x507, 0x00}, |
52 | {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, {0x50b, 0x00}, |
53 | {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, {0x50f, 0x00}, |
54 | {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, {0x521, 0x2f}, |
55 | {0x525, 0x0f}, {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, |
56 | {0x55c, 0x50}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, |
57 | {0x609, 0x2a}, {0x60c, 0x18}, {0x620, 0xff}, {0x621, 0xff}, |
58 | {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, |
59 | {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, {0x63c, 0x0a}, |
60 | {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, {0x640, 0x40}, |
61 | {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, {0x66e, 0x05}, |
62 | {0x6a0, 0xff}, {0x6a1, 0xff}, {0x6a2, 0xff}, {0x6a3, 0xff}, |
63 | {0x6a4, 0xff}, {0x6a5, 0xff}, {0x6de, 0x84}, {0x700, 0x21}, |
64 | {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, |
65 | {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, {0x718, 0x40}, |
66 | {0x7c0, 0x38}, {0x7c2, 0x0f}, {0x7c3, 0xc0}, {0x073, 0x04}, |
67 | {0x7c4, 0x77}, {0x024, 0xc7}, {0x7ec, 0xff}, {0x7ed, 0xff}, |
68 | {0x7ee, 0xff}, {0x7ef, 0xff}, |
69 | {0xffff, 0xff}, |
70 | }; |
71 | |
72 | /* If updating the phy init table, also update rtl8192f_revise_cck_tx_psf(). */ |
73 | static const struct rtl8xxxu_reg32val rtl8192fu_phy_init_table[] = { |
74 | {0x800, 0x80006C00}, {0x804, 0x00004001}, |
75 | {0x808, 0x0000FC00}, {0x80C, 0x00000000}, |
76 | {0x810, 0x20200322}, {0x814, 0x020C3910}, |
77 | {0x818, 0x00000385}, {0x81C, 0x07000000}, |
78 | {0x820, 0x01000100}, {0x824, 0x00390204}, |
79 | {0x828, 0x01000100}, {0x82C, 0x00390204}, |
80 | {0x830, 0x25252525}, {0x834, 0x25252525}, |
81 | {0x838, 0x25252525}, {0x83C, 0x25252525}, |
82 | {0x840, 0x00010000}, {0x844, 0x00010000}, |
83 | {0x848, 0x25252525}, {0x84C, 0x25252525}, |
84 | {0x850, 0x00031FE0}, {0x854, 0x00000000}, |
85 | {0x858, 0x569A569A}, {0x85C, 0x00400040}, |
86 | {0x860, 0x66F60000}, {0x864, 0x061F0000}, |
87 | {0x868, 0x25252525}, {0x86C, 0x25252525}, |
88 | {0x870, 0x00000300}, {0x874, 0x04003400}, |
89 | {0x878, 0x08080808}, {0x87C, 0x004F0201}, |
90 | {0x880, 0xD8001402}, {0x884, 0xC0000120}, |
91 | {0x888, 0x00000000}, {0x88C, 0xCC0000C0}, |
92 | {0x890, 0x00000000}, {0x894, 0xFFFFFFFE}, |
93 | {0x898, 0x40302010}, {0x89C, 0x00706050}, |
94 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
95 | {0x908, 0x00000F00}, {0x90C, 0x81121313}, |
96 | {0x910, 0x024C0000}, {0x914, 0x00000000}, |
97 | {0x918, 0x00000000}, {0x91C, 0x00000000}, |
98 | {0x920, 0x00000000}, {0x924, 0x00000000}, |
99 | {0x928, 0x00000000}, {0x92C, 0x00000000}, |
100 | {0x930, 0x88000000}, {0x934, 0x00000245}, |
101 | {0x938, 0x00024588}, {0x93C, 0x00000000}, |
102 | {0x940, 0x000007FF}, {0x944, 0x3F3F0000}, |
103 | {0x948, 0x000001A3}, {0x94C, 0x20200008}, |
104 | {0x950, 0x00338A98}, {0x954, 0x00000000}, |
105 | {0x958, 0xCBCAD87A}, {0x95C, 0x06EB5735}, |
106 | {0x960, 0x00000000}, {0x964, 0x00000000}, |
107 | {0x968, 0x00000000}, {0x96C, 0x00000003}, |
108 | {0x970, 0x00000000}, {0x974, 0x00000000}, |
109 | {0x978, 0x00000000}, {0x97C, 0x10030000}, |
110 | {0x980, 0x00000000}, {0x984, 0x02800280}, |
111 | {0x988, 0x020A5704}, {0x98C, 0x1461C826}, |
112 | {0x990, 0x0001469E}, {0x994, 0x008858D1}, |
113 | {0x998, 0x400086C9}, {0x99C, 0x44444242}, |
114 | {0x9A0, 0x00000000}, {0x9A4, 0x00000000}, |
115 | {0x9A8, 0x00000000}, {0x9AC, 0xC0000000}, |
116 | {0xA00, 0x00D047C8}, {0xA04, 0xC1FF0008}, |
117 | {0xA08, 0x88838300}, {0xA0C, 0x2E20100F}, |
118 | {0xA10, 0x9500BB78}, {0xA14, 0x11144028}, |
119 | {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, |
120 | {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, |
121 | {0xA28, 0x00158810}, {0xA2C, 0x10BB8000}, |
122 | {0xA70, 0x00008000}, {0xA74, 0x80800100}, |
123 | {0xA78, 0x000089F0}, {0xA7C, 0x225B0606}, |
124 | {0xA80, 0x20803210}, {0xA84, 0x00200200}, |
125 | {0xA88, 0x00000000}, {0xA8C, 0x00000000}, |
126 | {0xA90, 0x00000000}, {0xA94, 0x00000000}, |
127 | {0xA98, 0x00000000}, {0xA9C, 0x00460000}, |
128 | {0xAA0, 0x00000000}, {0xAA4, 0x00020014}, |
129 | {0xAA8, 0xBA0A0008}, {0xAAC, 0x01235667}, |
130 | {0xAB0, 0x00000000}, {0xAB4, 0x00201402}, |
131 | {0xAB8, 0x0000001C}, {0xABC, 0x0000F7FF}, |
132 | {0xAC0, 0xD4C0A742}, {0xAC4, 0x00000000}, |
133 | {0xAC8, 0x00000F08}, {0xACC, 0x00000F07}, |
134 | {0xAD0, 0xA1052A10}, {0xAD4, 0x0D9D8452}, |
135 | {0xAD8, 0x9E024024}, {0xADC, 0x0023C001}, |
136 | {0xAE0, 0x00000391}, {0xB2C, 0x00000000}, |
137 | {0xC00, 0x00000080}, {0xC04, 0x6F005433}, |
138 | {0xC08, 0x000004E4}, {0xC0C, 0x6C6C6C6C}, |
139 | {0xC10, 0x22000000}, {0xC14, 0x40000100}, |
140 | {0xC18, 0x22000000}, {0xC1C, 0x40000100}, |
141 | {0xC20, 0x00000000}, {0xC24, 0x40000100}, |
142 | {0xC28, 0x00000000}, {0xC2C, 0x40000100}, |
143 | {0xC30, 0x0401E809}, {0xC34, 0x30000020}, |
144 | {0xC38, 0x23808080}, {0xC3C, 0x00002F44}, |
145 | {0xC40, 0x1CF8403F}, {0xC44, 0x000100C7}, |
146 | {0xC48, 0xEC060106}, {0xC4C, 0x007F037F}, |
147 | {0xC50, 0x00E48020}, {0xC54, 0x04008017}, |
148 | {0xC58, 0x00000020}, {0xC5C, 0x00708492}, |
149 | {0xC60, 0x09280200}, {0xC64, 0x5014838B}, |
150 | {0xC68, 0x47C006C7}, {0xC6C, 0x00000035}, |
151 | {0xC70, 0x00001007}, {0xC74, 0x02815269}, |
152 | {0xC78, 0x0FE07F1F}, {0xC7C, 0x00B91612}, |
153 | {0xC80, 0x40000100}, {0xC84, 0x32000000}, |
154 | {0xC88, 0x40000100}, {0xC8C, 0xA0240000}, |
155 | {0xC90, 0x400E161E}, {0xC94, 0x00000F00}, |
156 | {0xC98, 0x400E161E}, {0xC9C, 0x0000BDC8}, |
157 | {0xCA0, 0x00000000}, {0xCA4, 0x098300A0}, |
158 | {0xCA8, 0x00006B00}, {0xCAC, 0x87F45B1A}, |
159 | {0xCB0, 0x0000002D}, {0xCB4, 0x00000000}, |
160 | {0xCB8, 0x00000000}, {0xCBC, 0x28100200}, |
161 | {0xCC0, 0x0010A3D0}, {0xCC4, 0x00000F7D}, |
162 | {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, |
163 | {0xCD0, 0x593659AD}, {0xCD4, 0xB7545121}, |
164 | {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, |
165 | {0xCE0, 0x40201000}, {0xCE4, 0x00000000}, |
166 | {0xCE8, 0x40E04407}, {0xCEC, 0x2E572000}, |
167 | {0xD00, 0x000D8780}, {0xD04, 0x40020403}, |
168 | {0xD08, 0x0002907F}, {0xD0C, 0x20010201}, |
169 | {0xD10, 0x06288888}, {0xD14, 0x8888367B}, |
170 | {0xD18, 0x7D806DB3}, {0xD1C, 0x0000007F}, |
171 | {0xD20, 0x567600B8}, {0xD24, 0x0000018B}, |
172 | {0xD28, 0xD513FF7D}, {0xD2C, 0xCC979975}, |
173 | {0xD30, 0x04928000}, {0xD34, 0x40608000}, |
174 | {0xD38, 0x88DDA000}, {0xD3C, 0x00026EE2}, |
175 | {0xD50, 0x67270001}, {0xD54, 0x20500000}, |
176 | {0xD58, 0x16161616}, {0xD5C, 0x71F20064}, |
177 | {0xD60, 0x4653DA60}, {0xD64, 0x3E718A3C}, |
178 | {0xD68, 0x00000183}, {0xD7C, 0x00000000}, |
179 | {0xD80, 0x50000000}, {0xD84, 0x31310400}, |
180 | {0xD88, 0xF5B50000}, {0xD8C, 0x00000000}, |
181 | {0xD90, 0x00000000}, {0xD94, 0x44BBBB44}, |
182 | {0xD98, 0x44BB44FF}, {0xD9C, 0x06033688}, |
183 | {0xE00, 0x25252525}, {0xE04, 0x25252525}, |
184 | {0xE08, 0x25252525}, {0xE10, 0x25252525}, |
185 | {0xE14, 0x25252525}, {0xE18, 0x25252525}, |
186 | {0xE1C, 0x25252525}, {0xE20, 0x00000000}, |
187 | {0xE24, 0x00200000}, {0xE28, 0x00000000}, |
188 | {0xE2C, 0x00000000}, {0xE30, 0x01007C00}, |
189 | {0xE34, 0x01004800}, {0xE38, 0x10008C0F}, |
190 | {0xE3C, 0x3C008C0F}, {0xE40, 0x01007C00}, |
191 | {0xE44, 0x00000000}, {0xE48, 0x00000000}, |
192 | {0xE4C, 0x00000000}, {0xE50, 0x01007C00}, |
193 | {0xE54, 0x01004800}, {0xE58, 0x10008C0F}, |
194 | {0xE5C, 0x3C008C0F}, {0xE60, 0x02100000}, |
195 | {0xE64, 0xBBBBBBBB}, {0xE68, 0x40404040}, |
196 | {0xE6C, 0x80408040}, {0xE70, 0x80408040}, |
197 | {0xE74, 0x40404040}, {0xE78, 0x00400040}, |
198 | {0xE7C, 0x40404040}, {0xE80, 0x00FF0000}, |
199 | {0xE84, 0x80408040}, {0xE88, 0x40404040}, |
200 | {0xE8C, 0x80408040}, {0xED0, 0x80408040}, |
201 | {0xED4, 0x80408040}, {0xED8, 0x80408040}, |
202 | {0xEDC, 0xC040C040}, {0xEE0, 0xC040C040}, |
203 | {0xEE4, 0x00400040}, {0xEE8, 0xD8001402}, |
204 | {0xEEC, 0xC0000120}, {0xEF0, 0x02000B09}, |
205 | {0xEF4, 0x00000001}, {0xEF8, 0x00000000}, |
206 | {0xF00, 0x00000300}, {0xF04, 0x00000002}, |
207 | {0xF08, 0x00007D0C}, {0xF0C, 0x0000A907}, |
208 | {0xF10, 0x00005807}, {0xF14, 0x00000003}, |
209 | {0xF18, 0x07D003E8}, {0xF1C, 0x8000001F}, |
210 | {0xF20, 0x00000000}, {0xF24, 0x00000000}, |
211 | {0xF28, 0x00000000}, {0xF2C, 0x00000000}, |
212 | {0xF30, 0x00000000}, {0xF34, 0x00000000}, |
213 | {0xF38, 0x00030055}, {0xF3C, 0x0000003A}, |
214 | {0xF40, 0x00000002}, {0xF44, 0x00000000}, |
215 | {0xF48, 0x00000000}, {0xF4C, 0x0B000000}, |
216 | {0xF50, 0x00000000}, |
217 | {0xffff, 0xffffffff}, |
218 | }; |
219 | |
220 | static const struct rtl8xxxu_reg32val rtl8192f_agc_table[] = { |
221 | {0xC78, 0x0FA0001F}, {0xC78, 0x0FA0011F}, |
222 | {0xC78, 0x0FA0021F}, {0xC78, 0x0FA0031F}, |
223 | {0xC78, 0x0FA0041F}, {0xC78, 0x0FA0051F}, |
224 | {0xC78, 0x0F90061F}, {0xC78, 0x0F80071F}, |
225 | {0xC78, 0x0F70081F}, {0xC78, 0x0F60091F}, |
226 | {0xC78, 0x0F500A1F}, {0xC78, 0x0F400B1F}, |
227 | {0xC78, 0x0F300C1F}, {0xC78, 0x0F200D1F}, |
228 | {0xC78, 0x0F100E1F}, {0xC78, 0x0F000F1F}, |
229 | {0xC78, 0x0EF0101F}, {0xC78, 0x0EE0111F}, |
230 | {0xC78, 0x0ED0121F}, {0xC78, 0x0EC0131F}, |
231 | {0xC78, 0x0EB0141F}, {0xC78, 0x0EA0151F}, |
232 | {0xC78, 0x0E90161F}, {0xC78, 0x0E80171F}, |
233 | {0xC78, 0x0E70181F}, {0xC78, 0x0E60191F}, |
234 | {0xC78, 0x0E501A1F}, {0xC78, 0x0E401B1F}, |
235 | {0xC78, 0x0E301C1F}, {0xC78, 0x0C701D1F}, |
236 | {0xC78, 0x0C601E1F}, {0xC78, 0x0C501F1F}, |
237 | {0xC78, 0x0C40201F}, {0xC78, 0x0C30211F}, |
238 | {0xC78, 0x0A60221F}, {0xC78, 0x0A50231F}, |
239 | {0xC78, 0x0A40241F}, {0xC78, 0x0A30251F}, |
240 | {0xC78, 0x0860261F}, {0xC78, 0x0850271F}, |
241 | {0xC78, 0x0840281F}, {0xC78, 0x0830291F}, |
242 | {0xC78, 0x06702A1F}, {0xC78, 0x06602B1F}, |
243 | {0xC78, 0x06502C1F}, {0xC78, 0x06402D1F}, |
244 | {0xC78, 0x06302E1F}, {0xC78, 0x04602F1F}, |
245 | {0xC78, 0x0450301F}, {0xC78, 0x0440311F}, |
246 | {0xC78, 0x0430321F}, {0xC78, 0x0260331F}, |
247 | {0xC78, 0x0250341F}, {0xC78, 0x0240351F}, |
248 | {0xC78, 0x0230361F}, {0xC78, 0x0050371F}, |
249 | {0xC78, 0x0040381F}, {0xC78, 0x0030391F}, |
250 | {0xC78, 0x00203A1F}, {0xC78, 0x00103B1F}, |
251 | {0xC78, 0x00003C1F}, {0xC78, 0x00003D1F}, |
252 | {0xC78, 0x00003E1F}, {0xC78, 0x00003F1F}, |
253 | |
254 | {0xC78, 0x0FA0401F}, {0xC78, 0x0FA0411F}, |
255 | {0xC78, 0x0FA0421F}, {0xC78, 0x0FA0431F}, |
256 | {0xC78, 0x0F90441F}, {0xC78, 0x0F80451F}, |
257 | {0xC78, 0x0F70461F}, {0xC78, 0x0F60471F}, |
258 | {0xC78, 0x0F50481F}, {0xC78, 0x0F40491F}, |
259 | {0xC78, 0x0F304A1F}, {0xC78, 0x0F204B1F}, |
260 | {0xC78, 0x0F104C1F}, {0xC78, 0x0F004D1F}, |
261 | {0xC78, 0x0EF04E1F}, {0xC78, 0x0EE04F1F}, |
262 | {0xC78, 0x0ED0501F}, {0xC78, 0x0EC0511F}, |
263 | {0xC78, 0x0EB0521F}, {0xC78, 0x0EA0531F}, |
264 | {0xC78, 0x0E90541F}, {0xC78, 0x0E80551F}, |
265 | {0xC78, 0x0E70561F}, {0xC78, 0x0E60571F}, |
266 | {0xC78, 0x0E50581F}, {0xC78, 0x0E40591F}, |
267 | {0xC78, 0x0E305A1F}, {0xC78, 0x0E205B1F}, |
268 | {0xC78, 0x0E105C1F}, {0xC78, 0x0C505D1F}, |
269 | {0xC78, 0x0C405E1F}, {0xC78, 0x0C305F1F}, |
270 | {0xC78, 0x0C20601F}, {0xC78, 0x0C10611F}, |
271 | {0xC78, 0x0A40621F}, {0xC78, 0x0A30631F}, |
272 | {0xC78, 0x0A20641F}, {0xC78, 0x0A10651F}, |
273 | {0xC78, 0x0840661F}, {0xC78, 0x0830671F}, |
274 | {0xC78, 0x0820681F}, {0xC78, 0x0810691F}, |
275 | {0xC78, 0x06506A1F}, {0xC78, 0x06406B1F}, |
276 | {0xC78, 0x06306C1F}, {0xC78, 0x06206D1F}, |
277 | {0xC78, 0x06106E1F}, {0xC78, 0x04406F1F}, |
278 | {0xC78, 0x0430701F}, {0xC78, 0x0420711F}, |
279 | {0xC78, 0x0410721F}, {0xC78, 0x0240731F}, |
280 | {0xC78, 0x0230741F}, {0xC78, 0x0220751F}, |
281 | {0xC78, 0x0210761F}, {0xC78, 0x0030771F}, |
282 | {0xC78, 0x0020781F}, {0xC78, 0x0010791F}, |
283 | {0xC78, 0x00007A1F}, {0xC78, 0x00007B1F}, |
284 | {0xC78, 0x00007C1F}, {0xC78, 0x00007D1F}, |
285 | {0xC78, 0x00007E1F}, {0xC78, 0x00007F1F}, |
286 | |
287 | {0xC78, 0x0FA0801F}, {0xC78, 0x0FA0811F}, |
288 | {0xC78, 0x0FA0821F}, {0xC78, 0x0FA0831F}, |
289 | {0xC78, 0x0FA0841F}, {0xC78, 0x0FA0851F}, |
290 | {0xC78, 0x0F90861F}, {0xC78, 0x0F80871F}, |
291 | {0xC78, 0x0F70881F}, {0xC78, 0x0F60891F}, |
292 | {0xC78, 0x0F508A1F}, {0xC78, 0x0F408B1F}, |
293 | {0xC78, 0x0F308C1F}, {0xC78, 0x0F208D1F}, |
294 | {0xC78, 0x0F108E1F}, {0xC78, 0x0B908F1F}, |
295 | {0xC78, 0x0B80901F}, {0xC78, 0x0B70911F}, |
296 | {0xC78, 0x0B60921F}, {0xC78, 0x0B50931F}, |
297 | {0xC78, 0x0B40941F}, {0xC78, 0x0B30951F}, |
298 | {0xC78, 0x0B20961F}, {0xC78, 0x0B10971F}, |
299 | {0xC78, 0x0B00981F}, {0xC78, 0x0AF0991F}, |
300 | {0xC78, 0x0AE09A1F}, {0xC78, 0x0AD09B1F}, |
301 | {0xC78, 0x0AC09C1F}, {0xC78, 0x0AB09D1F}, |
302 | {0xC78, 0x0AA09E1F}, {0xC78, 0x0A909F1F}, |
303 | {0xC78, 0x0A80A01F}, {0xC78, 0x0A70A11F}, |
304 | {0xC78, 0x0A60A21F}, {0xC78, 0x0A50A31F}, |
305 | {0xC78, 0x0A40A41F}, {0xC78, 0x0A30A51F}, |
306 | {0xC78, 0x0A20A61F}, {0xC78, 0x0A10A71F}, |
307 | {0xC78, 0x0A00A81F}, {0xC78, 0x0830A91F}, |
308 | {0xC78, 0x0820AA1F}, {0xC78, 0x0810AB1F}, |
309 | {0xC78, 0x0800AC1F}, {0xC78, 0x0640AD1F}, |
310 | {0xC78, 0x0630AE1F}, {0xC78, 0x0620AF1F}, |
311 | {0xC78, 0x0610B01F}, {0xC78, 0x0600B11F}, |
312 | {0xC78, 0x0430B21F}, {0xC78, 0x0420B31F}, |
313 | {0xC78, 0x0410B41F}, {0xC78, 0x0400B51F}, |
314 | {0xC78, 0x0230B61F}, {0xC78, 0x0220B71F}, |
315 | {0xC78, 0x0210B81F}, {0xC78, 0x0200B91F}, |
316 | {0xC78, 0x0000BA1F}, {0xC78, 0x0000BB1F}, |
317 | {0xC78, 0x0000BC1F}, {0xC78, 0x0000BD1F}, |
318 | {0xC78, 0x0000BE1F}, {0xC78, 0x0000BF1F}, |
319 | {0xC50, 0x00E48024}, {0xC50, 0x00E48020}, |
320 | {0xffff, 0xffffffff} |
321 | }; |
322 | |
323 | static const struct rtl8xxxu_rfregval rtl8192fu_radioa_init_table[] = { |
324 | {0x00, 0x30000}, {0x18, 0x0FC07}, {0x81, 0x0FC00}, {0x82, 0x003C0}, |
325 | {0x84, 0x00005}, {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, |
326 | {0x8E, 0x64540}, {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, |
327 | {0x53, 0x10061}, {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, |
328 | {0x57, 0x2CC00}, {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, |
329 | {0x5C, 0x00015}, {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, |
330 | {0xEF, 0x00002}, {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, |
331 | {0xEF, 0x00000}, {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, |
332 | {0xEF, 0x00800}, {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, |
333 | {0x33, 0x0C84B}, {0x33, 0x1088A}, {0x33, 0x14C50}, {0x33, 0x18C8E}, |
334 | {0x33, 0x1CCCD}, {0x33, 0x20CD0}, {0x33, 0x24CD3}, {0x33, 0x28CD6}, |
335 | {0x33, 0x4002B}, {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, |
336 | {0x33, 0x50888}, {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, |
337 | {0x33, 0x60CCF}, {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, |
338 | {0xEF, 0x00400}, {0x33, 0x01C23}, {0x33, 0x05C23}, {0x33, 0x09D23}, |
339 | {0x33, 0x0DD23}, {0x33, 0x11FA3}, {0x33, 0x15FA3}, {0x33, 0x19FAB}, |
340 | {0x33, 0x1DFAB}, {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, |
341 | {0x33, 0x04030}, {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, |
342 | {0x33, 0x14030}, {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, |
343 | {0x33, 0x24030}, {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, |
344 | {0x33, 0x34030}, {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, |
345 | {0xEF, 0x00100}, {0x33, 0x44001}, {0x33, 0x48001}, {0x33, 0x4C001}, |
346 | {0x33, 0x50001}, {0x33, 0x54001}, {0x33, 0x58001}, {0x33, 0x5C001}, |
347 | {0x33, 0x60001}, {0x33, 0x64001}, {0x33, 0x68001}, {0x33, 0x6C001}, |
348 | {0x33, 0x70001}, {0x33, 0x74001}, {0x33, 0x78001}, {0x33, 0x04000}, |
349 | {0x33, 0x08000}, {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, |
350 | {0x33, 0x18001}, {0x33, 0x1C002}, {0x33, 0x20002}, {0x33, 0x24002}, |
351 | {0x33, 0x28002}, {0x33, 0x2C002}, {0x33, 0x30002}, {0x33, 0x34002}, |
352 | {0x33, 0x38002}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, |
353 | {0x30, 0x20000}, {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, |
354 | {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, |
355 | {0x32, 0xF1DF3}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, |
356 | {0x30, 0x38000}, {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, |
357 | {0x1B, 0x746CE}, {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, |
358 | {0x33, 0x70000}, {0x33, 0x78000}, {0xEF, 0x00000}, {0xDF, 0x08000}, |
359 | {0xB0, 0xFFBCB}, {0xB3, 0x06000}, {0xB7, 0x18DF0}, {0xB8, 0x38FF0}, |
360 | {0xC9, 0x00600}, {0xDF, 0x00000}, {0xB1, 0x33B8F}, {0xB2, 0x33762}, |
361 | {0xB4, 0x141F0}, {0xB5, 0x14080}, {0xB6, 0x12425}, {0xB9, 0xC0008}, |
362 | {0xBA, 0x40005}, {0xC2, 0x02C01}, {0xC3, 0x0000B}, {0xC4, 0x81E2F}, |
363 | {0xC5, 0x5C28F}, {0xC6, 0x000A0}, {0xCA, 0x02000}, {0xFE, 0x00000}, |
364 | {0x18, 0x08C07}, {0xFE, 0x00000}, {0xFE, 0x00000}, {0xFE, 0x00000}, |
365 | {0x00, 0x31DD5}, |
366 | {0xff, 0xffffffff} |
367 | }; |
368 | |
369 | static const struct rtl8xxxu_rfregval rtl8192fu_radiob_init_table[] = { |
370 | {0x00, 0x30000}, {0x81, 0x0FC00}, {0x82, 0x003C0}, {0x84, 0x00005}, |
371 | {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, {0x8E, 0x64540}, |
372 | {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, {0x53, 0x10061}, |
373 | {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, {0x57, 0x2CC00}, |
374 | {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, {0x5C, 0x00015}, |
375 | {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, {0xEF, 0x00002}, |
376 | {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, {0xEF, 0x00000}, |
377 | {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, {0xEF, 0x00800}, |
378 | {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, {0x33, 0x0C84B}, |
379 | {0x33, 0x1088A}, {0x33, 0x14CC8}, {0x33, 0x18CCB}, {0x33, 0x1CCCE}, |
380 | {0x33, 0x20CD1}, {0x33, 0x24CD4}, {0x33, 0x28CD7}, {0x33, 0x4002B}, |
381 | {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, {0x33, 0x50888}, |
382 | {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, {0x33, 0x60CCF}, |
383 | {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, {0xEF, 0x00400}, |
384 | {0x33, 0x01D23}, {0x33, 0x05D23}, {0x33, 0x09FA3}, {0x33, 0x0DFA3}, |
385 | {0x33, 0x11D2B}, {0x33, 0x15D2B}, {0x33, 0x19FAB}, {0x33, 0x1DFAB}, |
386 | {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, {0x33, 0x04030}, |
387 | {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, {0x33, 0x14030}, |
388 | {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, {0x33, 0x24030}, |
389 | {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, {0x33, 0x34030}, |
390 | {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, {0xEF, 0x00100}, |
391 | {0x33, 0x44000}, {0x33, 0x48000}, {0x33, 0x4C000}, {0x33, 0x50000}, |
392 | {0x33, 0x54000}, {0x33, 0x58000}, {0x33, 0x5C000}, {0x33, 0x60000}, |
393 | {0x33, 0x64000}, {0x33, 0x68000}, {0x33, 0x6C000}, {0x33, 0x70000}, |
394 | {0x33, 0x74000}, {0x33, 0x78000}, {0x33, 0x04000}, {0x33, 0x08000}, |
395 | {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, {0x33, 0x18000}, |
396 | {0x33, 0x1C001}, {0x33, 0x20001}, {0x33, 0x24001}, {0x33, 0x28001}, |
397 | {0x33, 0x2C001}, {0x33, 0x30001}, {0x33, 0x34001}, {0x33, 0x38001}, |
398 | {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, {0x30, 0x20000}, |
399 | {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, {0x84, 0x00000}, |
400 | {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, {0x32, 0xF1DF3}, |
401 | {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x38000}, |
402 | {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, {0x1B, 0x746CE}, |
403 | {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, {0x33, 0x70000}, |
404 | {0x33, 0x78000}, {0xEF, 0x00000}, {0x00, 0x31DD5}, |
405 | {0xff, 0xffffffff} |
406 | }; |
407 | |
408 | static int rtl8192fu_identify_chip(struct rtl8xxxu_priv *priv) |
409 | { |
410 | struct device *dev = &priv->udev->dev; |
411 | u32 sys_cfg, vendor, val32; |
412 | |
413 | strscpy(priv->chip_name, "8192FU" , sizeof(priv->chip_name)); |
414 | priv->rtl_chip = RTL8192F; |
415 | priv->rf_paths = 2; |
416 | priv->rx_paths = 2; |
417 | priv->tx_paths = 2; |
418 | |
419 | sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); |
420 | priv->chip_cut = u32_get_bits(v: sys_cfg, SYS_CFG_CHIP_VERSION_MASK); |
421 | if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { |
422 | dev_info(dev, "Unsupported test chip\n" ); |
423 | return -EOPNOTSUPP; |
424 | } |
425 | |
426 | val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); |
427 | priv->has_wifi = u32_get_bits(v: val32, MULTI_WIFI_FUNC_EN); |
428 | priv->has_bluetooth = u32_get_bits(v: val32, MULTI_BT_FUNC_EN); |
429 | priv->has_gps = u32_get_bits(v: val32, MULTI_GPS_FUNC_EN); |
430 | priv->is_multi_func = 1; |
431 | |
432 | vendor = sys_cfg & SYS_CFG_VENDOR_ID; |
433 | rtl8xxxu_identify_vendor_1bit(priv, vendor); |
434 | |
435 | val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); |
436 | priv->rom_rev = u32_get_bits(v: val32, GPIO_RF_RL_ID); |
437 | |
438 | return rtl8xxxu_config_endpoints_no_sie(priv); |
439 | } |
440 | |
441 | static void |
442 | rtl8192f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) |
443 | { |
444 | u8 cck, ofdmbase, mcsbase; |
445 | u32 val32, ofdm, mcs; |
446 | int group, cck_group; |
447 | |
448 | rtl8188f_channel_to_group(channel, group: &group, cck_group: &cck_group); |
449 | |
450 | cck = priv->cck_tx_power_index_A[cck_group]; |
451 | |
452 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, mask: 0x00007f00, val: cck); |
453 | |
454 | val32 = (cck << 16) | (cck << 8) | cck; |
455 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, |
456 | mask: 0x7f7f7f00, val: val32); |
457 | |
458 | ofdmbase = priv->ht40_1s_tx_power_index_A[group]; |
459 | ofdmbase += priv->ofdm_tx_power_diff[RF_A].a; |
460 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; |
461 | |
462 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, mask: 0x7f7f7f7f, val: ofdm); |
463 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, mask: 0x7f7f7f7f, val: ofdm); |
464 | |
465 | mcsbase = priv->ht40_1s_tx_power_index_A[group]; |
466 | if (ht40) |
467 | mcsbase += priv->ht40_tx_power_diff[RF_A].a; |
468 | else |
469 | mcsbase += priv->ht20_tx_power_diff[RF_A].a; |
470 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; |
471 | |
472 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, mask: 0x7f7f7f7f, val: mcs); |
473 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, mask: 0x7f7f7f7f, val: mcs); |
474 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, mask: 0x7f7f7f7f, val: mcs); |
475 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, mask: 0x7f7f7f7f, val: mcs); |
476 | |
477 | if (priv->tx_paths == 1) |
478 | return; |
479 | |
480 | cck = priv->cck_tx_power_index_B[cck_group]; |
481 | |
482 | val32 = (cck << 16) | (cck << 8) | cck; |
483 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK1_55_MCS32, |
484 | mask: 0x7f7f7f00, val: val32); |
485 | |
486 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, |
487 | mask: 0x0000007f, val: cck); |
488 | |
489 | ofdmbase = priv->ht40_1s_tx_power_index_B[group]; |
490 | ofdmbase += priv->ofdm_tx_power_diff[RF_B].b; |
491 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; |
492 | |
493 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, mask: 0x7f7f7f7f, val: ofdm); |
494 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, mask: 0x7f7f7f7f, val: ofdm); |
495 | |
496 | mcsbase = priv->ht40_1s_tx_power_index_B[group]; |
497 | if (ht40) |
498 | mcsbase += priv->ht40_tx_power_diff[RF_B].b; |
499 | else |
500 | mcsbase += priv->ht20_tx_power_diff[RF_B].b; |
501 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; |
502 | |
503 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, mask: 0x7f7f7f7f, val: mcs); |
504 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, mask: 0x7f7f7f7f, val: mcs); |
505 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, mask: 0x7f7f7f7f, val: mcs); |
506 | rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, mask: 0x7f7f7f7f, val: mcs); |
507 | } |
508 | |
509 | static void rtl8192f_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) |
510 | { |
511 | if (channel == 13) { |
512 | /* Special value for channel 13 */ |
513 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, val: 0xf8fe0001); |
514 | /* Normal values */ |
515 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, val: 0x64B80C1C); |
516 | rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, val: 0x8810); |
517 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, val: 0x01235667); |
518 | } else if (channel == 14) { |
519 | /* Normal value */ |
520 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, val: 0xE82C0001); |
521 | /* Special values for channel 14 */ |
522 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, val: 0x0000B81C); |
523 | rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, val: 0x0000); |
524 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, val: 0x00003667); |
525 | } else { |
526 | /* Restore normal values from the phy init table */ |
527 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, val: 0xE82C0001); |
528 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, val: 0x64B80C1C); |
529 | rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, val: 0x8810); |
530 | rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, val: 0x01235667); |
531 | } |
532 | } |
533 | |
534 | static void rtl8192fu_config_kfree(struct rtl8xxxu_priv *priv, u8 channel) |
535 | { |
536 | u8 bb_gain[3] = { EFUSE_UNDEFINED, EFUSE_UNDEFINED, EFUSE_UNDEFINED }; |
537 | u8 bb_gain_path_mask[2] = { 0x0f, 0xf0 }; |
538 | enum rtl8xxxu_rfpath rfpath; |
539 | u8 bb_gain_for_path; |
540 | u8 channel_idx = 0; |
541 | |
542 | if (channel >= 1 && channel <= 3) |
543 | channel_idx = 0; |
544 | if (channel >= 4 && channel <= 9) |
545 | channel_idx = 1; |
546 | if (channel >= 10 && channel <= 14) |
547 | channel_idx = 2; |
548 | |
549 | rtl8xxxu_read_efuse8(priv, offset: 0x1ee, data: &bb_gain[1]); |
550 | rtl8xxxu_read_efuse8(priv, offset: 0x1ec, data: &bb_gain[0]); |
551 | rtl8xxxu_read_efuse8(priv, offset: 0x1ea, data: &bb_gain[2]); |
552 | |
553 | if (bb_gain[1] == EFUSE_UNDEFINED) |
554 | return; |
555 | |
556 | if (bb_gain[0] == EFUSE_UNDEFINED) |
557 | bb_gain[0] = bb_gain[1]; |
558 | |
559 | if (bb_gain[2] == EFUSE_UNDEFINED) |
560 | bb_gain[2] = bb_gain[1]; |
561 | |
562 | for (rfpath = RF_A; rfpath < priv->rf_paths; rfpath++) { |
563 | /* power_trim based on 55[19:14] */ |
564 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_UNKNOWN_55, |
565 | BIT(5), val: 1); |
566 | |
567 | /* enable 55[14] for 0.5db step */ |
568 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_GAIN_CTRL, |
569 | BIT(18), val: 1); |
570 | |
571 | /* enter power_trim debug mode */ |
572 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_GAIN_CCA, |
573 | BIT(7), val: 1); |
574 | |
575 | /* write enable */ |
576 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_WE_LUT, BIT(7), val: 1); |
577 | |
578 | bb_gain_for_path = (bb_gain[channel_idx] & bb_gain_path_mask[rfpath]); |
579 | bb_gain_for_path >>= __ffs(bb_gain_path_mask[rfpath]); |
580 | |
581 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_TXPA_G3, |
582 | mask: 0x70000, val: channel_idx * 2); |
583 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_TXPA_G3, |
584 | mask: 0x3f, val: bb_gain_for_path); |
585 | |
586 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_TXPA_G3, |
587 | mask: 0x70000, val: channel_idx * 2 + 1); |
588 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_TXPA_G3, |
589 | mask: 0x3f, val: bb_gain_for_path); |
590 | |
591 | /* leave power_trim debug mode */ |
592 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_GAIN_CCA, |
593 | BIT(7), val: 0); |
594 | |
595 | /* write disable */ |
596 | rtl8xxxu_write_rfreg_mask(priv, path: rfpath, RF6052_REG_WE_LUT, BIT(7), val: 0); |
597 | } |
598 | } |
599 | |
600 | static void rtl8192fu_config_channel(struct ieee80211_hw *hw) |
601 | { |
602 | struct rtl8xxxu_priv *priv = hw->priv; |
603 | bool ht40 = conf_is_ht40(conf: &hw->conf); |
604 | u8 channel, subchannel = 0; |
605 | bool sec_ch_above = 0; |
606 | u32 val32; |
607 | |
608 | channel = (u8)hw->conf.chandef.chan->hw_value; |
609 | |
610 | if (conf_is_ht40_plus(conf: &hw->conf)) { |
611 | sec_ch_above = 1; |
612 | channel += 2; |
613 | subchannel = 2; |
614 | } else if (conf_is_ht40_minus(conf: &hw->conf)) { |
615 | sec_ch_above = 0; |
616 | channel -= 2; |
617 | subchannel = 1; |
618 | } |
619 | |
620 | val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG); |
621 | |
622 | rtl8192f_revise_cck_tx_psf(priv, channel); |
623 | |
624 | /* Set channel */ |
625 | val32 &= ~(BIT(18) | BIT(17)); /* select the 2.4G band(?) */ |
626 | u32p_replace_bits(p: &val32, val: channel, field: 0xff); |
627 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG, data: val32); |
628 | if (priv->rf_paths > 1) |
629 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_MODE_AG, data: val32); |
630 | |
631 | rtl8192fu_config_kfree(priv, channel); |
632 | |
633 | rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, val: subchannel); |
634 | |
635 | /* small BW */ |
636 | rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30)); |
637 | |
638 | rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, val: ht40); |
639 | rtl8xxxu_write32_mask(priv, REG_FPGA1_RF_MODE, FPGA_RF_MODE, val: ht40); |
640 | |
641 | /* ADC clock = 160M */ |
642 | rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), val: 4); |
643 | |
644 | /* DAC clock = 80M */ |
645 | rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), val: 2); |
646 | |
647 | /* ADC buffer clk */ |
648 | rtl8xxxu_write32_mask(priv, REG_ANTDIV_PARA1, BIT(27) | BIT(26), val: 2); |
649 | |
650 | if (ht40) |
651 | /* Set Control channel to upper or lower. */ |
652 | rtl8xxxu_write32_mask(priv, REG_CCK0_SYSTEM, |
653 | CCK0_SIDEBAND, val: !sec_ch_above); |
654 | |
655 | /* Enable CCK */ |
656 | rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK); |
657 | |
658 | /* RF TRX_BW */ |
659 | val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG); |
660 | val32 &= ~MODE_AG_BW_MASK; |
661 | if (ht40) |
662 | val32 |= MODE_AG_BW_40MHZ_8723B; |
663 | else |
664 | val32 |= MODE_AG_BW_20MHZ_8723B; |
665 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_MODE_AG, data: val32); |
666 | if (priv->rf_paths > 1) |
667 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_MODE_AG, data: val32); |
668 | |
669 | /* Modify RX DFIR parameters */ |
670 | rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, BIT(21) | BIT(20), val: 2); |
671 | |
672 | rtl8xxxu_write32_mask(priv, REG_DOWNSAM_FACTOR, BIT(29) | BIT(28), val: 2); |
673 | |
674 | if (ht40) |
675 | val32 = 0x3; |
676 | else |
677 | val32 = 0x1a3; |
678 | rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, mask: 0x1ff, val: val32); |
679 | } |
680 | |
681 | static void rtl8192fu_init_aggregation(struct rtl8xxxu_priv *priv) |
682 | { |
683 | u32 agg_rx; |
684 | u8 agg_ctrl; |
685 | |
686 | /* RX aggregation */ |
687 | agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); |
688 | agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; |
689 | |
690 | agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); |
691 | agg_rx &= ~RXDMA_USB_AGG_ENABLE; |
692 | agg_rx &= ~0xFF0F; /* reset agg size and timeout */ |
693 | |
694 | rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, val: agg_ctrl); |
695 | rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, val: agg_rx); |
696 | } |
697 | |
698 | static int rtl8192fu_parse_efuse(struct rtl8xxxu_priv *priv) |
699 | { |
700 | struct rtl8192fu_efuse *efuse = &priv->efuse_wifi.efuse8192fu; |
701 | int i; |
702 | |
703 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
704 | return -EINVAL; |
705 | |
706 | ether_addr_copy(dst: priv->mac_addr, src: efuse->mac_addr); |
707 | |
708 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
709 | sizeof(efuse->tx_power_index_A.cck_base)); |
710 | memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, |
711 | sizeof(efuse->tx_power_index_B.cck_base)); |
712 | |
713 | memcpy(priv->ht40_1s_tx_power_index_A, |
714 | efuse->tx_power_index_A.ht40_base, |
715 | sizeof(efuse->tx_power_index_A.ht40_base)); |
716 | memcpy(priv->ht40_1s_tx_power_index_B, |
717 | efuse->tx_power_index_B.ht40_base, |
718 | sizeof(efuse->tx_power_index_B.ht40_base)); |
719 | |
720 | priv->ht20_tx_power_diff[0].a = |
721 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; |
722 | priv->ht20_tx_power_diff[0].b = |
723 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; |
724 | |
725 | priv->ht40_tx_power_diff[0].a = 0; |
726 | priv->ht40_tx_power_diff[0].b = 0; |
727 | |
728 | for (i = 1; i < RTL8723B_TX_COUNT; i++) { |
729 | priv->ofdm_tx_power_diff[i].a = |
730 | efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; |
731 | priv->ofdm_tx_power_diff[i].b = |
732 | efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; |
733 | |
734 | priv->ht20_tx_power_diff[i].a = |
735 | efuse->tx_power_index_A.pwr_diff[i - 1].ht20; |
736 | priv->ht20_tx_power_diff[i].b = |
737 | efuse->tx_power_index_B.pwr_diff[i - 1].ht20; |
738 | |
739 | priv->ht40_tx_power_diff[i].a = |
740 | efuse->tx_power_index_A.pwr_diff[i - 1].ht40; |
741 | priv->ht40_tx_power_diff[i].b = |
742 | efuse->tx_power_index_B.pwr_diff[i - 1].ht40; |
743 | } |
744 | |
745 | priv->default_crystal_cap = efuse->xtal_k & 0x3f; |
746 | |
747 | priv->rfe_type = efuse->rfe_option & 0x1f; |
748 | |
749 | if (priv->rfe_type != 5 && priv->rfe_type != 1) |
750 | dev_warn(&priv->udev->dev, |
751 | "%s: RFE type %d was not tested. Please send an email to linux-wireless@vger.kernel.org about this.\n" , |
752 | __func__, priv->rfe_type); |
753 | |
754 | return 0; |
755 | } |
756 | |
757 | static int rtl8192fu_load_firmware(struct rtl8xxxu_priv *priv) |
758 | { |
759 | return rtl8xxxu_load_firmware(priv, fw_name: "rtlwifi/rtl8192fufw.bin" ); |
760 | } |
761 | |
762 | static void rtl8192fu_init_phy_bb(struct rtl8xxxu_priv *priv) |
763 | { |
764 | /* Enable BB and RF */ |
765 | rtl8xxxu_write16_set(priv, REG_SYS_FUNC, |
766 | SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); |
767 | |
768 | rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); |
769 | |
770 | /* To Fix MAC loopback mode fail. */ |
771 | rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, val: 0xf); |
772 | rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, val: 0xe9); |
773 | |
774 | rtl8xxxu_init_phy_regs(priv, array: rtl8192fu_phy_init_table); |
775 | |
776 | rtl8xxxu_init_phy_regs(priv, array: rtl8192f_agc_table); |
777 | } |
778 | |
779 | static int rtl8192fu_init_phy_rf(struct rtl8xxxu_priv *priv) |
780 | { |
781 | int ret; |
782 | |
783 | ret = rtl8xxxu_init_phy_rf(priv, table: rtl8192fu_radioa_init_table, path: RF_A); |
784 | if (ret) |
785 | return ret; |
786 | |
787 | return rtl8xxxu_init_phy_rf(priv, table: rtl8192fu_radiob_init_table, path: RF_B); |
788 | } |
789 | |
790 | static void rtl8192f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) |
791 | { |
792 | u32 backup_mask = BIT(31) | BIT(30); |
793 | u32 backup; |
794 | u32 val32; |
795 | |
796 | /* Aries's NarrowBand */ |
797 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); |
798 | backup = u32_get_bits(v: val32, field: backup_mask); |
799 | |
800 | u32p_replace_bits(p: &val32, val: 0, field: backup_mask); |
801 | rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val: val32); |
802 | |
803 | rtl8188f_phy_lc_calibrate(priv); |
804 | |
805 | /* Aries's NarrowBand */ |
806 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); |
807 | u32p_replace_bits(p: &val32, val: backup, field: backup_mask); |
808 | rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val: val32); |
809 | |
810 | /* reset OFDM state */ |
811 | rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); |
812 | rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); |
813 | } |
814 | |
815 | static int rtl8192fu_iqk_path_a(struct rtl8xxxu_priv *priv) |
816 | { |
817 | u32 reg_eac, reg_e94, reg_e9c, val32; |
818 | u32 rf_0x58_i, rf_0x58_q; |
819 | u8 rfe = priv->rfe_type; |
820 | int result = 0; |
821 | int ktime, i; |
822 | |
823 | /* Leave IQK mode */ |
824 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
825 | |
826 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: 0xccf000c0); |
827 | rtl8xxxu_write32(priv, REG_ANAPWR1, val: 0x44ffbb44); |
828 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val: 0x00400040); |
829 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x6f005403); |
830 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000804e4); |
831 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x04203400); |
832 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000100); |
833 | |
834 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(4), val: 1); |
835 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(11), val: 1); |
836 | if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) |
837 | val32 = 0x30; |
838 | else |
839 | val32 = 0xe9; |
840 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_PAD_TXG, mask: 0x003ff, val: val32); |
841 | |
842 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
843 | |
844 | /* path-A IQK setting */ |
845 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x18008c1c); |
846 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x38008c1c); |
847 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, val: 0x38008c1c); |
848 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, val: 0x38008c1c); |
849 | |
850 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: 0x8214000f); |
851 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: 0x28140000); |
852 | |
853 | rtl8xxxu_write32(priv, REG_TX_IQK, val: 0x01007c00); |
854 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x01004800); |
855 | |
856 | /* LO calibration setting */ |
857 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x00e62911); |
858 | |
859 | /* One shot, path A LOK & IQK */ |
860 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xfa005800); |
861 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8005800); |
862 | |
863 | mdelay(15); |
864 | |
865 | ktime = 0; |
866 | while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { |
867 | mdelay(5); |
868 | ktime += 5; |
869 | } |
870 | |
871 | /* Check failed */ |
872 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
873 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
874 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
875 | |
876 | /* reload 0xdf and CCK_IND off */ |
877 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
878 | |
879 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_WE_LUT, BIT(4), val: 1); |
880 | |
881 | val32 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_TXMOD); |
882 | rf_0x58_i = u32_get_bits(v: val32, field: 0xfc000); |
883 | rf_0x58_q = u32_get_bits(v: val32, field: 0x003f0); |
884 | |
885 | for (i = 0; i < 8; i++) { |
886 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_TXPA_G3, |
887 | mask: 0x1c000, val: i); |
888 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_TXPA_G3, |
889 | mask: 0x00fc0, val: rf_0x58_i); |
890 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_TXPA_G3, |
891 | mask: 0x0003f, val: rf_0x58_q); |
892 | } |
893 | |
894 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_AC, BIT(14), val: 0); |
895 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_WE_LUT, BIT(4), val: 0); |
896 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, mask: 0x00810, val: 0); |
897 | |
898 | if (!(reg_eac & BIT(28)) && |
899 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
900 | ((reg_e9c & 0x03ff0000) != 0x00420000)) |
901 | result |= 0x01; |
902 | |
903 | return result; |
904 | } |
905 | |
906 | static int rtl8192fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) |
907 | { |
908 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; |
909 | int result = 0; |
910 | int ktime; |
911 | |
912 | /* Leave IQK mode */ |
913 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
914 | |
915 | /* PA/PAD control by 0x56, and set = 0x0 */ |
916 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(1), val: 1); |
917 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_P1, data: 0); |
918 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(11), val: 1); |
919 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_PAD_TXG, mask: 0x003ff, val: 0x27); |
920 | |
921 | /* Enter IQK mode */ |
922 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
923 | |
924 | /* path-A IQK setting */ |
925 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x18008c1c); |
926 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x38008c1c); |
927 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, val: 0x38008c1c); |
928 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, val: 0x38008c1c); |
929 | |
930 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: 0x82160027); |
931 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: 0x28160000); |
932 | |
933 | /* Tx IQK setting */ |
934 | rtl8xxxu_write32(priv, REG_TX_IQK, val: 0x01007c00); |
935 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x01004800); |
936 | |
937 | /* LO calibration setting */ |
938 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x0086a911); |
939 | |
940 | /* One shot, path A LOK & IQK */ |
941 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xfa005800); |
942 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8005800); |
943 | |
944 | mdelay(15); |
945 | |
946 | ktime = 0; |
947 | while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { |
948 | mdelay(5); |
949 | ktime += 5; |
950 | } |
951 | |
952 | /* Check failed */ |
953 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
954 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
955 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
956 | |
957 | if (!(reg_eac & BIT(28)) && |
958 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
959 | ((reg_e9c & 0x03ff0000) != 0x00420000)) { |
960 | result |= 0x01; |
961 | } else { /* If TX not OK, ignore RX */ |
962 | /* PA/PAD controlled by 0x0 */ |
963 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
964 | |
965 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, |
966 | BIT(11), val: 0); |
967 | |
968 | return result; |
969 | } |
970 | |
971 | val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); |
972 | rtl8xxxu_write32(priv, REG_TX_IQK, val: val32); |
973 | |
974 | /* Modify RX IQK mode table */ |
975 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
976 | |
977 | /* PA/PAD control by 0x56, and set = 0x0 */ |
978 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(1), val: 1); |
979 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_P1, data: 0); |
980 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(11), val: 1); |
981 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_PAD_TXG, mask: 0x003ff, val: 0x1e0); |
982 | |
983 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: 0xccf000c0); |
984 | rtl8xxxu_write32(priv, REG_ANAPWR1, val: 0x44ffbb44); |
985 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val: 0x00400040); |
986 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x6f005403); |
987 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000804e4); |
988 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x04203400); |
989 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000100); |
990 | |
991 | /* Enter IQK mode */ |
992 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
993 | |
994 | /* path-A IQK setting */ |
995 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x38008c1c); |
996 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x18008c1c); |
997 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, val: 0x38008c1c); |
998 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, val: 0x38008c1c); |
999 | |
1000 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, val: 0x82170000); |
1001 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val: 0x28170000); |
1002 | |
1003 | /* RX IQK setting */ |
1004 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x01004800); |
1005 | |
1006 | /* LO calibration setting */ |
1007 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x0046a8d1); |
1008 | |
1009 | /* One shot, path A LOK & IQK */ |
1010 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xfa005800); |
1011 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8005800); |
1012 | |
1013 | mdelay(15); |
1014 | |
1015 | ktime = 0; |
1016 | while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) { |
1017 | mdelay(5); |
1018 | ktime += 5; |
1019 | } |
1020 | |
1021 | /* Check failed */ |
1022 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
1023 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
1024 | |
1025 | /* Leave IQK mode */ |
1026 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1027 | |
1028 | rtl8xxxu_write_rfreg_mask(priv, path: RF_A, RF6052_REG_GAIN_CCA, BIT(11), val: 0); |
1029 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_P1, data: 0x02000); |
1030 | |
1031 | if (!(reg_eac & BIT(27)) && |
1032 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
1033 | ((reg_eac & 0x03ff0000) != 0x00360000)) |
1034 | result |= 0x02; |
1035 | |
1036 | return result; |
1037 | } |
1038 | |
1039 | static int rtl8192fu_iqk_path_b(struct rtl8xxxu_priv *priv) |
1040 | { |
1041 | u32 reg_eac, reg_eb4, reg_ebc, val32; |
1042 | u32 rf_0x58_i, rf_0x58_q; |
1043 | u8 rfe = priv->rfe_type; |
1044 | int result = 0; |
1045 | int ktime, i; |
1046 | |
1047 | /* PA/PAD controlled by 0x0 */ |
1048 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1049 | |
1050 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: 0xccf000c0); |
1051 | rtl8xxxu_write32(priv, REG_ANAPWR1, val: 0x44ffbb44); |
1052 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val: 0x00400040); |
1053 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x6f005403); |
1054 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000804e4); |
1055 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x04203400); |
1056 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000000); |
1057 | |
1058 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(4), val: 1); |
1059 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(11), val: 1); |
1060 | if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) |
1061 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_PAD_TXG, |
1062 | mask: 0x003ff, val: 0x30); |
1063 | else |
1064 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_PAD_TXG, |
1065 | mask: 0x00fff, val: 0xe9); |
1066 | |
1067 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
1068 | |
1069 | /* Path B IQK setting */ |
1070 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x38008c1c); |
1071 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x38008c1c); |
1072 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, val: 0x18008c1c); |
1073 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, val: 0x38008c1c); |
1074 | |
1075 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, val: 0x8214000F); |
1076 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, val: 0x28140000); |
1077 | |
1078 | rtl8xxxu_write32(priv, REG_TX_IQK, val: 0x01007c00); |
1079 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x01004800); |
1080 | |
1081 | /* LO calibration setting */ |
1082 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x00e62911); |
1083 | |
1084 | /* One shot, path B LOK & IQK */ |
1085 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xfa005800); |
1086 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8005800); |
1087 | |
1088 | mdelay(15); |
1089 | |
1090 | ktime = 0; |
1091 | while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { |
1092 | mdelay(5); |
1093 | ktime += 5; |
1094 | } |
1095 | |
1096 | /* Check failed */ |
1097 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
1098 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
1099 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
1100 | |
1101 | /* reload 0xdf and CCK_IND off */ |
1102 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1103 | |
1104 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_WE_LUT, BIT(4), val: 1); |
1105 | |
1106 | val32 = rtl8xxxu_read_rfreg(priv, path: RF_B, RF6052_REG_TXMOD); |
1107 | rf_0x58_i = u32_get_bits(v: val32, field: 0xfc000); |
1108 | rf_0x58_q = u32_get_bits(v: val32, field: 0x003f0); |
1109 | |
1110 | for (i = 0; i < 8; i++) { |
1111 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_TXPA_G3, |
1112 | mask: 0x1c000, val: i); |
1113 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_TXPA_G3, |
1114 | mask: 0x00fc0, val: rf_0x58_i); |
1115 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_TXPA_G3, |
1116 | mask: 0x0003f, val: rf_0x58_q); |
1117 | } |
1118 | |
1119 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_AC, BIT(14), val: 0); |
1120 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_WE_LUT, BIT(4), val: 0); |
1121 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, mask: 0x00810, val: 0); |
1122 | |
1123 | if (!(reg_eac & BIT(31)) && |
1124 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && |
1125 | ((reg_ebc & 0x03ff0000) != 0x00420000)) |
1126 | result |= 0x01; |
1127 | else |
1128 | dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n" , |
1129 | __func__); |
1130 | |
1131 | return result; |
1132 | } |
1133 | |
1134 | static int rtl8192fu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) |
1135 | { |
1136 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; |
1137 | int result = 0; |
1138 | int ktime; |
1139 | |
1140 | /* Leave IQK mode */ |
1141 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1142 | |
1143 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(1), val: 1); |
1144 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_GAIN_P1, data: 0); |
1145 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(11), val: 1); |
1146 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_PAD_TXG, mask: 0x003ff, val: 0x67); |
1147 | |
1148 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: 0xccf000c0); |
1149 | rtl8xxxu_write32(priv, REG_ANAPWR1, val: 0x44ffbb44); |
1150 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val: 0x00400040); |
1151 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x6f005403); |
1152 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000804e4); |
1153 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x04203400); |
1154 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000000); |
1155 | |
1156 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
1157 | |
1158 | /* path-B IQK setting */ |
1159 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x38008c1c); |
1160 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x38008c1c); |
1161 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, val: 0x18008c1c); |
1162 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, val: 0x38008c1c); |
1163 | |
1164 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, val: 0x82160027); |
1165 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, val: 0x28160000); |
1166 | |
1167 | /* LO calibration setting */ |
1168 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x0086a911); |
1169 | |
1170 | /* One shot, path A LOK & IQK */ |
1171 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xfa005800); |
1172 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8005800); |
1173 | |
1174 | mdelay(15); |
1175 | |
1176 | ktime = 0; |
1177 | while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { |
1178 | mdelay(5); |
1179 | ktime += 5; |
1180 | } |
1181 | |
1182 | /* Check failed */ |
1183 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
1184 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
1185 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
1186 | |
1187 | if (!(reg_eac & BIT(31)) && |
1188 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && |
1189 | ((reg_ebc & 0x03ff0000) != 0x00420000)) { |
1190 | result |= 0x01; |
1191 | } else { |
1192 | /* PA/PAD controlled by 0x0 */ |
1193 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1194 | |
1195 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, |
1196 | BIT(11), val: 0); |
1197 | |
1198 | return result; |
1199 | } |
1200 | |
1201 | val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); |
1202 | rtl8xxxu_write32(priv, REG_TX_IQK, val: val32); |
1203 | |
1204 | /* Modify RX IQK mode table */ |
1205 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1206 | |
1207 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(1), val: 1); |
1208 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_GAIN_P1, data: 0); |
1209 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(11), val: 1); |
1210 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_PAD_TXG, mask: 0x003ff, val: 0x1e0); |
1211 | |
1212 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: 0xccf000c0); |
1213 | rtl8xxxu_write32(priv, REG_ANAPWR1, val: 0x44ffbb44); |
1214 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val: 0x00400040); |
1215 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x6f005403); |
1216 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000804e4); |
1217 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x04203400); |
1218 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000000); |
1219 | |
1220 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
1221 | |
1222 | /* Path B IQK setting */ |
1223 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, val: 0x38008c1c); |
1224 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, val: 0x38008c1c); |
1225 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, val: 0x38008c1c); |
1226 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, val: 0x18008c1c); |
1227 | |
1228 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, val: 0x82170000); |
1229 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, val: 0x28170000); |
1230 | |
1231 | /* IQK setting */ |
1232 | rtl8xxxu_write32(priv, REG_RX_IQK, val: 0x01004800); |
1233 | |
1234 | /* LO calibration setting */ |
1235 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, val: 0x0046a911); |
1236 | |
1237 | /* One shot, path A LOK & IQK */ |
1238 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xfa005800); |
1239 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, val: 0xf8005800); |
1240 | |
1241 | mdelay(15); |
1242 | |
1243 | ktime = 0; |
1244 | while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) { |
1245 | mdelay(5); |
1246 | ktime += 5; |
1247 | } |
1248 | |
1249 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
1250 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
1251 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
1252 | |
1253 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1254 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000100); |
1255 | |
1256 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(11), val: 0); |
1257 | rtl8xxxu_write_rfreg_mask(priv, path: RF_B, RF6052_REG_GAIN_CCA, BIT(1), val: 0); |
1258 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_GAIN_P1, data: 0x02000); |
1259 | |
1260 | if (!(reg_eac & BIT(30)) && |
1261 | ((reg_ec4 & 0x03ff0000) != 0x01320000) && |
1262 | ((reg_ecc & 0x03ff0000) != 0x00360000)) |
1263 | result |= 0x02; |
1264 | else |
1265 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n" , |
1266 | __func__); |
1267 | |
1268 | return result; |
1269 | } |
1270 | |
1271 | static void rtl8192fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
1272 | int result[][8], int t) |
1273 | { |
1274 | static const u32 adda_regs[2] = { |
1275 | REG_ANAPWR1, REG_RX_WAIT_CCA |
1276 | }; |
1277 | static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
1278 | REG_TXPAUSE, REG_BEACON_CTRL, |
1279 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
1280 | }; |
1281 | static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
1282 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
1283 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
1284 | REG_DPDT_CTRL, REG_RFE_CTRL_ANTA_SRC, |
1285 | REG_RFE_CTRL_ANT_SRC2, REG_CCK0_AFE_SETTING |
1286 | }; |
1287 | u32 rx_initial_gain_a, rx_initial_gain_b; |
1288 | struct device *dev = &priv->udev->dev; |
1289 | int path_a_ok, path_b_ok; |
1290 | u8 rfe = priv->rfe_type; |
1291 | int retry = 2; |
1292 | u32 i, val32; |
1293 | |
1294 | /* |
1295 | * Note: IQ calibration must be performed after loading |
1296 | * PHY_REG.txt , and radio_a, radio_b.txt |
1297 | */ |
1298 | |
1299 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1300 | |
1301 | rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); |
1302 | rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); |
1303 | |
1304 | if (t == 0) { |
1305 | /* Save ADDA parameters, turn Path A ADDA on */ |
1306 | rtl8xxxu_save_regs(priv, regs: adda_regs, backup: priv->adda_backup, |
1307 | ARRAY_SIZE(adda_regs)); |
1308 | rtl8xxxu_save_mac_regs(priv, reg: iqk_mac_regs, backup: priv->mac_backup); |
1309 | rtl8xxxu_save_regs(priv, regs: iqk_bb_regs, |
1310 | backup: priv->bb_backup, RTL8XXXU_BB_REGS); |
1311 | } |
1312 | |
1313 | /* Instead of rtl8xxxu_path_adda_on */ |
1314 | rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); |
1315 | |
1316 | /* MAC settings */ |
1317 | rtl8xxxu_write8(priv, REG_TXPAUSE, val: 0xff); |
1318 | rtl8xxxu_write8_clear(priv, REG_GPIO_MUXCFG, GPIO_MUXCFG_IO_SEL_ENBT); |
1319 | |
1320 | if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { |
1321 | /* in ePA IQK, rfe_func_config & SW both pull down */ |
1322 | /* path A */ |
1323 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, mask: 0xF, val: 0x7); |
1324 | rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, mask: 0x1, val: 0x0); |
1325 | |
1326 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, mask: 0xF00, val: 0x7); |
1327 | rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, mask: 0x4, val: 0x0); |
1328 | |
1329 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, mask: 0xF000, val: 0x7); |
1330 | rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, mask: 0x8, val: 0x0); |
1331 | |
1332 | /* path B */ |
1333 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, mask: 0xF0, val: 0x7); |
1334 | rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, mask: 0x20000, val: 0x0); |
1335 | |
1336 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, mask: 0xF0000, val: 0x7); |
1337 | rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, mask: 0x100000, val: 0x0); |
1338 | |
1339 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, mask: 0xF000, val: 0x7); |
1340 | rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, mask: 0x8000000, val: 0x0); |
1341 | } |
1342 | |
1343 | if (priv->rf_paths > 1) { |
1344 | /* path B standby */ |
1345 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x000000); |
1346 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_AC, data: 0x10000); |
1347 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0x808000); |
1348 | } |
1349 | |
1350 | for (i = 0; i < retry; i++) { |
1351 | path_a_ok = rtl8192fu_iqk_path_a(priv); |
1352 | |
1353 | if (path_a_ok == 0x01) { |
1354 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
1355 | result[t][0] = (val32 >> 16) & 0x3ff; |
1356 | |
1357 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
1358 | result[t][1] = (val32 >> 16) & 0x3ff; |
1359 | break; |
1360 | } else { |
1361 | result[t][0] = 0x100; |
1362 | result[t][1] = 0x0; |
1363 | } |
1364 | } |
1365 | |
1366 | for (i = 0; i < retry; i++) { |
1367 | path_a_ok = rtl8192fu_rx_iqk_path_a(priv); |
1368 | |
1369 | if (path_a_ok == 0x03) { |
1370 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
1371 | result[t][2] = (val32 >> 16) & 0x3ff; |
1372 | |
1373 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
1374 | result[t][3] = (val32 >> 16) & 0x3ff; |
1375 | break; |
1376 | } else { |
1377 | result[t][2] = 0x100; |
1378 | result[t][3] = 0x0; |
1379 | } |
1380 | } |
1381 | |
1382 | if (!path_a_ok) |
1383 | dev_warn(dev, "%s: Path A IQK failed!\n" , __func__); |
1384 | |
1385 | if (priv->rf_paths > 1) { |
1386 | for (i = 0; i < retry; i++) { |
1387 | path_b_ok = rtl8192fu_iqk_path_b(priv); |
1388 | |
1389 | if (path_b_ok == 0x01) { |
1390 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
1391 | result[t][4] = (val32 >> 16) & 0x3ff; |
1392 | |
1393 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
1394 | result[t][5] = (val32 >> 16) & 0x3ff; |
1395 | break; |
1396 | } else { |
1397 | result[t][4] = 0x100; |
1398 | result[t][5] = 0x0; |
1399 | } |
1400 | } |
1401 | |
1402 | for (i = 0; i < retry; i++) { |
1403 | path_b_ok = rtl8192fu_rx_iqk_path_b(priv); |
1404 | |
1405 | if (path_b_ok == 0x03) { |
1406 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
1407 | result[t][6] = (val32 >> 16) & 0x3ff; |
1408 | |
1409 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
1410 | result[t][7] = (val32 >> 16) & 0x3ff; |
1411 | break; |
1412 | } else { |
1413 | result[t][6] = 0x100; |
1414 | result[t][7] = 0x0; |
1415 | } |
1416 | } |
1417 | |
1418 | if (!path_b_ok) |
1419 | dev_warn(dev, "%s: Path B IQK failed!\n" , __func__); |
1420 | } |
1421 | |
1422 | /* Back to BB mode, load original value */ |
1423 | rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, mask: 0xffffff00, val: 0); |
1424 | |
1425 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, val: 0xcc0000c0); |
1426 | |
1427 | rtl8xxxu_write32(priv, REG_ANAPWR1, val: 0x44bbbb44); |
1428 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val: 0x80408040); |
1429 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: 0x6f005433); |
1430 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, val: 0x000004e4); |
1431 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, val: 0x04003400); |
1432 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val: 0x01000100); |
1433 | |
1434 | /* Reload ADDA power saving parameters */ |
1435 | rtl8xxxu_restore_regs(priv, regs: adda_regs, backup: priv->adda_backup, |
1436 | ARRAY_SIZE(adda_regs)); |
1437 | |
1438 | /* Reload MAC parameters */ |
1439 | rtl8xxxu_restore_mac_regs(priv, reg: iqk_mac_regs, backup: priv->mac_backup); |
1440 | |
1441 | /* Reload BB parameters */ |
1442 | rtl8xxxu_restore_regs(priv, regs: iqk_bb_regs, backup: priv->bb_backup, RTL8XXXU_BB_REGS); |
1443 | |
1444 | rtl8xxxu_write32_clear(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); |
1445 | |
1446 | /* Restore RX initial gain */ |
1447 | rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, mask: 0xff, val: 0x50); |
1448 | rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, mask: 0xff, |
1449 | val: rx_initial_gain_a & 0xff); |
1450 | if (priv->rf_paths > 1) { |
1451 | rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, mask: 0xff, val: 0x50); |
1452 | rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, mask: 0xff, |
1453 | val: rx_initial_gain_b & 0xff); |
1454 | } |
1455 | } |
1456 | |
1457 | static void rtl8192fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
1458 | { |
1459 | s32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
1460 | s32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
1461 | struct device *dev = &priv->udev->dev; |
1462 | u32 path_a_0xdf, path_a_0x35; |
1463 | u32 path_b_0xdf, path_b_0x35; |
1464 | bool path_a_ok, path_b_ok; |
1465 | u8 rfe = priv->rfe_type; |
1466 | u32 rfe_path_select; |
1467 | int result[4][8]; /* last is final result */ |
1468 | int i, candidate; |
1469 | s32 reg_tmp = 0; |
1470 | bool simu; |
1471 | u32 val32; |
1472 | |
1473 | rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT); |
1474 | |
1475 | path_a_0xdf = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA); |
1476 | path_a_0x35 = rtl8xxxu_read_rfreg(priv, path: RF_A, RF6052_REG_GAIN_P1); |
1477 | path_b_0xdf = rtl8xxxu_read_rfreg(priv, path: RF_B, RF6052_REG_GAIN_CCA); |
1478 | path_b_0x35 = rtl8xxxu_read_rfreg(priv, path: RF_B, RF6052_REG_GAIN_P1); |
1479 | |
1480 | memset(result, 0, sizeof(result)); |
1481 | candidate = -1; |
1482 | |
1483 | path_a_ok = false; |
1484 | path_b_ok = false; |
1485 | |
1486 | for (i = 0; i < 3; i++) { |
1487 | rtl8192fu_phy_iqcalibrate(priv, result, t: i); |
1488 | |
1489 | if (i == 1) { |
1490 | simu = rtl8xxxu_gen2_simularity_compare(priv, result, c1: 0, c2: 1); |
1491 | if (simu) { |
1492 | candidate = 0; |
1493 | break; |
1494 | } |
1495 | } |
1496 | |
1497 | if (i == 2) { |
1498 | simu = rtl8xxxu_gen2_simularity_compare(priv, result, c1: 0, c2: 2); |
1499 | if (simu) { |
1500 | candidate = 0; |
1501 | break; |
1502 | } |
1503 | |
1504 | simu = rtl8xxxu_gen2_simularity_compare(priv, result, c1: 1, c2: 2); |
1505 | if (simu) { |
1506 | candidate = 1; |
1507 | } else { |
1508 | for (i = 0; i < 8; i++) |
1509 | reg_tmp += result[3][i]; |
1510 | |
1511 | if (reg_tmp) |
1512 | candidate = 3; |
1513 | else |
1514 | candidate = -1; |
1515 | } |
1516 | } |
1517 | } |
1518 | |
1519 | if (candidate >= 0) { |
1520 | reg_e94 = result[candidate][0]; |
1521 | reg_e9c = result[candidate][1]; |
1522 | reg_ea4 = result[candidate][2]; |
1523 | reg_eac = result[candidate][3]; |
1524 | reg_eb4 = result[candidate][4]; |
1525 | reg_ebc = result[candidate][5]; |
1526 | reg_ec4 = result[candidate][6]; |
1527 | reg_ecc = result[candidate][7]; |
1528 | |
1529 | dev_dbg(dev, "%s: candidate is %x\n" , __func__, candidate); |
1530 | dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%c\n" , |
1531 | __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, |
1532 | reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
1533 | |
1534 | path_a_ok = true; |
1535 | path_b_ok = true; |
1536 | } |
1537 | |
1538 | rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, mask: 0x3ff00000, val: 0x100); |
1539 | rtl8xxxu_write32_mask(priv, REG_NP_ANTA, mask: 0x3ff, val: 0); |
1540 | rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, mask: 0x3ff00000, val: 0x100); |
1541 | rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, mask: 0x3ff, val: 0); |
1542 | |
1543 | if (candidate >= 0) { |
1544 | if (reg_e94) |
1545 | rtl8xxxu_fill_iqk_matrix_a(priv, iqk_ok: path_a_ok, result, |
1546 | candidate, tx_only: (reg_ea4 == 0)); |
1547 | |
1548 | if (reg_eb4) |
1549 | rtl8xxxu_fill_iqk_matrix_b(priv, iqk_ok: path_b_ok, result, |
1550 | candidate, tx_only: (reg_ec4 == 0)); |
1551 | } |
1552 | |
1553 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_CCA, data: path_a_0xdf); |
1554 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_GAIN_P1, data: path_a_0x35); |
1555 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_GAIN_CCA, data: path_b_0xdf); |
1556 | rtl8xxxu_write_rfreg(priv, path: RF_B, RF6052_REG_GAIN_P1, data: path_b_0x35); |
1557 | |
1558 | if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { |
1559 | rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, bits: 0x70000); |
1560 | rtl8xxxu_write32_clear(priv, REG_LEDCFG0, bits: 0x6c00000); |
1561 | rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28)); |
1562 | rtl8xxxu_write32_clear(priv, REG_SW_GPIO_SHARE_CTRL_0, |
1563 | bits: 0x600000 | BIT(4)); |
1564 | |
1565 | /* |
1566 | * Originally: |
1567 | * odm_set_bb_reg(dm, R_0x944, BIT(11) | 0x1F, 0x3F); |
1568 | * |
1569 | * It clears bit 11 and sets bits 0..4. The mask doesn't cover |
1570 | * bit 5 so it's not modified. Is that what it's supposed to |
1571 | * accomplish? |
1572 | */ |
1573 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
1574 | val32 &= ~BIT(11); |
1575 | val32 |= 0x1f; |
1576 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val: val32); |
1577 | |
1578 | if (rfe == 7) { |
1579 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, |
1580 | mask: 0xfffff, val: 0x23200); |
1581 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, |
1582 | mask: 0xfffff, val: 0x23200); |
1583 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, |
1584 | mask: 0xf000, val: 0x3); |
1585 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, |
1586 | mask: 0xf000, val: 0x3); |
1587 | } else { |
1588 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, |
1589 | mask: 0xfffff, val: 0x22200); |
1590 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, |
1591 | mask: 0xfffff, val: 0x22200); |
1592 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, |
1593 | mask: 0xf000, val: 0x2); |
1594 | rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, |
1595 | mask: 0xf000, val: 0x2); |
1596 | } |
1597 | |
1598 | rtl8xxxu_write32_clear(priv, REG_RFE_OPT62, BIT(2)); |
1599 | |
1600 | if (rfe == 7) |
1601 | rtl8xxxu_write32(priv, REG_RFE_OPT, val: 0x03000003); |
1602 | |
1603 | rtl8xxxu_write32(priv, REG_RFE_PATH_SELECT, val: rfe_path_select); |
1604 | } |
1605 | } |
1606 | |
1607 | static void rtl8192fu_disabled_to_emu(struct rtl8xxxu_priv *priv) |
1608 | { |
1609 | rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, |
1610 | APS_FSMCO_HW_POWERDOWN | APS_FSMCO_HW_SUSPEND); |
1611 | |
1612 | rtl8xxxu_write32_clear(priv, REG_GPIO_INTM, BIT(16)); |
1613 | |
1614 | rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, |
1615 | APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); |
1616 | } |
1617 | |
1618 | static int rtl8192fu_emu_to_active(struct rtl8xxxu_priv *priv) |
1619 | { |
1620 | u32 val32; |
1621 | u16 val16; |
1622 | int count; |
1623 | |
1624 | /* enable LDOA12 MACRO block for all interface */ |
1625 | rtl8xxxu_write8_set(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); |
1626 | |
1627 | /* disable BT_GPS_SEL pins */ |
1628 | rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28)); |
1629 | |
1630 | mdelay(1); |
1631 | |
1632 | /* release analog Ips to digital */ |
1633 | rtl8xxxu_write8_clear(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); |
1634 | |
1635 | val16 = APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND | APS_FSMCO_SW_LPS; |
1636 | rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, bits: val16); |
1637 | |
1638 | /* wait till 0x04[17] = 1 power ready */ |
1639 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
1640 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1641 | if (val32 & BIT(17)) |
1642 | break; |
1643 | |
1644 | udelay(10); |
1645 | } |
1646 | |
1647 | if (!count) |
1648 | return -EBUSY; |
1649 | |
1650 | rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); |
1651 | |
1652 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
1653 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1654 | if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0) |
1655 | break; |
1656 | |
1657 | udelay(10); |
1658 | } |
1659 | |
1660 | if (!count) |
1661 | return -EBUSY; |
1662 | |
1663 | /* SWR OCP enable */ |
1664 | rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18)); |
1665 | |
1666 | rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN); |
1667 | |
1668 | rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, |
1669 | APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); |
1670 | |
1671 | /* 0x7c[31]=1, LDO has max output capability */ |
1672 | rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31)); |
1673 | |
1674 | rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_ENABLE); |
1675 | |
1676 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
1677 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1678 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) |
1679 | break; |
1680 | |
1681 | udelay(10); |
1682 | } |
1683 | |
1684 | if (!count) |
1685 | return -EBUSY; |
1686 | |
1687 | /* Enable WL control XTAL setting */ |
1688 | rtl8xxxu_write8_set(priv, REG_AFE_MISC, AFE_MISC_WL_XTAL_CTRL); |
1689 | |
1690 | /* Enable falling edge triggering interrupt */ |
1691 | rtl8xxxu_write16_set(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); |
1692 | |
1693 | /* Enable GPIO9 data mode */ |
1694 | rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_IRQ); |
1695 | |
1696 | /* Enable GPIO9 input mode */ |
1697 | rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_INPUT); |
1698 | |
1699 | /* Enable HSISR GPIO[C:0] interrupt */ |
1700 | rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0)); |
1701 | |
1702 | /* RF HW ON/OFF Enable */ |
1703 | rtl8xxxu_write8_clear(priv, REG_MULTI_FUNC_CTRL, MULTI_WIFI_HW_ROF_EN); |
1704 | |
1705 | /* Register Lock Disable */ |
1706 | rtl8xxxu_write8_set(priv, REG_RSV_CTRL, BIT(7)); |
1707 | |
1708 | /* For GPIO9 internal pull high setting */ |
1709 | rtl8xxxu_write16_set(priv, REG_MULTI_FUNC_CTRL, BIT(14)); |
1710 | |
1711 | /* reset RF path S1 */ |
1712 | rtl8xxxu_write8(priv, REG_RF_CTRL, val: 0); |
1713 | |
1714 | /* reset RF path S0 */ |
1715 | rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, val: 0); |
1716 | |
1717 | /* enable RF path S1 */ |
1718 | rtl8xxxu_write8(priv, REG_RF_CTRL, RF_SDMRSTB | RF_RSTB | RF_ENABLE); |
1719 | |
1720 | /* enable RF path S0 */ |
1721 | rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, RF_SDMRSTB | RF_RSTB | RF_ENABLE); |
1722 | |
1723 | /* AFE_Ctrl */ |
1724 | rtl8xxxu_write8_set(priv, REG_RSVD_1, BIT(5)); |
1725 | |
1726 | /* AFE_Ctrl */ |
1727 | rtl8xxxu_write8(priv, REG_RSVD_4, val: 0xcc); |
1728 | |
1729 | /* AFE_Ctrl 0x24[4:3]=00 for xtal gmn */ |
1730 | rtl8xxxu_write8_clear(priv, REG_AFE_XTAL_CTRL, BIT(4) | BIT(3)); |
1731 | |
1732 | /* GPIO_A[31:0] Pull down software register */ |
1733 | rtl8xxxu_write32(priv, REG_GPIO_A0, val: 0xffffffff); |
1734 | |
1735 | /* GPIO_B[7:0] Pull down software register */ |
1736 | rtl8xxxu_write8(priv, REG_GPIO_B0, val: 0xff); |
1737 | |
1738 | /* Register Lock Enable */ |
1739 | rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(7)); |
1740 | |
1741 | return 0; |
1742 | } |
1743 | |
1744 | static int rtl8192fu_active_to_emu(struct rtl8xxxu_priv *priv) |
1745 | { |
1746 | u32 val32; |
1747 | int count; |
1748 | |
1749 | /* Reset BB, RF enter Power Down mode */ |
1750 | rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); |
1751 | |
1752 | /* Enable rising edge triggering interrupt */ |
1753 | rtl8xxxu_write16_clear(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); |
1754 | |
1755 | /* release WLON reset */ |
1756 | rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); |
1757 | |
1758 | /* turn off MAC by HW state machine */ |
1759 | rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_OFF); |
1760 | |
1761 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
1762 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
1763 | if ((val32 & APS_FSMCO_MAC_OFF) == 0) |
1764 | break; |
1765 | |
1766 | udelay(10); |
1767 | } |
1768 | |
1769 | if (!count) |
1770 | return -EBUSY; |
1771 | |
1772 | /* analog Ips to digital, 1:isolation */ |
1773 | rtl8xxxu_write8_set(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); |
1774 | |
1775 | /* disable LDOA12 MACRO block */ |
1776 | rtl8xxxu_write8_clear(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); |
1777 | |
1778 | return 0; |
1779 | } |
1780 | |
1781 | static int rtl8192fu_emu_to_disabled(struct rtl8xxxu_priv *priv) |
1782 | { |
1783 | u16 val16; |
1784 | |
1785 | /* SOP option to disable BG/MB */ |
1786 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, val: 0x20); |
1787 | |
1788 | /* 0x04[12:11] = 2b'01 enable WL suspend */ |
1789 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
1790 | val16 &= ~APS_FSMCO_PCIE; |
1791 | val16 |= APS_FSMCO_HW_SUSPEND; |
1792 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val: val16); |
1793 | |
1794 | /* enable GPIO9 as EXT WAKEUP */ |
1795 | rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16)); |
1796 | |
1797 | return 0; |
1798 | } |
1799 | |
1800 | static int rtl8192fu_active_to_lps(struct rtl8xxxu_priv *priv) |
1801 | { |
1802 | struct device *dev = &priv->udev->dev; |
1803 | u16 val16; |
1804 | u32 val32; |
1805 | int retry; |
1806 | |
1807 | /* Tx Pause */ |
1808 | rtl8xxxu_write8(priv, REG_TXPAUSE, val: 0xff); |
1809 | |
1810 | retry = 100; |
1811 | |
1812 | /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ |
1813 | do { |
1814 | val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); |
1815 | if (!val32) |
1816 | break; |
1817 | |
1818 | udelay(10); |
1819 | } while (retry--); |
1820 | |
1821 | if (!retry) { |
1822 | dev_warn(dev, "%s: Failed to flush TX queue\n" , __func__); |
1823 | return -EBUSY; |
1824 | } |
1825 | |
1826 | /* Disable CCK and OFDM, clock gated */ |
1827 | rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); |
1828 | |
1829 | udelay(2); |
1830 | |
1831 | /* Whole BB is reset */ |
1832 | rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BB_GLB_RSTN); |
1833 | |
1834 | /* Reset MAC TRX */ |
1835 | val16 = rtl8xxxu_read16(priv, REG_CR); |
1836 | val16 &= 0xff00; |
1837 | val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE; |
1838 | val16 &= ~CR_SECURITY_ENABLE; |
1839 | rtl8xxxu_write16(priv, REG_CR, val: val16); |
1840 | |
1841 | /* Respond TxOK to scheduler */ |
1842 | rtl8xxxu_write8_set(priv, REG_DUAL_TSF_RST, DUAL_TSF_TX_OK); |
1843 | |
1844 | return 0; |
1845 | } |
1846 | |
1847 | static int rtl8192fu_power_on(struct rtl8xxxu_priv *priv) |
1848 | { |
1849 | u16 val16; |
1850 | int ret; |
1851 | |
1852 | rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, val: 0x80); |
1853 | |
1854 | rtl8192fu_disabled_to_emu(priv); |
1855 | |
1856 | ret = rtl8192fu_emu_to_active(priv); |
1857 | if (ret) |
1858 | return ret; |
1859 | |
1860 | rtl8xxxu_write16(priv, REG_CR, val: 0); |
1861 | |
1862 | val16 = rtl8xxxu_read16(priv, REG_CR); |
1863 | |
1864 | val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
1865 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
1866 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
1867 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE; |
1868 | rtl8xxxu_write16(priv, REG_CR, val: val16); |
1869 | |
1870 | return 0; |
1871 | } |
1872 | |
1873 | static void rtl8192fu_power_off(struct rtl8xxxu_priv *priv) |
1874 | { |
1875 | rtl8xxxu_flush_fifo(priv); |
1876 | |
1877 | /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ |
1878 | rtl8xxxu_write8_clear(priv, REG_TX_REPORT_CTRL, |
1879 | TX_REPORT_CTRL_TIMER_ENABLE); |
1880 | |
1881 | /* stop rx */ |
1882 | rtl8xxxu_write8(priv, REG_CR, val: 0x00); |
1883 | |
1884 | rtl8192fu_active_to_lps(priv); |
1885 | |
1886 | /* Reset Firmware if running in RAM */ |
1887 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) |
1888 | rtl8xxxu_firmware_self_reset(priv); |
1889 | |
1890 | /* Reset MCU */ |
1891 | rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); |
1892 | |
1893 | /* Reset MCU ready status */ |
1894 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val: 0x00); |
1895 | |
1896 | rtl8192fu_active_to_emu(priv); |
1897 | rtl8192fu_emu_to_disabled(priv); |
1898 | } |
1899 | |
1900 | static void rtl8192f_reset_8051(struct rtl8xxxu_priv *priv) |
1901 | { |
1902 | rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); |
1903 | |
1904 | rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0)); |
1905 | |
1906 | rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); |
1907 | |
1908 | rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); |
1909 | |
1910 | rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0)); |
1911 | |
1912 | rtl8xxxu_write16_set(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); |
1913 | } |
1914 | |
1915 | static void rtl8192f_enable_rf(struct rtl8xxxu_priv *priv) |
1916 | { |
1917 | u32 val32; |
1918 | |
1919 | rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); |
1920 | |
1921 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
1922 | val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); |
1923 | val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | |
1924 | OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; |
1925 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: val32); |
1926 | |
1927 | rtl8xxxu_write8(priv, REG_TXPAUSE, val: 0x00); |
1928 | } |
1929 | |
1930 | static void rtl8192f_disable_rf(struct rtl8xxxu_priv *priv) |
1931 | { |
1932 | u32 val32; |
1933 | |
1934 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
1935 | val32 &= ~OFDM_RF_PATH_TX_MASK; |
1936 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val: val32); |
1937 | |
1938 | /* Power down RF module */ |
1939 | rtl8xxxu_write_rfreg(priv, path: RF_A, RF6052_REG_AC, data: 0); |
1940 | } |
1941 | |
1942 | static void rtl8192f_usb_quirks(struct rtl8xxxu_priv *priv) |
1943 | { |
1944 | u16 val16; |
1945 | |
1946 | rtl8xxxu_gen2_usb_quirks(priv); |
1947 | |
1948 | val16 = rtl8xxxu_read16(priv, REG_CR); |
1949 | val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); |
1950 | rtl8xxxu_write16(priv, REG_CR, val: val16); |
1951 | } |
1952 | |
1953 | #define XTAL1 GENMASK(6, 1) |
1954 | #define XTAL0 GENMASK(30, 25) |
1955 | |
1956 | static void rtl8192f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) |
1957 | { |
1958 | struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; |
1959 | u32 xtal1, xtal0; |
1960 | |
1961 | if (crystal_cap == cfo->crystal_cap) |
1962 | return; |
1963 | |
1964 | xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL); |
1965 | xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); |
1966 | |
1967 | dev_dbg(&priv->udev->dev, |
1968 | "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n" , |
1969 | __func__, |
1970 | cfo->crystal_cap, |
1971 | u32_get_bits(xtal1, XTAL1), |
1972 | u32_get_bits(xtal0, XTAL0), |
1973 | crystal_cap); |
1974 | |
1975 | u32p_replace_bits(p: &xtal1, val: crystal_cap, XTAL1); |
1976 | u32p_replace_bits(p: &xtal0, val: crystal_cap, XTAL0); |
1977 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, val: xtal1); |
1978 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val: xtal0); |
1979 | |
1980 | cfo->crystal_cap = crystal_cap; |
1981 | } |
1982 | |
1983 | static s8 (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) |
1984 | { |
1985 | struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; |
1986 | u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l; |
1987 | u8 vga_idx = phy_stats0->vga; |
1988 | s8 rx_pwr_all; |
1989 | |
1990 | switch (lna_idx) { |
1991 | case 7: |
1992 | rx_pwr_all = -44 - (2 * vga_idx); |
1993 | break; |
1994 | case 5: |
1995 | rx_pwr_all = -28 - (2 * vga_idx); |
1996 | break; |
1997 | case 3: |
1998 | rx_pwr_all = -10 - (2 * vga_idx); |
1999 | break; |
2000 | case 0: |
2001 | rx_pwr_all = 14 - (2 * vga_idx); |
2002 | break; |
2003 | default: |
2004 | rx_pwr_all = 0; |
2005 | break; |
2006 | } |
2007 | |
2008 | return rx_pwr_all; |
2009 | } |
2010 | |
2011 | static int rtl8192fu_led_brightness_set(struct led_classdev *led_cdev, |
2012 | enum led_brightness brightness) |
2013 | { |
2014 | struct rtl8xxxu_priv *priv = container_of(led_cdev, |
2015 | struct rtl8xxxu_priv, |
2016 | led_cdev); |
2017 | u32 ledcfg; |
2018 | |
2019 | /* Values obtained by observing the USB traffic from the Windows driver. */ |
2020 | rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, val: 0x20080); |
2021 | rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, val: 0x1b0000); |
2022 | |
2023 | ledcfg = rtl8xxxu_read32(priv, REG_LEDCFG0); |
2024 | |
2025 | /* Comfast CF-826F uses LED1. Asus USB-N13 C1 uses LED0. Set both. */ |
2026 | |
2027 | u32p_replace_bits(p: &ledcfg, LED_GPIO_ENABLE, LEDCFG0_LED2EN); |
2028 | u32p_replace_bits(p: &ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED0_IO_MODE); |
2029 | u32p_replace_bits(p: &ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED1_IO_MODE); |
2030 | |
2031 | if (brightness == LED_OFF) { |
2032 | u32p_replace_bits(p: &ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); |
2033 | u32p_replace_bits(p: &ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); |
2034 | u32p_replace_bits(p: &ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); |
2035 | u32p_replace_bits(p: &ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); |
2036 | } else if (brightness == LED_ON) { |
2037 | u32p_replace_bits(p: &ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); |
2038 | u32p_replace_bits(p: &ledcfg, LED_SW_ON, LEDCFG0_LED0SV); |
2039 | u32p_replace_bits(p: &ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); |
2040 | u32p_replace_bits(p: &ledcfg, LED_SW_ON, LEDCFG0_LED1SV); |
2041 | } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { |
2042 | u32p_replace_bits(p: &ledcfg, LED_MODE_TX_OR_RX_EVENTS, |
2043 | LEDCFG0_LED0CM); |
2044 | u32p_replace_bits(p: &ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); |
2045 | u32p_replace_bits(p: &ledcfg, LED_MODE_TX_OR_RX_EVENTS, |
2046 | LEDCFG0_LED1CM); |
2047 | u32p_replace_bits(p: &ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); |
2048 | } |
2049 | |
2050 | rtl8xxxu_write32(priv, REG_LEDCFG0, val: ledcfg); |
2051 | |
2052 | return 0; |
2053 | } |
2054 | |
2055 | struct rtl8xxxu_fileops rtl8192fu_fops = { |
2056 | .identify_chip = rtl8192fu_identify_chip, |
2057 | .parse_efuse = rtl8192fu_parse_efuse, |
2058 | .load_firmware = rtl8192fu_load_firmware, |
2059 | .power_on = rtl8192fu_power_on, |
2060 | .power_off = rtl8192fu_power_off, |
2061 | .read_efuse = rtl8xxxu_read_efuse, |
2062 | .reset_8051 = rtl8192f_reset_8051, |
2063 | .llt_init = rtl8xxxu_auto_llt_table, |
2064 | .init_phy_bb = rtl8192fu_init_phy_bb, |
2065 | .init_phy_rf = rtl8192fu_init_phy_rf, |
2066 | .phy_lc_calibrate = rtl8192f_phy_lc_calibrate, |
2067 | .phy_iq_calibrate = rtl8192fu_phy_iq_calibrate, |
2068 | .config_channel = rtl8192fu_config_channel, |
2069 | .parse_rx_desc = rtl8xxxu_parse_rxdesc24, |
2070 | .parse_phystats = jaguar2_rx_parse_phystats, |
2071 | .init_aggregation = rtl8192fu_init_aggregation, |
2072 | .init_burst = rtl8xxxu_init_burst, |
2073 | .enable_rf = rtl8192f_enable_rf, |
2074 | .disable_rf = rtl8192f_disable_rf, |
2075 | .usb_quirks = rtl8192f_usb_quirks, |
2076 | .set_tx_power = rtl8192f_set_tx_power, |
2077 | .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, |
2078 | .report_connect = rtl8xxxu_gen2_report_connect, |
2079 | .report_rssi = rtl8xxxu_gen2_report_rssi, |
2080 | .fill_txdesc = rtl8xxxu_fill_txdesc_v2, |
2081 | .set_crystal_cap = rtl8192f_set_crystal_cap, |
2082 | .cck_rssi = rtl8192f_cck_rssi, |
2083 | .led_classdev_brightness_set = rtl8192fu_led_brightness_set, |
2084 | .writeN_block_size = 254, |
2085 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), |
2086 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), |
2087 | .has_tx_report = 1, |
2088 | .gen2_thermal_meter = 1, |
2089 | .needs_full_init = 1, |
2090 | .init_reg_rxfltmap = 1, |
2091 | .init_reg_pkt_life_time = 1, |
2092 | .init_reg_hmtfr = 1, |
2093 | .ampdu_max_time = 0x5e, |
2094 | .ustime_tsf_edca = 0x50, |
2095 | .max_aggr_num = 0x1f1f, |
2096 | .supports_ap = 1, |
2097 | .max_macid_num = 128, |
2098 | .max_sec_cam_num = 64, |
2099 | .trxff_boundary = 0x3f3f, |
2100 | .pbp_rx = PBP_PAGE_SIZE_256, |
2101 | .pbp_tx = PBP_PAGE_SIZE_256, |
2102 | .mactable = rtl8192f_mac_init_table, |
2103 | .total_page_num = TX_TOTAL_PAGE_NUM_8192F, |
2104 | .page_num_hi = TX_PAGE_NUM_HI_PQ_8192F, |
2105 | .page_num_lo = TX_PAGE_NUM_LO_PQ_8192F, |
2106 | .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192F, |
2107 | }; |
2108 | |