1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4#ifndef __RTL_WIFI_H__
5#define __RTL_WIFI_H__
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9#include <linux/sched.h>
10#include <linux/firmware.h>
11#include <linux/etherdevice.h>
12#include <linux/vmalloc.h>
13#include <linux/usb.h>
14#include <net/mac80211.h>
15#include <linux/completion.h>
16#include <linux/bitfield.h>
17#include "debug.h"
18
19#define MASKBYTE0 0xff
20#define MASKBYTE1 0xff00
21#define MASKBYTE2 0xff0000
22#define MASKBYTE3 0xff000000
23#define MASKHWORD 0xffff0000
24#define MASKLWORD 0x0000ffff
25#define MASKDWORD 0xffffffff
26#define MASK12BITS 0xfff
27#define MASKH4BITS 0xf0000000
28#define MASKOFDM_D 0xffc00000
29#define MASKCCK 0x3f3f3f3f
30
31#define MASK4BITS 0x0f
32#define MASK20BITS 0xfffff
33#define RFREG_OFFSET_MASK 0xfffff
34
35#define MASKBYTE0 0xff
36#define MASKBYTE1 0xff00
37#define MASKBYTE2 0xff0000
38#define MASKBYTE3 0xff000000
39#define MASKHWORD 0xffff0000
40#define MASKLWORD 0x0000ffff
41#define MASKDWORD 0xffffffff
42#define MASK12BITS 0xfff
43#define MASKH4BITS 0xf0000000
44#define MASKOFDM_D 0xffc00000
45#define MASKCCK 0x3f3f3f3f
46
47#define MASK4BITS 0x0f
48#define MASK20BITS 0xfffff
49#define RFREG_OFFSET_MASK 0xfffff
50
51#define RF_CHANGE_BY_INIT 0
52#define RF_CHANGE_BY_IPS BIT(28)
53#define RF_CHANGE_BY_PS BIT(29)
54#define RF_CHANGE_BY_HW BIT(30)
55#define RF_CHANGE_BY_SW BIT(31)
56
57#define IQK_ADDA_REG_NUM 16
58#define IQK_MAC_REG_NUM 4
59#define IQK_THRESHOLD 8
60
61#define MAX_KEY_LEN 61
62#define KEY_BUF_SIZE 5
63
64/* QoS related. */
65/*aci: 0x00 Best Effort*/
66/*aci: 0x01 Background*/
67/*aci: 0x10 Video*/
68/*aci: 0x11 Voice*/
69/*Max: define total number.*/
70#define AC0_BE 0
71#define AC1_BK 1
72#define AC2_VI 2
73#define AC3_VO 3
74#define AC_MAX 4
75#define QOS_QUEUE_NUM 4
76#define RTL_MAC80211_NUM_QUEUE 5
77#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
78#define RTL_USB_MAX_RX_COUNT 100
79#define QBSS_LOAD_SIZE 5
80#define MAX_WMMELE_LENGTH 64
81#define ASPM_L1_LATENCY 7
82
83#define TOTAL_CAM_ENTRY 32
84
85/*slot time for 11g. */
86#define RTL_SLOT_TIME_9 9
87#define RTL_SLOT_TIME_20 20
88
89/*related to tcp/ip. */
90#define SNAP_SIZE 6
91#define PROTOC_TYPE_SIZE 2
92
93/*related with 802.11 frame*/
94#define MAC80211_3ADDR_LEN 24
95#define MAC80211_4ADDR_LEN 30
96
97#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
98#define CHANNEL_MAX_NUMBER_2G 14
99#define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
100 *"phy_GetChnlGroup8812A" and
101 * "Hal_ReadTxPowerInfo8812A"
102 */
103#define CHANNEL_MAX_NUMBER_5G_80M 7
104#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
105#define MAX_PG_GROUP 13
106#define CHANNEL_GROUP_MAX_2G 3
107#define CHANNEL_GROUP_IDX_5GL 3
108#define CHANNEL_GROUP_IDX_5GM 6
109#define CHANNEL_GROUP_IDX_5GH 9
110#define CHANNEL_GROUP_MAX_5G 9
111#define AVG_THERMAL_NUM 8
112#define AVG_THERMAL_NUM_88E 4
113#define AVG_THERMAL_NUM_8723BE 4
114#define MAX_TID_COUNT 9
115
116/* for early mode */
117#define FCS_LEN 4
118#define EM_HDR_LEN 8
119
120enum rtl8192c_h2c_cmd {
121 H2C_AP_OFFLOAD = 0,
122 H2C_SETPWRMODE = 1,
123 H2C_JOINBSSRPT = 2,
124 H2C_RSVDPAGE = 3,
125 H2C_RSSI_REPORT = 5,
126 H2C_RA_MASK = 6,
127 H2C_MACID_PS_MODE = 7,
128 H2C_P2P_PS_OFFLOAD = 8,
129 H2C_MAC_MODE_SEL = 9,
130 H2C_PWRM = 15,
131 H2C_P2P_PS_CTW_CMD = 24,
132 MAX_H2CCMD
133};
134
135enum {
136 H2C_BT_PORT_ID = 0x71,
137};
138
139enum rtl_c2h_evt_v1 {
140 C2H_DBG = 0,
141 C2H_LB = 1,
142 C2H_TXBF = 2,
143 C2H_TX_REPORT = 3,
144 C2H_BT_INFO = 9,
145 C2H_BT_MP = 11,
146 C2H_RA_RPT = 12,
147
148 C2H_FW_SWCHNL = 0x10,
149 C2H_IQK_FINISH = 0x11,
150
151 C2H_EXT_V2 = 0xFF,
152};
153
154enum rtl_c2h_evt_v2 {
155 C2H_V2_CCX_RPT = 0x0F,
156};
157
158#define GET_C2H_CMD_ID(c2h) ({u8 *__c2h = c2h; __c2h[0]; })
159#define GET_C2H_SEQ(c2h) ({u8 *__c2h = c2h; __c2h[1]; })
160#define C2H_DATA_OFFSET 2
161#define GET_C2H_DATA_PTR(c2h) ({u8 *__c2h = c2h; &__c2h[C2H_DATA_OFFSET]; })
162
163#define GET_TX_REPORT_SN_V1(c2h) (c2h[6])
164#define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0)
165#define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F)
166#define GET_TX_REPORT_SN_V2(c2h) (c2h[6])
167#define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0)
168#define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F)
169
170#define MAX_TX_COUNT 4
171#define MAX_REGULATION_NUM 4
172#define MAX_RF_PATH_NUM 4
173#define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
174#define MAX_2_4G_BANDWIDTH_NUM 4
175#define MAX_5G_BANDWIDTH_NUM 4
176#define MAX_RF_PATH 4
177#define MAX_CHNL_GROUP_24G 6
178#define MAX_CHNL_GROUP_5G 14
179
180#define TX_PWR_BY_RATE_NUM_BAND 2
181#define TX_PWR_BY_RATE_NUM_RF 4
182#define TX_PWR_BY_RATE_NUM_SECTION 12
183#define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */
184#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
185#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
186
187#define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
188
189#define DEL_SW_IDX_SZ 30
190
191/* For now, it's just for 8192ee
192 * but not OK yet, keep it 0
193 */
194#define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
195
196enum rf_tx_num {
197 RF_1TX = 0,
198 RF_2TX,
199 RF_MAX_TX_NUM,
200 RF_TX_NUM_NONIMPLEMENT,
201};
202
203#define PACKET_NORMAL 0
204#define PACKET_DHCP 1
205#define PACKET_ARP 2
206#define PACKET_EAPOL 3
207
208#define MAX_SUPPORT_WOL_PATTERN_NUM 16
209#define RSVD_WOL_PATTERN_NUM 1
210#define WKFMCAM_ADDR_NUM 6
211#define WKFMCAM_SIZE 24
212
213#define MAX_WOL_BIT_MASK_SIZE 16
214/* MIN LEN keeps 13 here */
215#define MIN_WOL_PATTERN_SIZE 13
216#define MAX_WOL_PATTERN_SIZE 128
217
218#define WAKE_ON_MAGIC_PACKET BIT(0)
219#define WAKE_ON_PATTERN_MATCH BIT(1)
220
221#define WOL_REASON_PTK_UPDATE BIT(0)
222#define WOL_REASON_GTK_UPDATE BIT(1)
223#define WOL_REASON_DISASSOC BIT(2)
224#define WOL_REASON_DEAUTH BIT(3)
225#define WOL_REASON_AP_LOST BIT(4)
226#define WOL_REASON_MAGIC_PKT BIT(5)
227#define WOL_REASON_UNICAST_PKT BIT(6)
228#define WOL_REASON_PATTERN_PKT BIT(7)
229#define WOL_REASON_RTD3_SSID_MATCH BIT(8)
230#define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
231#define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
232
233struct rtlwifi_firmware_header {
234 __le16 signature;
235 u8 category;
236 u8 function;
237 __le16 version;
238 u8 subversion;
239 u8 rsvd1;
240 u8 month;
241 u8 date;
242 u8 hour;
243 u8 minute;
244 __le16 ramcodesize;
245 __le16 rsvd2;
246 __le32 svnindex;
247 __le32 rsvd3;
248 __le32 rsvd4;
249 __le32 rsvd5;
250};
251
252struct txpower_info_2g {
253 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
254 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
255 /*If only one tx, only BW20 and OFDM are used.*/
256 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
260 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
261 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
262};
263
264struct txpower_info_5g {
265 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
266 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
267 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
268 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
269 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
270 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
271 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
272};
273
274enum rate_section {
275 CCK = 0,
276 OFDM,
277 HT_MCS0_MCS7,
278 HT_MCS8_MCS15,
279 VHT_1SSMCS0_1SSMCS9,
280 VHT_2SSMCS0_2SSMCS9,
281 MAX_RATE_SECTION,
282};
283
284enum intf_type {
285 INTF_PCI = 0,
286 INTF_USB = 1,
287};
288
289enum radio_path {
290 RF90_PATH_A = 0,
291 RF90_PATH_B = 1,
292 RF90_PATH_C = 2,
293 RF90_PATH_D = 3,
294};
295
296enum radio_mask {
297 RF_MASK_A = BIT(0),
298 RF_MASK_B = BIT(1),
299 RF_MASK_C = BIT(2),
300 RF_MASK_D = BIT(3),
301};
302
303enum regulation_txpwr_lmt {
304 TXPWR_LMT_FCC = 0,
305 TXPWR_LMT_MKK = 1,
306 TXPWR_LMT_ETSI = 2,
307 TXPWR_LMT_WW = 3,
308
309 TXPWR_LMT_MAX_REGULATION_NUM = 4
310};
311
312enum rt_eeprom_type {
313 EEPROM_93C46,
314 EEPROM_93C56,
315 EEPROM_BOOT_EFUSE,
316};
317
318enum ttl_status {
319 RTL_STATUS_INTERFACE_START = 0,
320};
321
322enum hardware_type {
323 HARDWARE_TYPE_RTL8192E,
324 HARDWARE_TYPE_RTL8192U,
325 HARDWARE_TYPE_RTL8192SE,
326 HARDWARE_TYPE_RTL8192SU,
327 HARDWARE_TYPE_RTL8192CE,
328 HARDWARE_TYPE_RTL8192CU,
329 HARDWARE_TYPE_RTL8192DE,
330 HARDWARE_TYPE_RTL8192DU,
331 HARDWARE_TYPE_RTL8723AE,
332 HARDWARE_TYPE_RTL8723U,
333 HARDWARE_TYPE_RTL8188EE,
334 HARDWARE_TYPE_RTL8723BE,
335 HARDWARE_TYPE_RTL8192EE,
336 HARDWARE_TYPE_RTL8821AE,
337 HARDWARE_TYPE_RTL8812AE,
338 HARDWARE_TYPE_RTL8822BE,
339
340 /* keep it last */
341 HARDWARE_TYPE_NUM
342};
343
344#define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
345#define IS_NEW_GENERATION_IC(rtlpriv) \
346 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
347#define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
348 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
349#define IS_HARDWARE_TYPE_8812(rtlpriv) \
350 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
351#define IS_HARDWARE_TYPE_8821(rtlpriv) \
352 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
353#define IS_HARDWARE_TYPE_8723A(rtlpriv) \
354 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
355#define IS_HARDWARE_TYPE_8723B(rtlpriv) \
356 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
357#define IS_HARDWARE_TYPE_8192E(rtlpriv) \
358 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
359#define IS_HARDWARE_TYPE_8822B(rtlpriv) \
360 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
361
362#define RX_HAL_IS_CCK_RATE(rxmcs) \
363 ((rxmcs) == DESC_RATE1M || \
364 (rxmcs) == DESC_RATE2M || \
365 (rxmcs) == DESC_RATE5_5M || \
366 (rxmcs) == DESC_RATE11M)
367
368enum scan_operation_backup_opt {
369 SCAN_OPT_BACKUP = 0,
370 SCAN_OPT_BACKUP_BAND0 = 0,
371 SCAN_OPT_BACKUP_BAND1,
372 SCAN_OPT_RESTORE,
373 SCAN_OPT_MAX
374};
375
376/*RF state.*/
377enum rf_pwrstate {
378 ERFON,
379 ERFSLEEP,
380 ERFOFF
381};
382
383struct bb_reg_def {
384 u32 rfintfs;
385 u32 rfintfi;
386 u32 rfintfo;
387 u32 rfintfe;
388 u32 rf3wire_offset;
389 u32 rflssi_select;
390 u32 rftxgain_stage;
391 u32 rfhssi_para1;
392 u32 rfhssi_para2;
393 u32 rfsw_ctrl;
394 u32 rfagc_control1;
395 u32 rfagc_control2;
396 u32 rfrxiq_imbal;
397 u32 rfrx_afe;
398 u32 rftxiq_imbal;
399 u32 rftx_afe;
400 u32 rf_rb; /* rflssi_readback */
401 u32 rf_rbpi; /* rflssi_readbackpi */
402};
403
404enum io_type {
405 IO_CMD_PAUSE_DM_BY_SCAN = 0,
406 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
407 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
408 IO_CMD_RESUME_DM_BY_SCAN = 2,
409};
410
411enum hw_variables {
412 HW_VAR_ETHER_ADDR = 0x0,
413 HW_VAR_MULTICAST_REG = 0x1,
414 HW_VAR_BASIC_RATE = 0x2,
415 HW_VAR_BSSID = 0x3,
416 HW_VAR_MEDIA_STATUS = 0x4,
417 HW_VAR_SECURITY_CONF = 0x5,
418 HW_VAR_BEACON_INTERVAL = 0x6,
419 HW_VAR_ATIM_WINDOW = 0x7,
420 HW_VAR_LISTEN_INTERVAL = 0x8,
421 HW_VAR_CS_COUNTER = 0x9,
422 HW_VAR_DEFAULTKEY0 = 0xa,
423 HW_VAR_DEFAULTKEY1 = 0xb,
424 HW_VAR_DEFAULTKEY2 = 0xc,
425 HW_VAR_DEFAULTKEY3 = 0xd,
426 HW_VAR_SIFS = 0xe,
427 HW_VAR_R2T_SIFS = 0xf,
428 HW_VAR_DIFS = 0x10,
429 HW_VAR_EIFS = 0x11,
430 HW_VAR_SLOT_TIME = 0x12,
431 HW_VAR_ACK_PREAMBLE = 0x13,
432 HW_VAR_CW_CONFIG = 0x14,
433 HW_VAR_CW_VALUES = 0x15,
434 HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
435 HW_VAR_CONTENTION_WINDOW = 0x17,
436 HW_VAR_RETRY_COUNT = 0x18,
437 HW_VAR_TR_SWITCH = 0x19,
438 HW_VAR_COMMAND = 0x1a,
439 HW_VAR_WPA_CONFIG = 0x1b,
440 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
441 HW_VAR_SHORTGI_DENSITY = 0x1d,
442 HW_VAR_AMPDU_FACTOR = 0x1e,
443 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
444 HW_VAR_AC_PARAM = 0x20,
445 HW_VAR_ACM_CTRL = 0x21,
446 HW_VAR_DIS_REQ_QSIZE = 0x22,
447 HW_VAR_CCX_CHNL_LOAD = 0x23,
448 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
449 HW_VAR_CCX_CLM_NHM = 0x25,
450 HW_VAR_TXOPLIMIT = 0x26,
451 HW_VAR_TURBO_MODE = 0x27,
452 HW_VAR_RF_STATE = 0x28,
453 HW_VAR_RF_OFF_BY_HW = 0x29,
454 HW_VAR_BUS_SPEED = 0x2a,
455 HW_VAR_SET_DEV_POWER = 0x2b,
456
457 HW_VAR_RCR = 0x2c,
458 HW_VAR_RATR_0 = 0x2d,
459 HW_VAR_RRSR = 0x2e,
460 HW_VAR_CPU_RST = 0x2f,
461 HW_VAR_CHECK_BSSID = 0x30,
462 HW_VAR_LBK_MODE = 0x31,
463 HW_VAR_AES_11N_FIX = 0x32,
464 HW_VAR_USB_RX_AGGR = 0x33,
465 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
466 HW_VAR_RETRY_LIMIT = 0x35,
467 HW_VAR_INIT_TX_RATE = 0x36,
468 HW_VAR_TX_RATE_REG = 0x37,
469 HW_VAR_EFUSE_USAGE = 0x38,
470 HW_VAR_EFUSE_BYTES = 0x39,
471 HW_VAR_AUTOLOAD_STATUS = 0x3a,
472 HW_VAR_RF_2R_DISABLE = 0x3b,
473 HW_VAR_SET_RPWM = 0x3c,
474 HW_VAR_H2C_FW_PWRMODE = 0x3d,
475 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
476 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
477 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
478 HW_VAR_FW_PSMODE_STATUS = 0x41,
479 HW_VAR_INIT_RTS_RATE = 0x42,
480 HW_VAR_RESUME_CLK_ON = 0x43,
481 HW_VAR_FW_LPS_ACTION = 0x44,
482 HW_VAR_1X1_RECV_COMBINE = 0x45,
483 HW_VAR_STOP_SEND_BEACON = 0x46,
484 HW_VAR_TSF_TIMER = 0x47,
485 HW_VAR_IO_CMD = 0x48,
486
487 HW_VAR_RF_RECOVERY = 0x49,
488 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
489 HW_VAR_WF_MASK = 0x4b,
490 HW_VAR_WF_CRC = 0x4c,
491 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
492 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
493 HW_VAR_RESET_WFCRC = 0x4f,
494
495 HW_VAR_HANDLE_FW_C2H = 0x50,
496 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
497 HW_VAR_AID = 0x52,
498 HW_VAR_HW_SEQ_ENABLE = 0x53,
499 HW_VAR_CORRECT_TSF = 0x54,
500 HW_VAR_BCN_VALID = 0x55,
501 HW_VAR_FWLPS_RF_ON = 0x56,
502 HW_VAR_DUAL_TSF_RST = 0x57,
503 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
504 HW_VAR_INT_MIGRATION = 0x59,
505 HW_VAR_INT_AC = 0x5a,
506 HW_VAR_RF_TIMING = 0x5b,
507
508 HAL_DEF_WOWLAN = 0x5c,
509 HW_VAR_MRC = 0x5d,
510 HW_VAR_KEEP_ALIVE = 0x5e,
511 HW_VAR_NAV_UPPER = 0x5f,
512
513 HW_VAR_MGT_FILTER = 0x60,
514 HW_VAR_CTRL_FILTER = 0x61,
515 HW_VAR_DATA_FILTER = 0x62,
516};
517
518enum rt_media_status {
519 RT_MEDIA_DISCONNECT = 0,
520 RT_MEDIA_CONNECT = 1
521};
522
523enum rt_oem_id {
524 RT_CID_DEFAULT = 0,
525 RT_CID_8187_ALPHA0 = 1,
526 RT_CID_8187_SERCOMM_PS = 2,
527 RT_CID_8187_HW_LED = 3,
528 RT_CID_8187_NETGEAR = 4,
529 RT_CID_WHQL = 5,
530 RT_CID_819X_CAMEO = 6,
531 RT_CID_819X_RUNTOP = 7,
532 RT_CID_819X_SENAO = 8,
533 RT_CID_TOSHIBA = 9,
534 RT_CID_819X_NETCORE = 10,
535 RT_CID_NETTRONIX = 11,
536 RT_CID_DLINK = 12,
537 RT_CID_PRONET = 13,
538 RT_CID_COREGA = 14,
539 RT_CID_819X_ALPHA = 15,
540 RT_CID_819X_SITECOM = 16,
541 RT_CID_CCX = 17,
542 RT_CID_819X_LENOVO = 18,
543 RT_CID_819X_QMI = 19,
544 RT_CID_819X_EDIMAX_BELKIN = 20,
545 RT_CID_819X_SERCOMM_BELKIN = 21,
546 RT_CID_819X_CAMEO1 = 22,
547 RT_CID_819X_MSI = 23,
548 RT_CID_819X_ACER = 24,
549 RT_CID_819X_HP = 27,
550 RT_CID_819X_CLEVO = 28,
551 RT_CID_819X_ARCADYAN_BELKIN = 29,
552 RT_CID_819X_SAMSUNG = 30,
553 RT_CID_819X_WNC_COREGA = 31,
554 RT_CID_819X_FOXCOON = 32,
555 RT_CID_819X_DELL = 33,
556 RT_CID_819X_PRONETS = 34,
557 RT_CID_819X_EDIMAX_ASUS = 35,
558 RT_CID_NETGEAR = 36,
559 RT_CID_PLANEX = 37,
560 RT_CID_CC_C = 38,
561 RT_CID_LENOVO_CHINA = 40,
562};
563
564enum hw_descs {
565 HW_DESC_OWN,
566 HW_DESC_RXOWN,
567 HW_DESC_TX_NEXTDESC_ADDR,
568 HW_DESC_TXBUFF_ADDR,
569 HW_DESC_RXBUFF_ADDR,
570 HW_DESC_RXPKT_LEN,
571 HW_DESC_RXERO,
572 HW_DESC_RX_PREPARE,
573};
574
575enum prime_sc {
576 PRIME_CHNL_OFFSET_DONT_CARE = 0,
577 PRIME_CHNL_OFFSET_LOWER = 1,
578 PRIME_CHNL_OFFSET_UPPER = 2,
579};
580
581enum rf_type {
582 RF_1T1R = 0,
583 RF_1T2R = 1,
584 RF_2T2R = 2,
585 RF_2T2R_GREEN = 3,
586 RF_2T3R = 4,
587 RF_2T4R = 5,
588 RF_3T3R = 6,
589 RF_3T4R = 7,
590 RF_4T4R = 8,
591};
592
593enum ht_channel_width {
594 HT_CHANNEL_WIDTH_20 = 0,
595 HT_CHANNEL_WIDTH_20_40 = 1,
596 HT_CHANNEL_WIDTH_80 = 2,
597 HT_CHANNEL_WIDTH_MAX,
598};
599
600/* Ref: 802.11i spec D10.0 7.3.2.25.1
601 * Cipher Suites Encryption Algorithms
602 */
603enum rt_enc_alg {
604 NO_ENCRYPTION = 0,
605 WEP40_ENCRYPTION = 1,
606 TKIP_ENCRYPTION = 2,
607 RSERVED_ENCRYPTION = 3,
608 AESCCMP_ENCRYPTION = 4,
609 WEP104_ENCRYPTION = 5,
610 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
611};
612
613enum rtl_hal_state {
614 _HAL_STATE_STOP = 0,
615 _HAL_STATE_START = 1,
616};
617
618enum rtl_desc_rate {
619 DESC_RATE1M = 0x00,
620 DESC_RATE2M = 0x01,
621 DESC_RATE5_5M = 0x02,
622 DESC_RATE11M = 0x03,
623
624 DESC_RATE6M = 0x04,
625 DESC_RATE9M = 0x05,
626 DESC_RATE12M = 0x06,
627 DESC_RATE18M = 0x07,
628 DESC_RATE24M = 0x08,
629 DESC_RATE36M = 0x09,
630 DESC_RATE48M = 0x0a,
631 DESC_RATE54M = 0x0b,
632
633 DESC_RATEMCS0 = 0x0c,
634 DESC_RATEMCS1 = 0x0d,
635 DESC_RATEMCS2 = 0x0e,
636 DESC_RATEMCS3 = 0x0f,
637 DESC_RATEMCS4 = 0x10,
638 DESC_RATEMCS5 = 0x11,
639 DESC_RATEMCS6 = 0x12,
640 DESC_RATEMCS7 = 0x13,
641 DESC_RATEMCS8 = 0x14,
642 DESC_RATEMCS9 = 0x15,
643 DESC_RATEMCS10 = 0x16,
644 DESC_RATEMCS11 = 0x17,
645 DESC_RATEMCS12 = 0x18,
646 DESC_RATEMCS13 = 0x19,
647 DESC_RATEMCS14 = 0x1a,
648 DESC_RATEMCS15 = 0x1b,
649 DESC_RATEMCS15_SG = 0x1c,
650 DESC_RATEMCS32 = 0x20,
651
652 DESC_RATEVHT1SS_MCS0 = 0x2c,
653 DESC_RATEVHT1SS_MCS1 = 0x2d,
654 DESC_RATEVHT1SS_MCS2 = 0x2e,
655 DESC_RATEVHT1SS_MCS3 = 0x2f,
656 DESC_RATEVHT1SS_MCS4 = 0x30,
657 DESC_RATEVHT1SS_MCS5 = 0x31,
658 DESC_RATEVHT1SS_MCS6 = 0x32,
659 DESC_RATEVHT1SS_MCS7 = 0x33,
660 DESC_RATEVHT1SS_MCS8 = 0x34,
661 DESC_RATEVHT1SS_MCS9 = 0x35,
662 DESC_RATEVHT2SS_MCS0 = 0x36,
663 DESC_RATEVHT2SS_MCS1 = 0x37,
664 DESC_RATEVHT2SS_MCS2 = 0x38,
665 DESC_RATEVHT2SS_MCS3 = 0x39,
666 DESC_RATEVHT2SS_MCS4 = 0x3a,
667 DESC_RATEVHT2SS_MCS5 = 0x3b,
668 DESC_RATEVHT2SS_MCS6 = 0x3c,
669 DESC_RATEVHT2SS_MCS7 = 0x3d,
670 DESC_RATEVHT2SS_MCS8 = 0x3e,
671 DESC_RATEVHT2SS_MCS9 = 0x3f,
672};
673
674enum rtl_var_map {
675 /*reg map */
676 SYS_ISO_CTRL = 0,
677 SYS_FUNC_EN,
678 SYS_CLK,
679 MAC_RCR_AM,
680 MAC_RCR_AB,
681 MAC_RCR_ACRC32,
682 MAC_RCR_ACF,
683 MAC_RCR_AAP,
684 MAC_HIMR,
685 MAC_HIMRE,
686 MAC_HSISR,
687
688 /*efuse map */
689 EFUSE_TEST,
690 EFUSE_CTRL,
691 EFUSE_CLK,
692 EFUSE_CLK_CTRL,
693 EFUSE_PWC_EV12V,
694 EFUSE_FEN_ELDR,
695 EFUSE_LOADER_CLK_EN,
696 EFUSE_ANA8M,
697 EFUSE_HWSET_MAX_SIZE,
698 EFUSE_MAX_SECTION_MAP,
699 EFUSE_REAL_CONTENT_SIZE,
700 EFUSE_OOB_PROTECT_BYTES_LEN,
701 EFUSE_ACCESS,
702
703 /*CAM map */
704 RWCAM,
705 WCAMI,
706 RCAMO,
707 CAMDBG,
708 SECR,
709 SEC_CAM_NONE,
710 SEC_CAM_WEP40,
711 SEC_CAM_TKIP,
712 SEC_CAM_AES,
713 SEC_CAM_WEP104,
714
715 /*IMR map */
716 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
717 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
718 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
719 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
720 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
721 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
722 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
723 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
724 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
725 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
726 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
727 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
728 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
729 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
730 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
731 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
732 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
733 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
734 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
735 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
736 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
737 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
738 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
739 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
740 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
741 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
742 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
743 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
744 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
745 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
746 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
747 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
748 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
749 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
750 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
751 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
752 * RTL_IMR_TBDER)
753 */
754 RTL_IMR_C2HCMD, /*fw interrupt*/
755
756 /*CCK Rates, TxHT = 0 */
757 RTL_RC_CCK_RATE1M,
758 RTL_RC_CCK_RATE2M,
759 RTL_RC_CCK_RATE5_5M,
760 RTL_RC_CCK_RATE11M,
761
762 /*OFDM Rates, TxHT = 0 */
763 RTL_RC_OFDM_RATE6M,
764 RTL_RC_OFDM_RATE9M,
765 RTL_RC_OFDM_RATE12M,
766 RTL_RC_OFDM_RATE18M,
767 RTL_RC_OFDM_RATE24M,
768 RTL_RC_OFDM_RATE36M,
769 RTL_RC_OFDM_RATE48M,
770 RTL_RC_OFDM_RATE54M,
771
772 RTL_RC_HT_RATEMCS7,
773 RTL_RC_HT_RATEMCS15,
774
775 RTL_RC_VHT_RATE_1SS_MCS7,
776 RTL_RC_VHT_RATE_1SS_MCS8,
777 RTL_RC_VHT_RATE_1SS_MCS9,
778 RTL_RC_VHT_RATE_2SS_MCS7,
779 RTL_RC_VHT_RATE_2SS_MCS8,
780 RTL_RC_VHT_RATE_2SS_MCS9,
781
782 /*keep it last */
783 RTL_VAR_MAP_MAX,
784};
785
786/*Firmware PS mode for control LPS.*/
787enum _fw_ps_mode {
788 FW_PS_ACTIVE_MODE = 0,
789 FW_PS_MIN_MODE = 1,
790 FW_PS_MAX_MODE = 2,
791 FW_PS_DTIM_MODE = 3,
792 FW_PS_VOIP_MODE = 4,
793 FW_PS_UAPSD_WMM_MODE = 5,
794 FW_PS_UAPSD_MODE = 6,
795 FW_PS_IBSS_MODE = 7,
796 FW_PS_WWLAN_MODE = 8,
797 FW_PS_PM_RADIO_OFF = 9,
798 FW_PS_PM_CARD_DISABLE = 10,
799};
800
801enum rt_psmode {
802 EACTIVE, /*Active/Continuous access. */
803 EMAXPS, /*Max power save mode. */
804 EFASTPS, /*Fast power save mode. */
805 EAUTOPS, /*Auto power save mode. */
806};
807
808/*LED related.*/
809enum led_ctl_mode {
810 LED_CTL_POWER_ON = 1,
811 LED_CTL_LINK = 2,
812 LED_CTL_NO_LINK = 3,
813 LED_CTL_TX = 4,
814 LED_CTL_RX = 5,
815 LED_CTL_SITE_SURVEY = 6,
816 LED_CTL_POWER_OFF = 7,
817 LED_CTL_START_TO_LINK = 8,
818 LED_CTL_START_WPS = 9,
819 LED_CTL_STOP_WPS = 10,
820};
821
822enum rtl_led_pin {
823 LED_PIN_GPIO0,
824 LED_PIN_LED0,
825 LED_PIN_LED1,
826 LED_PIN_LED2
827};
828
829/*QoS related.*/
830/*acm implementation method.*/
831enum acm_method {
832 EACMWAY0_SWANDHW = 0,
833 EACMWAY1_HW = 1,
834 EACMWAY2_SW = 2,
835};
836
837enum macphy_mode {
838 SINGLEMAC_SINGLEPHY = 0,
839 DUALMAC_DUALPHY,
840 DUALMAC_SINGLEPHY,
841};
842
843enum band_type {
844 BAND_ON_2_4G = 0,
845 BAND_ON_5G,
846 BAND_ON_BOTH,
847 BANDMAX
848};
849
850/* aci/aifsn Field.
851 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
852 */
853union aci_aifsn {
854 u8 char_data;
855
856 struct {
857 u8 aifsn:4;
858 u8 acm:1;
859 u8 aci:2;
860 u8 reserved:1;
861 } f; /* Field */
862};
863
864/*mlme related.*/
865enum wireless_mode {
866 WIRELESS_MODE_UNKNOWN = 0x00,
867 WIRELESS_MODE_A = 0x01,
868 WIRELESS_MODE_B = 0x02,
869 WIRELESS_MODE_G = 0x04,
870 WIRELESS_MODE_AUTO = 0x08,
871 WIRELESS_MODE_N_24G = 0x10,
872 WIRELESS_MODE_N_5G = 0x20,
873 WIRELESS_MODE_AC_5G = 0x40,
874 WIRELESS_MODE_AC_24G = 0x80,
875 WIRELESS_MODE_AC_ONLY = 0x100,
876 WIRELESS_MODE_MAX = 0x800
877};
878
879#define IS_WIRELESS_MODE_A(wirelessmode) \
880 (wirelessmode == WIRELESS_MODE_A)
881#define IS_WIRELESS_MODE_B(wirelessmode) \
882 (wirelessmode == WIRELESS_MODE_B)
883#define IS_WIRELESS_MODE_G(wirelessmode) \
884 (wirelessmode == WIRELESS_MODE_G)
885#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
886 (wirelessmode == WIRELESS_MODE_N_24G)
887#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
888 (wirelessmode == WIRELESS_MODE_N_5G)
889
890enum ratr_table_mode {
891 RATR_INX_WIRELESS_NGB = 0,
892 RATR_INX_WIRELESS_NG = 1,
893 RATR_INX_WIRELESS_NB = 2,
894 RATR_INX_WIRELESS_N = 3,
895 RATR_INX_WIRELESS_GB = 4,
896 RATR_INX_WIRELESS_G = 5,
897 RATR_INX_WIRELESS_B = 6,
898 RATR_INX_WIRELESS_MC = 7,
899 RATR_INX_WIRELESS_A = 8,
900 RATR_INX_WIRELESS_AC_5N = 8,
901 RATR_INX_WIRELESS_AC_24N = 9,
902};
903
904enum ratr_table_mode_new {
905 RATEID_IDX_BGN_40M_2SS = 0,
906 RATEID_IDX_BGN_40M_1SS = 1,
907 RATEID_IDX_BGN_20M_2SS_BN = 2,
908 RATEID_IDX_BGN_20M_1SS_BN = 3,
909 RATEID_IDX_GN_N2SS = 4,
910 RATEID_IDX_GN_N1SS = 5,
911 RATEID_IDX_BG = 6,
912 RATEID_IDX_G = 7,
913 RATEID_IDX_B = 8,
914 RATEID_IDX_VHT_2SS = 9,
915 RATEID_IDX_VHT_1SS = 10,
916 RATEID_IDX_MIX1 = 11,
917 RATEID_IDX_MIX2 = 12,
918 RATEID_IDX_VHT_3SS = 13,
919 RATEID_IDX_BGN_3SS = 14,
920};
921
922enum rtl_link_state {
923 MAC80211_NOLINK = 0,
924 MAC80211_LINKING = 1,
925 MAC80211_LINKED = 2,
926 MAC80211_LINKED_SCANNING = 3,
927};
928
929enum act_category {
930 ACT_CAT_QOS = 1,
931 ACT_CAT_DLS = 2,
932 ACT_CAT_BA = 3,
933 ACT_CAT_HT = 7,
934 ACT_CAT_WMM = 17,
935};
936
937enum ba_action {
938 ACT_ADDBAREQ = 0,
939 ACT_ADDBARSP = 1,
940 ACT_DELBA = 2,
941};
942
943enum rt_polarity_ctl {
944 RT_POLARITY_LOW_ACT = 0,
945 RT_POLARITY_HIGH_ACT = 1,
946};
947
948/* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
949enum fw_wow_reason_v2 {
950 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
951 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
952 FW_WOW_V2_DISASSOC_EVENT = 0x04,
953 FW_WOW_V2_DEAUTH_EVENT = 0x08,
954 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
955 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
956 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
957 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
958 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
959 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
960 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
961 FW_WOW_V2_REASON_MAX = 0xff,
962};
963
964enum wolpattern_type {
965 UNICAST_PATTERN = 0,
966 MULTICAST_PATTERN = 1,
967 BROADCAST_PATTERN = 2,
968 DONT_CARE_DA = 3,
969 UNKNOWN_TYPE = 4,
970};
971
972enum package_type {
973 PACKAGE_DEFAULT,
974 PACKAGE_QFN68,
975 PACKAGE_TFBGA90,
976 PACKAGE_TFBGA80,
977 PACKAGE_TFBGA79
978};
979
980enum rtl_spec_ver {
981 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
982 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
983 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */
984};
985
986enum dm_info_query {
987 DM_INFO_FA_OFDM,
988 DM_INFO_FA_CCK,
989 DM_INFO_FA_TOTAL,
990 DM_INFO_CCA_OFDM,
991 DM_INFO_CCA_CCK,
992 DM_INFO_CCA_ALL,
993 DM_INFO_CRC32_OK_VHT,
994 DM_INFO_CRC32_OK_HT,
995 DM_INFO_CRC32_OK_LEGACY,
996 DM_INFO_CRC32_OK_CCK,
997 DM_INFO_CRC32_ERROR_VHT,
998 DM_INFO_CRC32_ERROR_HT,
999 DM_INFO_CRC32_ERROR_LEGACY,
1000 DM_INFO_CRC32_ERROR_CCK,
1001 DM_INFO_EDCCA_FLAG,
1002 DM_INFO_OFDM_ENABLE,
1003 DM_INFO_CCK_ENABLE,
1004 DM_INFO_CRC32_OK_HT_AGG,
1005 DM_INFO_CRC32_ERROR_HT_AGG,
1006 DM_INFO_DBG_PORT_0,
1007 DM_INFO_CURR_IGI,
1008 DM_INFO_RSSI_MIN,
1009 DM_INFO_RSSI_MAX,
1010 DM_INFO_CLM_RATIO,
1011 DM_INFO_NHM_RATIO,
1012 DM_INFO_IQK_ALL,
1013 DM_INFO_IQK_OK,
1014 DM_INFO_IQK_NG,
1015 DM_INFO_SIZE,
1016};
1017
1018enum rx_packet_type {
1019 NORMAL_RX,
1020 TX_REPORT1,
1021 TX_REPORT2,
1022 HIS_REPORT,
1023 C2H_PACKET,
1024};
1025
1026struct rtlwifi_tx_info {
1027 int sn;
1028 unsigned long send_time;
1029};
1030
1031static inline struct rtlwifi_tx_info *rtl_tx_skb_cb_info(struct sk_buff *skb)
1032{
1033 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1034
1035 BUILD_BUG_ON(sizeof(struct rtlwifi_tx_info) >
1036 sizeof(info->status.status_driver_data));
1037
1038 return (struct rtlwifi_tx_info *)(info->status.status_driver_data);
1039}
1040
1041struct octet_string {
1042 u8 *octet;
1043 u16 length;
1044};
1045
1046struct rtl_hdr_3addr {
1047 __le16 frame_ctl;
1048 __le16 duration_id;
1049 u8 addr1[ETH_ALEN];
1050 u8 addr2[ETH_ALEN];
1051 u8 addr3[ETH_ALEN];
1052 __le16 seq_ctl;
1053 u8 payload[];
1054} __packed;
1055
1056struct rtl_info_element {
1057 u8 id;
1058 u8 len;
1059 u8 data[];
1060} __packed;
1061
1062struct rtl_probe_rsp {
1063 struct rtl_hdr_3addr header;
1064 u32 time_stamp[2];
1065 __le16 beacon_interval;
1066 __le16 capability;
1067 /*SSID, supported rates, FH params, DS params,
1068 * CF params, IBSS params, TIM (if beacon), RSN
1069 */
1070 struct rtl_info_element info_element[];
1071} __packed;
1072
1073struct rtl_led_ctl {
1074 bool led_opendrain;
1075 enum rtl_led_pin sw_led0;
1076 enum rtl_led_pin sw_led1;
1077};
1078
1079struct rtl_qos_parameters {
1080 __le16 cw_min;
1081 __le16 cw_max;
1082 u8 aifs;
1083 u8 flag;
1084 __le16 tx_op;
1085} __packed;
1086
1087struct rt_smooth_data {
1088 u32 elements[100]; /*array to store values */
1089 u32 index; /*index to current array to store */
1090 u32 total_num; /*num of valid elements */
1091 u32 total_val; /*sum of valid elements */
1092};
1093
1094struct false_alarm_statistics {
1095 u32 cnt_parity_fail;
1096 u32 cnt_rate_illegal;
1097 u32 cnt_crc8_fail;
1098 u32 cnt_mcs_fail;
1099 u32 cnt_fast_fsync_fail;
1100 u32 cnt_sb_search_fail;
1101 u32 cnt_ofdm_fail;
1102 u32 cnt_cck_fail;
1103 u32 cnt_all;
1104 u32 cnt_ofdm_cca;
1105 u32 cnt_cck_cca;
1106 u32 cnt_cca_all;
1107 u32 cnt_bw_usc;
1108 u32 cnt_bw_lsc;
1109};
1110
1111struct init_gain {
1112 u8 xaagccore1;
1113 u8 xbagccore1;
1114 u8 xcagccore1;
1115 u8 xdagccore1;
1116 u8 cca;
1117
1118};
1119
1120struct wireless_stats {
1121 u64 txbytesunicast;
1122 u64 txbytesmulticast;
1123 u64 txbytesbroadcast;
1124 u64 rxbytesunicast;
1125
1126 u64 txbytesunicast_inperiod;
1127 u64 rxbytesunicast_inperiod;
1128 u32 txbytesunicast_inperiod_tp;
1129 u32 rxbytesunicast_inperiod_tp;
1130 u64 txbytesunicast_last;
1131 u64 rxbytesunicast_last;
1132
1133 long rx_snr_db[4];
1134 /*Correct smoothed ss in Dbm, only used
1135 * in driver to report real power now.
1136 */
1137 long recv_signal_power;
1138 long signal_quality;
1139 long last_sigstrength_inpercent;
1140
1141 u32 rssi_calculate_cnt;
1142 u32 pwdb_all_cnt;
1143
1144 /* Transformed, in dbm. Beautified signal
1145 * strength for UI, not correct.
1146 */
1147 long signal_strength;
1148
1149 u8 rx_rssi_percentage[4];
1150 u8 rx_evm_dbm[4];
1151 u8 rx_evm_percentage[2];
1152
1153 u16 rx_cfo_short[4];
1154 u16 rx_cfo_tail[4];
1155
1156 struct rt_smooth_data ui_rssi;
1157 struct rt_smooth_data ui_link_quality;
1158};
1159
1160struct rate_adaptive {
1161 u8 rate_adaptive_disabled;
1162 u8 ratr_state;
1163 u16 reserve;
1164
1165 u32 high_rssi_thresh_for_ra;
1166 u32 high2low_rssi_thresh_for_ra;
1167 u8 low2high_rssi_thresh_for_ra40m;
1168 u32 low_rssi_thresh_for_ra40m;
1169 u8 low2high_rssi_thresh_for_ra20m;
1170 u32 low_rssi_thresh_for_ra20m;
1171 u32 upper_rssi_threshold_ratr;
1172 u32 middleupper_rssi_threshold_ratr;
1173 u32 middle_rssi_threshold_ratr;
1174 u32 middlelow_rssi_threshold_ratr;
1175 u32 low_rssi_threshold_ratr;
1176 u32 ultralow_rssi_threshold_ratr;
1177 u32 low_rssi_threshold_ratr_40m;
1178 u32 low_rssi_threshold_ratr_20m;
1179 u8 ping_rssi_enable;
1180 u32 ping_rssi_ratr;
1181 u32 ping_rssi_thresh_for_ra;
1182 u32 last_ratr;
1183 u8 pre_ratr_state;
1184 u8 ldpc_thres;
1185 bool use_ldpc;
1186 bool lower_rts_rate;
1187 bool is_special_data;
1188};
1189
1190struct regd_pair_mapping {
1191 u16 reg_dmnenum;
1192 u16 reg_5ghz_ctl;
1193 u16 reg_2ghz_ctl;
1194};
1195
1196struct dynamic_primary_cca {
1197 u8 pricca_flag;
1198 u8 intf_flag;
1199 u8 intf_type;
1200 u8 dup_rts_flag;
1201 u8 monitor_flag;
1202 u8 ch_offset;
1203 u8 mf_state;
1204};
1205
1206struct rtl_regulatory {
1207 s8 alpha2[2];
1208 u16 country_code;
1209 u16 max_power_level;
1210 u32 tp_scale;
1211 u16 current_rd;
1212 u16 current_rd_ext;
1213 int16_t power_limit;
1214 struct regd_pair_mapping *regpair;
1215};
1216
1217struct rtl_rfkill {
1218 bool rfkill_state; /*0 is off, 1 is on */
1219};
1220
1221/*for P2P PS**/
1222#define P2P_MAX_NOA_NUM 2
1223
1224enum p2p_role {
1225 P2P_ROLE_DISABLE = 0,
1226 P2P_ROLE_DEVICE = 1,
1227 P2P_ROLE_CLIENT = 2,
1228 P2P_ROLE_GO = 3
1229};
1230
1231enum p2p_ps_state {
1232 P2P_PS_DISABLE = 0,
1233 P2P_PS_ENABLE = 1,
1234 P2P_PS_SCAN = 2,
1235 P2P_PS_SCAN_DONE = 3,
1236 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1237};
1238
1239enum p2p_ps_mode {
1240 P2P_PS_NONE = 0,
1241 P2P_PS_CTWINDOW = 1,
1242 P2P_PS_NOA = 2,
1243 P2P_PS_MIX = 3, /* CTWindow and NoA */
1244};
1245
1246struct rtl_p2p_ps_info {
1247 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1248 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1249 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1250 /* Client traffic window. A period of time in TU after TBTT. */
1251 u8 ctwindow;
1252 u8 opp_ps; /* opportunistic power save. */
1253 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1254 /* Count for owner, Type of client. */
1255 u8 noa_count_type[P2P_MAX_NOA_NUM];
1256 /* Max duration for owner, preferred or min acceptable duration
1257 * for client.
1258 */
1259 u32 noa_duration[P2P_MAX_NOA_NUM];
1260 /* Length of interval for owner, preferred or max acceptable intervali
1261 * of client.
1262 */
1263 u32 noa_interval[P2P_MAX_NOA_NUM];
1264 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1265 u32 noa_start_time[P2P_MAX_NOA_NUM];
1266};
1267
1268struct p2p_ps_offload_t {
1269 u8 offload_en:1;
1270 u8 role:1; /* 1: Owner, 0: Client */
1271 u8 ctwindow_en:1;
1272 u8 noa0_en:1;
1273 u8 noa1_en:1;
1274 u8 allstasleep:1;
1275 u8 discovery:1;
1276 u8 reserved:1;
1277};
1278
1279#define IQK_MATRIX_REG_NUM 8
1280#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1281
1282struct iqk_matrix_regs {
1283 bool iqk_done;
1284 long value[1][IQK_MATRIX_REG_NUM];
1285};
1286
1287struct phy_parameters {
1288 u16 length;
1289 u32 *pdata;
1290};
1291
1292enum hw_param_tab_index {
1293 PHY_REG_2T,
1294 PHY_REG_1T,
1295 PHY_REG_PG,
1296 RADIOA_2T,
1297 RADIOB_2T,
1298 RADIOA_1T,
1299 RADIOB_1T,
1300 MAC_REG,
1301 AGCTAB_2T,
1302 AGCTAB_1T,
1303 MAX_TAB
1304};
1305
1306struct rtl_phy {
1307 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1308 struct init_gain initgain_backup;
1309 enum io_type current_io_type;
1310
1311 u8 rf_mode;
1312 u8 rf_type;
1313 u8 current_chan_bw;
1314 u8 set_bwmode_inprogress;
1315 u8 sw_chnl_inprogress;
1316 u8 sw_chnl_stage;
1317 u8 sw_chnl_step;
1318 u8 current_channel;
1319 u8 set_io_inprogress;
1320 u8 lck_inprogress;
1321
1322 /* record for power tracking */
1323 s32 reg_e94;
1324 s32 reg_e9c;
1325 s32 reg_ea4;
1326 s32 reg_eac;
1327 s32 reg_eb4;
1328 s32 reg_ebc;
1329 s32 reg_ec4;
1330 s32 reg_ecc;
1331 u32 reg_c04, reg_c08, reg_874;
1332 u32 adda_backup[16];
1333 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1334 u32 iqk_bb_backup[10];
1335 bool iqk_initialized;
1336
1337 bool rfpath_rx_enable[MAX_RF_PATH];
1338 u8 reg_837;
1339 /* Dual mac */
1340 bool need_iqk;
1341 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1342
1343 bool rfpi_enable;
1344
1345 u8 pwrgroup_cnt;
1346 u8 cck_high_power;
1347 /* this is for 88E & 8723A */
1348 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1349 /* MAX_PG_GROUP groups of pwr diff by rates */
1350 u32 mcs_offset[MAX_PG_GROUP][16];
1351 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1352 [TX_PWR_BY_RATE_NUM_RF]
1353 [TX_PWR_BY_RATE_NUM_RF]
1354 [TX_PWR_BY_RATE_NUM_RATE];
1355 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1356 [TX_PWR_BY_RATE_NUM_RF]
1357 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1358 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1359 [TX_PWR_BY_RATE_NUM_RF]
1360 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1361 u8 default_initialgain[4];
1362
1363 /* the current Tx power level */
1364 u8 cur_cck_txpwridx;
1365 u8 cur_ofdm24g_txpwridx;
1366 u8 cur_bw20_txpwridx;
1367 u8 cur_bw40_txpwridx;
1368
1369 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1370 [MAX_2_4G_BANDWIDTH_NUM]
1371 [MAX_RATE_SECTION_NUM]
1372 [CHANNEL_MAX_NUMBER_2G]
1373 [MAX_RF_PATH_NUM];
1374 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1375 [MAX_5G_BANDWIDTH_NUM]
1376 [MAX_RATE_SECTION_NUM]
1377 [CHANNEL_MAX_NUMBER_5G]
1378 [MAX_RF_PATH_NUM];
1379
1380 u32 rfreg_chnlval[2];
1381 u32 reg_rf3c[2]; /* pathA / pathB */
1382
1383 u32 backup_rf_0x1a;/*92ee*/
1384 /* bfsync */
1385 u8 framesync;
1386 u32 framesync_c34;
1387
1388 u8 num_total_rfpath;
1389 struct phy_parameters hwparam_tables[MAX_TAB];
1390 u16 rf_pathmap;
1391
1392 enum rt_polarity_ctl polarity_ctl;
1393};
1394
1395#define MAX_TID_COUNT 9
1396#define RTL_AGG_STOP 0
1397#define RTL_AGG_PROGRESS 1
1398#define RTL_AGG_START 2
1399#define RTL_AGG_OPERATIONAL 3
1400#define RTL_RX_AGG_START 1
1401#define RTL_RX_AGG_STOP 0
1402#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1403#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1404
1405struct rtl_ht_agg {
1406 u16 txq_id;
1407 u16 wait_for_ba;
1408 u16 start_idx;
1409 u64 bitmap;
1410 u32 rate_n_flags;
1411 u8 agg_state;
1412 u8 rx_agg_state;
1413};
1414
1415struct rssi_sta {
1416 long undec_sm_pwdb;
1417 long undec_sm_cck;
1418};
1419
1420struct rtl_tid_data {
1421 struct rtl_ht_agg agg;
1422};
1423
1424struct rtl_sta_info {
1425 struct list_head list;
1426 struct rtl_tid_data tids[MAX_TID_COUNT];
1427 /* just used for ap adhoc or mesh*/
1428 struct rssi_sta rssi_stat;
1429 u8 rssi_level;
1430 u16 wireless_mode;
1431 u8 ratr_index;
1432 u8 mimo_ps;
1433 u8 mac_addr[ETH_ALEN];
1434} __packed;
1435
1436struct rtl_priv;
1437struct rtl_io {
1438 struct device *dev;
1439 struct mutex bb_mutex;
1440
1441 /*PCI MEM map */
1442 unsigned long pci_mem_end; /*shared mem end */
1443 unsigned long pci_mem_start; /*shared mem start */
1444
1445 /*PCI IO map */
1446 unsigned long pci_base_addr; /*device I/O address */
1447
1448 void (*write8)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1449 void (*write16)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1450 void (*write32)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1451 void (*write_chunk)(struct rtl_priv *rtlpriv, u32 addr, u32 length,
1452 u8 *data);
1453
1454 u8 (*read8)(struct rtl_priv *rtlpriv, u32 addr);
1455 u16 (*read16)(struct rtl_priv *rtlpriv, u32 addr);
1456 u32 (*read32)(struct rtl_priv *rtlpriv, u32 addr);
1457
1458};
1459
1460struct rtl_mac {
1461 u8 mac_addr[ETH_ALEN];
1462 u8 mac80211_registered;
1463 u8 beacon_enabled;
1464
1465 u32 tx_ss_num;
1466 u32 rx_ss_num;
1467
1468 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1469 struct ieee80211_hw *hw;
1470 struct ieee80211_vif *vif;
1471 enum nl80211_iftype opmode;
1472
1473 /*Probe Beacon management */
1474 enum rtl_link_state link_state;
1475
1476 int n_channels;
1477 int n_bitrates;
1478
1479 bool offchan_delay;
1480 u8 p2p; /*using p2p role*/
1481 bool p2p_in_use;
1482
1483 /*filters */
1484 u32 rx_conf;
1485 u16 rx_mgt_filter;
1486 u16 rx_ctrl_filter;
1487 u16 rx_data_filter;
1488
1489 bool act_scanning;
1490 u8 cnt_after_linked;
1491 bool skip_scan;
1492
1493 /* early mode */
1494 /* skb wait queue */
1495 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1496
1497 u8 ht_stbc_cap;
1498 u8 ht_cur_stbc;
1499
1500 /*vht support*/
1501 u8 vht_enable;
1502 u8 bw_80;
1503 u8 vht_cur_ldpc;
1504 u8 vht_cur_stbc;
1505 u8 vht_stbc_cap;
1506 u8 vht_ldpc_cap;
1507
1508 /*RDG*/
1509 bool rdg_en;
1510
1511 /*AP*/
1512 u8 bssid[ETH_ALEN] __aligned(2);
1513 u32 vendor;
1514 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1515 u32 basic_rates; /* b/g rates */
1516 u8 ht_enable;
1517 u8 sgi_40;
1518 u8 sgi_20;
1519 u8 bw_40;
1520 u16 mode; /* wireless mode */
1521 u8 slot_time;
1522 u8 short_preamble;
1523 u8 use_cts_protect;
1524 u8 cur_40_prime_sc;
1525 u8 cur_40_prime_sc_bk;
1526 u8 cur_80_prime_sc;
1527 u64 tsf;
1528 u8 retry_short;
1529 u8 retry_long;
1530 u16 assoc_id;
1531 bool hiddenssid;
1532
1533 /*IBSS*/
1534 int beacon_interval;
1535
1536 /*AMPDU*/
1537 u8 min_space_cfg; /*For Min spacing configurations */
1538 u8 max_mss_density;
1539 u8 current_ampdu_factor;
1540 u8 current_ampdu_density;
1541
1542 /*QOS & EDCA */
1543 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1544 struct rtl_qos_parameters ac[AC_MAX];
1545
1546 /* counters */
1547 u64 last_txok_cnt;
1548 u64 last_rxok_cnt;
1549 u32 last_bt_edca_ul;
1550 u32 last_bt_edca_dl;
1551};
1552
1553struct btdm_8723 {
1554 bool all_off;
1555 bool agc_table_en;
1556 bool adc_back_off_on;
1557 bool b2_ant_hid_en;
1558 bool low_penalty_rate_adaptive;
1559 bool rf_rx_lpf_shrink;
1560 bool reject_aggre_pkt;
1561 bool tra_tdma_on;
1562 u8 tra_tdma_nav;
1563 u8 tra_tdma_ant;
1564 bool tdma_on;
1565 u8 tdma_ant;
1566 u8 tdma_nav;
1567 u8 tdma_dac_swing;
1568 u8 fw_dac_swing_lvl;
1569 bool ps_tdma_on;
1570 u8 ps_tdma_byte[5];
1571 bool pta_on;
1572 u32 val_0x6c0;
1573 u32 val_0x6c8;
1574 u32 val_0x6cc;
1575 bool sw_dac_swing_on;
1576 u32 sw_dac_swing_lvl;
1577 u32 wlan_act_hi;
1578 u32 wlan_act_lo;
1579 u32 bt_retry_index;
1580 bool dec_bt_pwr;
1581 bool ignore_wlan_act;
1582};
1583
1584struct bt_coexist_8723 {
1585 u32 high_priority_tx;
1586 u32 high_priority_rx;
1587 u32 low_priority_tx;
1588 u32 low_priority_rx;
1589 u8 c2h_bt_info;
1590 bool c2h_bt_info_req_sent;
1591 bool c2h_bt_inquiry_page;
1592 unsigned long bt_inq_page_start_time;
1593 u8 bt_retry_cnt;
1594 u8 c2h_bt_info_original;
1595 u8 bt_inquiry_page_cnt;
1596 struct btdm_8723 btdm;
1597};
1598
1599struct rtl_hal {
1600 struct ieee80211_hw *hw;
1601 bool driver_is_goingto_unload;
1602 bool up_first_time;
1603 bool first_init;
1604 bool being_init_adapter;
1605 bool mac_func_enable;
1606 bool pre_edcca_enable;
1607 struct bt_coexist_8723 hal_coex_8723;
1608
1609 enum intf_type interface;
1610 u16 hw_type; /*92c or 92d or 92s and so on */
1611 u8 ic_class;
1612 u8 oem_id;
1613 u32 version; /*version of chip */
1614 u8 state; /*stop 0, start 1 */
1615 u8 board_type;
1616 u8 package_type;
1617
1618 u8 pa_type_2g;
1619 u8 pa_type_5g;
1620 u8 lna_type_2g;
1621 u8 lna_type_5g;
1622 u8 external_pa_2g;
1623 u8 external_lna_2g;
1624 u8 external_pa_5g;
1625 u8 external_lna_5g;
1626 u8 type_glna;
1627 u8 type_gpa;
1628 u8 type_alna;
1629 u8 type_apa;
1630 u8 rfe_type;
1631
1632 /*firmware */
1633 u32 fwsize;
1634 u8 *pfirmware;
1635 u16 fw_version;
1636 u16 fw_subversion;
1637 bool h2c_setinprogress;
1638 u8 last_hmeboxnum;
1639 bool fw_ready;
1640 /*Reserve page start offset except beacon in TxQ. */
1641 u8 fw_rsvdpage_startoffset;
1642 u8 h2c_txcmd_seq;
1643 u8 current_ra_rate;
1644
1645 /* FW Cmd IO related */
1646 u16 fwcmd_iomap;
1647 u32 fwcmd_ioparam;
1648 bool set_fwcmd_inprogress;
1649 u8 current_fwcmd_io;
1650
1651 struct p2p_ps_offload_t p2p_ps_offload;
1652 bool fw_clk_change_in_progress;
1653 bool allow_sw_to_change_hwclc;
1654 u8 fw_ps_state;
1655
1656 /*AMPDU init min space*/
1657 u8 minspace_cfg; /*For Min spacing configurations */
1658
1659 /* Dual mac */
1660 enum macphy_mode macphymode;
1661 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1662 enum band_type current_bandtypebackup;
1663 enum band_type bandset;
1664 /* dual MAC 0--Mac0 1--Mac1 */
1665 u32 interfaceindex;
1666 /* just for DualMac S3S4 */
1667 u8 macphyctl_reg;
1668 bool earlymode_enable;
1669 u8 max_earlymode_num;
1670 /* Dual mac*/
1671 bool during_mac0init_radiob;
1672 bool during_mac1init_radioa;
1673 bool reloadtxpowerindex;
1674 /* True if IMR or IQK have done
1675 * for 2.4G in scan progress
1676 */
1677 bool load_imrandiqk_setting_for2g;
1678
1679 bool disable_amsdu_8k;
1680 bool master_of_dmsp;
1681 bool slave_of_dmsp;
1682
1683 /*for wowlan*/
1684 bool enter_pnp_sleep;
1685 bool wake_from_pnp_sleep;
1686 time64_t last_suspend_sec;
1687 u32 wowlan_fwsize;
1688 u8 *wowlan_firmware;
1689
1690 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1691
1692 bool real_wow_v2_enable;
1693 bool re_init_llt_table;
1694};
1695
1696struct rtl_security {
1697 /*default 0 */
1698 bool use_sw_sec;
1699
1700 bool being_setkey;
1701 bool use_defaultkey;
1702 /*Encryption Algorithm for Unicast Packet */
1703 enum rt_enc_alg pairwise_enc_algorithm;
1704 /*Encryption Algorithm for Brocast/Multicast */
1705 enum rt_enc_alg group_enc_algorithm;
1706 /*Cam Entry Bitmap */
1707 u32 hwsec_cam_bitmap;
1708 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1709 /*local Key buffer, indx 0 is for
1710 * pairwise key 1-4 is for agoup key.
1711 */
1712 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1713 u8 key_len[KEY_BUF_SIZE];
1714
1715 /*The pointer of Pairwise Key,
1716 * it always points to KeyBuf[4]
1717 */
1718 u8 *pairwise_key;
1719};
1720
1721#define ASSOCIATE_ENTRY_NUM 33
1722
1723struct fast_ant_training {
1724 u8 bssid[6];
1725 u8 antsel_rx_keep_0;
1726 u8 antsel_rx_keep_1;
1727 u8 antsel_rx_keep_2;
1728 u32 ant_sum[7];
1729 u32 ant_cnt[7];
1730 u32 ant_ave[7];
1731 u8 fat_state;
1732 u32 train_idx;
1733 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1734 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1735 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1736 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1737 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1738 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1739 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1740 u8 rx_idle_ant;
1741 bool becomelinked;
1742};
1743
1744struct dm_phy_dbg_info {
1745 s8 rx_snrdb[4];
1746 u64 num_qry_phy_status;
1747 u64 num_qry_phy_status_cck;
1748 u64 num_qry_phy_status_ofdm;
1749 u16 num_qry_beacon_pkt;
1750 u16 num_non_be_pkt;
1751 s32 rx_evm[4];
1752};
1753
1754struct rtl_dm {
1755 /*PHY status for Dynamic Management */
1756 long entry_min_undec_sm_pwdb;
1757 long undec_sm_cck;
1758 long undec_sm_pwdb; /*out dm */
1759 long entry_max_undec_sm_pwdb;
1760 s32 ofdm_pkt_cnt;
1761 bool dm_initialgain_enable;
1762 bool dynamic_txpower_enable;
1763 bool current_turbo_edca;
1764 bool is_any_nonbepkts; /*out dm */
1765 bool is_cur_rdlstate;
1766 bool txpower_trackinginit;
1767 bool disable_framebursting;
1768 bool cck_inch14;
1769 bool txpower_tracking;
1770 bool useramask;
1771 bool rfpath_rxenable[4];
1772 bool inform_fw_driverctrldm;
1773 bool current_mrc_switch;
1774 u8 txpowercount;
1775 u8 powerindex_backup[6];
1776
1777 u8 thermalvalue_rxgain;
1778 u8 thermalvalue_iqk;
1779 u8 thermalvalue_lck;
1780 u8 thermalvalue;
1781 u8 last_dtp_lvl;
1782 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1783 u8 thermalvalue_avg_index;
1784 u8 tm_trigger;
1785 bool done_txpower;
1786 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1787 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1788 u8 dm_flag_tmp;
1789 u8 dm_type;
1790 u8 dm_rssi_sel;
1791 u8 txpower_track_control;
1792 bool interrupt_migration;
1793 bool disable_tx_int;
1794 s8 ofdm_index[MAX_RF_PATH];
1795 u8 default_ofdm_index;
1796 u8 default_cck_index;
1797 s8 cck_index;
1798 s8 delta_power_index[MAX_RF_PATH];
1799 s8 delta_power_index_last[MAX_RF_PATH];
1800 s8 power_index_offset[MAX_RF_PATH];
1801 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1802 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1803 s8 remnant_cck_idx;
1804 bool modify_txagc_flag_path_a;
1805 bool modify_txagc_flag_path_b;
1806
1807 bool one_entry_only;
1808 struct dm_phy_dbg_info dbginfo;
1809
1810 /* Dynamic ATC switch */
1811 bool atc_status;
1812 bool large_cfo_hit;
1813 bool is_freeze;
1814 int cfo_tail[2];
1815 int cfo_ave_pre;
1816 int crystal_cap;
1817 u8 cfo_threshold;
1818 u32 packet_count;
1819 u32 packet_count_pre;
1820 u8 tx_rate;
1821
1822 /*88e tx power tracking*/
1823 u8 swing_idx_ofdm[MAX_RF_PATH];
1824 u8 swing_idx_ofdm_cur;
1825 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1826 bool swing_flag_ofdm;
1827 u8 swing_idx_cck;
1828 u8 swing_idx_cck_cur;
1829 u8 swing_idx_cck_base;
1830 bool swing_flag_cck;
1831
1832 s8 swing_diff_2g;
1833 s8 swing_diff_5g;
1834
1835 /* DMSP */
1836 bool supp_phymode_switch;
1837
1838 /* DulMac */
1839 struct fast_ant_training fat_table;
1840
1841 u8 resp_tx_path;
1842 u8 path_sel;
1843 u32 patha_sum;
1844 u32 pathb_sum;
1845 u32 patha_cnt;
1846 u32 pathb_cnt;
1847
1848 u8 pre_channel;
1849 u8 *p_channel;
1850 u8 linked_interval;
1851
1852 u64 last_tx_ok_cnt;
1853 u64 last_rx_ok_cnt;
1854};
1855
1856#define EFUSE_MAX_LOGICAL_SIZE 512
1857
1858struct rtl_efuse {
1859 const struct rtl_efuse_ops *efuse_ops;
1860 bool autoload_ok;
1861 bool bootfromefuse;
1862 u16 max_physical_size;
1863
1864 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1865 u16 efuse_usedbytes;
1866 u8 efuse_usedpercentage;
1867
1868 u8 autoload_failflag;
1869 u8 autoload_status;
1870
1871 short epromtype;
1872 u16 eeprom_vid;
1873 u16 eeprom_did;
1874 u16 eeprom_svid;
1875 u16 eeprom_smid;
1876 u8 eeprom_oemid;
1877 u16 eeprom_channelplan;
1878 u8 eeprom_version;
1879 u8 board_type;
1880 u8 external_pa;
1881
1882 u8 dev_addr[6];
1883 u8 wowlan_enable;
1884 u8 antenna_div_cfg;
1885 u8 antenna_div_type;
1886
1887 bool txpwr_fromeprom;
1888 u8 eeprom_crystalcap;
1889 u8 eeprom_tssi[2];
1890 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1891 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1892 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1893 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1894 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1895 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1896
1897 u8 internal_pa_5g[2]; /* pathA / pathB */
1898 u8 eeprom_c9;
1899 u8 eeprom_cc;
1900
1901 /*For power group */
1902 u8 eeprom_pwrgroup[2][3];
1903 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1904 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1905
1906 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1907 /*For HT 40MHZ pwr */
1908 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1909 /*For HT 40MHZ pwr */
1910 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1911
1912 /*--------------------------------------------------------*
1913 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1914 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1915 * define new arrays in Windows code.
1916 * BUT, in linux code, we use the same array for all ICs.
1917 *
1918 * The Correspondance relation between two arrays is:
1919 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1920 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1921 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1922 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1923 *
1924 * Sizes of these arrays are decided by the larger ones.
1925 */
1926 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1927 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1928 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1929 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1930
1931 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1932 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1933 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1934 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1935 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1936 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1937
1938 u8 txpwr_safetyflag; /* Band edge enable flag */
1939 u16 eeprom_txpowerdiff;
1940 u8 antenna_txpwdiff[3];
1941
1942 u8 eeprom_regulatory;
1943 u8 eeprom_thermalmeter;
1944 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1945 u16 tssi_13dbm;
1946 u8 crystalcap; /* CrystalCap. */
1947 u8 delta_iqk;
1948 u8 delta_lck;
1949
1950 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1951 bool apk_thermalmeterignore;
1952
1953 bool b1x1_recvcombine;
1954 bool b1ss_support;
1955
1956 /*channel plan */
1957 u8 channel_plan;
1958};
1959
1960struct rtl_efuse_ops {
1961 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data);
1962 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type,
1963 u16 offset, u32 *value);
1964};
1965
1966struct rtl_tx_report {
1967 atomic_t sn;
1968 u16 last_sent_sn;
1969 unsigned long last_sent_time;
1970 u16 last_recv_sn;
1971 struct sk_buff_head queue;
1972};
1973
1974struct rtl_ps_ctl {
1975 bool pwrdomain_protect;
1976 bool in_powersavemode;
1977 bool rfchange_inprogress;
1978 bool swrf_processing;
1979 bool hwradiooff;
1980 /* just for PCIE ASPM
1981 * If it supports ASPM, Offset[560h] = 0x40,
1982 * otherwise Offset[560h] = 0x00.
1983 */
1984 bool support_aspm;
1985 bool support_backdoor;
1986
1987 /*for LPS */
1988 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1989 bool swctrl_lps;
1990 bool leisure_ps;
1991 bool fwctrl_lps;
1992 u8 fwctrl_psmode;
1993 /*For Fw control LPS mode */
1994 u8 reg_fwctrl_lps;
1995 /*Record Fw PS mode status. */
1996 bool fw_current_inpsmode;
1997 u8 reg_max_lps_awakeintvl;
1998 bool report_linked;
1999 bool low_power_enable;/*for 32k*/
2000
2001 /*for IPS */
2002 bool inactiveps;
2003
2004 u32 rfoff_reason;
2005
2006 /*RF OFF Level */
2007 u32 cur_ps_level;
2008 u32 reg_rfps_level;
2009
2010 bool pwrdown_mode;
2011
2012 enum rf_pwrstate inactive_pwrstate;
2013 enum rf_pwrstate rfpwr_state; /*cur power state */
2014
2015 /* for SW LPS*/
2016 bool sw_ps_enabled;
2017 bool state_inap;
2018 bool multi_buffered;
2019 u16 nullfunc_seq;
2020 unsigned int dtim_counter;
2021 unsigned long last_sleep_jiffies;
2022 unsigned long last_awake_jiffies;
2023 unsigned long last_delaylps_stamp_jiffies;
2024 unsigned long last_dtim;
2025 unsigned long last_beacon;
2026
2027 /*For P2P PS */
2028 struct rtl_p2p_ps_info p2p_ps_info;
2029 u8 pwr_mode;
2030 u8 smart_ps;
2031
2032 /* wake up on line */
2033 u8 wo_wlan_mode;
2034 u8 arp_offload_enable;
2035 u8 gtk_offload_enable;
2036 /* Used for WOL, indicates the reason for waking event.*/
2037 u32 wakeup_reason;
2038};
2039
2040struct rtl_stats {
2041 u8 psaddr[ETH_ALEN];
2042 u32 mac_time[2];
2043 s8 rssi;
2044 u8 signal;
2045 u8 noise;
2046 u8 rate; /* hw desc rate */
2047 u8 received_channel;
2048 u8 control;
2049 u8 mask;
2050 u8 freq;
2051 u16 len;
2052 u64 tsf;
2053 u32 beacon_time;
2054 u8 nic_type;
2055 u16 length;
2056 u8 signalquality; /*in 0-100 index. */
2057 /* Real power in dBm for this packet,
2058 * no beautification and aggregation.
2059 */
2060 s32 recvsignalpower;
2061 s8 rxpower; /*in dBm Translate from PWdB */
2062 u8 signalstrength; /*in 0-100 index. */
2063 u16 hwerror:1;
2064 u16 crc:1;
2065 u16 icv:1;
2066 u16 shortpreamble:1;
2067 u16 antenna:1;
2068 u16 decrypted:1;
2069 u16 wakeup:1;
2070 u32 timestamp_low;
2071 u32 timestamp_high;
2072 bool shift;
2073
2074 u8 rx_drvinfo_size;
2075 u8 rx_bufshift;
2076 bool isampdu;
2077 bool isfirst_ampdu;
2078 bool rx_is40mhzpacket;
2079 u8 rx_packet_bw;
2080 u32 rx_pwdb_all;
2081 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2082 s8 rx_mimo_signalquality[4];
2083 u8 rx_mimo_evm_dbm[4];
2084 u16 cfo_short[4]; /* per-path's Cfo_short */
2085 u16 cfo_tail[4];
2086
2087 s8 rx_mimo_sig_qual[4];
2088 u8 rx_pwr[4]; /* per-path's pwdb */
2089 u8 rx_snr[4]; /* per-path's SNR */
2090 u8 bandwidth;
2091 u8 bt_coex_pwr_adjust;
2092 bool packet_matchbssid;
2093 bool is_cck;
2094 bool is_ht;
2095 bool packet_toself;
2096 bool packet_beacon; /*for rssi */
2097 s8 cck_adc_pwdb[4]; /*for rx path selection */
2098
2099 bool is_vht;
2100 bool is_short_gi;
2101 u8 vht_nss;
2102
2103 u8 packet_report_type;
2104
2105 u32 macid;
2106 u32 bt_rx_rssi_percentage;
2107 u32 macid_valid_entry[2];
2108};
2109
2110struct rt_link_detect {
2111 /* count for roaming */
2112 u32 bcn_rx_inperiod;
2113 u32 roam_times;
2114
2115 u32 num_tx_in4period[4];
2116 u32 num_rx_in4period[4];
2117
2118 u32 num_tx_inperiod;
2119 u32 num_rx_inperiod;
2120
2121 bool busytraffic;
2122 bool tx_busy_traffic;
2123 bool rx_busy_traffic;
2124 bool higher_busytraffic;
2125 bool higher_busyrxtraffic;
2126
2127 u32 tidtx_in4period[MAX_TID_COUNT][4];
2128 u32 tidtx_inperiod[MAX_TID_COUNT];
2129 bool higher_busytxtraffic[MAX_TID_COUNT];
2130};
2131
2132struct rtl_tcb_desc {
2133 u8 packet_bw:2;
2134 u8 multicast:1;
2135 u8 broadcast:1;
2136
2137 u8 rts_stbc:1;
2138 u8 rts_enable:1;
2139 u8 cts_enable:1;
2140 u8 rts_use_shortpreamble:1;
2141 u8 rts_use_shortgi:1;
2142 u8 rts_sc:1;
2143 u8 rts_bw:1;
2144 u8 rts_rate;
2145
2146 u8 use_shortgi:1;
2147 u8 use_shortpreamble:1;
2148 u8 use_driver_rate:1;
2149 u8 disable_ratefallback:1;
2150
2151 u8 use_spe_rpt:1;
2152
2153 u8 ratr_index;
2154 u8 mac_id;
2155 u8 hw_rate;
2156
2157 u8 last_inipkt:1;
2158 u8 cmd_or_init:1;
2159 u8 queue_index;
2160
2161 /* early mode */
2162 u8 empkt_num;
2163 /* The max value by HW */
2164 u32 empkt_len[10];
2165 bool tx_enable_sw_calc_duration;
2166};
2167
2168struct rtl_wow_pattern {
2169 u8 type;
2170 u16 crc;
2171 u32 mask[4];
2172};
2173
2174/* struct to store contents of interrupt vectors */
2175struct rtl_int {
2176 u32 inta;
2177 u32 intb;
2178 u32 intc;
2179 u32 intd;
2180};
2181
2182struct rtl_hal_ops {
2183 int (*init_sw_vars)(struct ieee80211_hw *hw);
2184 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2185 void (*read_chip_version)(struct ieee80211_hw *hw);
2186 void (*read_eeprom_info)(struct ieee80211_hw *hw);
2187 void (*interrupt_recognized)(struct ieee80211_hw *hw,
2188 struct rtl_int *intvec);
2189 int (*hw_init)(struct ieee80211_hw *hw);
2190 void (*hw_disable)(struct ieee80211_hw *hw);
2191 void (*hw_suspend)(struct ieee80211_hw *hw);
2192 void (*hw_resume)(struct ieee80211_hw *hw);
2193 void (*enable_interrupt)(struct ieee80211_hw *hw);
2194 void (*disable_interrupt)(struct ieee80211_hw *hw);
2195 int (*set_network_type)(struct ieee80211_hw *hw,
2196 enum nl80211_iftype type);
2197 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2198 bool check_bssid);
2199 void (*set_bw_mode)(struct ieee80211_hw *hw,
2200 enum nl80211_channel_type ch_type);
2201 u8 (*switch_channel)(struct ieee80211_hw *hw);
2202 void (*set_qos)(struct ieee80211_hw *hw, int aci);
2203 void (*set_bcn_reg)(struct ieee80211_hw *hw);
2204 void (*set_bcn_intv)(struct ieee80211_hw *hw);
2205 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2206 u32 add_msr, u32 rm_msr);
2207 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2208 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2209 void (*update_rate_tbl)(struct ieee80211_hw *hw,
2210 struct ieee80211_sta *sta, u8 rssi_leve,
2211 bool update_bw);
2212 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2213 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2214 u8 queue_index);
2215 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2216 u8 queue_index);
2217 void (*fill_tx_desc)(struct ieee80211_hw *hw,
2218 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2219 u8 *pbd_desc_tx,
2220 struct ieee80211_tx_info *info,
2221 struct ieee80211_sta *sta,
2222 struct sk_buff *skb, u8 hw_queue,
2223 struct rtl_tcb_desc *ptcb_desc);
2224 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2225 struct sk_buff *skb);
2226 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2227 u8 *pdesc, u8 *pbd_desc,
2228 struct sk_buff *skb, u8 hw_queue);
2229 bool (*query_rx_desc)(struct ieee80211_hw *hw,
2230 struct rtl_stats *stats,
2231 struct ieee80211_rx_status *rx_status,
2232 u8 *pdesc, struct sk_buff *skb);
2233 void (*set_channel_access)(struct ieee80211_hw *hw);
2234 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2235 void (*dm_watchdog)(struct ieee80211_hw *hw);
2236 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2237 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2238 enum rf_pwrstate rfpwr_state);
2239 void (*led_control)(struct ieee80211_hw *hw,
2240 enum led_ctl_mode ledaction);
2241 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2242 u8 desc_name, u8 *val);
2243 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2244 u8 desc_name);
2245 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2246 u8 hw_queue, u16 index);
2247 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2248 void (*enable_hw_sec)(struct ieee80211_hw *hw);
2249 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2250 u8 *macaddr, bool is_group, u8 enc_algo,
2251 bool is_wepkey, bool clear_all);
2252 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2253 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2254 u32 data);
2255 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2256 u32 regaddr, u32 bitmask);
2257 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2258 u32 regaddr, u32 bitmask, u32 data);
2259 void (*linked_set_reg)(struct ieee80211_hw *hw);
2260 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2261 bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2262 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2263 u8 *powerlevel);
2264 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2265 u8 *ppowerlevel, u8 channel);
2266 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2267 u8 configtype);
2268 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2269 u8 configtype);
2270 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2271 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2272 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2273 void (*c2h_command_handle)(struct ieee80211_hw *hw);
2274 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2275 bool mstate);
2276 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2277 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2278 u32 cmd_len, u8 *p_cmdbuffer);
2279 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2280 bool (*get_btc_status)(void);
2281 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2282 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2283 struct rtl_wow_pattern *rtl_pattern,
2284 u8 index);
2285 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2286 void (*c2h_ra_report_handler)(struct ieee80211_hw *hw,
2287 u8 *cmd_buf, u8 cmd_len);
2288};
2289
2290struct rtl_intf_ops {
2291 /*com */
2292 int (*adapter_start)(struct ieee80211_hw *hw);
2293 void (*adapter_stop)(struct ieee80211_hw *hw);
2294 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2295 struct rtl_priv **buddy_priv);
2296
2297 int (*adapter_tx)(struct ieee80211_hw *hw,
2298 struct ieee80211_sta *sta,
2299 struct sk_buff *skb,
2300 struct rtl_tcb_desc *ptcb_desc);
2301 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2302 int (*reset_trx_ring)(struct ieee80211_hw *hw);
2303 bool (*waitq_insert)(struct ieee80211_hw *hw,
2304 struct ieee80211_sta *sta,
2305 struct sk_buff *skb);
2306
2307 /*pci */
2308 void (*disable_aspm)(struct ieee80211_hw *hw);
2309 void (*enable_aspm)(struct ieee80211_hw *hw);
2310
2311 /*usb */
2312};
2313
2314struct rtl_mod_params {
2315 /* default: 0,0 */
2316 u64 debug_mask;
2317 /* default: 0 = using hardware encryption */
2318 bool sw_crypto;
2319
2320 /* default: 0 = DBG_EMERG (0)*/
2321 int debug_level;
2322
2323 /* default: 1 = using no linked power save */
2324 bool inactiveps;
2325
2326 /* default: 1 = using linked sw power save */
2327 bool swctrl_lps;
2328
2329 /* default: 1 = using linked fw power save */
2330 bool fwctrl_lps;
2331
2332 /* default: 0 = not using MSI interrupts mode
2333 * submodules should set their own default value
2334 */
2335 bool msi_support;
2336
2337 /* default: 0 = dma 32 */
2338 bool dma64;
2339
2340 /* default: 1 = enable aspm */
2341 int aspm_support;
2342
2343 /* default 0: 1 means disable */
2344 bool disable_watchdog;
2345
2346 /* default 0: 1 means do not disable interrupts */
2347 bool int_clear;
2348
2349 /* select antenna */
2350 int ant_sel;
2351};
2352
2353struct rtl_hal_usbint_cfg {
2354 /* data - rx */
2355 u32 rx_urb_num;
2356 u32 rx_max_size;
2357
2358 /* op - rx */
2359 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2360 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2361 struct sk_buff_head *);
2362
2363 /* tx */
2364 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2365 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2366 struct sk_buff *);
2367 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2368 struct sk_buff_head *);
2369
2370 /* endpoint mapping */
2371 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2372 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2373};
2374
2375struct rtl_hal_cfg {
2376 u8 bar_id;
2377 bool write_readback;
2378 char *name;
2379 char *alt_fw_name;
2380 struct rtl_hal_ops *ops;
2381 struct rtl_mod_params *mod_params;
2382 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2383 enum rtl_spec_ver spec_ver;
2384
2385 /*this map used for some registers or vars
2386 * defined int HAL but used in MAIN
2387 */
2388 u32 maps[RTL_VAR_MAP_MAX];
2389
2390};
2391
2392struct rtl_locks {
2393 /* mutex */
2394 struct mutex conf_mutex;
2395 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2396 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2397
2398 /*spin lock */
2399 spinlock_t irq_th_lock;
2400 spinlock_t h2c_lock;
2401 spinlock_t rf_ps_lock;
2402 spinlock_t rf_lock;
2403 spinlock_t waitq_lock;
2404 spinlock_t entry_list_lock;
2405 spinlock_t usb_lock;
2406 spinlock_t scan_list_lock; /* lock for the scan list */
2407
2408 /*FW clock change */
2409 spinlock_t fw_ps_lock;
2410
2411 /*Dual mac*/
2412 spinlock_t cck_and_rw_pagea_lock;
2413
2414 spinlock_t iqk_lock;
2415};
2416
2417struct rtl_works {
2418 struct ieee80211_hw *hw;
2419
2420 /*timer */
2421 struct timer_list watchdog_timer;
2422 struct timer_list fw_clockoff_timer;
2423 struct timer_list fast_antenna_training_timer;
2424 /*task */
2425 struct tasklet_struct irq_tasklet;
2426 struct tasklet_struct irq_prepare_bcn_tasklet;
2427
2428 /*work queue */
2429 struct workqueue_struct *rtl_wq;
2430 struct delayed_work watchdog_wq;
2431 struct delayed_work ips_nic_off_wq;
2432 struct delayed_work c2hcmd_wq;
2433
2434 /* For SW LPS */
2435 struct delayed_work ps_work;
2436 struct delayed_work ps_rfon_wq;
2437 struct delayed_work fwevt_wq;
2438
2439 struct work_struct lps_change_work;
2440 struct work_struct fill_h2c_cmd;
2441 struct work_struct update_beacon_work;
2442};
2443
2444struct rtl_debug {
2445 /* add for debug */
2446 struct dentry *debugfs_dir;
2447 char debugfs_name[20];
2448};
2449
2450#define MIMO_PS_STATIC 0
2451#define MIMO_PS_DYNAMIC 1
2452#define MIMO_PS_NOLIMIT 3
2453
2454struct rtl_dmsp_ctl {
2455 bool activescan_for_slaveofdmsp;
2456 bool scan_for_anothermac_fordmsp;
2457 bool scan_for_itself_fordmsp;
2458 bool writedig_for_anothermacofdmsp;
2459 u32 curdigvalue_for_anothermacofdmsp;
2460 bool changecckpdstate_for_anothermacofdmsp;
2461 u8 curcckpdstate_for_anothermacofdmsp;
2462 bool changetxhighpowerlvl_for_anothermacofdmsp;
2463 u8 curtxhighlvl_for_anothermacofdmsp;
2464 long rssivalmin_for_anothermacofdmsp;
2465};
2466
2467struct ps_t {
2468 u8 pre_ccastate;
2469 u8 cur_ccasate;
2470 u8 pre_rfstate;
2471 u8 cur_rfstate;
2472 u8 initialize;
2473 long rssi_val_min;
2474};
2475
2476struct dig_t {
2477 u32 rssi_lowthresh;
2478 u32 rssi_highthresh;
2479 u32 fa_lowthresh;
2480 u32 fa_highthresh;
2481 long last_min_undec_pwdb_for_dm;
2482 long rssi_highpower_lowthresh;
2483 long rssi_highpower_highthresh;
2484 u32 recover_cnt;
2485 u32 pre_igvalue;
2486 u32 cur_igvalue;
2487 long rssi_val;
2488 u8 dig_enable_flag;
2489 u8 dig_ext_port_stage;
2490 u8 dig_algorithm;
2491 u8 dig_twoport_algorithm;
2492 u8 dig_dbgmode;
2493 u8 dig_slgorithm_switch;
2494 u8 cursta_cstate;
2495 u8 presta_cstate;
2496 u8 curmultista_cstate;
2497 u8 stop_dig;
2498 s8 back_val;
2499 s8 back_range_max;
2500 s8 back_range_min;
2501 u8 rx_gain_max;
2502 u8 rx_gain_min;
2503 u8 min_undec_pwdb_for_dm;
2504 u8 rssi_val_min;
2505 u8 pre_cck_cca_thres;
2506 u8 cur_cck_cca_thres;
2507 u8 pre_cck_pd_state;
2508 u8 cur_cck_pd_state;
2509 u8 pre_cck_fa_state;
2510 u8 cur_cck_fa_state;
2511 u8 pre_ccastate;
2512 u8 cur_ccasate;
2513 u8 large_fa_hit;
2514 u8 forbidden_igi;
2515 u8 dig_state;
2516 u8 dig_highpwrstate;
2517 u8 cur_sta_cstate;
2518 u8 pre_sta_cstate;
2519 u8 cur_ap_cstate;
2520 u8 pre_ap_cstate;
2521 u8 cur_pd_thstate;
2522 u8 pre_pd_thstate;
2523 u8 cur_cs_ratiostate;
2524 u8 pre_cs_ratiostate;
2525 u8 backoff_enable_flag;
2526 s8 backoffval_range_max;
2527 s8 backoffval_range_min;
2528 u8 dig_min_0;
2529 u8 dig_min_1;
2530 u8 bt30_cur_igi;
2531 bool media_connect_0;
2532 bool media_connect_1;
2533
2534 u32 antdiv_rssi_max;
2535 u32 rssi_max;
2536};
2537
2538struct rtl_global_var {
2539 /* from this list we can get
2540 * other adapter's rtl_priv
2541 */
2542 struct list_head glb_priv_list;
2543 spinlock_t glb_list_lock;
2544};
2545
2546#define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2547
2548struct rtl_btc_info {
2549 u8 bt_type;
2550 u8 btcoexist;
2551 u8 ant_num;
2552 u8 single_ant_path;
2553
2554 u8 ap_num;
2555 bool in_4way;
2556 unsigned long in_4way_ts;
2557};
2558
2559struct bt_coexist_info {
2560 struct rtl_btc_ops *btc_ops;
2561 struct rtl_btc_info btc_info;
2562 /* btc context */
2563 void *btc_context;
2564 void *wifi_only_context;
2565 /* EEPROM BT info. */
2566 u8 eeprom_bt_coexist;
2567 u8 eeprom_bt_type;
2568 u8 eeprom_bt_ant_num;
2569 u8 eeprom_bt_ant_isol;
2570 u8 eeprom_bt_radio_shared;
2571
2572 u8 bt_coexistence;
2573 u8 bt_ant_num;
2574 u8 bt_coexist_type;
2575 u8 bt_state;
2576 u8 bt_cur_state; /* 0:on, 1:off */
2577 u8 bt_ant_isolation; /* 0:good, 1:bad */
2578 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2579 u8 bt_service;
2580 u8 bt_radio_shared_type;
2581 u8 bt_rfreg_origin_1e;
2582 u8 bt_rfreg_origin_1f;
2583 u8 bt_rssi_state;
2584 u32 ratio_tx;
2585 u32 ratio_pri;
2586 u32 bt_edca_ul;
2587 u32 bt_edca_dl;
2588
2589 bool init_set;
2590 bool bt_busy_traffic;
2591 bool bt_traffic_mode_set;
2592 bool bt_non_traffic_mode_set;
2593
2594 bool fw_coexist_all_off;
2595 bool sw_coexist_all_off;
2596 bool hw_coexist_all_off;
2597 u32 cstate;
2598 u32 previous_state;
2599 u32 cstate_h;
2600 u32 previous_state_h;
2601
2602 u8 bt_pre_rssi_state;
2603 u8 bt_pre_rssi_state1;
2604
2605 u8 reg_bt_iso;
2606 u8 reg_bt_sco;
2607 bool balance_on;
2608 u8 bt_active_zero_cnt;
2609 bool cur_bt_disabled;
2610 bool pre_bt_disabled;
2611
2612 u8 bt_profile_case;
2613 u8 bt_profile_action;
2614 bool bt_busy;
2615 bool hold_for_bt_operation;
2616 u8 lps_counter;
2617};
2618
2619struct rtl_btc_ops {
2620 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2621 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2622 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2623 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2624 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2625 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2626 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2627 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2628 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2629 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2630 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2631 u8 scantype);
2632 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2633 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2634 enum rt_media_status mstatus);
2635 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2636 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2637 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2638 u8 *tmp_buf, u8 length);
2639 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2640 u8 *tmp_buf, u8 length);
2641 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2642 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2643 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2644 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2645 u8 pkt_type);
2646 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2647 bool scanning);
2648 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2649 u8 type, bool scanning);
2650 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2651 struct seq_file *m);
2652 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2653 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2654 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2655 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2656 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2657 u8 *ctrl_agg_size, u8 *agg_size);
2658 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2659};
2660
2661struct proxim {
2662 bool proxim_on;
2663
2664 void *proximity_priv;
2665 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2666 struct sk_buff *skb);
2667 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2668};
2669
2670struct rtl_c2hcmd {
2671 struct list_head list;
2672 u8 tag;
2673 u8 len;
2674 u8 *val;
2675};
2676
2677struct rtl_bssid_entry {
2678 struct list_head list;
2679 u8 bssid[ETH_ALEN];
2680 unsigned long age;
2681};
2682
2683struct rtl_scan_list {
2684 int num;
2685 struct list_head list; /* sort by age */
2686};
2687
2688struct rtl_priv {
2689 struct ieee80211_hw *hw;
2690 struct completion firmware_loading_complete;
2691 struct list_head list;
2692 struct rtl_priv *buddy_priv;
2693 struct rtl_global_var *glb_var;
2694 struct rtl_dmsp_ctl dmsp_ctl;
2695 struct rtl_locks locks;
2696 struct rtl_works works;
2697 struct rtl_mac mac80211;
2698 struct rtl_hal rtlhal;
2699 struct rtl_regulatory regd;
2700 struct rtl_rfkill rfkill;
2701 struct rtl_io io;
2702 struct rtl_phy phy;
2703 struct rtl_dm dm;
2704 struct rtl_security sec;
2705 struct rtl_efuse efuse;
2706 struct rtl_led_ctl ledctl;
2707 struct rtl_tx_report tx_report;
2708 struct rtl_scan_list scan_list;
2709
2710 struct rtl_ps_ctl psc;
2711 struct rate_adaptive ra;
2712 struct dynamic_primary_cca primarycca;
2713 struct wireless_stats stats;
2714 struct rt_link_detect link_info;
2715 struct false_alarm_statistics falsealm_cnt;
2716
2717 struct rtl_rate_priv *rate_priv;
2718
2719 /* sta entry list for ap adhoc or mesh */
2720 struct list_head entry_list;
2721
2722 /* c2hcmd list for kthread level access */
2723 struct sk_buff_head c2hcmd_queue;
2724
2725 struct rtl_debug dbg;
2726 int max_fw_size;
2727
2728 /* hal_cfg : for diff cards
2729 * intf_ops : for diff interrface usb/pcie
2730 */
2731 struct rtl_hal_cfg *cfg;
2732 const struct rtl_intf_ops *intf_ops;
2733
2734 /* this var will be set by set_bit,
2735 * and was used to indicate status of
2736 * interface or hardware
2737 */
2738 unsigned long status;
2739
2740 /* tables for dm */
2741 struct dig_t dm_digtable;
2742 struct ps_t dm_pstable;
2743
2744 u32 reg_874;
2745 u32 reg_c70;
2746 u32 reg_85c;
2747 u32 reg_a74;
2748 bool reg_init; /* true if regs saved */
2749 bool bt_operation_on;
2750 __le32 *usb_data;
2751 int usb_data_index;
2752 bool initialized;
2753 bool enter_ps; /* true when entering PS */
2754 u8 rate_mask[5];
2755
2756 /* intel Proximity, should be alloc mem
2757 * in intel Proximity module and can only
2758 * be used in intel Proximity mode
2759 */
2760 struct proxim proximity;
2761
2762 /*for bt coexist use*/
2763 struct bt_coexist_info btcoexist;
2764
2765 /* separate 92ee from other ICs,
2766 * 92ee use new trx flow.
2767 */
2768 bool use_new_trx_flow;
2769
2770#ifdef CONFIG_PM
2771 struct wiphy_wowlan_support wowlan;
2772#endif
2773 /* This must be the last item so
2774 * that it points to the data allocated
2775 * beyond this structure like:
2776 * rtl_pci_priv or rtl_usb_priv
2777 */
2778 u8 priv[] __aligned(sizeof(void *));
2779};
2780
2781#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2782#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2783#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2784#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2785#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2786
2787/* Bluetooth Co-existence Related */
2788
2789enum bt_ant_num {
2790 ANT_X2 = 0,
2791 ANT_X1 = 1,
2792};
2793
2794enum bt_ant_path {
2795 ANT_MAIN = 0,
2796 ANT_AUX = 1,
2797};
2798
2799enum bt_co_type {
2800 BT_2WIRE = 0,
2801 BT_ISSC_3WIRE = 1,
2802 BT_ACCEL = 2,
2803 BT_CSR_BC4 = 3,
2804 BT_CSR_BC8 = 4,
2805 BT_RTL8756 = 5,
2806 BT_RTL8723A = 6,
2807 BT_RTL8821A = 7,
2808 BT_RTL8723B = 8,
2809 BT_RTL8192E = 9,
2810 BT_RTL8812A = 11,
2811};
2812
2813enum bt_cur_state {
2814 BT_OFF = 0,
2815 BT_ON = 1,
2816};
2817
2818enum bt_service_type {
2819 BT_SCO = 0,
2820 BT_A2DP = 1,
2821 BT_HID = 2,
2822 BT_HID_IDLE = 3,
2823 BT_SCAN = 4,
2824 BT_IDLE = 5,
2825 BT_OTHER_ACTION = 6,
2826 BT_BUSY = 7,
2827 BT_OTHERBUSY = 8,
2828 BT_PAN = 9,
2829};
2830
2831enum bt_radio_shared {
2832 BT_RADIO_SHARED = 0,
2833 BT_RADIO_INDIVIDUAL = 1,
2834};
2835
2836/****************************************
2837 * mem access macro define start
2838 * Call endian free function when
2839 * 1. Read/write packet content.
2840 * 2. Before write integer to IO.
2841 * 3. After read integer from IO.
2842 ****************************************/
2843
2844#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2845 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2846
2847/* mem access macro define end */
2848
2849#define byte(x, n) ((x >> (8 * n)) & 0xff)
2850
2851#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2852#define RTL_WATCH_DOG_TIME 2000
2853#define MSECS(t) msecs_to_jiffies(t)
2854#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2855#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2856#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2857#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2858#define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2859
2860#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2861#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2862#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2863/*NIC halt, re-initialize hw parameters*/
2864#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2865#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2866#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2867/*Always enable ASPM and Clock Req in initialization.*/
2868#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2869/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2870#define RT_PS_LEVEL_ASPM BIT(7)
2871/*When LPS is on, disable 2R if no packet is received or transmittd.*/
2872#define RT_RF_LPS_DISALBE_2R BIT(30)
2873#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2874#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2875 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2876#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2877 (ppsc->cur_ps_level &= (~(_ps_flg)))
2878#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2879 (ppsc->cur_ps_level |= _ps_flg)
2880
2881#define FILL_OCTET_STRING(_os, _octet, _len) \
2882 (_os).octet = (u8 *)(_octet); \
2883 (_os).length = (_len);
2884
2885#define CP_MACADDR(des, src) \
2886 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2887 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2888 (des)[4] = (src)[4], (des)[5] = (src)[5])
2889
2890#define LDPC_HT_ENABLE_RX BIT(0)
2891#define LDPC_HT_ENABLE_TX BIT(1)
2892#define LDPC_HT_TEST_TX_ENABLE BIT(2)
2893#define LDPC_HT_CAP_TX BIT(3)
2894
2895#define STBC_HT_ENABLE_RX BIT(0)
2896#define STBC_HT_ENABLE_TX BIT(1)
2897#define STBC_HT_TEST_TX_ENABLE BIT(2)
2898#define STBC_HT_CAP_TX BIT(3)
2899
2900#define LDPC_VHT_ENABLE_RX BIT(0)
2901#define LDPC_VHT_ENABLE_TX BIT(1)
2902#define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2903#define LDPC_VHT_CAP_TX BIT(3)
2904
2905#define STBC_VHT_ENABLE_RX BIT(0)
2906#define STBC_VHT_ENABLE_TX BIT(1)
2907#define STBC_VHT_TEST_TX_ENABLE BIT(2)
2908#define STBC_VHT_CAP_TX BIT(3)
2909
2910extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2911
2912extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2913
2914static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2915{
2916 return rtlpriv->io.read8(rtlpriv, addr);
2917}
2918
2919static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2920{
2921 return rtlpriv->io.read16(rtlpriv, addr);
2922}
2923
2924static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2925{
2926 return rtlpriv->io.read32(rtlpriv, addr);
2927}
2928
2929static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2930{
2931 rtlpriv->io.write8(rtlpriv, addr, val8);
2932
2933 if (rtlpriv->cfg->write_readback)
2934 rtlpriv->io.read8(rtlpriv, addr);
2935}
2936
2937static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
2938 u32 addr, u32 val8)
2939{
2940 struct rtl_priv *rtlpriv = rtl_priv(hw);
2941
2942 rtl_write_byte(rtlpriv, addr, val8: (u8)val8);
2943}
2944
2945static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2946{
2947 rtlpriv->io.write16(rtlpriv, addr, val16);
2948
2949 if (rtlpriv->cfg->write_readback)
2950 rtlpriv->io.read16(rtlpriv, addr);
2951}
2952
2953static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2954 u32 addr, u32 val32)
2955{
2956 rtlpriv->io.write32(rtlpriv, addr, val32);
2957
2958 if (rtlpriv->cfg->write_readback)
2959 rtlpriv->io.read32(rtlpriv, addr);
2960}
2961
2962static inline void rtl_write_chunk(struct rtl_priv *rtlpriv,
2963 u32 addr, u32 length, u8 *data)
2964{
2965 rtlpriv->io.write_chunk(rtlpriv, addr, length, data);
2966}
2967
2968static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2969 u32 regaddr, u32 bitmask)
2970{
2971 struct rtl_priv *rtlpriv = hw->priv;
2972
2973 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2974}
2975
2976static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2977 u32 bitmask, u32 data)
2978{
2979 struct rtl_priv *rtlpriv = hw->priv;
2980
2981 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2982}
2983
2984static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
2985 u32 regaddr, u32 data)
2986{
2987 rtl_set_bbreg(hw, regaddr, bitmask: 0xffffffff, data);
2988}
2989
2990static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2991 enum radio_path rfpath, u32 regaddr,
2992 u32 bitmask)
2993{
2994 struct rtl_priv *rtlpriv = hw->priv;
2995
2996 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2997}
2998
2999static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3000 enum radio_path rfpath, u32 regaddr,
3001 u32 bitmask, u32 data)
3002{
3003 struct rtl_priv *rtlpriv = hw->priv;
3004
3005 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3006}
3007
3008static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3009{
3010 return (_HAL_STATE_STOP == rtlhal->state);
3011}
3012
3013static inline void set_hal_start(struct rtl_hal *rtlhal)
3014{
3015 rtlhal->state = _HAL_STATE_START;
3016}
3017
3018static inline void set_hal_stop(struct rtl_hal *rtlhal)
3019{
3020 rtlhal->state = _HAL_STATE_STOP;
3021}
3022
3023static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3024{
3025 return rtlphy->rf_type;
3026}
3027
3028static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3029{
3030 return (struct ieee80211_hdr *)(skb->data);
3031}
3032
3033static inline __le16 rtl_get_fc(struct sk_buff *skb)
3034{
3035 return rtl_get_hdr(skb)->frame_control;
3036}
3037
3038static inline u16 rtl_get_tid(struct sk_buff *skb)
3039{
3040 return ieee80211_get_tid(hdr: rtl_get_hdr(skb));
3041}
3042
3043static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3044 struct ieee80211_vif *vif,
3045 const u8 *bssid)
3046{
3047 return ieee80211_find_sta(vif, addr: bssid);
3048}
3049
3050static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3051 u8 *mac_addr)
3052{
3053 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3054
3055 return ieee80211_find_sta(vif: mac->vif, addr: mac_addr);
3056}
3057
3058static inline u32 calculate_bit_shift(u32 bitmask)
3059{
3060 if (WARN_ON_ONCE(!bitmask))
3061 return 0;
3062
3063 return __ffs(bitmask);
3064}
3065#endif
3066

source code of linux/drivers/net/wireless/realtek/rtlwifi/wifi.h