1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2018-2019 Realtek Corporation |
3 | */ |
4 | |
5 | #ifndef __RTW_COEX_H__ |
6 | #define __RTW_COEX_H__ |
7 | |
8 | #define COEX_CCK_2 0x1 |
9 | #define COEX_RESP_ACK_BY_WL_FW 0x1 |
10 | #define COEX_REQUEST_TIMEOUT msecs_to_jiffies(10) |
11 | |
12 | #define COEX_MIN_DELAY 10 /* delay unit in ms */ |
13 | #define COEX_RFK_TIMEOUT 600 /* RFK timeout in ms */ |
14 | #define COEX_BT_GAMEHID_CNT 800 |
15 | |
16 | #define COEX_RF_OFF 0x0 |
17 | #define COEX_RF_ON 0x1 |
18 | |
19 | #define COEX_H2C69_WL_LEAKAP 0xc |
20 | #define PARA1_H2C69_DIS_5MS 0x1 |
21 | #define PARA1_H2C69_EN_5MS 0x0 |
22 | |
23 | #define COEX_H2C69_TDMA_SLOT 0xb |
24 | #define PARA1_H2C69_TDMA_4SLOT 0xc1 |
25 | #define PARA1_H2C69_TDMA_2SLOT 0x1 |
26 | #define PARA1_H2C69_TBTT_TIMES GENMASK(5, 0) |
27 | #define PARA1_H2C69_TBTT_DIV100 BIT(7) |
28 | |
29 | #define COEX_H2C69_TOGGLE_TABLE_A 0xd |
30 | #define COEX_H2C69_TOGGLE_TABLE_B 0x7 |
31 | |
32 | #define TDMA_4SLOT BIT(8) |
33 | |
34 | #define TDMA_TIMER_TYPE_2SLOT 0 |
35 | #define TDMA_TIMER_TYPE_4SLOT 3 |
36 | |
37 | #define 4 |
38 | |
39 | #define (rssi) \ |
40 | ({ typeof(rssi) __rssi__ = rssi; \ |
41 | (__rssi__ == COEX_RSSI_STATE_HIGH || \ |
42 | __rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); }) |
43 | |
44 | #define (rssi) \ |
45 | ({ typeof(rssi) __rssi__ = rssi; \ |
46 | (__rssi__ == COEX_RSSI_STATE_MEDIUM || \ |
47 | __rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); }) |
48 | |
49 | #define (rssi) \ |
50 | ({ typeof(rssi) __rssi__ = rssi; \ |
51 | (__rssi__ == COEX_RSSI_STATE_LOW || \ |
52 | __rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); }) |
53 | |
54 | #define GET_COEX_RESP_BT_SUPP_VER(payload) \ |
55 | le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 32)) |
56 | #define GET_COEX_RESP_BT_SUPP_FEAT(payload) \ |
57 | le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24)) |
58 | #define GET_COEX_RESP_BT_PATCH_VER(payload) \ |
59 | le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(55, 24)) |
60 | #define GET_COEX_RESP_BT_REG_VAL(payload) \ |
61 | le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24)) |
62 | #define GET_COEX_RESP_BT_SCAN_TYPE(payload) \ |
63 | le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24)) |
64 | |
65 | enum coex_mp_info_op { |
66 | BT_MP_INFO_OP_PATCH_VER = 0x00, |
67 | BT_MP_INFO_OP_READ_REG = 0x11, |
68 | BT_MP_INFO_OP_SUPP_FEAT = 0x2a, |
69 | BT_MP_INFO_OP_SUPP_VER = 0x2b, |
70 | BT_MP_INFO_OP_SCAN_TYPE = 0x2d, |
71 | BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32, |
72 | }; |
73 | |
74 | enum coex_set_ant_phase { |
75 | COEX_SET_ANT_INIT, |
76 | COEX_SET_ANT_WONLY, |
77 | COEX_SET_ANT_WOFF, |
78 | COEX_SET_ANT_2G, |
79 | COEX_SET_ANT_5G, |
80 | COEX_SET_ANT_POWERON, |
81 | COEX_SET_ANT_2G_WLBT, |
82 | COEX_SET_ANT_2G_FREERUN, |
83 | |
84 | COEX_SET_ANT_MAX |
85 | }; |
86 | |
87 | enum coex_runreason { |
88 | COEX_RSN_2GSCANSTART = 0, |
89 | COEX_RSN_5GSCANSTART = 1, |
90 | COEX_RSN_SCANFINISH = 2, |
91 | COEX_RSN_2GSWITCHBAND = 3, |
92 | COEX_RSN_5GSWITCHBAND = 4, |
93 | COEX_RSN_2GCONSTART = 5, |
94 | COEX_RSN_5GCONSTART = 6, |
95 | COEX_RSN_2GCONFINISH = 7, |
96 | COEX_RSN_5GCONFINISH = 8, |
97 | COEX_RSN_2GMEDIA = 9, |
98 | COEX_RSN_5GMEDIA = 10, |
99 | COEX_RSN_MEDIADISCON = 11, |
100 | COEX_RSN_BTINFO = 12, |
101 | COEX_RSN_LPS = 13, |
102 | COEX_RSN_WLSTATUS = 14, |
103 | COEX_RSN_BTSTATUS = 15, |
104 | |
105 | COEX_RSN_MAX |
106 | }; |
107 | |
108 | enum coex_lte_coex_table_type { |
109 | COEX_CTT_WL_VS_LTE, |
110 | COEX_CTT_BT_VS_LTE, |
111 | }; |
112 | |
113 | enum coex_gnt_setup_state { |
114 | COEX_GNT_SET_HW_PTA = 0x0, |
115 | COEX_GNT_SET_SW_LOW = 0x1, |
116 | COEX_GNT_SET_SW_HIGH = 0x3, |
117 | }; |
118 | |
119 | enum coex_ext_ant_switch_pos_type { |
120 | COEX_SWITCH_TO_BT, |
121 | COEX_SWITCH_TO_WLG, |
122 | COEX_SWITCH_TO_WLA, |
123 | COEX_SWITCH_TO_NOCARE, |
124 | COEX_SWITCH_TO_WLG_BT, |
125 | |
126 | COEX_SWITCH_TO_MAX |
127 | }; |
128 | |
129 | enum coex_ext_ant_switch_ctrl_type { |
130 | COEX_SWITCH_CTRL_BY_BBSW, |
131 | COEX_SWITCH_CTRL_BY_PTA, |
132 | COEX_SWITCH_CTRL_BY_ANTDIV, |
133 | COEX_SWITCH_CTRL_BY_MAC, |
134 | COEX_SWITCH_CTRL_BY_BT, |
135 | COEX_SWITCH_CTRL_BY_FW, |
136 | |
137 | COEX_SWITCH_CTRL_MAX |
138 | }; |
139 | |
140 | enum coex_algorithm { |
141 | COEX_ALGO_NOPROFILE = 0, |
142 | COEX_ALGO_HFP = 1, |
143 | COEX_ALGO_HID = 2, |
144 | COEX_ALGO_A2DP = 3, |
145 | COEX_ALGO_PAN = 4, |
146 | COEX_ALGO_A2DP_HID = 5, |
147 | COEX_ALGO_A2DP_PAN = 6, |
148 | COEX_ALGO_PAN_HID = 7, |
149 | COEX_ALGO_A2DP_PAN_HID = 8, |
150 | |
151 | COEX_ALGO_MAX |
152 | }; |
153 | |
154 | enum coex_bt_profile { |
155 | BPM_NOPROFILE = 0, |
156 | BPM_HFP = BIT(0), |
157 | BPM_HID = BIT(1), |
158 | BPM_A2DP = BIT(2), |
159 | BPM_PAN = BIT(3), |
160 | BPM_HID_HFP = BPM_HID | BPM_HFP, |
161 | BPM_A2DP_HFP = BPM_A2DP | BPM_HFP, |
162 | BPM_A2DP_HID = BPM_A2DP | BPM_HID, |
163 | BPM_A2DP_HID_HFP = BPM_A2DP | BPM_HID | BPM_HFP, |
164 | BPM_PAN_HFP = BPM_PAN | BPM_HFP, |
165 | BPM_PAN_HID = BPM_PAN | BPM_HID, |
166 | BPM_PAN_HID_HFP = BPM_PAN | BPM_HID | BPM_HFP, |
167 | BPM_PAN_A2DP = BPM_PAN | BPM_A2DP, |
168 | BPM_PAN_A2DP_HFP = BPM_PAN | BPM_A2DP | BPM_HFP, |
169 | BPM_PAN_A2DP_HID = BPM_PAN | BPM_A2DP | BPM_HID, |
170 | BPM_PAN_A2DP_HID_HFP = BPM_PAN | BPM_A2DP | BPM_HID | BPM_HFP, |
171 | }; |
172 | |
173 | enum coex_wl_link_mode { |
174 | COEX_WLINK_2G1PORT = 0x0, |
175 | COEX_WLINK_5G = 0x3, |
176 | COEX_WLINK_2GFREE = 0x7, |
177 | COEX_WLINK_MAX |
178 | }; |
179 | |
180 | enum coex_wl2bt_scoreboard { |
181 | COEX_SCBD_ACTIVE = BIT(0), |
182 | COEX_SCBD_ONOFF = BIT(1), |
183 | COEX_SCBD_SCAN = BIT(2), |
184 | COEX_SCBD_UNDERTEST = BIT(3), |
185 | COEX_SCBD_RXGAIN = BIT(4), |
186 | COEX_SCBD_BT_RFK = BIT(5), |
187 | COEX_SCBD_WLBUSY = BIT(6), |
188 | COEX_SCBD_EXTFEM = BIT(8), |
189 | COEX_SCBD_TDMA = BIT(9), |
190 | COEX_SCBD_FIX2M = BIT(10), |
191 | COEX_SCBD_ALL = GENMASK(15, 0), |
192 | }; |
193 | |
194 | enum coex_power_save_type { |
195 | COEX_PS_WIFI_NATIVE = 0, |
196 | COEX_PS_LPS_ON = 1, |
197 | COEX_PS_LPS_OFF = 2, |
198 | }; |
199 | |
200 | enum { |
201 | , |
202 | , |
203 | , |
204 | , |
205 | , |
206 | , |
207 | }; |
208 | |
209 | enum coex_notify_type_ips { |
210 | COEX_IPS_LEAVE = 0x0, |
211 | COEX_IPS_ENTER = 0x1, |
212 | }; |
213 | |
214 | enum coex_notify_type_lps { |
215 | COEX_LPS_DISABLE = 0x0, |
216 | COEX_LPS_ENABLE = 0x1, |
217 | }; |
218 | |
219 | enum coex_notify_type_scan { |
220 | COEX_SCAN_FINISH, |
221 | COEX_SCAN_START, |
222 | COEX_SCAN_START_2G, |
223 | COEX_SCAN_START_5G, |
224 | }; |
225 | |
226 | enum coex_notify_type_switchband { |
227 | COEX_NOT_SWITCH, |
228 | COEX_SWITCH_TO_24G, |
229 | COEX_SWITCH_TO_5G, |
230 | COEX_SWITCH_TO_24G_NOFORSCAN, |
231 | }; |
232 | |
233 | enum coex_notify_type_associate { |
234 | COEX_ASSOCIATE_FINISH, |
235 | COEX_ASSOCIATE_START, |
236 | COEX_ASSOCIATE_5G_FINISH, |
237 | COEX_ASSOCIATE_5G_START, |
238 | }; |
239 | |
240 | enum coex_notify_type_media_status { |
241 | COEX_MEDIA_DISCONNECT, |
242 | COEX_MEDIA_CONNECT, |
243 | COEX_MEDIA_CONNECT_5G, |
244 | }; |
245 | |
246 | enum coex_bt_status { |
247 | COEX_BTSTATUS_NCON_IDLE = 0, |
248 | COEX_BTSTATUS_CON_IDLE = 1, |
249 | COEX_BTSTATUS_INQ_PAGE = 2, |
250 | COEX_BTSTATUS_ACL_BUSY = 3, |
251 | COEX_BTSTATUS_SCO_BUSY = 4, |
252 | COEX_BTSTATUS_ACL_SCO_BUSY = 5, |
253 | |
254 | COEX_BTSTATUS_MAX |
255 | }; |
256 | |
257 | enum coex_wl_tput_dir { |
258 | COEX_WL_TPUT_TX = 0x0, |
259 | COEX_WL_TPUT_RX = 0x1, |
260 | COEX_WL_TPUT_MAX |
261 | }; |
262 | |
263 | enum coex_wl_priority_mask { |
264 | COEX_WLPRI_RX_RSP = 2, |
265 | COEX_WLPRI_TX_RSP = 3, |
266 | COEX_WLPRI_TX_BEACON = 4, |
267 | COEX_WLPRI_TX_OFDM = 11, |
268 | COEX_WLPRI_TX_CCK = 12, |
269 | COEX_WLPRI_TX_BEACONQ = 27, |
270 | COEX_WLPRI_RX_CCK = 28, |
271 | COEX_WLPRI_RX_OFDM = 29, |
272 | COEX_WLPRI_MAX |
273 | }; |
274 | |
275 | enum coex_commom_chip_setup { |
276 | COEX_CSETUP_INIT_HW = 0x0, |
277 | COEX_CSETUP_ANT_SWITCH = 0x1, |
278 | COEX_CSETUP_GNT_FIX = 0x2, |
279 | COEX_CSETUP_GNT_DEBUG = 0x3, |
280 | COEX_CSETUP_RFE_TYPE = 0x4, |
281 | COEX_CSETUP_COEXINFO_HW = 0x5, |
282 | COEX_CSETUP_WL_TX_POWER = 0x6, |
283 | COEX_CSETUP_WL_RX_GAIN = 0x7, |
284 | COEX_CSETUP_WLAN_ACT_IPS = 0x8, |
285 | COEX_CSETUP_MAX |
286 | }; |
287 | |
288 | enum coex_indirect_reg_type { |
289 | COEX_INDIRECT_1700 = 0x0, |
290 | COEX_INDIRECT_7C0 = 0x1, |
291 | COEX_INDIRECT_MAX |
292 | }; |
293 | |
294 | enum coex_pstdma_type { |
295 | COEX_PSTDMA_FORCE_LPSOFF = 0x0, |
296 | COEX_PSTDMA_FORCE_LPSON = 0x1, |
297 | COEX_PSTDMA_MAX |
298 | }; |
299 | |
300 | enum { |
301 | = 0x0, |
302 | = 0x1, |
303 | |
304 | }; |
305 | |
306 | struct coex_table_para { |
307 | u32 bt; |
308 | u32 wl; |
309 | }; |
310 | |
311 | struct coex_tdma_para { |
312 | u8 para[5]; |
313 | }; |
314 | |
315 | struct coex_5g_afh_map { |
316 | u32 wl_5g_ch; |
317 | u8 bt_skip_ch; |
318 | u8 bt_skip_span; |
319 | }; |
320 | |
321 | struct coex_rf_para { |
322 | u8 wl_pwr_dec_lvl; |
323 | u8 bt_pwr_dec_lvl; |
324 | bool wl_low_gain_en; |
325 | u8 bt_lna_lvl; |
326 | }; |
327 | |
328 | static inline void rtw_coex_set_init(struct rtw_dev *rtwdev) |
329 | { |
330 | const struct rtw_chip_info *chip = rtwdev->chip; |
331 | |
332 | chip->ops->coex_set_init(rtwdev); |
333 | } |
334 | |
335 | static inline |
336 | void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type) |
337 | { |
338 | const struct rtw_chip_info *chip = rtwdev->chip; |
339 | |
340 | if (!chip->ops->coex_set_ant_switch) |
341 | return; |
342 | |
343 | chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type); |
344 | } |
345 | |
346 | static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev) |
347 | { |
348 | const struct rtw_chip_info *chip = rtwdev->chip; |
349 | |
350 | chip->ops->coex_set_gnt_fix(rtwdev); |
351 | } |
352 | |
353 | static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev) |
354 | { |
355 | const struct rtw_chip_info *chip = rtwdev->chip; |
356 | |
357 | chip->ops->coex_set_gnt_debug(rtwdev); |
358 | } |
359 | |
360 | static inline void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev) |
361 | { |
362 | const struct rtw_chip_info *chip = rtwdev->chip; |
363 | |
364 | chip->ops->coex_set_rfe_type(rtwdev); |
365 | } |
366 | |
367 | static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) |
368 | { |
369 | const struct rtw_chip_info *chip = rtwdev->chip; |
370 | |
371 | chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr); |
372 | } |
373 | |
374 | static inline |
375 | void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) |
376 | { |
377 | const struct rtw_chip_info *chip = rtwdev->chip; |
378 | |
379 | chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain); |
380 | } |
381 | |
382 | void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb); |
383 | u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr); |
384 | void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr, |
385 | u32 mask, u32 val); |
386 | void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set); |
387 | |
388 | void rtw_coex_bt_relink_work(struct work_struct *work); |
389 | void rtw_coex_bt_reenable_work(struct work_struct *work); |
390 | void rtw_coex_defreeze_work(struct work_struct *work); |
391 | void rtw_coex_wl_remain_work(struct work_struct *work); |
392 | void rtw_coex_bt_remain_work(struct work_struct *work); |
393 | void rtw_coex_wl_connecting_work(struct work_struct *work); |
394 | void rtw_coex_bt_multi_link_remain_work(struct work_struct *work); |
395 | void rtw_coex_wl_ccklock_work(struct work_struct *work); |
396 | |
397 | void rtw_coex_power_on_setting(struct rtw_dev *rtwdev); |
398 | void rtw_coex_power_off_setting(struct rtw_dev *rtwdev); |
399 | void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only); |
400 | void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type); |
401 | void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type); |
402 | void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type); |
403 | void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 type); |
404 | void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 type); |
405 | void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length); |
406 | void rtw_coex_bt_hid_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length); |
407 | void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length); |
408 | void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type); |
409 | void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev, u32 type); |
410 | void rtw_coex_wl_status_check(struct rtw_dev *rtwdev); |
411 | void rtw_coex_query_bt_hid_list(struct rtw_dev *rtwdev); |
412 | void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m); |
413 | |
414 | static inline bool rtw_coex_disabled(struct rtw_dev *rtwdev) |
415 | { |
416 | struct rtw_coex *coex = &rtwdev->coex; |
417 | struct rtw_coex_stat *coex_stat = &coex->stat; |
418 | |
419 | return coex_stat->bt_disabled; |
420 | } |
421 | |
422 | #endif |
423 | |