1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2018-2019 Realtek Corporation |
3 | */ |
4 | |
5 | #ifndef __RTW_FW_H_ |
6 | #define __RTW_FW_H_ |
7 | |
8 | #define H2C_PKT_SIZE 32 |
9 | #define H2C_PKT_HDR_SIZE 8 |
10 | |
11 | /* FW bin information */ |
12 | #define FW_HDR_SIZE 64 |
13 | #define FW_HDR_CHKSUM_SIZE 8 |
14 | |
15 | #define FW_NLO_INFO_CHECK_SIZE 4 |
16 | |
17 | #define FIFO_PAGE_SIZE_SHIFT 12 |
18 | #define FIFO_PAGE_SIZE 4096 |
19 | #define FIFO_DUMP_ADDR 0x8000 |
20 | |
21 | #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 |
22 | #define DLFW_PAGE_SIZE_LEGACY 0x1000 |
23 | #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 |
24 | #define DLFW_BLK_SIZE_LEGACY 4 |
25 | #define FW_START_ADDR_LEGACY 0x1000 |
26 | |
27 | #define BCN_LOSS_CNT 10 |
28 | #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0 |
29 | #define BCN_FILTER_CONNECTION_LOSS 1 |
30 | #define BCN_FILTER_CONNECTED 2 |
31 | #define BCN_FILTER_NOTIFY_BEACON_LOSS 3 |
32 | |
33 | #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10) |
34 | |
35 | #define RTW_CHANNEL_TIME 45 |
36 | #define RTW_OFF_CHAN_TIME 100 |
37 | #define RTW_PASS_CHAN_TIME 105 |
38 | #define RTW_DFS_CHAN_TIME 20 |
39 | #define RTW_CH_INFO_SIZE 4 |
40 | #define RTW_EX_CH_INFO_SIZE 3 |
41 | #define RTW_EX_CH_INFO_HDR_SIZE 2 |
42 | #define RTW_SCAN_WIDTH 0 |
43 | #define RTW_PRI_CH_IDX 1 |
44 | #define RTW_OLD_PROBE_PG_CNT 2 |
45 | #define RTW_PROBE_PG_CNT 4 |
46 | |
47 | #define RTW_DEBUG_DUMP_TIMES 10 |
48 | |
49 | enum rtw_c2h_cmd_id { |
50 | C2H_CCX_TX_RPT = 0x03, |
51 | C2H_BT_INFO = 0x09, |
52 | C2H_BT_MP_INFO = 0x0b, |
53 | C2H_BT_HID_INFO = 0x45, |
54 | C2H_RA_RPT = 0x0c, |
55 | C2H_HW_FEATURE_REPORT = 0x19, |
56 | C2H_WLAN_INFO = 0x27, |
57 | C2H_WLAN_RFON = 0x32, |
58 | C2H_BCN_FILTER_NOTIFY = 0x36, |
59 | C2H_ADAPTIVITY = 0x37, |
60 | C2H_SCAN_RESULT = 0x38, |
61 | C2H_HW_FEATURE_DUMP = 0xfd, |
62 | C2H_HALMAC = 0xff, |
63 | }; |
64 | |
65 | enum rtw_c2h_cmd_id_ext { |
66 | C2H_SCAN_STATUS_RPT = 0x3, |
67 | C2H_CCX_RPT = 0x0f, |
68 | C2H_CHAN_SWITCH = 0x22, |
69 | }; |
70 | |
71 | struct rtw_c2h_cmd { |
72 | u8 id; |
73 | u8 seq; |
74 | u8 payload[]; |
75 | } __packed; |
76 | |
77 | struct rtw_c2h_adaptivity { |
78 | u8 density; |
79 | u8 igi; |
80 | u8 l2h_th_init; |
81 | u8 l2h; |
82 | u8 h2l; |
83 | u8 option; |
84 | } __packed; |
85 | |
86 | struct rtw_h2c_register { |
87 | u32 w0; |
88 | u32 w1; |
89 | } __packed; |
90 | |
91 | #define RTW_H2C_W0_CMDID GENMASK(7, 0) |
92 | |
93 | /* H2C_CMD_DEFAULT_PORT command */ |
94 | #define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8) |
95 | #define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16) |
96 | |
97 | struct rtw_h2c_cmd { |
98 | __le32 msg; |
99 | __le32 msg_ext; |
100 | } __packed; |
101 | |
102 | enum rtw_rsvd_packet_type { |
103 | RSVD_BEACON, |
104 | RSVD_DUMMY, |
105 | RSVD_PS_POLL, |
106 | RSVD_PROBE_RESP, |
107 | RSVD_NULL, |
108 | RSVD_QOS_NULL, |
109 | RSVD_LPS_PG_DPK, |
110 | RSVD_LPS_PG_INFO, |
111 | RSVD_PROBE_REQ, |
112 | RSVD_NLO_INFO, |
113 | RSVD_CH_INFO, |
114 | }; |
115 | |
116 | enum rtw_fw_rf_type { |
117 | FW_RF_1T2R = 0, |
118 | FW_RF_2T4R = 1, |
119 | FW_RF_2T2R = 2, |
120 | FW_RF_2T3R = 3, |
121 | FW_RF_1T1R = 4, |
122 | FW_RF_2T2R_GREEN = 5, |
123 | FW_RF_3T3R = 6, |
124 | FW_RF_3T4R = 7, |
125 | FW_RF_4T4R = 8, |
126 | FW_RF_MAX_TYPE = 0xF, |
127 | }; |
128 | |
129 | enum rtw_fw_feature { |
130 | FW_FEATURE_SIG = BIT(0), |
131 | FW_FEATURE_LPS_C2H = BIT(1), |
132 | FW_FEATURE_LCLK = BIT(2), |
133 | FW_FEATURE_PG = BIT(3), |
134 | FW_FEATURE_TX_WAKE = BIT(4), |
135 | FW_FEATURE_BCN_FILTER = BIT(5), |
136 | FW_FEATURE_NOTIFY_SCAN = BIT(6), |
137 | FW_FEATURE_ADAPTIVITY = BIT(7), |
138 | FW_FEATURE_SCAN_OFFLOAD = BIT(8), |
139 | FW_FEATURE_MAX = BIT(31), |
140 | }; |
141 | |
142 | enum rtw_fw_feature_ext { |
143 | FW_FEATURE_EXT_OLD_PAGE_NUM = BIT(0), |
144 | }; |
145 | |
146 | enum rtw_beacon_filter_offload_mode { |
147 | BCN_FILTER_OFFLOAD_MODE_0 = 0, |
148 | BCN_FILTER_OFFLOAD_MODE_1, |
149 | BCN_FILTER_OFFLOAD_MODE_2, |
150 | BCN_FILTER_OFFLOAD_MODE_3, |
151 | |
152 | BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0, |
153 | }; |
154 | |
155 | struct rtw_coex_info_req { |
156 | u8 seq; |
157 | u8 op_code; |
158 | u8 para1; |
159 | u8 para2; |
160 | u8 para3; |
161 | }; |
162 | |
163 | struct rtw_iqk_para { |
164 | u8 clear; |
165 | u8 segment_iqk; |
166 | }; |
167 | |
168 | struct rtw_lps_pg_dpk_hdr { |
169 | u16 dpk_path_ok; |
170 | u8 dpk_txagc[2]; |
171 | u16 dpk_gs[2]; |
172 | u32 coef[2][20]; |
173 | u8 dpk_ch; |
174 | } __packed; |
175 | |
176 | struct rtw_lps_pg_info_hdr { |
177 | u8 macid; |
178 | u8 mbssid; |
179 | u8 pattern_count; |
180 | u8 mu_tab_group_id; |
181 | u8 sec_cam_count; |
182 | u8 tx_bu_page_count; |
183 | u16 rsvd; |
184 | u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; |
185 | } __packed; |
186 | |
187 | struct rtw_rsvd_page { |
188 | /* associated with each vif */ |
189 | struct list_head vif_list; |
190 | struct rtw_vif *rtwvif; |
191 | |
192 | /* associated when build rsvd page */ |
193 | struct list_head build_list; |
194 | |
195 | struct sk_buff *skb; |
196 | enum rtw_rsvd_packet_type type; |
197 | u8 page; |
198 | u16 tim_offset; |
199 | bool add_txdesc; |
200 | struct cfg80211_ssid *ssid; |
201 | u16 probe_req_size; |
202 | }; |
203 | |
204 | enum rtw_keep_alive_pkt_type { |
205 | KEEP_ALIVE_NULL_PKT = 0, |
206 | KEEP_ALIVE_ARP_RSP = 1, |
207 | }; |
208 | |
209 | struct rtw_nlo_info_hdr { |
210 | u8 nlo_count; |
211 | u8 hidden_ap_count; |
212 | u8 rsvd1[2]; |
213 | u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; |
214 | u8 rsvd2[8]; |
215 | u8 ssid_len[16]; |
216 | u8 chiper[16]; |
217 | u8 rsvd3[16]; |
218 | u8 location[8]; |
219 | } __packed; |
220 | |
221 | enum rtw_packet_type { |
222 | RTW_PACKET_PROBE_REQ = 0x00, |
223 | |
224 | RTW_PACKET_UNDEFINE = 0x7FFFFFFF, |
225 | }; |
226 | |
227 | struct rtw_fw_wow_keep_alive_para { |
228 | bool adopt; |
229 | u8 pkt_type; |
230 | u8 period; /* unit: sec */ |
231 | }; |
232 | |
233 | struct rtw_fw_wow_disconnect_para { |
234 | bool adopt; |
235 | u8 period; /* unit: sec */ |
236 | u8 retry_count; |
237 | }; |
238 | |
239 | enum rtw_channel_type { |
240 | RTW_CHANNEL_PASSIVE, |
241 | RTW_CHANNEL_ACTIVE, |
242 | RTW_CHANNEL_RADAR, |
243 | }; |
244 | |
245 | enum { |
246 | , |
247 | }; |
248 | |
249 | enum { |
250 | , |
251 | }; |
252 | |
253 | enum rtw_scan_report_code { |
254 | RTW_SCAN_REPORT_SUCCESS = 0x00, |
255 | RTW_SCAN_REPORT_ERR_PHYDM = 0x01, |
256 | RTW_SCAN_REPORT_ERR_ID = 0x02, |
257 | RTW_SCAN_REPORT_ERR_TX = 0x03, |
258 | RTW_SCAN_REPORT_CANCELED = 0x10, |
259 | RTW_SCAN_REPORT_CANCELED_EXT = 0x11, |
260 | RTW_SCAN_REPORT_FW_DISABLED = 0xF0, |
261 | }; |
262 | |
263 | enum rtw_scan_notify_id { |
264 | RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00, |
265 | RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01, |
266 | RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02, |
267 | RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03, |
268 | RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04, |
269 | RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05, |
270 | RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06, |
271 | RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07, |
272 | RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08, |
273 | RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09, |
274 | RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A, |
275 | }; |
276 | |
277 | enum rtw_scan_notify_status { |
278 | RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00, |
279 | RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01, |
280 | RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02, |
281 | RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03, |
282 | }; |
283 | |
284 | struct rtw_ch_switch_option { |
285 | u8 periodic_option; |
286 | u32 tsf_high; |
287 | u32 tsf_low; |
288 | u8 dest_ch_en; |
289 | u8 absolute_time_en; |
290 | u8 dest_ch; |
291 | u8 normal_period; |
292 | u8 normal_period_sel; |
293 | u8 normal_cycle; |
294 | u8 slow_period; |
295 | u8 slow_period_sel; |
296 | u8 nlo_en; |
297 | bool switch_en; |
298 | bool back_op_en; |
299 | }; |
300 | |
301 | struct rtw_fw_hdr { |
302 | __le16 signature; |
303 | u8 category; |
304 | u8 function; |
305 | __le16 version; /* 0x04 */ |
306 | u8 subversion; |
307 | u8 subindex; |
308 | __le32 rsvd; /* 0x08 */ |
309 | __le32 feature; /* 0x0C */ |
310 | u8 month; /* 0x10 */ |
311 | u8 day; |
312 | u8 hour; |
313 | u8 min; |
314 | __le16 year; /* 0x14 */ |
315 | __le16 rsvd3; |
316 | u8 mem_usage; /* 0x18 */ |
317 | u8 rsvd4[3]; |
318 | __le16 h2c_fmt_ver; /* 0x1C */ |
319 | __le16 rsvd5; |
320 | __le32 dmem_addr; /* 0x20 */ |
321 | __le32 dmem_size; |
322 | __le32 rsvd6; |
323 | __le32 rsvd7; |
324 | __le32 imem_size; /* 0x30 */ |
325 | __le32 emem_size; |
326 | __le32 emem_addr; |
327 | __le32 imem_addr; |
328 | } __packed; |
329 | |
330 | struct rtw_fw_hdr_legacy { |
331 | __le16 signature; |
332 | u8 category; |
333 | u8 function; |
334 | __le16 version; /* 0x04 */ |
335 | u8 subversion1; |
336 | u8 subversion2; |
337 | u8 month; /* 0x08 */ |
338 | u8 day; |
339 | u8 hour; |
340 | u8 minute; |
341 | __le16 size; |
342 | __le16 rsvd2; |
343 | __le32 idx; /* 0x10 */ |
344 | __le32 rsvd3; |
345 | __le32 rsvd4; /* 0x18 */ |
346 | __le32 rsvd5; |
347 | } __packed; |
348 | |
349 | #define RTW_FW_VER_CODE(ver, sub_ver, idx) \ |
350 | (((ver) << 16) | ((sub_ver) << 8) | (idx)) |
351 | #define RTW_FW_SUIT_VER_CODE(s) \ |
352 | RTW_FW_VER_CODE((s).version, (s).sub_version, (s).sub_index) |
353 | |
354 | /* C2H */ |
355 | #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) |
356 | #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) |
357 | #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) |
358 | #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) |
359 | |
360 | #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff) |
361 | |
362 | #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2]) |
363 | #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3]) |
364 | #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4]) |
365 | #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) |
366 | #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) |
367 | #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) |
368 | #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) |
369 | |
370 | #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf) |
371 | #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10) |
372 | #define (c2h_payload) (c2h_payload[2] - 100) |
373 | |
374 | /* PKT H2C */ |
375 | #define H2C_PKT_CMD_ID 0xFF |
376 | #define H2C_PKT_CATEGORY 0x01 |
377 | |
378 | #define H2C_PKT_GENERAL_INFO 0x0D |
379 | #define H2C_PKT_PHYDM_INFO 0x11 |
380 | #define H2C_PKT_IQK 0x0E |
381 | |
382 | #define H2C_PKT_CH_SWITCH 0x02 |
383 | #define H2C_PKT_UPDATE_PKT 0x0C |
384 | #define H2C_PKT_SCAN_OFFLOAD 0x19 |
385 | |
386 | #define H2C_PKT_CH_SWITCH_LEN 0x20 |
387 | #define H2C_PKT_UPDATE_PKT_LEN 0x4 |
388 | |
389 | #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ |
390 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) |
391 | #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ |
392 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
393 | #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ |
394 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) |
395 | #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ |
396 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) |
397 | |
398 | static inline void (u8 *h2c_pkt, u8 sub_id) |
399 | { |
400 | SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); |
401 | SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); |
402 | SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); |
403 | } |
404 | |
405 | #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ |
406 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) |
407 | #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ |
408 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) |
409 | |
410 | #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ |
411 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) |
412 | #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ |
413 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) |
414 | #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ |
415 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) |
416 | #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ |
417 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) |
418 | #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ |
419 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) |
420 | #define IQK_SET_CLEAR(h2c_pkt, value) \ |
421 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) |
422 | #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ |
423 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) |
424 | |
425 | #define CHSW_INFO_SET_CH(pkt, value) \ |
426 | le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) |
427 | #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ |
428 | le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) |
429 | #define CHSW_INFO_SET_BW(pkt, value) \ |
430 | le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) |
431 | #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ |
432 | le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) |
433 | #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ |
434 | le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) |
435 | #define (pkt, value) \ |
436 | le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31)) |
437 | |
438 | #define CH_INFO_SET_CH(pkt, value) \ |
439 | u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0)) |
440 | #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \ |
441 | u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0)) |
442 | #define CH_INFO_SET_BW(pkt, value) \ |
443 | u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4)) |
444 | #define CH_INFO_SET_TIMEOUT(pkt, value) \ |
445 | u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0)) |
446 | #define CH_INFO_SET_ACTION_ID(pkt, value) \ |
447 | u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0)) |
448 | #define (pkt, value) \ |
449 | u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7)) |
450 | |
451 | #define (pkt, value) \ |
452 | u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0)) |
453 | #define (pkt, value) \ |
454 | u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7)) |
455 | #define (pkt, value) \ |
456 | u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0)) |
457 | #define (pkt, value) \ |
458 | u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0)) |
459 | |
460 | #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ |
461 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) |
462 | #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ |
463 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) |
464 | #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ |
465 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) |
466 | |
467 | #define CH_SWITCH_SET_START(h2c_pkt, value) \ |
468 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) |
469 | #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ |
470 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) |
471 | #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ |
472 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) |
473 | #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ |
474 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) |
475 | #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \ |
476 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5)) |
477 | #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \ |
478 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6)) |
479 | #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ |
480 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) |
481 | #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ |
482 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) |
483 | #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ |
484 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) |
485 | #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ |
486 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) |
487 | #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ |
488 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) |
489 | #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ |
490 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) |
491 | #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ |
492 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) |
493 | #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ |
494 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) |
495 | #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ |
496 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) |
497 | #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ |
498 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) |
499 | #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ |
500 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) |
501 | #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ |
502 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) |
503 | #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ |
504 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) |
505 | |
506 | #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \ |
507 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) |
508 | #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \ |
509 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) |
510 | #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \ |
511 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) |
512 | #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \ |
513 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3)) |
514 | #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \ |
515 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4)) |
516 | #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \ |
517 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) |
518 | #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \ |
519 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16)) |
520 | #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \ |
521 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) |
522 | #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \ |
523 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8)) |
524 | #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \ |
525 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16)) |
526 | #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \ |
527 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20)) |
528 | #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \ |
529 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24)) |
530 | #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \ |
531 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0)) |
532 | #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \ |
533 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16)) |
534 | #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \ |
535 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0)) |
536 | #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \ |
537 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4)) |
538 | #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \ |
539 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8)) |
540 | |
541 | /* Command H2C */ |
542 | #define H2C_CMD_RSVD_PAGE 0x0 |
543 | #define H2C_CMD_MEDIA_STATUS_RPT 0x01 |
544 | #define H2C_CMD_SET_PWR_MODE 0x20 |
545 | #define H2C_CMD_LPS_PG_INFO 0x2b |
546 | #define H2C_CMD_DEFAULT_PORT 0x2c |
547 | #define H2C_CMD_RA_INFO 0x40 |
548 | #define 0x42 |
549 | #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56 |
550 | #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57 |
551 | #define H2C_CMD_WL_PHY_INFO 0x58 |
552 | #define H2C_CMD_SCAN 0x59 |
553 | #define H2C_CMD_ADAPTIVITY 0x5A |
554 | |
555 | #define H2C_CMD_COEX_TDMA_TYPE 0x60 |
556 | #define H2C_CMD_QUERY_BT_INFO 0x61 |
557 | #define H2C_CMD_FORCE_BT_TX_POWER 0x62 |
558 | #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 |
559 | #define H2C_CMD_WL_CH_INFO 0x66 |
560 | #define H2C_CMD_QUERY_BT_MP_INFO 0x67 |
561 | #define H2C_CMD_BT_WIFI_CONTROL 0x69 |
562 | #define H2C_CMD_WIFI_CALIBRATION 0x6d |
563 | #define H2C_CMD_QUERY_BT_HID_INFO 0x73 |
564 | |
565 | #define H2C_CMD_KEEP_ALIVE 0x03 |
566 | #define H2C_CMD_DISCONNECT_DECISION 0x04 |
567 | #define H2C_CMD_WOWLAN 0x80 |
568 | #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 |
569 | #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 |
570 | #define H2C_CMD_NLO_INFO 0x8C |
571 | |
572 | #define H2C_CMD_RECOVER_BT_DEV 0xD1 |
573 | |
574 | #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ |
575 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) |
576 | |
577 | #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ |
578 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
579 | #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ |
580 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
581 | |
582 | #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ |
583 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) |
584 | #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ |
585 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) |
586 | #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ |
587 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) |
588 | #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ |
589 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) |
590 | #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ |
591 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) |
592 | #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \ |
593 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
594 | #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \ |
595 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16)) |
596 | #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \ |
597 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17)) |
598 | #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \ |
599 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21)) |
600 | #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \ |
601 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
602 | #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \ |
603 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0)) |
604 | #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \ |
605 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4)) |
606 | |
607 | #define SET_SCAN_START(h2c_pkt, value) \ |
608 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
609 | |
610 | #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \ |
611 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8)) |
612 | #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \ |
613 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) |
614 | #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \ |
615 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
616 | #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \ |
617 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
618 | #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \ |
619 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) |
620 | |
621 | #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ |
622 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) |
623 | #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ |
624 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) |
625 | #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ |
626 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) |
627 | #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ |
628 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
629 | #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ |
630 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) |
631 | #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ |
632 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) |
633 | #define LPS_PG_INFO_LOC(h2c_pkt, value) \ |
634 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
635 | #define LPS_PG_DPK_LOC(h2c_pkt, value) \ |
636 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
637 | #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ |
638 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
639 | #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ |
640 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) |
641 | #define (h2c_pkt, value) \ |
642 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
643 | #define (h2c_pkt, value) \ |
644 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
645 | #define (h2c_pkt, value) \ |
646 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) |
647 | #define SET_RA_INFO_MACID(h2c_pkt, value) \ |
648 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
649 | #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ |
650 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) |
651 | #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ |
652 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) |
653 | #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ |
654 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) |
655 | #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ |
656 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) |
657 | #define SET_RA_INFO_LDPC(h2c_pkt, value) \ |
658 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) |
659 | #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ |
660 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) |
661 | #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ |
662 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) |
663 | #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ |
664 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) |
665 | #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ |
666 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) |
667 | #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ |
668 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) |
669 | #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ |
670 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) |
671 | #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ |
672 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) |
673 | #define SET_QUERY_BT_INFO(h2c_pkt, value) \ |
674 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
675 | #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ |
676 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
677 | #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ |
678 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
679 | #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ |
680 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
681 | #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ |
682 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) |
683 | #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ |
684 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
685 | #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ |
686 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
687 | #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ |
688 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) |
689 | #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ |
690 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) |
691 | #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ |
692 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
693 | #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ |
694 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
695 | #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ |
696 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
697 | #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ |
698 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
699 | #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ |
700 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
701 | #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ |
702 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) |
703 | #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ |
704 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) |
705 | #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ |
706 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
707 | #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ |
708 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
709 | #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ |
710 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
711 | #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ |
712 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) |
713 | #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ |
714 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) |
715 | #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ |
716 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) |
717 | |
718 | #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \ |
719 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
720 | #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \ |
721 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
722 | |
723 | #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ |
724 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
725 | #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ |
726 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) |
727 | #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ |
728 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) |
729 | #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ |
730 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
731 | |
732 | #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ |
733 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
734 | #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ |
735 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) |
736 | #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ |
737 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
738 | #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ |
739 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) |
740 | |
741 | #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ |
742 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
743 | #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ |
744 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) |
745 | #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ |
746 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) |
747 | #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ |
748 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) |
749 | #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ |
750 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) |
751 | #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ |
752 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) |
753 | |
754 | #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ |
755 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
756 | #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ |
757 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) |
758 | |
759 | #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ |
760 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) |
761 | #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ |
762 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
763 | |
764 | #define SET_NLO_FUN_EN(h2c_pkt, value) \ |
765 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
766 | #define SET_NLO_PS_32K(h2c_pkt, value) \ |
767 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) |
768 | #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ |
769 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) |
770 | #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ |
771 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) |
772 | |
773 | #define SET_RECOVER_BT_DEV_EN(h2c_pkt, value) \ |
774 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
775 | |
776 | #define GET_FW_DUMP_LEN(_header) \ |
777 | le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) |
778 | #define GET_FW_DUMP_SEQ(_header) \ |
779 | le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) |
780 | #define GET_FW_DUMP_MORE(_header) \ |
781 | le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) |
782 | #define GET_FW_DUMP_VERSION(_header) \ |
783 | le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) |
784 | #define GET_FW_DUMP_TLV_TYPE(_header) \ |
785 | le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) |
786 | #define GET_FW_DUMP_TLV_LEN(_header) \ |
787 | le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) |
788 | #define GET_FW_DUMP_TLV_VAL(_header) \ |
789 | le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) |
790 | |
791 | #define RFK_SET_INFORM_START(h2c_pkt, value) \ |
792 | le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) |
793 | static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) |
794 | { |
795 | u32 pkt_offset; |
796 | |
797 | pkt_offset = *((u32 *)skb->cb); |
798 | return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); |
799 | } |
800 | |
801 | static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw, |
802 | enum rtw_fw_feature feature) |
803 | { |
804 | return !!(fw->feature & feature); |
805 | } |
806 | |
807 | static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw, |
808 | enum rtw_fw_feature_ext feature) |
809 | { |
810 | return !!(fw->feature_ext & feature); |
811 | } |
812 | |
813 | void rtw_fw_dump_dbg_info(struct rtw_dev *rtwdev); |
814 | void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, |
815 | struct sk_buff *skb); |
816 | void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); |
817 | void rtw_fw_send_general_info(struct rtw_dev *rtwdev); |
818 | void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); |
819 | void rtw_fw_default_port(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif); |
820 | |
821 | void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); |
822 | void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); |
823 | void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); |
824 | void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); |
825 | void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); |
826 | void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); |
827 | void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, |
828 | struct rtw_coex_info_req *req); |
829 | void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); |
830 | void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); |
831 | void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, |
832 | u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); |
833 | void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data); |
834 | |
835 | void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); |
836 | void (struct rtw_dev *rtwdev, struct rtw_sta_info *si); |
837 | void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, |
838 | bool reset_ra_mask); |
839 | void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); |
840 | void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); |
841 | void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect, |
842 | struct ieee80211_vif *vif); |
843 | int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, |
844 | u8 *buf, u32 size); |
845 | void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, |
846 | struct rtw_vif *rtwvif); |
847 | void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, |
848 | struct rtw_vif *rtwvif); |
849 | void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, |
850 | struct rtw_vif *rtwvif); |
851 | void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, |
852 | struct rtw_vif *rtwvif); |
853 | int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); |
854 | void rtw_fw_update_beacon_work(struct work_struct *work); |
855 | void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); |
856 | int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, |
857 | u32 offset, u32 size, u32 *buf); |
858 | void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); |
859 | void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); |
860 | void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); |
861 | void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); |
862 | void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, |
863 | u8 pairwise_key_enc, |
864 | u8 group_key_enc); |
865 | |
866 | void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); |
867 | void rtw_fw_set_recover_bt_device(struct rtw_dev *rtwdev); |
868 | void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, |
869 | struct cfg80211_ssid *ssid); |
870 | void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); |
871 | void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); |
872 | void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); |
873 | int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, |
874 | u32 *buffer); |
875 | void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start); |
876 | void rtw_fw_adaptivity(struct rtw_dev *rtwdev); |
877 | void rtw_store_op_chan(struct rtw_dev *rtwdev, bool backup); |
878 | void rtw_clear_op_chan(struct rtw_dev *rtwdev); |
879 | void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, |
880 | struct ieee80211_scan_request *req); |
881 | void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, |
882 | bool aborted); |
883 | int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, |
884 | bool enable); |
885 | void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb); |
886 | void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb); |
887 | void rtw_hw_scan_abort(struct rtw_dev *rtwdev); |
888 | #endif |
889 | |