| 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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| 2 | /* Copyright(c) 2018-2019 Realtek Corporation |
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| 3 | */ |
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| 4 | |
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| 5 | #ifndef __RTW_MAC_H__ |
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| 6 | #define __RTW_MAC_H__ |
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| 7 | |
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| 8 | #define RTW_HW_PORT_NUM 5 |
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| 9 | #define cut_version_to_mask(cut) (0x1 << ((cut) + 1)) |
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| 10 | #define DDMA_POLLING_COUNT 1000 |
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| 11 | #define C2H_PKT_BUF 256 |
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| 12 | #define REPORT_BUF 128 |
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| 13 | #define PHY_STATUS_SIZE 4 |
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| 14 | #define ILLEGAL_KEY_GROUP 0xFAAAAA00 |
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| 15 | |
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| 16 | /* HW memory address */ |
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| 17 | #define OCPBASE_RXBUF_FW_88XX 0x18680000 |
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| 18 | #define OCPBASE_TXBUF_88XX 0x18780000 |
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| 19 | #define OCPBASE_ROM_88XX 0x00000000 |
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| 20 | #define OCPBASE_IMEM_88XX 0x00030000 |
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| 21 | #define OCPBASE_DMEM_88XX 0x00200000 |
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| 22 | #define OCPBASE_EMEM_88XX 0x00100000 |
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| 23 | |
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| 24 | #define RSVD_PG_DRV_NUM 16 |
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| 25 | #define 24 |
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| 26 | #define RSVD_PG_H2C_STATICINFO_NUM 8 |
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| 27 | #define RSVD_PG_H2CQ_NUM 8 |
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| 28 | #define RSVD_PG_CPU_INSTRUCTION_NUM 0 |
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| 29 | #define RSVD_PG_FW_TXBUF_NUM 4 |
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| 30 | |
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| 31 | void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, |
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| 32 | u8 primary_ch_idx); |
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| 33 | int rtw_mac_power_on(struct rtw_dev *rtwdev); |
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| 34 | void rtw_mac_power_off(struct rtw_dev *rtwdev); |
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| 35 | int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw); |
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| 36 | int rtw_mac_init(struct rtw_dev *rtwdev); |
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| 37 | void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop); |
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| 38 | int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size); |
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| 39 | |
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| 40 | static inline void rtw_mac_flush_all_queues(struct rtw_dev *rtwdev, bool drop) |
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| 41 | { |
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| 42 | rtw_mac_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, drop); |
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| 43 | } |
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| 44 | |
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| 45 | #endif |
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| 46 | |
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