| 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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| 2 | /* Copyright(c) 2018-2019 Realtek Corporation |
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| 3 | */ |
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| 4 | |
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| 5 | #ifndef __RTW_REG_DEF_H__ |
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| 6 | #define __RTW_REG_DEF_H__ |
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| 7 | |
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| 8 | #define REG_SYS_FUNC_EN 0x0002 |
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| 9 | #define BIT_FEN_EN_25_1 BIT(13) |
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| 10 | #define BIT_FEN_ELDR BIT(12) |
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| 11 | #define BIT_FEN_CPUEN BIT(2) |
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| 12 | #define BIT_FEN_BB_GLB_RST BIT(1) |
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| 13 | #define BIT_FEN_BB_RSTB BIT(0) |
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| 14 | #define BIT_R_DIS_PRST BIT(6) |
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| 15 | #define BIT_WLOCK_1C_B6 BIT(5) |
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| 16 | #define REG_SYS_PW_CTRL 0x0004 |
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| 17 | #define BIT_PFM_WOWL BIT(3) |
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| 18 | #define REG_SYS_CLK_CTRL 0x0008 |
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| 19 | #define BIT_CPU_CLK_EN BIT(14) |
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| 20 | |
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| 21 | #define REG_SYS_CLKR 0x0008 |
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| 22 | #define BIT_ANA8M BIT(1) |
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| 23 | #define BIT_WAKEPAD_EN BIT(3) |
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| 24 | #define BIT_LOADER_CLK_EN BIT(5) |
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| 25 | |
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| 26 | #define REG_RSV_CTRL 0x001C |
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| 27 | #define DISABLE_PI 0x3 |
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| 28 | #define ENABLE_PI 0x2 |
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| 29 | #define BITS_RFC_DIRECT (BIT(31) | BIT(30)) |
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| 30 | #define BIT_WLMCU_IOIF BIT(0) |
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| 31 | #define REG_RF_CTRL 0x001F |
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| 32 | #define BIT_RF_SDM_RSTB BIT(2) |
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| 33 | #define BIT_RF_RSTB BIT(1) |
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| 34 | #define BIT_RF_EN BIT(0) |
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| 35 | |
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| 36 | #define REG_AFE_CTRL1 0x0024 |
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| 37 | #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21)) |
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| 38 | #define REG_EFUSE_CTRL 0x0030 |
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| 39 | #define BIT_EF_FLAG BIT(31) |
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| 40 | #define BIT_SHIFT_EF_ADDR 8 |
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| 41 | #define BIT_MASK_EF_ADDR 0x3ff |
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| 42 | #define BIT_MASK_EF_DATA 0xff |
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| 43 | #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) |
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| 44 | #define BITS_PLL 0xf0 |
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| 45 | |
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| 46 | #define REG_AFE_XTAL_CTRL 0x24 |
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| 47 | #define REG_AFE_PLL_CTRL 0x28 |
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| 48 | #define REG_AFE_CTRL3 0x2c |
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| 49 | #define BIT_MASK_XTAL 0x00FFF000 |
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| 50 | #define BIT_XTAL_GMP_BIT4 BIT(28) |
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| 51 | |
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| 52 | #define REG_LDO_EFUSE_CTRL 0x0034 |
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| 53 | #define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9)) |
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| 54 | |
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| 55 | #define BIT_LDO25_VOLTAGE_V25 0x03 |
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| 56 | #define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4) |
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| 57 | #define BIT_SHIFT_LDO25_VOLTAGE 4 |
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| 58 | #define BIT_LDO25_EN BIT(7) |
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| 59 | |
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| 60 | #define REG_GPIO_MUXCFG 0x0040 |
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| 61 | #define BIT_FSPI_EN BIT(19) |
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| 62 | #define BIT_EN_SIC BIT(12) |
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| 63 | |
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| 64 | #define BIT_PO_BT_PTA_PINS BIT(9) |
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| 65 | #define BIT_BT_PTA_EN BIT(5) |
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| 66 | #define BIT_WLRFE_4_5_EN BIT(2) |
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| 67 | |
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| 68 | #define REG_LED_CFG 0x004C |
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| 69 | #define BIT_LNAON_SEL_EN BIT(26) |
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| 70 | #define BIT_PAPE_SEL_EN BIT(25) |
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| 71 | #define BIT_DPDT_WL_SEL BIT(24) |
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| 72 | #define BIT_DPDT_SEL_EN BIT(23) |
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| 73 | #define REG_LEDCFG2 0x004E |
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| 74 | #define REG_PAD_CTRL1 0x0064 |
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| 75 | #define BIT_BT_BTG_SEL BIT(31) |
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| 76 | #define BIT_PAPE_WLBT_SEL BIT(29) |
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| 77 | #define BIT_LNAON_WLBT_SEL BIT(28) |
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| 78 | #define BIT_BTGP_JTAG_EN BIT(24) |
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| 79 | #define BIT_BTGP_SPI_EN BIT(20) |
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| 80 | #define BIT_LED1DIS BIT(15) |
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| 81 | #define BIT_SW_DPDT_SEL_DATA BIT(0) |
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| 82 | #define REG_WL_BT_PWR_CTRL 0x0068 |
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| 83 | #define BIT_BT_FUNC_EN BIT(18) |
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| 84 | #define BIT_BT_DIG_CLK_EN BIT(8) |
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| 85 | #define REG_SYS_SDIO_CTRL 0x0070 |
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| 86 | #define BIT_DBG_GNT_WL_BT BIT(27) |
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| 87 | #define BIT_LTE_MUX_CTRL_PATH BIT(26) |
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| 88 | #define REG_HCI_OPT_CTRL 0x0074 |
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| 89 | #define BIT_USB_SUS_DIS BIT(8) |
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| 90 | #define BIT_SDIO_PAD_E5 BIT(18) |
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| 91 | |
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| 92 | #define REG_AFE_CTRL_4 0x0078 |
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| 93 | #define BIT_CK320M_AFE_EN BIT(4) |
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| 94 | #define BIT_EN_SYN BIT(15) |
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| 95 | |
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| 96 | #define REG_LDO_SWR_CTRL 0x007C |
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| 97 | #define LDO_SEL 0xC3 |
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| 98 | #define SPS_SEL 0x83 |
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| 99 | #define BIT_XTA1 BIT(29) |
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| 100 | #define BIT_XTA0 BIT(28) |
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| 101 | |
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| 102 | #define REG_MCUFW_CTRL 0x0080 |
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| 103 | #define BIT_ANA_PORT_EN BIT(22) |
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| 104 | #define BIT_MAC_PORT_EN BIT(21) |
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| 105 | #define BIT_BOOT_FSPI_EN BIT(20) |
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| 106 | #define BIT_ROM_DLEN BIT(19) |
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| 107 | #define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */ |
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| 108 | #define BIT_SHIFT_ROM_PGE 16 |
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| 109 | #define BIT_FW_INIT_RDY BIT(15) |
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| 110 | #define BIT_FW_DW_RDY BIT(14) |
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| 111 | #define BIT_RPWM_TOGGLE BIT(7) |
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| 112 | #define BIT_RAM_DL_SEL BIT(7) /* legacy only */ |
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| 113 | #define BIT_DMEM_CHKSUM_OK BIT(6) |
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| 114 | #define BIT_WINTINI_RDY BIT(6) /* legacy only */ |
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| 115 | #define BIT_DMEM_DW_OK BIT(5) |
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| 116 | #define BIT_IMEM_CHKSUM_OK BIT(4) |
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| 117 | #define BIT_IMEM_DW_OK BIT(3) |
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| 118 | #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2) |
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| 119 | #define BIT_FWDL_CHK_RPT BIT(2) /* legacy only */ |
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| 120 | #define BIT_MCUFWDL_RDY BIT(1) /* legacy only */ |
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| 121 | #define BIT_MCUFWDL_EN BIT(0) |
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| 122 | #define BIT_CHECK_SUM_OK (BIT(4) | BIT(6)) |
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| 123 | #define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \ |
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| 124 | BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \ |
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| 125 | BIT_CHECK_SUM_OK) |
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| 126 | #define FW_READY_LEGACY (BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT | \ |
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| 127 | BIT_WINTINI_RDY | BIT_RAM_DL_SEL) |
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| 128 | #define FW_READY_MASK 0xffff |
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| 129 | |
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| 130 | #define REG_MCU_TST_CFG 0x84 |
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| 131 | #define VAL_FW_TRIGGER 0x1 |
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| 132 | |
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| 133 | #define REG_PMC_DBG_CTRL1 0xa8 |
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| 134 | #define BITS_PMC_BT_IQK_STS GENMASK(22, 21) |
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| 135 | |
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| 136 | #define REG_EFUSE_ACCESS 0x00CF |
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| 137 | #define EFUSE_ACCESS_ON 0x69 |
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| 138 | #define EFUSE_ACCESS_OFF 0x00 |
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| 139 | |
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| 140 | #define REG_WLRF1 0x00EC |
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| 141 | #define REG_WIFI_BT_INFO 0x00AA |
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| 142 | #define BIT_BT_INT_EN BIT(15) |
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| 143 | #define REG_SYS_CFG1 0x00F0 |
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| 144 | #define BIT_RTL_ID BIT(23) |
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| 145 | #define BIT_LDO BIT(24) |
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| 146 | #define BIT_RF_TYPE_ID BIT(27) |
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| 147 | #define BIT_SHIFT_VENDOR_ID 16 |
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| 148 | #define BIT_MASK_VENDOR_ID 0xf |
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| 149 | #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) |
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| 150 | #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) |
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| 151 | #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) |
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| 152 | #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) |
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| 153 | #define BIT_SHIFT_CHIP_VER 12 |
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| 154 | #define BIT_MASK_CHIP_VER 0xf |
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| 155 | #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) |
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| 156 | #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) |
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| 157 | #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) |
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| 158 | #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) |
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| 159 | #define REG_SYS_STATUS1 0x00F4 |
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| 160 | #define REG_SYS_STATUS2 0x00F8 |
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| 161 | #define REG_SYS_CFG2 0x00FC |
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| 162 | #define REG_WLRF1 0x00EC |
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| 163 | #define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26)) |
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| 164 | #define REG_CR 0x0100 |
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| 165 | #define BIT_32K_CAL_TMR_EN BIT(10) |
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| 166 | #define BIT_MAC_SEC_EN BIT(9) |
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| 167 | #define BIT_ENSWBCN BIT(8) |
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| 168 | #define BIT_MACRXEN BIT(7) |
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| 169 | #define BIT_MACTXEN BIT(6) |
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| 170 | #define BIT_SCHEDULE_EN BIT(5) |
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| 171 | #define BIT_PROTOCOL_EN BIT(4) |
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| 172 | #define BIT_RXDMA_EN BIT(3) |
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| 173 | #define BIT_TXDMA_EN BIT(2) |
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| 174 | #define BIT_HCI_RXDMA_EN BIT(1) |
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| 175 | #define BIT_HCI_TXDMA_EN BIT(0) |
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| 176 | #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ |
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| 177 | BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ |
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| 178 | BIT_MACTXEN | BIT_MACRXEN) |
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| 179 | #define BIT_SHIFT_TXDMA_VOQ_MAP 4 |
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| 180 | #define BIT_MASK_TXDMA_VOQ_MAP 0x3 |
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| 181 | #define BIT_TXDMA_VOQ_MAP(x) \ |
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| 182 | (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) |
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| 183 | #define BIT_SHIFT_TXDMA_VIQ_MAP 6 |
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| 184 | #define BIT_MASK_TXDMA_VIQ_MAP 0x3 |
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| 185 | #define BIT_TXDMA_VIQ_MAP(x) \ |
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| 186 | (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) |
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| 187 | #define REG_TXDMA_PQ_MAP 0x010C |
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| 188 | #define BIT_RXDMA_ARBBW_EN BIT(0) |
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| 189 | #define BIT_RXSHFT_EN BIT(1) |
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| 190 | #define BIT_RXDMA_AGG_EN BIT(2) |
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| 191 | #define BIT_TXDMA_BW_EN BIT(3) |
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| 192 | #define BIT_SHIFT_TXDMA_BEQ_MAP 8 |
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| 193 | #define BIT_MASK_TXDMA_BEQ_MAP 0x3 |
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| 194 | #define BIT_TXDMA_BEQ_MAP(x) \ |
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| 195 | (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) |
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| 196 | #define BIT_SHIFT_TXDMA_BKQ_MAP 10 |
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| 197 | #define BIT_MASK_TXDMA_BKQ_MAP 0x3 |
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| 198 | #define BIT_TXDMA_BKQ_MAP(x) \ |
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| 199 | (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) |
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| 200 | #define BIT_SHIFT_TXDMA_MGQ_MAP 12 |
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| 201 | #define BIT_MASK_TXDMA_MGQ_MAP 0x3 |
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| 202 | #define BIT_TXDMA_MGQ_MAP(x) \ |
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| 203 | (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) |
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| 204 | #define BIT_SHIFT_TXDMA_HIQ_MAP 14 |
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| 205 | #define BIT_MASK_TXDMA_HIQ_MAP 0x3 |
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| 206 | #define BIT_TXDMA_HIQ_MAP(x) \ |
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| 207 | (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) |
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| 208 | #define BIT_SHIFT_TXSC_40M 4 |
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| 209 | #define BIT_MASK_TXSC_40M 0xf |
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| 210 | #define BIT_TXSC_40M(x) \ |
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| 211 | (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) |
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| 212 | #define BIT_SHIFT_TXSC_20M 0 |
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| 213 | #define BIT_MASK_TXSC_20M 0xf |
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| 214 | #define BIT_TXSC_20M(x) \ |
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| 215 | (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) |
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| 216 | #define BIT_SHIFT_MAC_CLK_SEL 20 |
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| 217 | #define MAC_CLK_HW_DEF_80M 0 |
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| 218 | #define MAC_CLK_HW_DEF_40M 1 |
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| 219 | #define MAC_CLK_HW_DEF_20M 2 |
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| 220 | #define MAC_CLK_SPEED 80 |
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| 221 | |
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| 222 | #define REG_CR 0x0100 |
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| 223 | #define REG_TRXFF_BNDY 0x0114 |
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| 224 | #define REG_RXFF_BNDY 0x011C |
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| 225 | #define REG_FE1IMR 0x0120 |
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| 226 | #define BIT_FS_RXDONE BIT(16) |
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| 227 | #define REG_CPWM 0x012C |
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| 228 | #define REG_FWIMR 0x0130 |
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| 229 | #define BIT_FS_H2CCMD_INT_EN BIT(4) |
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| 230 | #define BIT_FS_HRCV_INT_EN BIT(5) |
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| 231 | #define REG_FWISR 0x0134 |
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| 232 | #define BIT_FS_H2CCMD_INT BIT(4) |
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| 233 | #define BIT_FS_HRCV_INT BIT(5) |
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| 234 | #define REG_PKTBUF_DBG_CTRL 0x0140 |
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| 235 | #define REG_C2HEVT 0x01A0 |
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| 236 | #define REG_MCUTST_1 0x01C0 |
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| 237 | #define REG_MCUTST_II 0x01C4 |
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| 238 | #define REG_WOWLAN_WAKE_REASON 0x01C7 |
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| 239 | #define REG_HMETFR 0x01CC |
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| 240 | #define BIT_INT_BOX0 BIT(0) |
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| 241 | #define BIT_INT_BOX1 BIT(1) |
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| 242 | #define BIT_INT_BOX2 BIT(2) |
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| 243 | #define BIT_INT_BOX3 BIT(3) |
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| 244 | #define BIT_INT_BOX_ALL (BIT_INT_BOX0 | BIT_INT_BOX1 | BIT_INT_BOX2 | \ |
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| 245 | BIT_INT_BOX3) |
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| 246 | #define REG_HMEBOX0 0x01D0 |
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| 247 | #define REG_HMEBOX1 0x01D4 |
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| 248 | #define REG_HMEBOX2 0x01D8 |
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| 249 | #define REG_HMEBOX3 0x01DC |
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| 250 | #define REG_HMEBOX0_EX 0x01F0 |
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| 251 | #define REG_HMEBOX1_EX 0x01F4 |
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| 252 | #define REG_HMEBOX2_EX 0x01F8 |
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| 253 | #define REG_HMEBOX3_EX 0x01FC |
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| 254 | |
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| 255 | #define REG_RQPN 0x0200 |
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| 256 | #define BIT_MASK_HPQ 0xff |
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| 257 | #define BIT_SHIFT_HPQ 0 |
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| 258 | #define BIT_RQPN_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) |
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| 259 | #define BIT_MASK_LPQ 0xff |
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| 260 | #define BIT_SHIFT_LPQ 8 |
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| 261 | #define BIT_RQPN_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) |
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| 262 | #define BIT_MASK_PUBQ 0xff |
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| 263 | #define BIT_SHIFT_PUBQ 16 |
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| 264 | #define BIT_RQPN_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) |
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| 265 | #define BIT_RQPN_HLP(h, l, p) (BIT_LD_RQPN | BIT_RQPN_HPQ(h) | \ |
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| 266 | BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p)) |
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| 267 | |
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| 268 | #define REG_FIFOPAGE_CTRL_2 0x0204 |
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| 269 | #define BIT_BCN_VALID_V1 BIT(15) |
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| 270 | #define BIT_MASK_BCN_HEAD_1_V1 0xfff |
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| 271 | #define REG_AUTO_LLT_V1 0x0208 |
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| 272 | #define BIT_AUTO_INIT_LLT_V1 BIT(0) |
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| 273 | #define REG_DWBCN0_CTRL 0x0208 |
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| 274 | #define BIT_BCN_VALID BIT(16) |
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| 275 | #define REG_TXDMA_OFFSET_CHK 0x020C |
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| 276 | #define BIT_DROP_DATA_EN BIT(9) |
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| 277 | #define REG_TXDMA_STATUS 0x0210 |
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| 278 | #define BTI_PAGE_OVF BIT(2) |
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| 279 | |
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| 280 | #define REG_RQPN_NPQ 0x0214 |
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| 281 | #define BIT_MASK_NPQ 0xff |
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| 282 | #define BIT_SHIFT_NPQ 0 |
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| 283 | #define BIT_MASK_EPQ 0xff |
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| 284 | #define BIT_SHIFT_EPQ 16 |
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| 285 | #define BIT_RQPN_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) |
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| 286 | #define BIT_RQPN_EPQ(x) (((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ) |
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| 287 | #define BIT_RQPN_NE(n, e) (BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e)) |
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| 288 | |
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| 289 | #define REG_AUTO_LLT 0x0224 |
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| 290 | #define BIT_AUTO_INIT_LLT BIT(16) |
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| 291 | #define REG_RQPN_CTRL_1 0x0228 |
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| 292 | #define REG_RQPN_CTRL_2 0x022C |
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| 293 | #define BIT_LD_RQPN BIT(31) |
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| 294 | #define REG_FIFOPAGE_INFO_1 0x0230 |
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| 295 | #define REG_FIFOPAGE_INFO_2 0x0234 |
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| 296 | #define REG_FIFOPAGE_INFO_3 0x0238 |
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| 297 | #define REG_FIFOPAGE_INFO_4 0x023C |
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| 298 | #define REG_FIFOPAGE_INFO_5 0x0240 |
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| 299 | #define REG_H2C_HEAD 0x0244 |
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| 300 | #define REG_H2C_TAIL 0x0248 |
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| 301 | #define REG_H2C_READ_ADDR 0x024C |
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| 302 | #define REG_H2C_INFO 0x0254 |
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| 303 | #define REG_RXDMA_AGG_PG_TH 0x0280 |
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| 304 | #define BIT_RXDMA_AGG_PG_TH GENMASK(7, 0) |
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| 305 | #define BIT_DMA_AGG_TO_V1 GENMASK(15, 8) |
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| 306 | #define BIT_EN_PRE_CALC BIT(29) |
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| 307 | #define REG_RXPKT_NUM 0x0284 |
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| 308 | #define BIT_RXDMA_REQ BIT(19) |
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| 309 | #define BIT_RW_RELEASE BIT(18) |
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| 310 | #define BIT_RXDMA_IDLE BIT(17) |
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| 311 | #define REG_RXDMA_STATUS 0x0288 |
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| 312 | #define REG_RXDMA_DPR 0x028C |
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| 313 | #define REG_RXDMA_MODE 0x0290 |
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| 314 | #define BIT_DMA_MODE BIT(1) |
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| 315 | #define REG_RXPKTNUM 0x02B0 |
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| 316 | |
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| 317 | #define REG_INT_MIG 0x0304 |
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| 318 | #define REG_HCI_MIX_CFG 0x03FC |
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| 319 | #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26) |
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| 320 | |
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| 321 | #define REG_BCNQ_INFO 0x0418 |
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| 322 | #define BIT_MGQ_CPU_EMPTY BIT(24) |
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| 323 | #define REG_FWHW_TXQ_CTRL 0x0420 |
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| 324 | #define BIT_EN_BCNQ_DL BIT(22) |
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| 325 | #define BIT_EN_WR_FREE_TAIL BIT(20) |
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| 326 | #define REG_HWSEQ_CTRL 0x0423 |
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| 327 | |
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| 328 | #define REG_BCNQ_BDNY_V1 0x0424 |
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| 329 | #define REG_BCNQ_BDNY 0x0424 |
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| 330 | #define REG_MGQ_BDNY 0x0425 |
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| 331 | #define REG_LIFETIME_EN 0x0426 |
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| 332 | #define BIT_BA_PARSER_EN BIT(5) |
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| 333 | #define REG_SPEC_SIFS 0x0428 |
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| 334 | #define REG_RETRY_LIMIT 0x042a |
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| 335 | #define REG_DARFRC 0x0430 |
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| 336 | #define REG_DARFRCH 0x0434 |
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| 337 | #define REG_RARFRCH 0x043C |
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| 338 | #define REG_RRSR 0x0440 |
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| 339 | #define BITS_RRSR_RSC GENMASK(22, 21) |
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| 340 | #define REG_ARFR0 0x0444 |
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| 341 | #define REG_ARFRH0 0x0448 |
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| 342 | #define REG_ARFR1_V1 0x044C |
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| 343 | #define REG_ARFRH1_V1 0x0450 |
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| 344 | #define REG_CCK_CHECK 0x0454 |
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| 345 | #define BIT_CHECK_CCK_EN BIT(7) |
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| 346 | #define REG_AMPDU_MAX_TIME_V1 0x0455 |
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| 347 | #define REG_BCNQ1_BDNY_V1 0x0456 |
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| 348 | #define REG_AMPDU_MAX_TIME 0x0456 |
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| 349 | #define REG_WMAC_LBK_BF_HD 0x045D |
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| 350 | #define REG_TX_HANG_CTRL 0x045E |
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| 351 | #define BIT_EN_GNT_BT_AWAKE BIT(3) |
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| 352 | #define BIT_EN_EOF_V1 BIT(2) |
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| 353 | #define REG_DATA_SC 0x0483 |
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| 354 | #define REG_ARFR2_V1 0x048C |
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| 355 | #define REG_ARFRH2_V1 0x0490 |
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| 356 | #define REG_ARFR3_V1 0x0494 |
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| 357 | #define BIT_EXC_CODE GENMASK(6, 2) |
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| 358 | #define REG_ARFRH3_V1 0x0498 |
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| 359 | #define REG_ARFR4 0x049C |
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| 360 | #define BIT_WL_RFK BIT(0) |
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| 361 | #define REG_ARFRH4 0x04A0 |
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| 362 | #define REG_ARFR5 0x04A4 |
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| 363 | #define REG_ARFRH5 0x04A8 |
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| 364 | #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC |
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| 365 | #define BIT_PRE_TX_CMD BIT(6) |
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| 366 | #define REG_QUEUE_CTRL 0x04C6 |
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| 367 | #define BIT_PTA_WL_TX_EN BIT(4) |
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| 368 | #define BIT_PTA_EDCCA_EN BIT(5) |
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| 369 | #define REG_SINGLE_AMPDU_CTRL 0x04C7 |
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| 370 | #define BIT_EN_SINGLE_APMDU BIT(7) |
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| 371 | #define REG_PROT_MODE_CTRL 0x04C8 |
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| 372 | #define REG_MAX_AGGR_NUM 0x04CA |
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| 373 | #define REG_BAR_MODE_CTRL 0x04CC |
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| 374 | #define REG_PRECNT_CTRL 0x04E5 |
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| 375 | #define BIT_BTCCA_CTRL (BIT(0) | BIT(1)) |
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| 376 | #define BIT_EN_PRECNT BIT(11) |
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| 377 | #define REG_DUMMY_PAGE4_V1 0x04FC |
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| 378 | |
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| 379 | #define REG_EDCA_VO_PARAM 0x0500 |
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| 380 | #define REG_EDCA_VI_PARAM 0x0504 |
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| 381 | #define REG_EDCA_BE_PARAM 0x0508 |
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| 382 | #define REG_EDCA_BK_PARAM 0x050C |
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| 383 | #define BIT_MASK_TXOP_LMT GENMASK(26, 16) |
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| 384 | #define BIT_MASK_CWMAX GENMASK(15, 12) |
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| 385 | #define BIT_MASK_CWMIN GENMASK(11, 8) |
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| 386 | #define BIT_MASK_AIFS GENMASK(7, 0) |
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| 387 | #define REG_PIFS 0x0512 |
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| 388 | #define REG_SIFS 0x0514 |
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| 389 | #define BIT_SHIFT_SIFS_OFDM_CTX 8 |
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| 390 | #define BIT_SHIFT_SIFS_CCK_TRX 16 |
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| 391 | #define BIT_SHIFT_SIFS_OFDM_TRX 24 |
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| 392 | #define REG_AGGR_BREAK_TIME 0x051A |
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| 393 | #define REG_SLOT 0x051B |
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| 394 | #define REG_TX_PTCL_CTRL 0x0520 |
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| 395 | #define BIT_DIS_EDCCA BIT(15) |
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| 396 | #define BIT_SIFS_BK_EN BIT(12) |
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| 397 | #define REG_TXPAUSE 0x0522 |
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| 398 | #define BIT_AC_QUEUE GENMASK(7, 0) |
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| 399 | #define BIT_HIGH_QUEUE BIT(5) |
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| 400 | #define REG_RD_CTRL 0x0524 |
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| 401 | #define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) |
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| 402 | #define BIT_DIS_TXOP_CFE BIT(10) |
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| 403 | #define BIT_DIS_LSIG_CFE BIT(9) |
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| 404 | #define BIT_DIS_STBC_CFE BIT(8) |
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| 405 | #define REG_TBTT_PROHIBIT 0x0540 |
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| 406 | #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 |
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| 407 | #define REG_RD_NAV_NXT 0x0544 |
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| 408 | #define REG_NAV_PROT_LEN 0x0546 |
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| 409 | #define REG_BCN_CTRL 0x0550 |
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| 410 | #define BIT_DIS_TSF_UDT BIT(4) |
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| 411 | #define BIT_EN_BCN_FUNCTION BIT(3) |
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| 412 | #define BIT_EN_TXBCN_RPT BIT(2) |
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| 413 | #define REG_BCN_CTRL_CLINT0 0x0551 |
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| 414 | #define REG_DRVERLYINT 0x0558 |
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| 415 | #define REG_BCNDMATIM 0x0559 |
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| 416 | #define REG_ATIMWND 0x055A |
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| 417 | #define REG_USTIME_TSF 0x055C |
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| 418 | #define REG_BCN_MAX_ERR 0x055D |
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| 419 | #define REG_RXTSF_OFFSET_CCK 0x055E |
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| 420 | #define REG_MISC_CTRL 0x0577 |
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| 421 | #define BIT_EN_FREE_CNT BIT(3) |
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| 422 | #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1)) |
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| 423 | #define REG_HIQ_NO_LMT_EN 0x5A7 |
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| 424 | #define REG_DTIM_COUNTER_ROOT 0x5A8 |
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| 425 | #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) |
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| 426 | #define REG_TIMER0_SRC_SEL 0x05B4 |
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| 427 | #define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6)) |
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| 428 | |
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| 429 | #define REG_TCR 0x0604 |
|---|
| 430 | #define BIT_PWRMGT_HWDATA_EN BIT(7) |
|---|
| 431 | #define BIT_TCR_UPDATE_TIMIE BIT(5) |
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| 432 | #define BIT_TCR_UPDATE_HGQMD BIT(4) |
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| 433 | #define REG_RCR 0x0608 |
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| 434 | #define BIT_APP_FCS BIT(31) |
|---|
| 435 | #define BIT_APP_MIC BIT(30) |
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| 436 | #define BIT_APP_ICV BIT(29) |
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| 437 | #define BIT_APP_PHYSTS BIT(28) |
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| 438 | #define BIT_APP_BASSN BIT(27) |
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| 439 | #define BIT_VHT_DACK BIT(26) |
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| 440 | #define BIT_TCPOFLD_EN BIT(25) |
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| 441 | #define BIT_ENMBID BIT(24) |
|---|
| 442 | #define BIT_LSIGEN BIT(23) |
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| 443 | #define BIT_MFBEN BIT(22) |
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| 444 | #define BIT_DISCHKPPDLLEN BIT(21) |
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| 445 | #define BIT_PKTCTL_DLEN BIT(20) |
|---|
| 446 | #define BIT_DISGCLK BIT(19) |
|---|
| 447 | #define BIT_TIM_PARSER_EN BIT(18) |
|---|
| 448 | #define BIT_BC_MD_EN BIT(17) |
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| 449 | #define BIT_UC_MD_EN BIT(16) |
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| 450 | #define BIT_RXSK_PERPKT BIT(15) |
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| 451 | #define BIT_HTC_LOC_CTRL BIT(14) |
|---|
| 452 | #define BIT_RPFM_CAM_ENABLE BIT(12) |
|---|
| 453 | #define BIT_TA_BCN BIT(11) |
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| 454 | #define BIT_RCR_ADF BIT(11) |
|---|
| 455 | #define BIT_DISDECMYPKT BIT(10) |
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| 456 | #define BIT_AICV BIT(9) |
|---|
| 457 | #define BIT_ACRC32 BIT(8) |
|---|
| 458 | #define BIT_CBSSID_BCN BIT(7) |
|---|
| 459 | #define BIT_CBSSID_DATA BIT(6) |
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| 460 | #define BIT_APWRMGT BIT(5) |
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| 461 | #define BIT_ADD3 BIT(4) |
|---|
| 462 | #define BIT_AB BIT(3) |
|---|
| 463 | #define BIT_AM BIT(2) |
|---|
| 464 | #define BIT_APM BIT(1) |
|---|
| 465 | #define BIT_AAP BIT(0) |
|---|
| 466 | #define REG_RX_PKT_LIMIT 0x060C |
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| 467 | #define REG_RX_DRVINFO_SZ 0x060F |
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| 468 | #define BIT_APP_PHYSTS BIT(28) |
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| 469 | #define REG_MAR 0x0620 |
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| 470 | #define REG_USTIME_EDCA 0x0638 |
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| 471 | #define REG_ACKTO_CCK 0x0639 |
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| 472 | #define REG_MAC_SPEC_SIFS 0x063A |
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| 473 | #define REG_RESP_SIFS_CCK 0x063C |
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| 474 | #define REG_RESP_SIFS_OFDM 0x063E |
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| 475 | #define REG_ACKTO 0x0640 |
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| 476 | #define REG_EIFS 0x0642 |
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| 477 | #define REG_NAV_CTRL 0x0650 |
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| 478 | #define REG_WMAC_TRXPTCL_CTL 0x0668 |
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| 479 | #define BIT_RFMOD (BIT(7) | BIT(8)) |
|---|
| 480 | #define BIT_RFMOD_80M BIT(8) |
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| 481 | #define BIT_RFMOD_40M BIT(7) |
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| 482 | #define REG_WMAC_TRXPTCL_CTL_H 0x066C |
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| 483 | #define REG_WKFMCAM_CMD 0x0698 |
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| 484 | #define BIT_WKFCAM_POLLING_V1 BIT(31) |
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| 485 | #define BIT_WKFCAM_CLR_V1 BIT(30) |
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| 486 | #define BIT_WKFCAM_WE BIT(16) |
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| 487 | #define BIT_SHIFT_WKFCAM_ADDR_V2 8 |
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| 488 | #define BIT_MASK_WKFCAM_ADDR_V2 0xff |
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| 489 | #define BIT_WKFCAM_ADDR_V2(x) \ |
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| 490 | (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) |
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| 491 | #define REG_WKFMCAM_RWD 0x069C |
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| 492 | #define BIT_WKFMCAM_VALID BIT(31) |
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| 493 | #define BIT_WKFMCAM_BC BIT(26) |
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| 494 | #define BIT_WKFMCAM_MC BIT(25) |
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| 495 | #define BIT_WKFMCAM_UC BIT(24) |
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| 496 | |
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| 497 | #define REG_RXFLTMAP0 0x06A0 |
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| 498 | #define REG_RXFLTMAP1 0x06A2 |
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| 499 | #define REG_RXFLTMAP2 0x06A4 |
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| 500 | #define REG_RXFLTMAP4 0x068A |
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| 501 | #define REG_BT_COEX_TABLE0 0x06C0 |
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| 502 | #define REG_BT_COEX_TABLE1 0x06C4 |
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| 503 | #define REG_BT_COEX_BRK_TABLE 0x06C8 |
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| 504 | #define REG_BT_COEX_TABLE_H 0x06CC |
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| 505 | #define REG_BT_COEX_TABLE_H1 0x06CD |
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| 506 | #define REG_BT_COEX_TABLE_H2 0x06CE |
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| 507 | #define REG_BT_COEX_TABLE_H3 0x06CF |
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| 508 | #define REG_BBPSF_CTRL 0x06DC |
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| 509 | |
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| 510 | #define REG_BT_COEX_V2 0x0762 |
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| 511 | #define BIT_GNT_BT_POLARITY BIT(12) |
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| 512 | #define BIT_LTE_COEX_EN BIT(7) |
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| 513 | #define REG_BT_COEX_ENH_INTR_CTRL 0x76E |
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| 514 | #define BIT_R_GRANTALL_WLMASK BIT(3) |
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| 515 | #define BIT_STATIS_BT_EN BIT(2) |
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| 516 | #define REG_BT_ACT_STATISTICS 0x0770 |
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| 517 | #define REG_BT_ACT_STATISTICS_1 0x0774 |
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| 518 | #define REG_BT_STAT_CTRL 0x0778 |
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| 519 | #define REG_BT_TDMA_TIME 0x0790 |
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| 520 | #define BIT_MASK_SAMPLE_RATE GENMASK(5, 0) |
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| 521 | #define REG_LTR_IDLE_LATENCY 0x0798 |
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| 522 | #define REG_LTR_ACTIVE_LATENCY 0x079C |
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| 523 | #define REG_LTR_CTRL_BASIC 0x07A4 |
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| 524 | #define REG_WMAC_OPTION_FUNCTION 0x07D0 |
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| 525 | #define REG_WMAC_OPTION_FUNCTION_1 0x07D4 |
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| 526 | |
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| 527 | #define REG_FPGA0_RFMOD 0x0800 |
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| 528 | #define BIT_CCKEN BIT(24) |
|---|
| 529 | #define BIT_OFDMEN BIT(25) |
|---|
| 530 | #define REG_RX_GAIN_EN 0x081c |
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| 531 | |
|---|
| 532 | #define REG_RFE_CTRL_E 0x0974 |
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| 533 | #define REG_2ND_CCA_CTRL 0x0976 |
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| 534 | |
|---|
| 535 | #define REG_CCK0_FAREPORT 0xa2c |
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| 536 | #define BIT_CCK0_2RX BIT(18) |
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| 537 | #define BIT_CCK0_MRC BIT(22) |
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| 538 | |
|---|
| 539 | #define REG_DIS_DPD 0x0a70 |
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| 540 | #define DIS_DPD_MASK GENMASK(9, 0) |
|---|
| 541 | #define DIS_DPD_RATE6M BIT(0) |
|---|
| 542 | #define DIS_DPD_RATE9M BIT(1) |
|---|
| 543 | #define DIS_DPD_RATEMCS0 BIT(2) |
|---|
| 544 | #define DIS_DPD_RATEMCS1 BIT(3) |
|---|
| 545 | #define DIS_DPD_RATEMCS8 BIT(4) |
|---|
| 546 | #define DIS_DPD_RATEMCS9 BIT(5) |
|---|
| 547 | #define DIS_DPD_RATEVHT1SS_MCS0 BIT(6) |
|---|
| 548 | #define DIS_DPD_RATEVHT1SS_MCS1 BIT(7) |
|---|
| 549 | #define DIS_DPD_RATEVHT2SS_MCS0 BIT(8) |
|---|
| 550 | #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9) |
|---|
| 551 | #define DIS_DPD_RATEALL GENMASK(9, 0) |
|---|
| 552 | |
|---|
| 553 | #define REG_RFE_CTRL8 0x0cb4 |
|---|
| 554 | #define BIT_MASK_RFE_SEL89 GENMASK(7, 0) |
|---|
| 555 | #define REG_RFE_INV8 0x0cbd |
|---|
| 556 | #define BIT_MASK_RFE_INV89 GENMASK(1, 0) |
|---|
| 557 | #define REG_RFE_INV16 0x0cbe |
|---|
| 558 | #define BIT_RFE_BUF_EN BIT(3) |
|---|
| 559 | |
|---|
| 560 | #define REG_ANAPARSW_MAC_0 0x1010 |
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| 561 | #define BIT_CF_L_V2 GENMASK(29, 28) |
|---|
| 562 | |
|---|
| 563 | #define REG_ANAPAR_XTAL_0 0x1040 |
|---|
| 564 | #define BIT_XCAP_0 GENMASK(23, 10) |
|---|
| 565 | #define REG_CPU_DMEM_CON 0x1080 |
|---|
| 566 | #define BIT_WL_PLATFORM_RST BIT(16) |
|---|
| 567 | #define BIT_WL_SECURITY_CLK BIT(15) |
|---|
| 568 | #define BIT_DDMA_EN BIT(8) |
|---|
| 569 | |
|---|
| 570 | #define REG_H2C_PKT_READADDR 0x10D0 |
|---|
| 571 | #define REG_H2C_PKT_WRITEADDR 0x10D4 |
|---|
| 572 | #define REG_FW_DBG6 0x10F8 |
|---|
| 573 | #define REG_FW_DBG7 0x10FC |
|---|
| 574 | #define FW_KEY_MASK 0xffffff00 |
|---|
| 575 | |
|---|
| 576 | #define REG_CR_EXT 0x1100 |
|---|
| 577 | |
|---|
| 578 | #define REG_FT1IMR 0x1138 |
|---|
| 579 | #define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) |
|---|
| 580 | #define REG_FT1ISR 0x113c |
|---|
| 581 | #define BIT_FS_H2C_CMD_OK_INT BIT(25) |
|---|
| 582 | #define REG_DDMA_CH0SA 0x1200 |
|---|
| 583 | #define REG_DDMA_CH0DA 0x1204 |
|---|
| 584 | #define REG_DDMA_CH0CTRL 0x1208 |
|---|
| 585 | #define BIT_DDMACH0_OWN BIT(31) |
|---|
| 586 | #define BIT_DDMACH0_CHKSUM_EN BIT(29) |
|---|
| 587 | #define BIT_DDMACH0_CHKSUM_STS BIT(27) |
|---|
| 588 | #define BIT_DDMACH0_DDMA_MODE BIT(26) |
|---|
| 589 | #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) |
|---|
| 590 | #define BIT_DDMACH0_CHKSUM_CONT BIT(24) |
|---|
| 591 | #define BIT_MASK_DDMACH0_DLEN 0x3ffff |
|---|
| 592 | |
|---|
| 593 | #define REG_H2CQ_CSR 0x1330 |
|---|
| 594 | #define BIT_H2CQ_FULL BIT(31) |
|---|
| 595 | #define REG_FAST_EDCA_VOVI_SETTING 0x1448 |
|---|
| 596 | #define REG_FAST_EDCA_BEBK_SETTING 0x144C |
|---|
| 597 | |
|---|
| 598 | #define REG_RXPSF_CTRL 0x1610 |
|---|
| 599 | #define BIT_RXGCK_FIFOTHR_EN BIT(28) |
|---|
| 600 | |
|---|
| 601 | #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 |
|---|
| 602 | #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 |
|---|
| 603 | #define BIT_RXGCK_VHT_FIFOTHR(x) \ |
|---|
| 604 | (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) |
|---|
| 605 | #define BITS_RXGCK_VHT_FIFOTHR \ |
|---|
| 606 | (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) |
|---|
| 607 | |
|---|
| 608 | #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 |
|---|
| 609 | #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 |
|---|
| 610 | #define BIT_RXGCK_HT_FIFOTHR(x) \ |
|---|
| 611 | (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) |
|---|
| 612 | #define BITS_RXGCK_HT_FIFOTHR \ |
|---|
| 613 | (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) |
|---|
| 614 | |
|---|
| 615 | #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 |
|---|
| 616 | #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 |
|---|
| 617 | #define BIT_RXGCK_OFDM_FIFOTHR(x) \ |
|---|
| 618 | (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) |
|---|
| 619 | #define BITS_RXGCK_OFDM_FIFOTHR \ |
|---|
| 620 | (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) |
|---|
| 621 | |
|---|
| 622 | #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 |
|---|
| 623 | #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 |
|---|
| 624 | #define BIT_RXGCK_CCK_FIFOTHR(x) \ |
|---|
| 625 | (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) |
|---|
| 626 | #define BITS_RXGCK_CCK_FIFOTHR \ |
|---|
| 627 | (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) |
|---|
| 628 | |
|---|
| 629 | #define BIT_RXGCK_OFDMCCA_EN BIT(16) |
|---|
| 630 | |
|---|
| 631 | #define BIT_SHIFT_RXPSF_PKTLENTHR 13 |
|---|
| 632 | #define BIT_MASK_RXPSF_PKTLENTHR 0x7 |
|---|
| 633 | #define BIT_RXPSF_PKTLENTHR(x) \ |
|---|
| 634 | (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) |
|---|
| 635 | #define BITS_RXPSF_PKTLENTHR \ |
|---|
| 636 | (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) |
|---|
| 637 | #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) |
|---|
| 638 | #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ |
|---|
| 639 | (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) |
|---|
| 640 | |
|---|
| 641 | #define BIT_RXPSF_CTRLEN BIT(12) |
|---|
| 642 | #define BIT_RXPSF_VHTCHKEN BIT(11) |
|---|
| 643 | #define BIT_RXPSF_HTCHKEN BIT(10) |
|---|
| 644 | #define BIT_RXPSF_OFDMCHKEN BIT(9) |
|---|
| 645 | #define BIT_RXPSF_CCKCHKEN BIT(8) |
|---|
| 646 | #define BIT_RXPSF_OFDMRST BIT(7) |
|---|
| 647 | #define BIT_RXPSF_CCKRST BIT(6) |
|---|
| 648 | #define BIT_RXPSF_MHCHKEN BIT(5) |
|---|
| 649 | #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) |
|---|
| 650 | #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) |
|---|
| 651 | |
|---|
| 652 | #define BIT_SHIFT_RXPSF_ERRTHR 0 |
|---|
| 653 | #define BIT_MASK_RXPSF_ERRTHR 0x7 |
|---|
| 654 | #define BIT_RXPSF_ERRTHR(x) \ |
|---|
| 655 | (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) |
|---|
| 656 | #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) |
|---|
| 657 | #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) |
|---|
| 658 | #define BIT_GET_RXPSF_ERRTHR(x) \ |
|---|
| 659 | (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) |
|---|
| 660 | #define BIT_SET_RXPSF_ERRTHR(x, v) \ |
|---|
| 661 | (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) |
|---|
| 662 | |
|---|
| 663 | #define REG_RXPSF_TYPE_CTRL 0x1614 |
|---|
| 664 | #define REG_GENERAL_OPTION 0x1664 |
|---|
| 665 | #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) |
|---|
| 666 | |
|---|
| 667 | #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 |
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| 668 | #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 |
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| 669 | #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 |
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| 670 | #define LTECOEX_READY BIT(29) |
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| 671 | #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 |
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| 672 | #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 |
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| 673 | #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 |
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| 674 | |
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| 675 | #define REG_IGN_GNT_BT1 0x1860 |
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| 676 | |
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| 677 | #define REG_RFESEL_CTRL 0x1990 |
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| 678 | |
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| 679 | #define REG_NOMASK_TXBT 0x1ca7 |
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| 680 | #define REG_ANAPAR 0x1c30 |
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| 681 | #define BIT_ANAPAR_BTPS BIT(22) |
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| 682 | #define REG_RSTB_SEL 0x1c38 |
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| 683 | #define BIT_DAC_OFF_ENABLE BIT(4) |
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| 684 | #define BIT_PI_IGNORE_GNT_BT BIT(3) |
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| 685 | #define BIT_NOMASK_TXBT_ENABLE BIT(3) |
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| 686 | |
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| 687 | #define REG_HRCV_MSG 0x1cf |
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| 688 | |
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| 689 | #define REG_EDCCA_REPORT 0x2d38 |
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| 690 | #define BIT_EDCCA_FLAG BIT(24) |
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| 691 | |
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| 692 | #define REG_IGN_GNTBT4 0x4160 |
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| 693 | |
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| 694 | #define RF_MODE 0x00 |
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| 695 | #define RF_MODOPT 0x01 |
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| 696 | #define RF_WLINT 0x01 |
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| 697 | #define RF_WLSEL 0x02 |
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| 698 | #define RF_DTXLOK 0x08 |
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| 699 | #define RF_CFGCH 0x18 |
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| 700 | #define BIT_BAND GENMASK(18, 16) |
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| 701 | #define RF_RCK 0x1d |
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| 702 | #define RF_LUTWA 0x33 |
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| 703 | #define RF_LUTWD1 0x3e |
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| 704 | #define RF_LUTWD0 0x3f |
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| 705 | #define BIT_GAIN_EXT BIT(12) |
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| 706 | #define BIT_DATA_L GENMASK(11, 0) |
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| 707 | #define RF_T_METER 0x42 |
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| 708 | #define RF_BSPAD 0x54 |
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| 709 | #define RF_GAINTX 0x56 |
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| 710 | #define RF_TXATANK 0x64 |
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| 711 | #define RF_TRXIQ 0x66 |
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| 712 | #define RF_RXIQGEN 0x8d |
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| 713 | #define RF_SYN_PFD 0xb0 |
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| 714 | #define RF_XTALX2 0xb8 |
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| 715 | #define RF_SYN_CTRL 0xbb |
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| 716 | #define RF_MALSEL 0xbe |
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| 717 | #define RF_SYN_AAC 0xc9 |
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| 718 | #define RF_AAC_CTRL 0xca |
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| 719 | #define RF_FAST_LCK 0xcc |
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| 720 | #define RF_RCKD 0xde |
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| 721 | #define RF_TXADBG 0xde |
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| 722 | #define RF_LUTDBG 0xdf |
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| 723 | #define BIT_TXA_TANK BIT(4) |
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| 724 | #define RF_LUTWE2 0xee |
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| 725 | #define RF_LUTWE 0xef |
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| 726 | |
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| 727 | #define LTE_COEX_CTRL 0x38 |
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| 728 | #define LTE_WL_TRX_CTRL 0xa0 |
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| 729 | #define LTE_BT_TRX_CTRL 0xa4 |
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| 730 | |
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| 731 | #endif |
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| 732 | |
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