1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_FW_H__
6#define __RTW89_FW_H__
7
8#include "core.h"
9
10enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19};
20
21struct rtw89_c2hreg_hdr {
22 u32 w0;
23};
24
25#define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26#define RTW89_C2HREG_HDR_ACK BIT(7)
27#define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28#define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35} __packed;
36
37#define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38#define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39#define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40#define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41#define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50
51struct rtw89_h2creg_hdr {
52 u32 w0;
53};
54
55#define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
56#define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
57
58struct rtw89_h2creg_sch_tx_en {
59 u32 w0;
60 u32 w1;
61} __packed;
62
63#define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
64#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
65#define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
66
67#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
68
69#define RTW89_H2CREG_MAX 4
70#define RTW89_C2HREG_MAX 4
71#define RTW89_C2HREG_HDR_LEN 2
72#define RTW89_H2CREG_HDR_LEN 2
73#define RTW89_C2H_TIMEOUT 1000000
74struct rtw89_mac_c2h_info {
75 u8 id;
76 u8 content_len;
77 union {
78 u32 c2hreg[RTW89_C2HREG_MAX];
79 struct rtw89_c2hreg_hdr hdr;
80 struct rtw89_c2hreg_phycap phycap;
81 } u;
82};
83
84struct rtw89_mac_h2c_info {
85 u8 id;
86 u8 content_len;
87 union {
88 u32 h2creg[RTW89_H2CREG_MAX];
89 struct rtw89_h2creg_hdr hdr;
90 struct rtw89_h2creg_sch_tx_en sch_tx_en;
91 } u;
92};
93
94enum rtw89_mac_h2c_type {
95 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
96 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
97 RTW89_FWCMD_H2CREG_FUNC_FWERR,
98 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
99 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
100 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
101 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP = 0x6,
102 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL = 0xA,
103};
104
105enum rtw89_mac_c2h_type {
106 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
107 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
108 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
109 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
110 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
111 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
112 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
113};
114
115enum rtw89_fw_c2h_category {
116 RTW89_C2H_CAT_TEST,
117 RTW89_C2H_CAT_MAC,
118 RTW89_C2H_CAT_OUTSRC,
119};
120
121enum rtw89_fw_log_level {
122 RTW89_FW_LOG_LEVEL_OFF,
123 RTW89_FW_LOG_LEVEL_CRT,
124 RTW89_FW_LOG_LEVEL_SER,
125 RTW89_FW_LOG_LEVEL_WARN,
126 RTW89_FW_LOG_LEVEL_LOUD,
127 RTW89_FW_LOG_LEVEL_TR,
128};
129
130enum rtw89_fw_log_path {
131 RTW89_FW_LOG_LEVEL_UART,
132 RTW89_FW_LOG_LEVEL_C2H,
133 RTW89_FW_LOG_LEVEL_SNI,
134};
135
136enum rtw89_fw_log_comp {
137 RTW89_FW_LOG_COMP_VER,
138 RTW89_FW_LOG_COMP_INIT,
139 RTW89_FW_LOG_COMP_TASK,
140 RTW89_FW_LOG_COMP_CNS,
141 RTW89_FW_LOG_COMP_H2C,
142 RTW89_FW_LOG_COMP_C2H,
143 RTW89_FW_LOG_COMP_TX,
144 RTW89_FW_LOG_COMP_RX,
145 RTW89_FW_LOG_COMP_IPSEC,
146 RTW89_FW_LOG_COMP_TIMER,
147 RTW89_FW_LOG_COMP_DBGPKT,
148 RTW89_FW_LOG_COMP_PS,
149 RTW89_FW_LOG_COMP_ERROR,
150 RTW89_FW_LOG_COMP_WOWLAN,
151 RTW89_FW_LOG_COMP_SECURE_BOOT,
152 RTW89_FW_LOG_COMP_BTC,
153 RTW89_FW_LOG_COMP_BB,
154 RTW89_FW_LOG_COMP_TWT,
155 RTW89_FW_LOG_COMP_RF,
156 RTW89_FW_LOG_COMP_MCC = 20,
157 RTW89_FW_LOG_COMP_SCAN = 28,
158};
159
160enum rtw89_pkt_offload_op {
161 RTW89_PKT_OFLD_OP_ADD,
162 RTW89_PKT_OFLD_OP_DEL,
163 RTW89_PKT_OFLD_OP_READ,
164
165 NUM_OF_RTW89_PKT_OFFLOAD_OP,
166};
167
168#define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
169 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
170
171enum rtw89_scanofld_notify_reason {
172 RTW89_SCAN_DWELL_NOTIFY,
173 RTW89_SCAN_PRE_TX_NOTIFY,
174 RTW89_SCAN_POST_TX_NOTIFY,
175 RTW89_SCAN_ENTER_CH_NOTIFY,
176 RTW89_SCAN_LEAVE_CH_NOTIFY,
177 RTW89_SCAN_END_SCAN_NOTIFY,
178 RTW89_SCAN_REPORT_NOTIFY,
179 RTW89_SCAN_CHKPT_NOTIFY,
180 RTW89_SCAN_ENTER_OP_NOTIFY,
181 RTW89_SCAN_LEAVE_OP_NOTIFY,
182};
183
184enum rtw89_scanofld_status {
185 RTW89_SCAN_STATUS_NOTIFY,
186 RTW89_SCAN_STATUS_SUCCESS,
187 RTW89_SCAN_STATUS_FAIL,
188};
189
190enum rtw89_chan_type {
191 RTW89_CHAN_OPERATE = 0,
192 RTW89_CHAN_ACTIVE,
193 RTW89_CHAN_DFS,
194};
195
196enum rtw89_p2pps_action {
197 RTW89_P2P_ACT_INIT = 0,
198 RTW89_P2P_ACT_UPDATE = 1,
199 RTW89_P2P_ACT_REMOVE = 2,
200 RTW89_P2P_ACT_TERMINATE = 3,
201};
202
203#define RTW89_DEFAULT_CQM_HYST 4
204#define RTW89_DEFAULT_CQM_THOLD -70
205
206enum rtw89_bcn_fltr_offload_mode {
207 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
208 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
209 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
210 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
211
212 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
213};
214
215enum rtw89_bcn_fltr_type {
216 RTW89_BCN_FLTR_BEACON_LOSS,
217 RTW89_BCN_FLTR_RSSI,
218 RTW89_BCN_FLTR_NOTIFY,
219};
220
221enum rtw89_bcn_fltr_rssi_event {
222 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
223 RTW89_BCN_FLTR_RSSI_HIGH,
224 RTW89_BCN_FLTR_RSSI_LOW,
225};
226
227#define FWDL_SECTION_MAX_NUM 10
228#define FWDL_SECTION_CHKSUM_LEN 8
229#define FWDL_SECTION_PER_PKT_LEN 2020
230
231struct rtw89_fw_hdr_section_info {
232 u8 redl;
233 const u8 *addr;
234 u32 len;
235 u32 dladdr;
236 u32 mssc;
237 u8 type;
238 bool ignore;
239 const u8 *key_addr;
240 u32 key_len;
241 u32 key_idx;
242};
243
244struct rtw89_fw_bin_info {
245 u8 section_num;
246 u32 hdr_len;
247 bool dynamic_hdr_en;
248 u32 dynamic_hdr_len;
249 bool dsp_checksum;
250 bool secure_section_exist;
251 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
252};
253
254struct rtw89_fw_macid_pause_grp {
255 __le32 pause_grp[4];
256 __le32 mask_grp[4];
257} __packed;
258
259struct rtw89_fw_macid_pause_sleep_grp {
260 struct {
261 __le32 pause_grp[4];
262 __le32 pause_mask_grp[4];
263 __le32 sleep_grp[4];
264 __le32 sleep_mask_grp[4];
265 } __packed n[4];
266} __packed;
267
268#define RTW89_H2C_MAX_SIZE 2048
269#define RTW89_CHANNEL_TIME 45
270#define RTW89_CHANNEL_TIME_6G 20
271#define RTW89_DFS_CHAN_TIME 105
272#define RTW89_OFF_CHAN_TIME 100
273#define RTW89_DWELL_TIME 20
274#define RTW89_DWELL_TIME_6G 10
275#define RTW89_SCAN_WIDTH 0
276#define RTW89_SCANOFLD_MAX_SSID 8
277#define RTW89_SCANOFLD_MAX_IE_LEN 512
278#define RTW89_SCANOFLD_PKT_NONE 0xFF
279#define RTW89_SCANOFLD_DEBUG_MASK 0x1F
280#define RTW89_CHAN_INVALID 0xFF
281#define RTW89_MAC_CHINFO_SIZE 28
282#define RTW89_SCAN_LIST_GUARD 4
283#define RTW89_SCAN_LIST_LIMIT \
284 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
285
286#define RTW89_BCN_LOSS_CNT 10
287
288struct rtw89_mac_chinfo {
289 u8 period;
290 u8 dwell_time;
291 u8 central_ch;
292 u8 pri_ch;
293 u8 bw:3;
294 u8 notify_action:5;
295 u8 num_pkt:4;
296 u8 tx_pkt:1;
297 u8 pause_data:1;
298 u8 ch_band:2;
299 u8 probe_id;
300 u8 dfs_ch:1;
301 u8 tx_null:1;
302 u8 rand_seq_num:1;
303 u8 cfg_tx_pwr:1;
304 u8 rsvd0: 4;
305 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
306 u16 tx_pwr_idx;
307 u8 rsvd1;
308 struct list_head list;
309 bool is_psc;
310};
311
312struct rtw89_mac_chinfo_be {
313 u8 period;
314 u8 dwell_time;
315 u8 central_ch;
316 u8 pri_ch;
317 u8 bw:3;
318 u8 ch_band:2;
319 u8 dfs_ch:1;
320 u8 pause_data:1;
321 u8 tx_null:1;
322 u8 rand_seq_num:1;
323 u8 notify_action:5;
324 u8 probe_id;
325 u8 leave_crit;
326 u8 chkpt_timer;
327 u8 leave_time;
328 u8 leave_th;
329 u16 tx_pkt_ctrl;
330 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
331 u8 sw_def;
332 u16 fw_probe0_ssids;
333 u16 fw_probe0_shortssids;
334 u16 fw_probe0_bssids;
335
336 struct list_head list;
337 bool is_psc;
338};
339
340struct rtw89_pktofld_info {
341 struct list_head list;
342 u8 id;
343
344 /* Below fields are for 6 GHz RNR use only */
345 u8 ssid[IEEE80211_MAX_SSID_LEN];
346 u8 ssid_len;
347 u8 bssid[ETH_ALEN];
348 u16 channel_6ghz;
349 bool cancel;
350};
351
352struct rtw89_h2c_ra {
353 __le32 w0;
354 __le32 w1;
355 __le32 w2;
356 __le32 w3;
357} __packed;
358
359#define RTW89_H2C_RA_W0_IS_DIS BIT(0)
360#define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
361#define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
362#define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
363#define RTW89_H2C_RA_W0_DCM BIT(16)
364#define RTW89_H2C_RA_W0_ER BIT(17)
365#define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
366#define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
367#define RTW89_H2C_RA_W0_SGI BIT(21)
368#define RTW89_H2C_RA_W0_LDPC BIT(22)
369#define RTW89_H2C_RA_W0_STBC BIT(23)
370#define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
371#define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
372#define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
373#define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
374#define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
375#define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
376#define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
377#define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
378#define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
379#define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
380#define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
381#define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
382#define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
383#define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
384#define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
385#define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
386#define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
387
388struct rtw89_h2c_ra_v1 {
389 struct rtw89_h2c_ra v0;
390 __le32 w4;
391 __le32 w5;
392} __packed;
393
394#define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
395#define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
396#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
397#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
398
399static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
400{
401 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
402}
403
404static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
405{
406 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
407}
408
409static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
410{
411 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
412}
413
414static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
415{
416 le32p_replace_bits(p: (__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
417}
418
419static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
420{
421 le32p_replace_bits(p: (__le32 *)(cmd) + 0x01, val, BIT(4));
422}
423
424static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
425{
426 le32p_replace_bits(p: (__le32 *)(cmd) + 0x01, val, BIT(5));
427}
428
429static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
430{
431 le32p_replace_bits(p: (__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
432}
433
434static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
435{
436 le32p_replace_bits(p: (__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
437}
438
439static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
440{
441 le32p_replace_bits(p: (__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
442}
443
444static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
445{
446 le32p_replace_bits(p: (__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
447}
448
449static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
450{
451 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
452}
453
454static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
455{
456 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, BIT(3));
457}
458
459static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
460{
461 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, BIT(4));
462}
463
464static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
465{
466 le32p_replace_bits(p: (__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
467}
468
469static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
470{
471 le32p_replace_bits(p: (__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
472}
473#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
474#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
475#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
476#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
477
478#define FWDL_SECURITY_SECTION_TYPE 9
479#define FWDL_SECURITY_SIGLEN 512
480#define FWDL_SECURITY_CHKSUM_LEN 8
481
482struct rtw89_fw_dynhdr_sec {
483 __le32 w0;
484 u8 content[];
485} __packed;
486
487struct rtw89_fw_dynhdr_hdr {
488 __le32 hdr_len;
489 __le32 setcion_count;
490 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
491} __packed;
492
493struct rtw89_fw_hdr_section {
494 __le32 w0;
495 __le32 w1;
496 __le32 w2;
497 __le32 w3;
498} __packed;
499
500#define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
501#define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
502#define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
503#define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
504#define FWSECTION_HDR_W1_CHECKSUM BIT(28)
505#define FWSECTION_HDR_W1_REDL BIT(29)
506#define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
507
508struct rtw89_fw_hdr {
509 __le32 w0;
510 __le32 w1;
511 __le32 w2;
512 __le32 w3;
513 __le32 w4;
514 __le32 w5;
515 __le32 w6;
516 __le32 w7;
517 struct rtw89_fw_hdr_section sections[];
518 /* struct rtw89_fw_dynhdr_hdr (optional) */
519} __packed;
520
521#define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
522#define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
523#define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
524#define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
525#define FW_HDR_W2_COMMITID GENMASK(31, 0)
526#define FW_HDR_W3_LEN GENMASK(23, 16)
527#define FW_HDR_W3_HDR_VER GENMASK(31, 24)
528#define FW_HDR_W4_MONTH GENMASK(7, 0)
529#define FW_HDR_W4_DATE GENMASK(15, 8)
530#define FW_HDR_W4_HOUR GENMASK(23, 16)
531#define FW_HDR_W4_MIN GENMASK(31, 24)
532#define FW_HDR_W5_YEAR GENMASK(31, 0)
533#define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
534#define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
535#define FW_HDR_W7_DYN_HDR BIT(16)
536#define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
537
538struct rtw89_fw_hdr_section_v1 {
539 __le32 w0;
540 __le32 w1;
541 __le32 w2;
542 __le32 w3;
543} __packed;
544
545#define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
546#define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
547#define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
548#define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
549#define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
550#define FWSECTION_HDR_V1_W1_REDL BIT(29)
551#define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
552#define FORMATTED_MSSC 0xFF
553#define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
554
555struct rtw89_fw_hdr_v1 {
556 __le32 w0;
557 __le32 w1;
558 __le32 w2;
559 __le32 w3;
560 __le32 w4;
561 __le32 w5;
562 __le32 w6;
563 __le32 w7;
564 __le32 w8;
565 __le32 w9;
566 __le32 w10;
567 __le32 w11;
568 struct rtw89_fw_hdr_section_v1 sections[];
569} __packed;
570
571#define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
572#define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
573#define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
574#define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
575#define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
576#define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
577#define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
578#define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
579#define FW_HDR_V1_W4_DATE GENMASK(15, 8)
580#define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
581#define FW_HDR_V1_W4_MIN GENMASK(31, 24)
582#define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
583#define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
584#define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
585#define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
586#define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
587#define FW_HDR_V1_W7_DYN_HDR BIT(16)
588
589enum rtw89_fw_mss_pool_rmp_tbl_type {
590 MSS_POOL_RMP_TBL_BITMASK = 0x0,
591 MSS_POOL_RMP_TBL_RECORD = 0x1,
592};
593
594#define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
595
596struct rtw89_fw_mss_pool_hdr {
597 u8 signature[8]; /* equal to mss_signature[] */
598 __le32 rmp_tbl_offset;
599 __le32 key_raw_offset;
600 u8 defen;
601 u8 rsvd[3];
602 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
603 u8 mssdev_max;
604 __le16 keypair_num;
605 __le16 msscust_max;
606 __le16 msskey_num_max;
607 __le32 rsvd3;
608 u8 rmp_tbl[];
609} __packed;
610
611union rtw89_fw_section_mssc_content {
612 struct {
613 u8 pad[58];
614 __le32 v;
615 } __packed sb_sel_ver;
616 struct {
617 u8 pad[60];
618 __le16 v;
619 } __packed key_sign_len;
620} __packed;
621
622static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
623{
624 le32p_replace_bits(p: (__le32 *)(table) + 0, val, GENMASK(6, 0));
625}
626
627static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
628{
629 le32p_replace_bits(p: (__le32 *)(table) + 0, val, BIT(7));
630}
631#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
632static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
633{
634 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(8, 0));
635 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
636 GENMASK(8, 0));
637}
638#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
639static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
640{
641 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(9));
642 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
643 BIT(9));
644}
645#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
646static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
647{
648 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(11, 10));
649 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
650 GENMASK(11, 10));
651}
652#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
653static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
654{
655 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(14, 12));
656 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
657 GENMASK(14, 12));
658}
659#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
660static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
661{
662 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(15));
663 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
664 BIT(15));
665}
666#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
667static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
668{
669 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(19, 16));
670 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
671 GENMASK(19, 16));
672}
673#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
674static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
675{
676 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(20));
677 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
678 BIT(20));
679}
680#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
681static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
682{
683 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(21));
684 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
685 BIT(21));
686}
687#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
688static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
689{
690 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(22));
691 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
692 BIT(22));
693}
694#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
695static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
696{
697 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(23));
698 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
699 BIT(23));
700}
701#define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
702static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
703{
704 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(25));
705 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
706 BIT(25));
707}
708#define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
709static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
710{
711 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(26));
712 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
713 BIT(26));
714}
715#define SET_CMC_TBL_MASK_TRYRATE BIT(0)
716static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
717{
718 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(27));
719 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
720 BIT(27));
721}
722#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
723static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
724{
725 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(31, 28));
726 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
727 GENMASK(31, 28));
728}
729#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
730static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
731{
732 le32p_replace_bits(p: (__le32 *)(table) + 2, val, GENMASK(8, 0));
733 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
734 GENMASK(8, 0));
735}
736#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
737static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
738{
739 le32p_replace_bits(p: (__le32 *)(table) + 2, val, BIT(9));
740 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
741 BIT(9));
742}
743#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
744static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
745{
746 le32p_replace_bits(p: (__le32 *)(table) + 2, val, BIT(10));
747 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
748 BIT(10));
749}
750#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
751static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
752{
753 le32p_replace_bits(p: (__le32 *)(table) + 2, val, BIT(11));
754 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
755 BIT(11));
756}
757#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
758static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
759{
760 le32p_replace_bits(p: (__le32 *)(table) + 2, val, GENMASK(15, 12));
761 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
762 GENMASK(15, 12));
763}
764#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
765static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
766{
767 le32p_replace_bits(p: (__le32 *)(table) + 2, val, GENMASK(24, 16));
768 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
769 GENMASK(24, 16));
770}
771#define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
772static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
773{
774 le32p_replace_bits(p: (__le32 *)(table) + 2, val, BIT(27));
775 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
776 BIT(27));
777}
778#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
779static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
780{
781 le32p_replace_bits(p: (__le32 *)(table) + 2, val, GENMASK(31, 28));
782 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
783 GENMASK(31, 28));
784}
785#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
786static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
787{
788 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(5, 0));
789 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
790 GENMASK(5, 0));
791}
792#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
793static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
794{
795 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(6));
796 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
797 BIT(6));
798}
799#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
800static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
801{
802 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(7));
803 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
804 BIT(7));
805}
806#define SET_CMC_TBL_MASK_RTS_EN BIT(0)
807static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
808{
809 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(8));
810 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
811 BIT(8));
812}
813#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
814static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
815{
816 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(9));
817 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
818 BIT(9));
819}
820#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
821static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
822{
823 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(11, 10));
824 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
825 GENMASK(11, 10));
826}
827#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
828static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
829{
830 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(12));
831 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
832 BIT(12));
833}
834#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
835static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
836{
837 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(14, 13));
838 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
839 GENMASK(14, 13));
840}
841#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
842static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
843{
844 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(26, 16));
845 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
846 GENMASK(26, 16));
847}
848#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
849static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
850{
851 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(27));
852 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
853 BIT(27));
854}
855#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
856static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
857{
858 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(31, 28));
859 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
860 GENMASK(31, 28));
861}
862#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
863static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
864{
865 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(7, 0));
866 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
867 GENMASK(7, 0));
868}
869#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
870static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
871{
872 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(9, 8));
873 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
874 GENMASK(9, 8));
875}
876#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
877static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
878{
879 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(18, 16));
880 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
881 GENMASK(18, 16));
882}
883#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
884static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
885{
886 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(21, 19));
887 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
888 GENMASK(21, 19));
889}
890#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
891static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
892{
893 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(24, 22));
894 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
895 GENMASK(24, 22));
896}
897#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
898static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
899{
900 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(27, 25));
901 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
902 GENMASK(27, 25));
903}
904#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
905static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
906{
907 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(31, 28));
908 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
909 GENMASK(31, 28));
910}
911#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
912static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
913{
914 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(2, 0));
915 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
916 GENMASK(2, 0));
917}
918#define SET_CMC_TBL_MASK_BMC BIT(0)
919static inline void SET_CMC_TBL_BMC(void *table, u32 val)
920{
921 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(3));
922 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
923 BIT(3));
924}
925#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
926static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
927{
928 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(7, 4));
929 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
930 GENMASK(7, 4));
931}
932#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
933static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
934{
935 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(8));
936 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
937 BIT(8));
938}
939#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
940static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
941{
942 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(11, 9));
943 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
944 GENMASK(11, 9));
945}
946#define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
947static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
948{
949 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(12));
950 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
951 BIT(12));
952}
953#define SET_CMC_TBL_MASK_DATA_ER BIT(0)
954static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
955{
956 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(13));
957 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
958 BIT(13));
959}
960#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
961static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
962{
963 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(14));
964 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
965 BIT(14));
966}
967#define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
968static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
969{
970 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(15));
971 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
972 BIT(15));
973}
974#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
975static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
976{
977 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(16));
978 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
979 BIT(16));
980}
981#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
982static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
983{
984 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(17));
985 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
986 BIT(17));
987}
988#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
989static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
990{
991 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(18));
992 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
993 BIT(18));
994}
995#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
996static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
997{
998 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(19));
999 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1000 BIT(19));
1001}
1002#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1003static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1004{
1005 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(20));
1006 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1007 BIT(20));
1008}
1009#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1010static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1011{
1012 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(21));
1013 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1014 BIT(21));
1015}
1016#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1017static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1018{
1019 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(27));
1020 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1021 BIT(27));
1022}
1023#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
1024static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1025{
1026 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(31, 28));
1027 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1028 GENMASK(31, 28));
1029}
1030#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
1031static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1032{
1033 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(8, 0));
1034 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1035 GENMASK(8, 0));
1036}
1037#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1038static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1039{
1040 le32p_replace_bits(p: (__le32 *)(table) + 6, val, BIT(12));
1041 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1042 BIT(12));
1043}
1044#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1045static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1046{
1047 le32p_replace_bits(p: (__le32 *)(table) + 6, val, BIT(13));
1048 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1049 BIT(13));
1050}
1051#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
1052static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1053{
1054 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(19, 16));
1055 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1056 GENMASK(19, 16));
1057}
1058#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
1059static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1060{
1061 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(21, 20));
1062 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1063 GENMASK(21, 20));
1064}
1065#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
1066static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1067{
1068 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(23, 22));
1069 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1070 GENMASK(23, 22));
1071}
1072#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
1073static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1074{
1075 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(25, 24));
1076 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1077 GENMASK(25, 24));
1078}
1079#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
1080static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1081{
1082 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(27, 26));
1083 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1084 GENMASK(27, 26));
1085}
1086#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1087static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1088{
1089 le32p_replace_bits(p: (__le32 *)(table) + 6, val, BIT(28));
1090 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1091 BIT(28));
1092}
1093#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1094static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1095{
1096 le32p_replace_bits(p: (__le32 *)(table) + 6, val, BIT(29));
1097 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1098 BIT(29));
1099}
1100#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1101static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1102{
1103 le32p_replace_bits(p: (__le32 *)(table) + 6, val, BIT(30));
1104 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1105 BIT(30));
1106}
1107#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1108static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1109{
1110 le32p_replace_bits(p: (__le32 *)(table) + 6, val, BIT(31));
1111 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1112 BIT(31));
1113}
1114
1115#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1116static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1117{
1118 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(1, 0));
1119 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1120 GENMASK(1, 0));
1121}
1122
1123static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1124{
1125 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(3, 2));
1126 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1127 GENMASK(3, 2));
1128}
1129
1130static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1131{
1132 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(5, 4));
1133 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1134 GENMASK(5, 4));
1135}
1136
1137static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1138{
1139 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(7, 6));
1140 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1141 GENMASK(7, 6));
1142}
1143
1144#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1145static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1146{
1147 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(7, 0));
1148 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1149 GENMASK(7, 0));
1150}
1151#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1152static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1153{
1154 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(16, 8));
1155 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1156 GENMASK(16, 8));
1157}
1158#define SET_CMC_TBL_MASK_ULDL BIT(0)
1159static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1160{
1161 le32p_replace_bits(p: (__le32 *)(table) + 7, val, BIT(17));
1162 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1163 BIT(17));
1164}
1165#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
1166static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1167{
1168 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(19, 18));
1169 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1170 GENMASK(19, 18));
1171}
1172static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1173{
1174 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(21, 20));
1175 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1176 GENMASK(21, 20));
1177}
1178
1179static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1180{
1181 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(23, 22));
1182 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1183 GENMASK(23, 22));
1184}
1185#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1186static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1187{
1188 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(27, 24));
1189 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1190 GENMASK(27, 24));
1191}
1192
1193static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1194{
1195 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(31, 30));
1196 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1197 GENMASK(31, 30));
1198}
1199#define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1200static inline void SET_CMC_TBL_NC(void *table, u32 val)
1201{
1202 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(2, 0));
1203 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1204 GENMASK(2, 0));
1205}
1206#define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1207static inline void SET_CMC_TBL_NR(void *table, u32 val)
1208{
1209 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(5, 3));
1210 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1211 GENMASK(5, 3));
1212}
1213#define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1214static inline void SET_CMC_TBL_NG(void *table, u32 val)
1215{
1216 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(7, 6));
1217 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1218 GENMASK(7, 6));
1219}
1220#define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1221static inline void SET_CMC_TBL_CB(void *table, u32 val)
1222{
1223 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(9, 8));
1224 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1225 GENMASK(9, 8));
1226}
1227#define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1228static inline void SET_CMC_TBL_CS(void *table, u32 val)
1229{
1230 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(11, 10));
1231 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1232 GENMASK(11, 10));
1233}
1234#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1235static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1236{
1237 le32p_replace_bits(p: (__le32 *)(table) + 8, val, BIT(12));
1238 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1239 BIT(12));
1240}
1241#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1242static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1243{
1244 le32p_replace_bits(p: (__le32 *)(table) + 8, val, BIT(13));
1245 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1246 BIT(13));
1247}
1248#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1249static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1250{
1251 le32p_replace_bits(p: (__le32 *)(table) + 8, val, BIT(14));
1252 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1253 BIT(14));
1254}
1255#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1256static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1257{
1258 le32p_replace_bits(p: (__le32 *)(table) + 8, val, BIT(15));
1259 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1260 BIT(15));
1261}
1262#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1263static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1264{
1265 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(24, 16));
1266 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1267 GENMASK(24, 16));
1268}
1269#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1270static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1271{
1272 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(27, 25));
1273 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1274 GENMASK(27, 25));
1275}
1276
1277static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1278{
1279 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(29, 28));
1280 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1281 GENMASK(29, 28));
1282}
1283
1284#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1285static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1286{
1287 le32p_replace_bits(p: (__le32 *)(table) + 8, val, GENMASK(31, 30));
1288 le32p_replace_bits(p: (__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1289 GENMASK(31, 30));
1290}
1291
1292struct rtw89_h2c_cctlinfo_ud_g7 {
1293 __le32 c0;
1294 __le32 w0;
1295 __le32 w1;
1296 __le32 w2;
1297 __le32 w3;
1298 __le32 w4;
1299 __le32 w5;
1300 __le32 w6;
1301 __le32 w7;
1302 __le32 w8;
1303 __le32 w9;
1304 __le32 w10;
1305 __le32 w11;
1306 __le32 w12;
1307 __le32 w13;
1308 __le32 w14;
1309 __le32 w15;
1310 __le32 m0;
1311 __le32 m1;
1312 __le32 m2;
1313 __le32 m3;
1314 __le32 m4;
1315 __le32 m5;
1316 __le32 m6;
1317 __le32 m7;
1318 __le32 m8;
1319 __le32 m9;
1320 __le32 m10;
1321 __le32 m11;
1322 __le32 m12;
1323 __le32 m13;
1324 __le32 m14;
1325 __le32 m15;
1326} __packed;
1327
1328#define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1329#define CCTLINFO_G7_C0_OP BIT(7)
1330
1331#define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1332#define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1333#define CCTLINFO_G7_W0_TRYRATE BIT(15)
1334#define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1335#define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1336#define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1337#define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1338#define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1339#define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1340#define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1341#define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1342#define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1343#define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1344#define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1345#define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1346#define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1347#define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1348#define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1349#define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1350#define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1351#define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1352#define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1353#define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1354#define CCTLINFO_G7_W2_RTS_EN BIT(8)
1355#define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1356#define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1357#define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1358#define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1359#define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1360#define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1361#define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1362#define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1363#define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1364#define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1365#define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1366#define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1367#define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1368#define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1369#define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1370#define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1371#define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1372#define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1373#define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1374#define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1375#define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1376#define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1377#define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1378#define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1379#define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1380#define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1381#define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1382#define CCTLINFO_G7_W4_DATA_ER BIT(9)
1383#define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1384#define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1385#define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1386#define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1387#define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1388#define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1389#define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1390#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1391#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1392#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1393#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1394#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1395#define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1396#define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1397#define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1398#define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1399#define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1400#define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1401#define CCTLINFO_G7_W6_ULDL BIT(31)
1402#define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1403#define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1404#define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1405#define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1406#define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1407#define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1408#define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1409#define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1410#define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1411#define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1412#define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1413#define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1414#define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1415#define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1416#define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1417#define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1418#define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1419#define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1420#define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1421#define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1422#define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1423#define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1424#define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1425/* W9~13 are reserved */
1426#define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1427#define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1428#define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1429#define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1430#define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1431#define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1432#define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1433#define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1434
1435static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1436{
1437 le32p_replace_bits(p: (__le32 *)(table) + 0, val, GENMASK(6, 0));
1438}
1439
1440static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1441{
1442 le32p_replace_bits(p: (__le32 *)(table) + 0, val, BIT(7));
1443}
1444
1445#define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
1446static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1447{
1448 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(7, 0));
1449 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1450 GENMASK(7, 0));
1451}
1452
1453#define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
1454static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1455{
1456 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(14, 8));
1457 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1458 GENMASK(14, 8));
1459}
1460
1461#define SET_DCTL_MASK_QOS_DATA BIT(0)
1462static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1463{
1464 le32p_replace_bits(p: (__le32 *)(table) + 1, val, BIT(15));
1465 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1466 BIT(15));
1467}
1468
1469#define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
1470static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1471{
1472 le32p_replace_bits(p: (__le32 *)(table) + 1, val, GENMASK(31, 16));
1473 le32p_replace_bits(p: (__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1474 GENMASK(31, 16));
1475}
1476
1477#define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
1478static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1479{
1480 le32p_replace_bits(p: (__le32 *)(table) + 2, val, GENMASK(31, 0));
1481 le32p_replace_bits(p: (__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1482 GENMASK(31, 0));
1483}
1484
1485#define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
1486static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1487{
1488 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(11, 0));
1489 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1490 GENMASK(11, 0));
1491}
1492
1493#define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
1494static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1495{
1496 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(23, 12));
1497 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1498 GENMASK(23, 12));
1499}
1500
1501#define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
1502static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1503{
1504 le32p_replace_bits(p: (__le32 *)(table) + 3, val, GENMASK(26, 24));
1505 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1506 GENMASK(26, 24));
1507}
1508
1509#define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
1510static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1511{
1512 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(27));
1513 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1514 BIT(27));
1515}
1516
1517#define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
1518static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1519{
1520 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(28));
1521 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1522 BIT(28));
1523}
1524
1525#define SET_DCTL_MASK_WITH_LLC BIT(0)
1526static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1527{
1528 le32p_replace_bits(p: (__le32 *)(table) + 3, val, BIT(29));
1529 le32p_replace_bits(p: (__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1530 BIT(29));
1531}
1532
1533#define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
1534static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1535{
1536 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(11, 0));
1537 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1538 GENMASK(11, 0));
1539}
1540
1541#define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
1542static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1543{
1544 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(23, 12));
1545 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1546 GENMASK(23, 12));
1547}
1548
1549#define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
1550static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1551{
1552 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(27, 24));
1553 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1554 GENMASK(27, 24));
1555}
1556
1557#define SET_DCTL_MASK_TGT_IND_EN BIT(0)
1558static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1559{
1560 le32p_replace_bits(p: (__le32 *)(table) + 4, val, BIT(28));
1561 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1562 BIT(28));
1563}
1564
1565#define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
1566static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1567{
1568 le32p_replace_bits(p: (__le32 *)(table) + 4, val, GENMASK(31, 29));
1569 le32p_replace_bits(p: (__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1570 GENMASK(31, 29));
1571}
1572
1573#define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
1574static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1575{
1576 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(4, 0));
1577 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1578 GENMASK(4, 0));
1579}
1580
1581#define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
1582static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1583{
1584 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(5));
1585 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1586 BIT(5));
1587}
1588
1589#define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
1590static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1591{
1592 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(7, 6));
1593 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1594 GENMASK(7, 6));
1595}
1596
1597#define SET_DCTL_MASK_HTC_ORDER BIT(0)
1598static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1599{
1600 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(8));
1601 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1602 BIT(8));
1603}
1604
1605#define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
1606static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1607{
1608 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(10, 9));
1609 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1610 GENMASK(10, 9));
1611}
1612
1613#define SET_DCTL_MASK_WAPI BIT(0)
1614static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1615{
1616 le32p_replace_bits(p: (__le32 *)(table) + 5, val, BIT(15));
1617 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1618 BIT(15));
1619}
1620
1621#define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
1622static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1623{
1624 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(17, 16));
1625 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1626 GENMASK(17, 16));
1627}
1628
1629#define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
1630static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1631{
1632 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(19, 18));
1633 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1634 GENMASK(19, 18));
1635}
1636
1637static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1638{
1639 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(21, 20));
1640 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1641 GENMASK(21, 20));
1642}
1643
1644static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1645{
1646 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(23, 22));
1647 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1648 GENMASK(23, 22));
1649}
1650
1651static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1652{
1653 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(25, 24));
1654 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1655 GENMASK(25, 24));
1656}
1657
1658static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1659{
1660 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(27, 26));
1661 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1662 GENMASK(27, 26));
1663}
1664
1665static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1666{
1667 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(29, 28));
1668 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1669 GENMASK(29, 28));
1670}
1671
1672static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1673{
1674 le32p_replace_bits(p: (__le32 *)(table) + 5, val, GENMASK(31, 30));
1675 le32p_replace_bits(p: (__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1676 GENMASK(31, 30));
1677}
1678
1679#define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
1680static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1681{
1682 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(7, 0));
1683 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1684 GENMASK(7, 0));
1685}
1686
1687#define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
1688static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1689{
1690 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(15, 8));
1691 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1692 GENMASK(15, 8));
1693}
1694
1695static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1696{
1697 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(23, 16));
1698 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1699 GENMASK(23, 16));
1700}
1701
1702static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1703{
1704 le32p_replace_bits(p: (__le32 *)(table) + 6, val, GENMASK(31, 24));
1705 le32p_replace_bits(p: (__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1706 GENMASK(31, 24));
1707}
1708
1709static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1710{
1711 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(7, 0));
1712 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1713 GENMASK(7, 0));
1714}
1715
1716static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1717{
1718 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(15, 8));
1719 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1720 GENMASK(15, 8));
1721}
1722
1723static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1724{
1725 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(23, 16));
1726 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1727 GENMASK(23, 16));
1728}
1729
1730static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1731{
1732 le32p_replace_bits(p: (__le32 *)(table) + 7, val, GENMASK(31, 24));
1733 le32p_replace_bits(p: (__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1734 GENMASK(31, 24));
1735}
1736
1737struct rtw89_h2c_bcn_upd {
1738 __le32 w0;
1739 __le32 w1;
1740 __le32 w2;
1741} __packed;
1742
1743#define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1744#define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1745#define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1746#define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1747#define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1748#define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1749#define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1750#define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1751#define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1752#define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1753#define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1754#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1755#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1756#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1757#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1758#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1759#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1760#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1761#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1762#define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1763
1764struct rtw89_h2c_bcn_upd_be {
1765 __le32 w0;
1766 __le32 w1;
1767 __le32 w2;
1768 __le32 w3;
1769 __le32 w4;
1770 __le32 w5;
1771 __le32 w6;
1772 __le32 w7;
1773 __le32 w8;
1774 __le32 w9;
1775 __le32 w10;
1776 __le32 w11;
1777 __le32 w12;
1778 __le32 w13;
1779 __le32 w14;
1780 __le32 w15;
1781 __le32 w16;
1782 __le32 w17;
1783 __le32 w18;
1784 __le32 w19;
1785 __le32 w20;
1786 __le32 w21;
1787 __le32 w22;
1788 __le32 w23;
1789 __le32 w24;
1790 __le32 w25;
1791 __le32 w26;
1792 __le32 w27;
1793 __le32 w28;
1794 __le32 w29;
1795} __packed;
1796
1797#define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1798#define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1799#define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1800#define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1801#define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1802#define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1803#define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1804#define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1805#define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1806#define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1807#define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1808#define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1809#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1810#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1811#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1812#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1813#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1814#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1815#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1816#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1817#define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1818#define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1819#define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1820#define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1821#define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1822#define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1823#define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1824#define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1825#define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1826#define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1827#define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1828#define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1829
1830static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1831{
1832 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(7, 0));
1833}
1834
1835static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1836{
1837 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(9, 8));
1838}
1839
1840static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1841{
1842 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(12, 10));
1843}
1844
1845static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1846{
1847 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(16, 13));
1848}
1849
1850enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1851 RTW89_FW_N_AC_STA = 0,
1852 RTW89_FW_AX_STA = 1,
1853 RTW89_FW_BE_STA = 2,
1854};
1855
1856struct rtw89_h2c_join {
1857 __le32 w0;
1858} __packed;
1859
1860struct rtw89_h2c_join_v1 {
1861 __le32 w0;
1862 __le32 w1;
1863 __le32 w2;
1864} __packed;
1865
1866#define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1867#define RTW89_H2C_JOININFO_W0_OP BIT(8)
1868#define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1869#define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1870#define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1871#define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1872#define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1873#define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1874#define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1875#define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1876#define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1877#define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1878#define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1879#define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1880#define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1881#define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1882#define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1883#define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1884#define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1885#define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1886#define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1887#define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1888#define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1889#define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1890
1891struct rtw89_h2c_notify_dbcc {
1892 __le32 w0;
1893} __packed;
1894
1895#define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1896
1897static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1898{
1899 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(7, 0));
1900}
1901
1902static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1903{
1904 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(15, 8));
1905}
1906
1907static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1908{
1909 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(23, 16));
1910}
1911
1912static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1913{
1914 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(31, 24));
1915}
1916
1917static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1918{
1919 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1920}
1921
1922static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1923{
1924 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1925}
1926
1927static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1928{
1929 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(7, 0));
1930}
1931
1932static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1933{
1934 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(15, 8));
1935}
1936
1937static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1938{
1939 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1940}
1941
1942static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1943{
1944 le32p_replace_bits(p: (__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1945}
1946
1947struct rtw89_h2c_ba_cam {
1948 __le32 w0;
1949 __le32 w1;
1950} __packed;
1951
1952#define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1953#define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1954#define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1955#define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1956#define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1957#define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1958#define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1959#define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1960#define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1961#define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1962#define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1963
1964struct rtw89_h2c_ba_cam_v1 {
1965 __le32 w0;
1966 __le32 w1;
1967} __packed;
1968
1969#define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1970#define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1971#define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1972#define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1973#define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1974#define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1975#define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1976#define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1977#define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1978#define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1979#define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1980
1981struct rtw89_h2c_ba_cam_init {
1982 __le32 w0;
1983} __packed;
1984
1985#define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1986#define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1987#define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1988
1989static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1990{
1991 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(7, 0));
1992}
1993
1994static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1995{
1996 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(15, 8));
1997}
1998
1999static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
2000{
2001 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(19, 16));
2002}
2003
2004static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
2005{
2006 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(23, 20));
2007}
2008
2009static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
2010{
2011 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(31, 24));
2012}
2013
2014static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
2015{
2016 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, BIT(0));
2017}
2018
2019static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
2020{
2021 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, BIT(1));
2022}
2023
2024static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
2025{
2026 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, BIT(2));
2027}
2028
2029static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
2030{
2031 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, BIT(3));
2032}
2033
2034static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
2035{
2036 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, GENMASK(15, 8));
2037}
2038
2039struct rtw89_h2c_lps_ch_info {
2040 struct {
2041 u8 pri_ch;
2042 u8 central_ch;
2043 u8 bw;
2044 u8 band;
2045 } __packed info[2];
2046
2047 __le32 mlo_dbcc_mode_lps;
2048} __packed;
2049
2050static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
2051{
2052 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 0));
2053}
2054
2055static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
2056{
2057 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(7, 0));
2058}
2059
2060static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
2061{
2062 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 8));
2063}
2064
2065static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
2066{
2067 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(23, 16));
2068}
2069
2070static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
2071{
2072 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 24));
2073}
2074
2075static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
2076{
2077 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(7, 0));
2078}
2079
2080static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
2081{
2082 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(15, 8));
2083}
2084
2085static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
2086{
2087 le32p_replace_bits(p: (__le32 *)cmd + 2, val, GENMASK(31, 0));
2088}
2089
2090static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
2091{
2092 le32p_replace_bits(p: (__le32 *)cmd + 3, val, GENMASK(31, 0));
2093}
2094
2095static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
2096{
2097 le32p_replace_bits(p: (__le32 *)cmd + 4, val, GENMASK(31, 0));
2098}
2099
2100static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
2101{
2102 le32p_replace_bits(p: (__le32 *)cmd + 5, val, GENMASK(31, 0));
2103}
2104
2105static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
2106{
2107 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(1, 0));
2108}
2109
2110static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
2111{
2112 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(15, 8));
2113}
2114
2115static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
2116{
2117 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(24, 16));
2118}
2119
2120static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
2121{
2122 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(31, 24));
2123}
2124
2125static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
2126{
2127 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(0));
2128}
2129
2130static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
2131{
2132 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(1));
2133}
2134
2135static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
2136{
2137 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(2));
2138}
2139
2140static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
2141{
2142 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(15, 8));
2143}
2144
2145static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
2146{
2147 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(23, 16));
2148}
2149
2150static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
2151{
2152 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(31, 24));
2153}
2154
2155static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
2156{
2157 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, GENMASK(7, 0));
2158}
2159
2160static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
2161{
2162 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(0));
2163}
2164
2165static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
2166{
2167 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(1));
2168}
2169
2170static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
2171{
2172 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(2));
2173}
2174
2175static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
2176{
2177 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(3));
2178}
2179
2180static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
2181{
2182 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(15, 8));
2183}
2184
2185static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
2186{
2187 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(23, 16));
2188}
2189
2190static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
2191{
2192 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(31, 24));
2193}
2194
2195static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
2196{
2197 le32p_replace_bits(p: (__le32 *)(h2c) + 1, val, GENMASK(31, 0));
2198}
2199
2200static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2201{
2202 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(0));
2203}
2204
2205static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2206{
2207 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(1));
2208}
2209
2210static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2211{
2212 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(2));
2213}
2214
2215static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2216{
2217 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(3));
2218}
2219
2220static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2221{
2222 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(4));
2223}
2224
2225static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2226{
2227 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(5));
2228}
2229
2230static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2231{
2232 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(6));
2233}
2234
2235static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2236{
2237 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(7));
2238}
2239
2240static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2241{
2242 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(31, 24));
2243}
2244
2245static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2246{
2247 le32p_replace_bits(p: (__le32 *)h2c, val, BIT(0));
2248}
2249
2250static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2251{
2252 le32p_replace_bits(p: (__le32 *)h2c, val, GENMASK(7, 1));
2253}
2254
2255static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2256{
2257 le32p_replace_bits(p: (__le32 *)h2c + 1, val, GENMASK(31, 0));
2258}
2259
2260static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2261{
2262 le32p_replace_bits(p: (__le32 *)h2c + 2, val, GENMASK(31, 0));
2263}
2264
2265static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2266{
2267 le32p_replace_bits(p: (__le32 *)h2c + 3, val, GENMASK(31, 0));
2268}
2269
2270static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2271{
2272 le32p_replace_bits(p: (__le32 *)h2c + 4, val, GENMASK(31, 0));
2273}
2274
2275static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2276{
2277 le32p_replace_bits(p: (__le32 *)h2c + 5, val, GENMASK(15, 0));
2278}
2279
2280static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2281{
2282 le32p_replace_bits(p: (__le32 *)h2c + 5, val, BIT(22));
2283}
2284
2285static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2286{
2287 le32p_replace_bits(p: (__le32 *)h2c + 5, val, BIT(23));
2288}
2289
2290static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2291{
2292 le32p_replace_bits(p: (__le32 *)h2c + 5, val, BIT(24));
2293}
2294
2295static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2296{
2297 le32p_replace_bits(p: (__le32 *)h2c + 5, val, BIT(25));
2298}
2299
2300static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2301{
2302 le32p_replace_bits(p: (__le32 *)h2c + 5, val, BIT(26));
2303}
2304
2305static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2306{
2307 le32p_replace_bits(p: (__le32 *)h2c + 5, val, BIT(31));
2308}
2309
2310enum rtw89_btc_btf_h2c_class {
2311 BTFC_SET = 0x10,
2312 BTFC_GET = 0x11,
2313 BTFC_FW_EVENT = 0x12,
2314};
2315
2316enum rtw89_btc_btf_set {
2317 SET_REPORT_EN = 0x0,
2318 SET_SLOT_TABLE,
2319 SET_MREG_TABLE,
2320 SET_CX_POLICY,
2321 SET_GPIO_DBG,
2322 SET_DRV_INFO,
2323 SET_DRV_EVENT,
2324 SET_BT_WREG_ADDR,
2325 SET_BT_WREG_VAL,
2326 SET_BT_RREG_ADDR,
2327 SET_BT_WL_CH_INFO,
2328 SET_BT_INFO_REPORT,
2329 SET_BT_IGNORE_WLAN_ACT,
2330 SET_BT_TX_PWR,
2331 SET_BT_LNA_CONSTRAIN,
2332 SET_BT_QUERY_DEV_LIST,
2333 SET_BT_QUERY_DEV_INFO,
2334 SET_BT_PSD_REPORT,
2335 SET_H2C_TEST,
2336 SET_IOFLD_RF,
2337 SET_IOFLD_BB,
2338 SET_IOFLD_MAC,
2339 SET_IOFLD_SCBD,
2340 SET_H2C_MACRO,
2341 SET_MAX1,
2342};
2343
2344enum rtw89_btc_cxdrvinfo {
2345 CXDRVINFO_INIT = 0,
2346 CXDRVINFO_ROLE,
2347 CXDRVINFO_DBCC,
2348 CXDRVINFO_SMAP,
2349 CXDRVINFO_RFK,
2350 CXDRVINFO_RUN,
2351 CXDRVINFO_CTRL,
2352 CXDRVINFO_SCAN,
2353 CXDRVINFO_TRX, /* WL traffic to WL fw */
2354 CXDRVINFO_TXPWR,
2355 CXDRVINFO_FDDT,
2356 CXDRVINFO_MLO,
2357 CXDRVINFO_OSI,
2358 CXDRVINFO_MAX,
2359};
2360
2361enum rtw89_scan_mode {
2362 RTW89_SCAN_IMMEDIATE,
2363};
2364
2365enum rtw89_scan_type {
2366 RTW89_SCAN_ONCE,
2367};
2368
2369static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2370{
2371 u8p_replace_bits(p: (u8 *)(cmd) + 0, val, GENMASK(7, 0));
2372}
2373
2374static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2375{
2376 u8p_replace_bits(p: (u8 *)(cmd) + 1, val, GENMASK(7, 0));
2377}
2378
2379struct rtw89_h2c_cxhdr {
2380 u8 type;
2381 u8 len;
2382} __packed;
2383
2384struct rtw89_h2c_cxhdr_v7 {
2385 u8 type;
2386 u8 ver;
2387 u8 len;
2388} __packed;
2389
2390struct rtw89_h2c_cxctrl_v7 {
2391 struct rtw89_h2c_cxhdr_v7 hdr;
2392 struct rtw89_btc_ctrl_v7 ctrl;
2393} __packed;
2394
2395#define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2396#define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2397
2398struct rtw89_h2c_cxinit {
2399 struct rtw89_h2c_cxhdr hdr;
2400 u8 ant_type;
2401 u8 ant_num;
2402 u8 ant_iso;
2403 u8 ant_info;
2404 u8 mod_rfe;
2405 u8 mod_cv;
2406 u8 mod_info;
2407 u8 mod_adie_kt;
2408 u8 wl_gch;
2409 u8 info;
2410 u8 rsvd;
2411 u8 rsvd1;
2412} __packed;
2413
2414#define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2415#define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2416#define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2417#define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2418
2419#define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2420#define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2421#define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2422#define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2423
2424#define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2425#define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2426#define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2427#define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2428#define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2429
2430struct rtw89_h2c_cxinit_v7 {
2431 struct rtw89_h2c_cxhdr_v7 hdr;
2432 struct rtw89_btc_init_info_v7 init;
2433} __packed;
2434
2435static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2436{
2437 u8p_replace_bits(p: (u8 *)(cmd) + 2, val, GENMASK(7, 0));
2438}
2439
2440static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2441{
2442 u8p_replace_bits(p: (u8 *)(cmd) + 3, val, GENMASK(7, 0));
2443}
2444
2445static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2446{
2447 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2448}
2449
2450static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2451{
2452 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2453}
2454
2455static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2456{
2457 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2458}
2459
2460static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2461{
2462 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2463}
2464
2465static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2466{
2467 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2468}
2469
2470static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2471{
2472 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2473}
2474
2475static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2476{
2477 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2478}
2479
2480static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2481{
2482 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2483}
2484
2485static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2486{
2487 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2488}
2489
2490static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2491{
2492 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2493}
2494
2495static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2496{
2497 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2498}
2499
2500static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2501{
2502 le16p_replace_bits(p: (__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2503}
2504
2505static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2506{
2507 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2508}
2509
2510static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2511{
2512 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2513}
2514
2515static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2516{
2517 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2518}
2519
2520static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2521{
2522 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2523}
2524
2525static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2526{
2527 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2528}
2529
2530static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2531{
2532 u8p_replace_bits(p: (u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2533}
2534
2535static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2536{
2537 u8p_replace_bits(p: (u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2538}
2539
2540static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2541{
2542 u8p_replace_bits(p: (u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2543}
2544
2545static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2546{
2547 u8p_replace_bits(p: (u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2548}
2549
2550static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2551{
2552 le16p_replace_bits(p: (__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2553}
2554
2555static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2556{
2557 le16p_replace_bits(p: (__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2558}
2559
2560static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2561{
2562 le16p_replace_bits(p: (__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2563}
2564
2565static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2566{
2567 le16p_replace_bits(p: (__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2568}
2569
2570static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2571{
2572 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2573}
2574
2575static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2576{
2577 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2578}
2579
2580static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2581{
2582 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2583}
2584
2585static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2586{
2587 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2588}
2589
2590static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2591{
2592 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2593}
2594
2595static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2596{
2597 u8p_replace_bits(p: (u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2598}
2599
2600static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2601{
2602 u8p_replace_bits(p: (u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2603}
2604
2605static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2606{
2607 u8p_replace_bits(p: (u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2608}
2609
2610static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2611{
2612 u8p_replace_bits(p: (u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2613}
2614
2615static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2616{
2617 u8p_replace_bits(p: (u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2618}
2619
2620static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2621{
2622 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2623}
2624
2625static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2626{
2627 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2628}
2629
2630static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2631{
2632 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2633}
2634
2635static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2636{
2637 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2638}
2639
2640static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2641{
2642 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2643}
2644
2645static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2646{
2647 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2648}
2649
2650static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2651{
2652 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2653}
2654
2655static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2656{
2657 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2658}
2659
2660static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2661{
2662 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2663}
2664
2665static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2666{
2667 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2668}
2669
2670static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2671{
2672 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2673}
2674
2675static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2676{
2677 u8p_replace_bits(p: (u8 *)cmd + 2, val, GENMASK(7, 0));
2678}
2679
2680static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2681{
2682 u8p_replace_bits(p: (u8 *)cmd + 3, val, GENMASK(7, 0));
2683}
2684
2685static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2686{
2687 u8p_replace_bits(p: (u8 *)cmd + 4, val, GENMASK(7, 0));
2688}
2689
2690static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2691{
2692 u8p_replace_bits(p: (u8 *)cmd + 5, val, GENMASK(7, 0));
2693}
2694
2695static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2696{
2697 u8p_replace_bits(p: (u8 *)cmd + 6, val, GENMASK(7, 0));
2698}
2699
2700static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2701{
2702 u8p_replace_bits(p: (u8 *)cmd + 7, val, GENMASK(7, 0));
2703}
2704
2705static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2706{
2707 u8p_replace_bits(p: (u8 *)cmd + 8, val, GENMASK(7, 0));
2708}
2709
2710static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2711{
2712 u8p_replace_bits(p: (u8 *)cmd + 9, val, GENMASK(7, 0));
2713}
2714
2715static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2716{
2717 u8p_replace_bits(p: (u8 *)cmd + 10, val, GENMASK(7, 0));
2718}
2719
2720static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2721{
2722 u8p_replace_bits(p: (u8 *)cmd + 11, val, GENMASK(7, 0));
2723}
2724
2725static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2726{
2727 u8p_replace_bits(p: (u8 *)cmd + 12, val, GENMASK(7, 0));
2728}
2729
2730static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2731{
2732 u8p_replace_bits(p: (u8 *)cmd + 13, val, GENMASK(7, 0));
2733}
2734
2735static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2736{
2737 le16p_replace_bits(p: (__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2738}
2739
2740static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2741{
2742 le16p_replace_bits(p: (__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2743}
2744
2745static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2746{
2747 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2748}
2749
2750static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2751{
2752 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2753}
2754
2755static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2756{
2757 le32p_replace_bits(p: (__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2758}
2759
2760static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2761{
2762 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2763}
2764
2765static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2766{
2767 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2768}
2769
2770static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2771{
2772 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2773}
2774
2775static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2776{
2777 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2778}
2779
2780static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2781{
2782 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2783}
2784
2785static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2786{
2787 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2788}
2789
2790static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2791{
2792 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2793}
2794
2795static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2796{
2797 le32p_replace_bits(p: (__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2798}
2799
2800struct rtw89_h2c_chinfo_elem {
2801 __le32 w0;
2802 __le32 w1;
2803 __le32 w2;
2804 __le32 w3;
2805 __le32 w4;
2806 __le32 w5;
2807 __le32 w6;
2808} __packed;
2809
2810#define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2811#define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2812#define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2813#define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2814#define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2815#define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2816#define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2817#define RTW89_H2C_CHINFO_W1_TX BIT(12)
2818#define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2819#define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2820#define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2821#define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2822#define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2823#define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2824#define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2825#define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2826#define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2827#define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2828#define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2829#define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2830#define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2831#define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2832#define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2833#define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2834
2835struct rtw89_h2c_chinfo_elem_be {
2836 __le32 w0;
2837 __le32 w1;
2838 __le32 w2;
2839 __le32 w3;
2840 __le32 w4;
2841 __le32 w5;
2842 __le32 w6;
2843} __packed;
2844
2845#define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2846#define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2847#define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2848#define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2849#define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2850#define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2851#define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2852#define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2853#define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2854#define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2855#define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2856#define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2857#define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2858#define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2859#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2860#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2861#define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2862#define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2863#define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2864#define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2865#define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2866#define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2867#define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2868#define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2869#define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2870#define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2871#define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2872#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2873#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2874
2875struct rtw89_h2c_chinfo {
2876 u8 ch_num;
2877 u8 elem_size;
2878 u8 arg;
2879 u8 rsvd0;
2880 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2881} __packed;
2882
2883#define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2884#define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2885
2886struct rtw89_h2c_scanofld {
2887 __le32 w0;
2888 __le32 w1;
2889 __le32 w2;
2890 __le32 tsf_high;
2891 __le32 tsf_low;
2892 __le32 w5;
2893 __le32 w6;
2894} __packed;
2895
2896#define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2897#define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2898#define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2899#define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2900#define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2901#define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2902#define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2903#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2904#define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2905#define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2906#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2907#define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2908#define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2909#define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2910#define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2911#define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2912
2913struct rtw89_h2c_scanofld_be_macc_role {
2914 __le32 w0;
2915} __packed;
2916
2917#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2918#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2919#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2920#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2921
2922struct rtw89_h2c_scanofld_be_opch {
2923 __le32 w0;
2924 __le32 w1;
2925 __le32 w2;
2926 __le32 w3;
2927} __packed;
2928
2929#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2930#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2931#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2932#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2933#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2934#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2935#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2936#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2937#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2938#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2939#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2940#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2941#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2942#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2943#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2944#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2945#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2946#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2947#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2948
2949struct rtw89_h2c_scanofld_be {
2950 __le32 w0;
2951 __le32 w1;
2952 __le32 w2;
2953 __le32 w3;
2954 __le32 w4;
2955 __le32 w5;
2956 __le32 w6;
2957 __le32 w7;
2958 struct rtw89_h2c_scanofld_be_macc_role role[];
2959} __packed;
2960
2961#define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2962#define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2963#define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2964#define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2965#define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2966#define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2967#define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2968#define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2969#define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2970#define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2971#define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2972#define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2973#define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2974#define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2975#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2976#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2977#define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2978#define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2979#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2980#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2981#define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2982#define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2983#define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2984#define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2985
2986static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2987{
2988 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(7, 0));
2989}
2990
2991static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2992{
2993 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(11, 8));
2994}
2995
2996static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2997{
2998 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 12));
2999}
3000
3001static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
3002{
3003 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(19, 16));
3004}
3005
3006static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
3007{
3008 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(20));
3009}
3010
3011static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
3012{
3013 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(21));
3014}
3015
3016static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
3017{
3018 *((__le32 *)cmd + 1) = val;
3019}
3020
3021static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
3022{
3023 *((__le32 *)cmd + 2) = val;
3024}
3025
3026static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
3027{
3028 *((__le32 *)cmd + 3) = val;
3029}
3030
3031static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
3032{
3033 le32p_replace_bits(p: (__le32 *)(cmd) + 4, val, GENMASK(7, 0));
3034}
3035
3036static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
3037{
3038 u8 ctwnd;
3039
3040 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
3041 return;
3042 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
3043 le32p_replace_bits(p: (__le32 *)(cmd) + 4, val: ctwnd, GENMASK(23, 8));
3044}
3045
3046static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
3047{
3048 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(0));
3049}
3050
3051static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
3052{
3053 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(1));
3054}
3055
3056static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
3057{
3058 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(4, 2));
3059}
3060
3061static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
3062{
3063 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 16));
3064}
3065
3066enum rtw89_fw_mcc_c2h_rpt_cfg {
3067 RTW89_FW_MCC_C2H_RPT_OFF = 0,
3068 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
3069 RTW89_FW_MCC_C2H_RPT_ALL = 2,
3070};
3071
3072struct rtw89_fw_mcc_add_req {
3073 u8 macid;
3074 u8 central_ch_seg0;
3075 u8 central_ch_seg1;
3076 u8 primary_ch;
3077 enum rtw89_bandwidth bandwidth: 4;
3078 u32 group: 2;
3079 u32 c2h_rpt: 2;
3080 u32 dis_tx_null: 1;
3081 u32 dis_sw_retry: 1;
3082 u32 in_curr_ch: 1;
3083 u32 sw_retry_count: 3;
3084 u32 tx_null_early: 4;
3085 u32 btc_in_2g: 1;
3086 u32 pta_en: 1;
3087 u32 rfk_by_pass: 1;
3088 u32 ch_band_type: 2;
3089 u32 rsvd0: 9;
3090 u32 duration;
3091 u8 courtesy_en;
3092 u8 courtesy_num;
3093 u8 courtesy_target;
3094 u8 rsvd1;
3095};
3096
3097static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
3098{
3099 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(7, 0));
3100}
3101
3102static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
3103{
3104 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 8));
3105}
3106
3107static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
3108{
3109 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(23, 16));
3110}
3111
3112static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
3113{
3114 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 24));
3115}
3116
3117static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
3118{
3119 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(3, 0));
3120}
3121
3122static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
3123{
3124 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(5, 4));
3125}
3126
3127static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3128{
3129 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(7, 6));
3130}
3131
3132static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3133{
3134 le32p_replace_bits(p: (__le32 *)cmd + 1, val, BIT(8));
3135}
3136
3137static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3138{
3139 le32p_replace_bits(p: (__le32 *)cmd + 1, val, BIT(9));
3140}
3141
3142static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3143{
3144 le32p_replace_bits(p: (__le32 *)cmd + 1, val, BIT(10));
3145}
3146
3147static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3148{
3149 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(13, 11));
3150}
3151
3152static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3153{
3154 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(17, 14));
3155}
3156
3157static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3158{
3159 le32p_replace_bits(p: (__le32 *)cmd + 1, val, BIT(18));
3160}
3161
3162static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3163{
3164 le32p_replace_bits(p: (__le32 *)cmd + 1, val, BIT(19));
3165}
3166
3167static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3168{
3169 le32p_replace_bits(p: (__le32 *)cmd + 1, val, BIT(20));
3170}
3171
3172static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3173{
3174 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(22, 21));
3175}
3176
3177static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3178{
3179 le32p_replace_bits(p: (__le32 *)cmd + 2, val, GENMASK(31, 0));
3180}
3181
3182static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3183{
3184 le32p_replace_bits(p: (__le32 *)cmd + 3, val, BIT(0));
3185}
3186
3187static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3188{
3189 le32p_replace_bits(p: (__le32 *)cmd + 3, val, GENMASK(15, 8));
3190}
3191
3192static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3193{
3194 le32p_replace_bits(p: (__le32 *)cmd + 3, val, GENMASK(23, 16));
3195}
3196
3197enum rtw89_fw_mcc_old_group_actions {
3198 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3199 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3200};
3201
3202struct rtw89_fw_mcc_start_req {
3203 u32 group: 2;
3204 u32 btc_in_group: 1;
3205 u32 old_group_action: 2;
3206 u32 old_group: 2;
3207 u32 rsvd0: 9;
3208 u32 notify_cnt: 3;
3209 u32 rsvd1: 2;
3210 u32 notify_rxdbg_en: 1;
3211 u32 rsvd2: 2;
3212 u32 macid: 8;
3213 u32 tsf_low;
3214 u32 tsf_high;
3215};
3216
3217static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3218{
3219 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3220}
3221
3222static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3223{
3224 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(2));
3225}
3226
3227static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3228{
3229 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(4, 3));
3230}
3231
3232static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3233{
3234 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(6, 5));
3235}
3236
3237static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3238{
3239 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(18, 16));
3240}
3241
3242static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3243{
3244 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(21));
3245}
3246
3247static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3248{
3249 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 24));
3250}
3251
3252static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3253{
3254 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(31, 0));
3255}
3256
3257static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3258{
3259 le32p_replace_bits(p: (__le32 *)cmd + 2, val, GENMASK(31, 0));
3260}
3261
3262static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3263{
3264 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(7, 0));
3265}
3266
3267static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3268{
3269 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(9, 8));
3270}
3271
3272static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3273{
3274 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(10));
3275}
3276
3277static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3278{
3279 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3280}
3281
3282static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3283{
3284 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(2));
3285}
3286
3287static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3288{
3289 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3290}
3291
3292struct rtw89_fw_mcc_tsf_req {
3293 u8 group: 2;
3294 u8 rsvd0: 6;
3295 u8 macid_x;
3296 u8 macid_y;
3297 u8 rsvd1;
3298};
3299
3300static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3301{
3302 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3303}
3304
3305static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3306{
3307 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 8));
3308}
3309
3310static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3311{
3312 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(23, 16));
3313}
3314
3315static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3316{
3317 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3318}
3319
3320static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3321{
3322 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 8));
3323}
3324
3325static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3326{
3327 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(23, 16));
3328}
3329
3330static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3331 u8 *bitmap, u8 len)
3332{
3333 memcpy((__le32 *)cmd + 1, bitmap, len);
3334}
3335
3336static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3337{
3338 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3339}
3340
3341static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3342{
3343 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 8));
3344}
3345
3346static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3347{
3348 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(23, 16));
3349}
3350
3351static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3352{
3353 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 24));
3354}
3355
3356struct rtw89_fw_mcc_duration {
3357 u32 group: 2;
3358 u32 btc_in_group: 1;
3359 u32 rsvd0: 5;
3360 u32 start_macid: 8;
3361 u32 macid_x: 8;
3362 u32 macid_y: 8;
3363 u32 start_tsf_low;
3364 u32 start_tsf_high;
3365 u32 duration_x;
3366 u32 duration_y;
3367};
3368
3369static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3370{
3371 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(1, 0));
3372}
3373
3374static
3375inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3376{
3377 le32p_replace_bits(p: (__le32 *)cmd, val, BIT(2));
3378}
3379
3380static
3381inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3382{
3383 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(15, 8));
3384}
3385
3386static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3387{
3388 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(23, 16));
3389}
3390
3391static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3392{
3393 le32p_replace_bits(p: (__le32 *)cmd, val, GENMASK(31, 24));
3394}
3395
3396static
3397inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3398{
3399 le32p_replace_bits(p: (__le32 *)cmd + 1, val, GENMASK(31, 0));
3400}
3401
3402static
3403inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3404{
3405 le32p_replace_bits(p: (__le32 *)cmd + 2, val, GENMASK(31, 0));
3406}
3407
3408static
3409inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3410{
3411 le32p_replace_bits(p: (__le32 *)cmd + 3, val, GENMASK(31, 0));
3412}
3413
3414static
3415inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3416{
3417 le32p_replace_bits(p: (__le32 *)cmd + 4, val, GENMASK(31, 0));
3418}
3419
3420enum rtw89_h2c_mrc_sch_types {
3421 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3422 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3423 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3424};
3425
3426enum rtw89_h2c_mrc_role_types {
3427 RTW89_H2C_MRC_ROLE_WIFI = 0,
3428 RTW89_H2C_MRC_ROLE_BT = 1,
3429 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3430};
3431
3432#define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3433#define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3434
3435struct rtw89_fw_mrc_add_slot_arg {
3436 u16 duration; /* unit: TU */
3437 bool courtesy_en;
3438 u8 courtesy_period;
3439 u8 courtesy_target; /* slot idx */
3440
3441 unsigned int role_num;
3442 struct {
3443 enum rtw89_h2c_mrc_role_types role_type;
3444 bool is_master;
3445 bool en_tx_null;
3446 enum rtw89_band band;
3447 enum rtw89_bandwidth bw;
3448 u8 macid;
3449 u8 central_ch;
3450 u8 primary_ch;
3451 u8 null_early; /* unit: TU */
3452
3453 /* if MLD, for macid: [0, chip::support_mld_num)
3454 * otherwise, for macid: [0, 32)
3455 */
3456 u32 macid_main_bitmap;
3457 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3458 u32 macid_paired_bitmap;
3459 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3460};
3461
3462struct rtw89_fw_mrc_add_arg {
3463 u8 sch_idx;
3464 enum rtw89_h2c_mrc_sch_types sch_type;
3465 bool btc_in_sch;
3466
3467 unsigned int slot_num;
3468 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3469};
3470
3471struct rtw89_h2c_mrc_add_role {
3472 __le32 w0;
3473 __le32 w1;
3474 __le32 w2;
3475 __le32 macid_main_bitmap;
3476 __le32 macid_paired_bitmap;
3477} __packed;
3478
3479#define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3480#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3481#define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3482#define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3483#define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3484#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3485#define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3486#define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3487#define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3488#define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3489#define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3490#define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3491#define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3492#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3493#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3494#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3495
3496struct rtw89_h2c_mrc_add_slot {
3497 __le32 w0;
3498 __le32 w1;
3499 struct rtw89_h2c_mrc_add_role roles[];
3500} __packed;
3501
3502#define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3503#define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3504#define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3505#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3506#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3507
3508struct rtw89_h2c_mrc_add {
3509 __le32 w0;
3510 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3511 * are other flexible array inside it. We cannot access them correctly
3512 * through this struct. So, in case misusing, we don't really declare
3513 * it here.
3514 */
3515} __packed;
3516
3517#define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3518#define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3519#define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3520#define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3521
3522enum rtw89_h2c_mrc_start_actions {
3523 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3524 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3525};
3526
3527struct rtw89_fw_mrc_start_arg {
3528 u8 sch_idx;
3529 u8 old_sch_idx;
3530 u64 start_tsf;
3531 enum rtw89_h2c_mrc_start_actions action;
3532};
3533
3534struct rtw89_h2c_mrc_start {
3535 __le32 w0;
3536 __le32 start_tsf_low;
3537 __le32 start_tsf_high;
3538} __packed;
3539
3540#define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3541#define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3542#define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3543
3544struct rtw89_h2c_mrc_del {
3545 __le32 w0;
3546} __packed;
3547
3548#define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3549#define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3550#define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3551#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3552#define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3553#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3554
3555#define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3556
3557struct rtw89_fw_mrc_req_tsf_arg {
3558 unsigned int num;
3559 struct {
3560 u8 band;
3561 u8 port;
3562 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3563};
3564
3565struct rtw89_h2c_mrc_req_tsf {
3566 u8 req_tsf_num;
3567 u8 infos[] __counted_by(req_tsf_num);
3568} __packed;
3569
3570#define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3571#define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3572
3573enum rtw89_h2c_mrc_upd_bitmap_actions {
3574 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3575 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3576};
3577
3578struct rtw89_fw_mrc_upd_bitmap_arg {
3579 u8 sch_idx;
3580 u8 macid;
3581 u8 client_macid;
3582 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3583};
3584
3585struct rtw89_h2c_mrc_upd_bitmap {
3586 __le32 w0;
3587 __le32 w1;
3588} __packed;
3589
3590#define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3591#define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3592#define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3593#define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3594
3595struct rtw89_fw_mrc_sync_arg {
3596 u8 offset; /* unit: TU */
3597 struct {
3598 u8 band;
3599 u8 port;
3600 } src, dest;
3601};
3602
3603struct rtw89_h2c_mrc_sync {
3604 __le32 w0;
3605 __le32 w1;
3606} __packed;
3607
3608#define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3609#define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3610#define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3611#define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3612#define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3613#define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3614
3615struct rtw89_fw_mrc_upd_duration_arg {
3616 u8 sch_idx;
3617 u64 start_tsf;
3618
3619 unsigned int slot_num;
3620 struct {
3621 u8 slot_idx;
3622 u16 duration; /* unit: TU */
3623 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3624};
3625
3626struct rtw89_h2c_mrc_upd_duration {
3627 __le32 w0;
3628 __le32 start_tsf_low;
3629 __le32 start_tsf_high;
3630 __le32 slots[];
3631} __packed;
3632
3633#define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3634#define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3635#define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3636#define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3637#define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3638
3639#define RTW89_C2H_HEADER_LEN 8
3640
3641struct rtw89_c2h_hdr {
3642 __le32 w0;
3643 __le32 w1;
3644} __packed;
3645
3646#define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3647#define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3648#define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3649#define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3650
3651struct rtw89_fw_c2h_attr {
3652 u8 category;
3653 u8 class;
3654 u8 func;
3655 u16 len;
3656};
3657
3658static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3659{
3660 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3661
3662 return (struct rtw89_fw_c2h_attr *)skb->cb;
3663}
3664
3665struct rtw89_c2h_done_ack {
3666 __le32 w0;
3667 __le32 w1;
3668 __le32 w2;
3669} __packed;
3670
3671#define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3672#define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3673#define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3674#define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3675#define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3676
3677#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3678 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3679#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3680 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3681#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3682 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3683#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3684 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3685
3686struct rtw89_fw_c2h_log_fmt {
3687 __le16 signature;
3688 u8 feature;
3689 u8 syntax;
3690 __le32 fmt_id;
3691 u8 file_num;
3692 __le16 line_num;
3693 u8 argc;
3694 union {
3695 DECLARE_FLEX_ARRAY(u8, raw);
3696 DECLARE_FLEX_ARRAY(__le32, argv);
3697 } __packed u;
3698} __packed;
3699
3700#define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3701#define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3702#define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3703#define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3704#define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3705
3706struct rtw89_c2h_mac_bcnfltr_rpt {
3707 __le32 w0;
3708 __le32 w1;
3709 __le32 w2;
3710} __packed;
3711
3712#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3713#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3714#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3715#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3716
3717struct rtw89_c2h_ra_rpt {
3718 struct rtw89_c2h_hdr hdr;
3719 __le32 w2;
3720 __le32 w3;
3721} __packed;
3722
3723#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3724#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3725#define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3726#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3727#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3728#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3729#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3730#define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3731#define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3732
3733/* For WiFi 6 chips:
3734 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3735 * HT-new: [6:5]: NA, [4:0]: MCS
3736 * For WiFi 7 chips (V1):
3737 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3738 */
3739#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3740#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3741#define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3742#define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3743#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3744#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3745 FIELD_PREP(GENMASK(2, 0), mcs))
3746
3747#define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3748 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3749#define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3750 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3751#define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3752 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3753
3754struct rtw89_c2h_scanofld {
3755 __le32 w0;
3756 __le32 w1;
3757 __le32 w2;
3758 __le32 w3;
3759 __le32 w4;
3760 __le32 w5;
3761 __le32 w6;
3762 __le32 w7;
3763} __packed;
3764
3765#define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3766#define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3767#define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3768#define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3769#define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3770#define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3771#define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3772#define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3773#define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3774#define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3775#define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3776#define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3777
3778#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3779 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3780#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3781 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3782
3783#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3784 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3785#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3786 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3787#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3788 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3789
3790struct rtw89_mac_mcc_tsf_rpt {
3791 u32 macid_x;
3792 u32 macid_y;
3793 u32 tsf_x_low;
3794 u32 tsf_x_high;
3795 u32 tsf_y_low;
3796 u32 tsf_y_high;
3797};
3798
3799static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3800
3801#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3802 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3803#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3804 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3805#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3806 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3807#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3808 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3809#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3810 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3811#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3812 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3813#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3814 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3815
3816#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3817 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3818#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3819 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3820#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3821 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3822#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3823 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3824#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3825 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3826
3827struct rtw89_mac_mrc_tsf_rpt {
3828 unsigned int num;
3829 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3830};
3831
3832static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3833
3834struct rtw89_c2h_mrc_tsf_rpt_info {
3835 __le32 tsf_low;
3836 __le32 tsf_high;
3837} __packed;
3838
3839struct rtw89_c2h_mrc_tsf_rpt {
3840 struct rtw89_c2h_hdr hdr;
3841 __le32 w2;
3842 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3843} __packed;
3844
3845#define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3846
3847struct rtw89_c2h_mrc_status_rpt {
3848 struct rtw89_c2h_hdr hdr;
3849 __le32 w2;
3850 __le32 tsf_low;
3851 __le32 tsf_high;
3852} __packed;
3853
3854#define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3855#define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3856
3857struct rtw89_c2h_pkt_ofld_rsp {
3858 __le32 w0;
3859 __le32 w1;
3860 __le32 w2;
3861} __packed;
3862
3863#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3864#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3865#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3866
3867struct rtw89_h2c_bcnfltr {
3868 __le32 w0;
3869} __packed;
3870
3871#define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3872#define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3873#define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3874#define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3875#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3876#define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3877#define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3878#define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3879
3880struct rtw89_h2c_ofld_rssi {
3881 __le32 w0;
3882 __le32 w1;
3883} __packed;
3884
3885#define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3886#define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3887#define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3888
3889struct rtw89_h2c_ofld {
3890 __le32 w0;
3891} __packed;
3892
3893#define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3894#define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3895#define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3896
3897#define RTW89_MFW_SIG 0xFF
3898
3899struct rtw89_mfw_info {
3900 u8 cv;
3901 u8 type; /* enum rtw89_fw_type */
3902 u8 mp;
3903 u8 rsvd;
3904 __le32 shift;
3905 __le32 size;
3906 u8 rsvd2[4];
3907} __packed;
3908
3909struct rtw89_mfw_hdr {
3910 u8 sig; /* RTW89_MFW_SIG */
3911 u8 fw_nr;
3912 u8 rsvd0[2];
3913 struct {
3914 u8 major;
3915 u8 minor;
3916 u8 sub;
3917 u8 idx;
3918 } ver;
3919 u8 rsvd1[8];
3920 struct rtw89_mfw_info info[];
3921} __packed;
3922
3923struct rtw89_fw_logsuit_hdr {
3924 __le32 rsvd;
3925 __le32 count;
3926 __le32 ids[];
3927} __packed;
3928
3929#define RTW89_FW_ELEMENT_ALIGN 16
3930
3931enum rtw89_fw_element_id {
3932 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3933 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3934 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3935 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3936 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3937 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3938 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3939 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3940 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3941 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3942 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3943 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3944 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3945 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3946 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3947 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3948 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3949 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3950 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3951 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3952
3953 RTW89_FW_ELEMENT_ID_NUM,
3954};
3955
3956#define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3957 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3958 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3959 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3960 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3961 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3962 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3963 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ) | \
3964 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3965 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3966
3967#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3968 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3969 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3970 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3971 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3972 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3973 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3974
3975struct __rtw89_fw_txpwr_element {
3976 u8 rsvd0;
3977 u8 rsvd1;
3978 u8 rfe_type;
3979 u8 ent_sz;
3980 __le32 num_ents;
3981 u8 content[];
3982} __packed;
3983
3984enum rtw89_fw_txpwr_trk_type {
3985 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3986 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3987 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3988 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3989 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3990 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3991
3992 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3993 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3994 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3995 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3996 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3997 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3998
3999 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
4000 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
4001 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
4002 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
4003 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
4004 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
4005 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
4006 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
4007 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
4008 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
4009
4010 RTW89_FW_TXPWR_TRK_TYPE_NR,
4011};
4012
4013struct rtw89_fw_txpwr_track_cfg {
4014 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
4015};
4016
4017#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
4018 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4019 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4020 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4021 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4022#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
4023 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4024 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4025 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4026 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4027#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
4028 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4029 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4030 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4031 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4032 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4033 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4034 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4035 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4036
4037struct rtw89_fw_element_hdr {
4038 __le32 id; /* enum rtw89_fw_element_id */
4039 __le32 size; /* exclude header size */
4040 u8 ver[4];
4041 __le32 rsvd0;
4042 __le32 rsvd1;
4043 __le32 rsvd2;
4044 union {
4045 struct {
4046 u8 priv[8];
4047 u8 contents[];
4048 } __packed common;
4049 struct {
4050 u8 idx;
4051 u8 rsvd[7];
4052 struct {
4053 __le32 addr;
4054 __le32 data;
4055 } __packed regs[];
4056 } __packed reg2;
4057 struct {
4058 u8 cv;
4059 u8 priv[7];
4060 u8 contents[];
4061 } __packed bbmcu;
4062 struct {
4063 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4064 __le32 rsvd;
4065 s8 contents[][DELTA_SWINGIDX_SIZE];
4066 } __packed txpwr_trk;
4067 struct {
4068 u8 nr;
4069 u8 rsvd[3];
4070 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4071 u8 rsvd1[3];
4072 __le16 offset[];
4073 } __packed rfk_log_fmt;
4074 struct __rtw89_fw_txpwr_element txpwr;
4075 } __packed u;
4076} __packed;
4077
4078struct fwcmd_hdr {
4079 __le32 hdr0;
4080 __le32 hdr1;
4081};
4082
4083union rtw89_compat_fw_hdr {
4084 struct rtw89_mfw_hdr mfw_hdr;
4085 struct rtw89_fw_hdr fw_hdr;
4086};
4087
4088static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4089{
4090 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4091
4092 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4093 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4094 else
4095 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4096}
4097
4098static inline void rtw89_fw_get_filename(char *buf, size_t size,
4099 const char *fw_basename, int fw_format)
4100{
4101 if (fw_format <= 0)
4102 snprintf(buf, size, fmt: "%s.bin", fw_basename);
4103 else
4104 snprintf(buf, size, fmt: "%s-%d.bin", fw_basename, fw_format);
4105}
4106
4107#define RTW89_H2C_RF_PAGE_SIZE 500
4108#define RTW89_H2C_RF_PAGE_NUM 3
4109struct rtw89_fw_h2c_rf_reg_info {
4110 enum rtw89_rf_path rf_path;
4111 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4112 u16 curr_idx;
4113};
4114
4115#define H2C_SEC_CAM_LEN 24
4116
4117#define H2C_HEADER_LEN 8
4118#define H2C_HDR_CAT GENMASK(1, 0)
4119#define H2C_HDR_CLASS GENMASK(7, 2)
4120#define H2C_HDR_FUNC GENMASK(15, 8)
4121#define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4122#define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4123#define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4124#define H2C_HDR_REC_ACK BIT(14)
4125#define H2C_HDR_DONE_ACK BIT(15)
4126
4127#define FWCMD_TYPE_H2C 0
4128
4129#define H2C_CAT_TEST 0x0
4130
4131/* CLASS 5 - FW STATUS TEST */
4132#define H2C_CL_FW_STATUS_TEST 0x5
4133#define H2C_FUNC_CPU_EXCEPTION 0x1
4134
4135#define H2C_CAT_MAC 0x1
4136
4137/* CLASS 0 - FW INFO */
4138#define H2C_CL_FW_INFO 0x0
4139#define H2C_FUNC_LOG_CFG 0x0
4140#define H2C_FUNC_MAC_GENERAL_PKT 0x1
4141
4142/* CLASS 1 - WOW */
4143#define H2C_CL_MAC_WOW 0x1
4144#define H2C_FUNC_KEEP_ALIVE 0x0
4145#define H2C_FUNC_DISCONNECT_DETECT 0x1
4146#define H2C_FUNC_WOW_GLOBAL 0x2
4147#define H2C_FUNC_WAKEUP_CTRL 0x8
4148#define H2C_FUNC_WOW_CAM_UPD 0xC
4149
4150/* CLASS 2 - PS */
4151#define H2C_CL_MAC_PS 0x2
4152#define H2C_FUNC_MAC_LPS_PARM 0x0
4153#define H2C_FUNC_P2P_ACT 0x1
4154
4155/* CLASS 3 - FW download */
4156#define H2C_CL_MAC_FWDL 0x3
4157#define H2C_FUNC_MAC_FWHDR_DL 0x0
4158
4159/* CLASS 5 - Frame Exchange */
4160#define H2C_CL_MAC_FR_EXCHG 0x5
4161#define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4162#define H2C_FUNC_MAC_BCN_UPD 0x5
4163#define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4164#define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4165#define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4166#define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4167#define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4168
4169/* CLASS 6 - Address CAM */
4170#define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4171#define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4172
4173/* CLASS 8 - Media Status Report */
4174#define H2C_CL_MAC_MEDIA_RPT 0x8
4175#define H2C_FUNC_MAC_JOININFO 0x0
4176#define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4177#define H2C_FUNC_NOTIFY_DBCC 0x5
4178
4179/* CLASS 9 - FW offload */
4180#define H2C_CL_MAC_FW_OFLD 0x9
4181enum rtw89_fw_ofld_h2c_func {
4182 H2C_FUNC_PACKET_OFLD = 0x1,
4183 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4184 H2C_FUNC_USR_EDCA = 0xF,
4185 H2C_FUNC_TSF32_TOGL = 0x10,
4186 H2C_FUNC_OFLD_CFG = 0x14,
4187 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4188 H2C_FUNC_SCANOFLD = 0x17,
4189 H2C_FUNC_PKT_DROP = 0x1b,
4190 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4191 H2C_FUNC_OFLD_RSSI = 0x1f,
4192 H2C_FUNC_OFLD_TP = 0x20,
4193 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4194 H2C_FUNC_SCANOFLD_BE = 0x2c,
4195
4196 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4197};
4198
4199#define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4200 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4201
4202#define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4203 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4204 H2C_FUNC_PACKET_OFLD)
4205
4206#define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4207
4208#define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4209#define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4210#define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4211#define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4212
4213
4214/* CLASS 10 - Security CAM */
4215#define H2C_CL_MAC_SEC_CAM 0xa
4216#define H2C_FUNC_MAC_SEC_UPD 0x1
4217
4218/* CLASS 12 - BA CAM */
4219#define H2C_CL_BA_CAM 0xc
4220#define H2C_FUNC_MAC_BA_CAM 0x0
4221#define H2C_FUNC_MAC_BA_CAM_V1 0x1
4222#define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4223
4224/* CLASS 14 - MCC */
4225#define H2C_CL_MCC 0xe
4226enum rtw89_mcc_h2c_func {
4227 H2C_FUNC_ADD_MCC = 0x0,
4228 H2C_FUNC_START_MCC = 0x1,
4229 H2C_FUNC_STOP_MCC = 0x2,
4230 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4231 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4232 H2C_FUNC_MCC_REQ_TSF = 0x5,
4233 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4234 H2C_FUNC_MCC_SYNC = 0x7,
4235 H2C_FUNC_MCC_SET_DURATION = 0x8,
4236
4237 NUM_OF_RTW89_MCC_H2C_FUNC,
4238};
4239
4240#define RTW89_MCC_WAIT_COND(group, func) \
4241 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4242
4243/* CLASS 24 - MRC */
4244#define H2C_CL_MRC 0x18
4245enum rtw89_mrc_h2c_func {
4246 H2C_FUNC_MRC_REQ_TSF = 0x0,
4247 H2C_FUNC_ADD_MRC = 0x1,
4248 H2C_FUNC_START_MRC = 0x2,
4249 H2C_FUNC_DEL_MRC = 0x3,
4250 H2C_FUNC_MRC_SYNC = 0x4,
4251 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4252 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4253
4254 NUM_OF_RTW89_MRC_H2C_FUNC,
4255};
4256
4257/* can consider MRC's sch_idx as MCC's group */
4258#define RTW89_MRC_WAIT_COND(sch_idx, func) \
4259 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4260
4261#define RTW89_MRC_WAIT_COND_REQ_TSF \
4262 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4263
4264#define H2C_CAT_OUTSRC 0x2
4265
4266#define H2C_CL_OUTSRC_RA 0x1
4267#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4268
4269#define H2C_CL_OUTSRC_DM 0x2
4270#define H2C_FUNC_FW_LPS_CH_INFO 0xb
4271
4272#define H2C_CL_OUTSRC_RF_REG_A 0x8
4273#define H2C_CL_OUTSRC_RF_REG_B 0x9
4274#define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4275#define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4276#define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4277
4278enum rtw89_rfk_offload_h2c_func {
4279 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4280 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4281 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4282 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4283 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4284 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4285 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4286};
4287
4288struct rtw89_fw_h2c_rf_get_mccch {
4289 __le32 ch_0;
4290 __le32 ch_1;
4291 __le32 band_0;
4292 __le32 band_1;
4293 __le32 current_channel;
4294 __le32 current_band_type;
4295} __packed;
4296
4297#define NUM_OF_RTW89_FW_RFK_PATH 2
4298#define NUM_OF_RTW89_FW_RFK_TBL 3
4299
4300struct rtw89_fw_h2c_rfk_pre_info {
4301 struct {
4302 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4303 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4304 } __packed dbcc;
4305
4306 __le32 mlo_mode;
4307 struct {
4308 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4309 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4310 } __packed tbl;
4311
4312 __le32 phy_idx;
4313 __le32 cur_band;
4314 __le32 cur_bw;
4315 __le32 cur_center_ch;
4316
4317 __le32 ktbl_sel0;
4318 __le32 ktbl_sel1;
4319 __le32 rfmod0;
4320 __le32 rfmod1;
4321
4322 __le32 mlo_1_1;
4323 __le32 rfe_type;
4324 __le32 drv_mode;
4325
4326 struct {
4327 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4328 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4329 } __packed mlo;
4330} __packed;
4331
4332struct rtw89_h2c_rf_tssi {
4333 __le16 len;
4334 u8 phy;
4335 u8 ch;
4336 u8 bw;
4337 u8 band;
4338 u8 hwtx_en;
4339 u8 cv;
4340 s8 curr_tssi_cck_de[2];
4341 s8 curr_tssi_cck_de_20m[2];
4342 s8 curr_tssi_cck_de_40m[2];
4343 s8 curr_tssi_efuse_cck_de[2];
4344 s8 curr_tssi_ofdm_de[2];
4345 s8 curr_tssi_ofdm_de_20m[2];
4346 s8 curr_tssi_ofdm_de_40m[2];
4347 s8 curr_tssi_ofdm_de_80m[2];
4348 s8 curr_tssi_ofdm_de_160m[2];
4349 s8 curr_tssi_ofdm_de_320m[2];
4350 s8 curr_tssi_efuse_ofdm_de[2];
4351 s8 curr_tssi_ofdm_de_diff_20m[2];
4352 s8 curr_tssi_ofdm_de_diff_80m[2];
4353 s8 curr_tssi_ofdm_de_diff_160m[2];
4354 s8 curr_tssi_ofdm_de_diff_320m[2];
4355 s8 curr_tssi_trim_de[2];
4356 u8 pg_thermal[2];
4357 u8 ftable[2][128];
4358 u8 tssi_mode;
4359} __packed;
4360
4361struct rtw89_h2c_rf_iqk {
4362 __le32 phy_idx;
4363 __le32 dbcc;
4364} __packed;
4365
4366struct rtw89_h2c_rf_dpk {
4367 u8 len;
4368 u8 phy;
4369 u8 dpk_enable;
4370 u8 kpath;
4371 u8 cur_band;
4372 u8 cur_bw;
4373 u8 cur_ch;
4374 u8 dpk_dbg_en;
4375} __packed;
4376
4377struct rtw89_h2c_rf_txgapk {
4378 u8 len;
4379 u8 ktype;
4380 u8 phy;
4381 u8 kpath;
4382 u8 band;
4383 u8 bw;
4384 u8 ch;
4385 u8 cv;
4386} __packed;
4387
4388struct rtw89_h2c_rf_dack {
4389 __le32 len;
4390 __le32 phy;
4391 __le32 type;
4392} __packed;
4393
4394struct rtw89_h2c_rf_rxdck {
4395 u8 len;
4396 u8 phy;
4397 u8 is_afe;
4398 u8 kpath;
4399 u8 cur_band;
4400 u8 cur_bw;
4401 u8 cur_ch;
4402 u8 rxdck_dbg_en;
4403} __packed;
4404
4405enum rtw89_rf_log_type {
4406 RTW89_RF_RUN_LOG = 0,
4407 RTW89_RF_RPT_LOG = 1,
4408};
4409
4410struct rtw89_c2h_rf_log_hdr {
4411 u8 type; /* enum rtw89_rf_log_type */
4412 __le16 len;
4413 u8 content[];
4414} __packed;
4415
4416struct rtw89_c2h_rf_run_log {
4417 __le32 fmt_idx;
4418 __le32 arg[4];
4419} __packed;
4420
4421struct rtw89_c2h_rf_dpk_rpt_log {
4422 u8 ver;
4423 u8 idx[2];
4424 u8 band[2];
4425 u8 bw[2];
4426 u8 ch[2];
4427 u8 path_ok[2];
4428 u8 txagc[2];
4429 u8 ther[2];
4430 u8 gs[2];
4431 u8 dc_i[4];
4432 u8 dc_q[4];
4433 u8 corr_val[2];
4434 u8 corr_idx[2];
4435 u8 is_timeout[2];
4436 u8 rxbb_ov[2];
4437 u8 rsvd;
4438} __packed;
4439
4440struct rtw89_c2h_rf_dack_rpt_log {
4441 u8 fwdack_ver;
4442 u8 fwdack_rpt_ver;
4443 u8 msbk_d[2][2][16];
4444 u8 dadck_d[2][2];
4445 u8 cdack_d[2][2][2];
4446 __le16 addck2_d[2][2][2];
4447 u8 adgaink_d[2][2];
4448 __le16 biask_d[2][2];
4449 u8 addck_timeout;
4450 u8 cdack_timeout;
4451 u8 dadck_timeout;
4452 u8 msbk_timeout;
4453 u8 adgaink_timeout;
4454 u8 dack_fail;
4455} __packed;
4456
4457struct rtw89_c2h_rf_rxdck_rpt_log {
4458 u8 ver;
4459 u8 band[2];
4460 u8 bw[2];
4461 u8 ch[2];
4462 u8 timeout[2];
4463} __packed;
4464
4465struct rtw89_c2h_rf_txgapk_rpt_log {
4466 __le32 r0x8010[2];
4467 __le32 chk_cnt;
4468 u8 track_d[2][17];
4469 u8 power_d[2][17];
4470 u8 is_txgapk_ok;
4471 u8 chk_id;
4472 u8 ver;
4473 u8 rsv1;
4474} __packed;
4475
4476struct rtw89_c2h_rfk_report {
4477 struct rtw89_c2h_hdr hdr;
4478 u8 state; /* enum rtw89_rfk_report_state */
4479 u8 version;
4480} __packed;
4481
4482#define RTW89_FW_RSVD_PLE_SIZE 0x800
4483
4484#define RTW89_FW_BACKTRACE_INFO_SIZE 8
4485#define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4486 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4487
4488#define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4489#define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4490
4491#define FWDL_WAIT_CNT 400000
4492
4493int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4494int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4495int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4496const struct firmware *
4497rtw89_early_fw_feature_recognize(struct device *device,
4498 const struct rtw89_chip_info *chip,
4499 struct rtw89_fw_info *early_fw,
4500 int *used_fw_format);
4501int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4502 bool include_bb);
4503void rtw89_load_firmware_work(struct work_struct *work);
4504void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4505int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4506int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4507void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4508void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4509 u8 type, u8 cat, u8 class, u8 func,
4510 bool rack, bool dack, u32 len);
4511int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4512 struct rtw89_vif *rtwvif,
4513 struct rtw89_sta *rtwsta);
4514int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4515 struct rtw89_vif *rtwvif,
4516 struct rtw89_sta *rtwsta);
4517int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4518 struct rtw89_vif *rtwvif,
4519 struct rtw89_sta *rtwsta);
4520int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4521 struct ieee80211_vif *vif,
4522 struct ieee80211_sta *sta);
4523int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4524 struct ieee80211_vif *vif,
4525 struct ieee80211_sta *sta);
4526int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4527 struct ieee80211_vif *vif,
4528 struct ieee80211_sta *sta);
4529int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4530 struct rtw89_sta *rtwsta);
4531int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4532 struct rtw89_sta *rtwsta);
4533int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4534 struct rtw89_vif *rtwvif);
4535int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4536 struct rtw89_vif *rtwvif);
4537int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
4538 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
4539int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4540 struct rtw89_vif *rtwvif,
4541 struct rtw89_sta *rtwsta);
4542int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4543 struct rtw89_vif *rtwvif,
4544 struct rtw89_sta *rtwsta);
4545void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4546void rtw89_fw_c2h_work(struct work_struct *work);
4547int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4548 struct rtw89_vif *rtwvif,
4549 struct rtw89_sta *rtwsta,
4550 enum rtw89_upd_mode upd_mode);
4551int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4552 struct rtw89_sta *rtwsta, bool dis_conn);
4553int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4554int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4555 bool pause);
4556int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4557 u8 ac, u32 val);
4558int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4559int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4560 struct ieee80211_vif *vif,
4561 bool connect);
4562int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4563 struct rtw89_rx_phy_ppdu *phy_ppdu);
4564int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4565int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4566int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4567int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4568int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4569int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4570int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4571int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4572int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4573int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4574int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4575int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4576int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4577 struct sk_buff *skb_ofld);
4578int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int ch_num,
4579 struct list_head *chan_list);
4580int rtw89_fw_h2c_scan_list_offload_be(struct rtw89_dev *rtwdev, int ch_num,
4581 struct list_head *chan_list);
4582int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
4583 struct rtw89_scan_option *opt,
4584 struct rtw89_vif *vif);
4585int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4586 struct rtw89_scan_option *opt,
4587 struct rtw89_vif *vif);
4588int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4589 struct rtw89_fw_h2c_rf_reg_info *info,
4590 u16 len, u8 page);
4591int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4592int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4593 enum rtw89_phy_idx phy_idx);
4594int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4595 enum rtw89_tssi_mode tssi_mode);
4596int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4597int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4598int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4599int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4600int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4601int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4602 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4603 bool rack, bool dack);
4604int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4605void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4606void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4607int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4608 u8 macid);
4609void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4610 struct rtw89_vif *rtwvif, bool notify_fw);
4611void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4612int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4613 bool valid, struct ieee80211_ampdu_params *params);
4614int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4615 bool valid, struct ieee80211_ampdu_params *params);
4616void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4617int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4618 u8 offset, u8 mac_idx);
4619
4620int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4621 struct rtw89_lps_parm *lps_param);
4622int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev,
4623 struct rtw89_vif *rtwvif);
4624struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4625struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4626int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4627 struct rtw89_mac_h2c_info *h2c_info,
4628 struct rtw89_mac_c2h_info *c2h_info);
4629int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4630void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4631void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4632 struct ieee80211_scan_request *req);
4633void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4634 bool aborted);
4635int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4636 bool enable);
4637void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
4638int rtw89_hw_scan_add_chan_list(struct rtw89_dev *rtwdev,
4639 struct rtw89_vif *rtwvif, bool connected);
4640int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4641 struct rtw89_vif *rtwvif, bool connected);
4642int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4643int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4644 const struct rtw89_pkt_drop_params *params);
4645int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4646 struct ieee80211_p2p_noa_desc *desc,
4647 u8 act, u8 noa_id);
4648int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4649 bool en);
4650int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4651 bool enable);
4652int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4653 struct rtw89_vif *rtwvif, bool enable);
4654int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4655 bool enable);
4656int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4657 struct rtw89_vif *rtwvif, bool enable);
4658int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4659 bool enable);
4660int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4661 struct rtw89_vif *rtwvif, bool enable);
4662int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4663 struct rtw89_wow_cam_info *cam_info);
4664int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4665 const struct rtw89_fw_mcc_add_req *p);
4666int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4667 const struct rtw89_fw_mcc_start_req *p);
4668int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4669 bool prev_groups);
4670int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4671 bool prev_groups);
4672int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4673int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4674 const struct rtw89_fw_mcc_tsf_req *req,
4675 struct rtw89_mac_mcc_tsf_rpt *rpt);
4676int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4677 u8 *bitmap);
4678int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4679 u8 target, u8 offset);
4680int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4681 const struct rtw89_fw_mcc_duration *p);
4682int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4683 const struct rtw89_fw_mrc_add_arg *arg);
4684int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4685 const struct rtw89_fw_mrc_start_arg *arg);
4686int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx);
4687int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4688 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4689 struct rtw89_mac_mrc_tsf_rpt *rpt);
4690int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4691 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4692int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4693 const struct rtw89_fw_mrc_sync_arg *arg);
4694int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4695 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4696
4697static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4698{
4699 const struct rtw89_chip_info *chip = rtwdev->chip;
4700
4701 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4702 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4703}
4704
4705static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4706 struct rtw89_vif *rtwvif,
4707 struct rtw89_sta *rtwsta)
4708{
4709 const struct rtw89_chip_info *chip = rtwdev->chip;
4710
4711 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta);
4712}
4713
4714static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4715 struct rtw89_vif *rtwvif,
4716 struct rtw89_sta *rtwsta)
4717{
4718 const struct rtw89_chip_info *chip = rtwdev->chip;
4719
4720 if (chip->ops->h2c_default_dmac_tbl)
4721 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta);
4722
4723 return 0;
4724}
4725
4726static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4727 struct rtw89_vif *rtwvif)
4728{
4729 const struct rtw89_chip_info *chip = rtwdev->chip;
4730
4731 return chip->ops->h2c_update_beacon(rtwdev, rtwvif);
4732}
4733
4734static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4735 struct ieee80211_vif *vif,
4736 struct ieee80211_sta *sta)
4737{
4738 const struct rtw89_chip_info *chip = rtwdev->chip;
4739
4740 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, vif, sta);
4741}
4742
4743static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4744 struct ieee80211_vif *vif,
4745 struct ieee80211_sta *sta)
4746{
4747 const struct rtw89_chip_info *chip = rtwdev->chip;
4748
4749 if (chip->ops->h2c_ampdu_cmac_tbl)
4750 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, vif, sta);
4751
4752 return 0;
4753}
4754
4755static inline
4756int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4757 bool valid, struct ieee80211_ampdu_params *params)
4758{
4759 const struct rtw89_chip_info *chip = rtwdev->chip;
4760
4761 return chip->ops->h2c_ba_cam(rtwdev, rtwsta, valid, params);
4762}
4763
4764/* must consider compatibility; don't insert new in the mid */
4765struct rtw89_fw_txpwr_byrate_entry {
4766 u8 band;
4767 u8 nss;
4768 u8 rs;
4769 u8 shf;
4770 u8 len;
4771 __le32 data;
4772 u8 bw;
4773 u8 ofdma;
4774} __packed;
4775
4776/* must consider compatibility; don't insert new in the mid */
4777struct rtw89_fw_txpwr_lmt_2ghz_entry {
4778 u8 bw;
4779 u8 nt;
4780 u8 rs;
4781 u8 bf;
4782 u8 regd;
4783 u8 ch_idx;
4784 s8 v;
4785} __packed;
4786
4787/* must consider compatibility; don't insert new in the mid */
4788struct rtw89_fw_txpwr_lmt_5ghz_entry {
4789 u8 bw;
4790 u8 nt;
4791 u8 rs;
4792 u8 bf;
4793 u8 regd;
4794 u8 ch_idx;
4795 s8 v;
4796} __packed;
4797
4798/* must consider compatibility; don't insert new in the mid */
4799struct rtw89_fw_txpwr_lmt_6ghz_entry {
4800 u8 bw;
4801 u8 nt;
4802 u8 rs;
4803 u8 bf;
4804 u8 regd;
4805 u8 reg_6ghz_power;
4806 u8 ch_idx;
4807 s8 v;
4808} __packed;
4809
4810/* must consider compatibility; don't insert new in the mid */
4811struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4812 u8 ru;
4813 u8 nt;
4814 u8 regd;
4815 u8 ch_idx;
4816 s8 v;
4817} __packed;
4818
4819/* must consider compatibility; don't insert new in the mid */
4820struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4821 u8 ru;
4822 u8 nt;
4823 u8 regd;
4824 u8 ch_idx;
4825 s8 v;
4826} __packed;
4827
4828/* must consider compatibility; don't insert new in the mid */
4829struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4830 u8 ru;
4831 u8 nt;
4832 u8 regd;
4833 u8 reg_6ghz_power;
4834 u8 ch_idx;
4835 s8 v;
4836} __packed;
4837
4838/* must consider compatibility; don't insert new in the mid */
4839struct rtw89_fw_tx_shape_lmt_entry {
4840 u8 band;
4841 u8 tx_shape_rs;
4842 u8 regd;
4843 u8 v;
4844} __packed;
4845
4846/* must consider compatibility; don't insert new in the mid */
4847struct rtw89_fw_tx_shape_lmt_ru_entry {
4848 u8 band;
4849 u8 regd;
4850 u8 v;
4851} __packed;
4852
4853const struct rtw89_rfe_parms *
4854rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4855 const struct rtw89_rfe_parms *init);
4856
4857#endif
4858

source code of linux/drivers/net/wireless/realtek/rtw89/fw.h