1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_PCI_H__
6#define __RTW89_PCI_H__
7
8#include "txrx.h"
9
10#define MDIO_PG0_G1 0
11#define MDIO_PG1_G1 1
12#define MDIO_PG0_G2 2
13#define MDIO_PG1_G2 3
14#define RAC_CTRL_PPR 0x00
15#define RAC_ANA0A 0x0A
16#define B_BAC_EQ_SEL BIT(5)
17#define RAC_ANA0C 0x0C
18#define B_PCIE_BIT_PSAVE BIT(15)
19#define RAC_ANA10 0x10
20#define B_PCIE_BIT_PINOUT_DIS BIT(3)
21#define RAC_REG_REV2 0x1B
22#define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)
23#define PCIE_DPHY_DLY_25US 0x1
24#define RAC_ANA19 0x19
25#define B_PCIE_BIT_RD_SEL BIT(2)
26#define RAC_REG_FLD_0 0x1D
27#define BAC_AUTOK_N_MASK GENMASK(3, 2)
28#define PCIE_AUTOK_4 0x3
29#define RAC_ANA1F 0x1F
30#define RAC_ANA24 0x24
31#define B_AX_DEGLITCH GENMASK(11, 8)
32#define RAC_ANA26 0x26
33#define B_AX_RXEN GENMASK(15, 14)
34#define RAC_CTRL_PPR_V1 0x30
35#define B_AX_CLK_CALIB_EN BIT(12)
36#define B_AX_CALIB_EN BIT(13)
37#define B_AX_DIV GENMASK(15, 14)
38#define RAC_SET_PPR_V1 0x31
39
40#define R_AX_DBI_FLAG 0x1090
41#define B_AX_DBI_RFLAG BIT(17)
42#define B_AX_DBI_WFLAG BIT(16)
43#define B_AX_DBI_WREN_MSK GENMASK(15, 12)
44#define B_AX_DBI_ADDR_MSK GENMASK(11, 2)
45#define B_AX_DBI_2LSB GENMASK(1, 0)
46#define R_AX_DBI_WDATA 0x1094
47#define R_AX_DBI_RDATA 0x1098
48
49#define R_AX_MDIO_WDATA 0x10A4
50#define R_AX_MDIO_RDATA 0x10A6
51
52#define R_AX_PCIE_PS_CTRL_V1 0x3008
53#define B_AX_CMAC_EXIT_L1_EN BIT(7)
54#define B_AX_DMAC0_EXIT_L1_EN BIT(6)
55#define B_AX_SEL_XFER_PENDING BIT(3)
56#define B_AX_SEL_REQ_ENTR_L1 BIT(2)
57#define B_AX_SEL_REQ_EXIT_L1 BIT(0)
58
59#define R_AX_PCIE_MIX_CFG_V1 0x300C
60#define B_AX_ASPM_CTRL_L1 BIT(17)
61#define B_AX_ASPM_CTRL_L0 BIT(16)
62#define B_AX_ASPM_CTRL_MASK GENMASK(17, 16)
63#define B_AX_XFER_PENDING_FW BIT(11)
64#define B_AX_XFER_PENDING BIT(10)
65#define B_AX_REQ_EXIT_L1 BIT(9)
66#define B_AX_REQ_ENTR_L1 BIT(8)
67#define B_AX_L1SUB_DISABLE BIT(0)
68
69#define R_AX_L1_CLK_CTRL 0x3010
70#define B_AX_CLK_REQ_N BIT(1)
71
72#define R_AX_PCIE_BG_CLR 0x303C
73#define B_AX_BG_CLR_ASYNC_M3 BIT(4)
74
75#define R_AX_PCIE_LAT_CTRL 0x3044
76#define B_AX_CLK_REQ_SEL_OPT BIT(1)
77#define B_AX_CLK_REQ_SEL BIT(0)
78
79#define R_AX_PCIE_IO_RCY_M1 0x3100
80#define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
81#define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
82#define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
83#define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
84
85#define R_AX_PCIE_WDT_TIMER_M1 0x3104
86#define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
87
88#define R_AX_PCIE_IO_RCY_M2 0x310C
89#define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
90#define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
91#define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
92#define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
93
94#define R_AX_PCIE_WDT_TIMER_M2 0x3110
95#define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
96
97#define R_AX_PCIE_IO_RCY_E0 0x3118
98#define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
99#define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
100#define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
101#define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
102
103#define R_AX_PCIE_WDT_TIMER_E0 0x311C
104#define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
105
106#define R_AX_PCIE_IO_RCY_S1 0x3124
107#define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
108#define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
109#define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
110#define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
111#define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
112#define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
113#define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
114
115#define R_AX_PCIE_WDT_TIMER_S1 0x3128
116#define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
117
118#define R_RAC_DIRECT_OFFSET_G1 0x3800
119#define FILTER_OUT_EQ_MASK GENMASK(14, 10)
120#define R_RAC_DIRECT_OFFSET_G2 0x3880
121#define REG_FILTER_OUT_MASK GENMASK(6, 2)
122#define RAC_MULT 2
123
124#define RTW89_PCI_WR_RETRY_CNT 20
125
126/* Interrupts */
127#define R_AX_HIMR0 0x01A0
128#define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
129#define B_AX_HALT_C2H_INT_EN BIT(21)
130#define R_AX_HISR0 0x01A4
131
132#define R_AX_HIMR1 0x01A8
133#define B_AX_GPIO18_INT_EN BIT(2)
134#define B_AX_GPIO17_INT_EN BIT(1)
135#define B_AX_GPIO16_INT_EN BIT(0)
136
137#define R_AX_HISR1 0x01AC
138#define B_AX_GPIO18_INT BIT(2)
139#define B_AX_GPIO17_INT BIT(1)
140#define B_AX_GPIO16_INT BIT(0)
141
142#define R_AX_MDIO_CFG 0x10A0
143#define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12)
144#define B_AX_MDIO_RFLAG BIT(9)
145#define B_AX_MDIO_WFLAG BIT(8)
146#define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)
147
148#define R_AX_PCIE_HIMR00 0x10B0
149#define R_AX_HAXI_HIMR00 0x10B0
150#define B_AX_HC00ISR_IND_INT_EN BIT(27)
151#define B_AX_HD1ISR_IND_INT_EN BIT(26)
152#define B_AX_HD0ISR_IND_INT_EN BIT(25)
153#define B_AX_HS0ISR_IND_INT_EN BIT(24)
154#define B_AX_HS0ISR_IND_INT_EN_WKARND BIT(23)
155#define B_AX_RETRAIN_INT_EN BIT(21)
156#define B_AX_RPQBD_FULL_INT_EN BIT(20)
157#define B_AX_RDU_INT_EN BIT(19)
158#define B_AX_RXDMA_STUCK_INT_EN BIT(18)
159#define B_AX_TXDMA_STUCK_INT_EN BIT(17)
160#define B_AX_PCIE_HOTRST_INT_EN BIT(16)
161#define B_AX_PCIE_FLR_INT_EN BIT(15)
162#define B_AX_PCIE_PERST_INT_EN BIT(14)
163#define B_AX_TXDMA_CH12_INT_EN BIT(13)
164#define B_AX_TXDMA_CH9_INT_EN BIT(12)
165#define B_AX_TXDMA_CH8_INT_EN BIT(11)
166#define B_AX_TXDMA_ACH7_INT_EN BIT(10)
167#define B_AX_TXDMA_ACH6_INT_EN BIT(9)
168#define B_AX_TXDMA_ACH5_INT_EN BIT(8)
169#define B_AX_TXDMA_ACH4_INT_EN BIT(7)
170#define B_AX_TXDMA_ACH3_INT_EN BIT(6)
171#define B_AX_TXDMA_ACH2_INT_EN BIT(5)
172#define B_AX_TXDMA_ACH1_INT_EN BIT(4)
173#define B_AX_TXDMA_ACH0_INT_EN BIT(3)
174#define B_AX_RPQDMA_INT_EN BIT(2)
175#define B_AX_RXP1DMA_INT_EN BIT(1)
176#define B_AX_RXDMA_INT_EN BIT(0)
177
178#define R_AX_PCIE_HISR00 0x10B4
179#define R_AX_HAXI_HISR00 0x10B4
180#define B_AX_HC00ISR_IND_INT BIT(27)
181#define B_AX_HD1ISR_IND_INT BIT(26)
182#define B_AX_HD0ISR_IND_INT BIT(25)
183#define B_AX_HS0ISR_IND_INT BIT(24)
184#define B_AX_RETRAIN_INT BIT(21)
185#define B_AX_RPQBD_FULL_INT BIT(20)
186#define B_AX_RDU_INT BIT(19)
187#define B_AX_RXDMA_STUCK_INT BIT(18)
188#define B_AX_TXDMA_STUCK_INT BIT(17)
189#define B_AX_PCIE_HOTRST_INT BIT(16)
190#define B_AX_PCIE_FLR_INT BIT(15)
191#define B_AX_PCIE_PERST_INT BIT(14)
192#define B_AX_TXDMA_CH12_INT BIT(13)
193#define B_AX_TXDMA_CH9_INT BIT(12)
194#define B_AX_TXDMA_CH8_INT BIT(11)
195#define B_AX_TXDMA_ACH7_INT BIT(10)
196#define B_AX_TXDMA_ACH6_INT BIT(9)
197#define B_AX_TXDMA_ACH5_INT BIT(8)
198#define B_AX_TXDMA_ACH4_INT BIT(7)
199#define B_AX_TXDMA_ACH3_INT BIT(6)
200#define B_AX_TXDMA_ACH2_INT BIT(5)
201#define B_AX_TXDMA_ACH1_INT BIT(4)
202#define B_AX_TXDMA_ACH0_INT BIT(3)
203#define B_AX_RPQDMA_INT BIT(2)
204#define B_AX_RXP1DMA_INT BIT(1)
205#define B_AX_RXDMA_INT BIT(0)
206
207#define R_AX_HAXI_IDCT_MSK 0x10B8
208#define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
209#define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
210#define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
211#define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
212
213#define R_AX_HAXI_IDCT 0x10BC
214#define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
215#define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
216#define B_AX_RXMDA_STUCK_IDCT BIT(1)
217#define B_AX_TXMDA_STUCK_IDCT BIT(0)
218
219#define R_AX_HAXI_HIMR10 0x11E0
220#define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
221#define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
222
223#define R_AX_PCIE_HIMR10 0x13B0
224#define B_AX_HC10ISR_IND_INT_EN BIT(28)
225#define B_AX_TXDMA_CH11_INT_EN BIT(12)
226#define B_AX_TXDMA_CH10_INT_EN BIT(11)
227
228#define R_AX_PCIE_HISR10 0x13B4
229#define B_AX_HC10ISR_IND_INT BIT(28)
230#define B_AX_TXDMA_CH11_INT BIT(12)
231#define B_AX_TXDMA_CH10_INT BIT(11)
232
233#define R_AX_PCIE_HIMR00_V1 0x30B0
234#define B_AX_HCI_AXIDMA_INT_EN BIT(29)
235#define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28)
236#define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27)
237#define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26)
238#define B_AX_HS1ISR_IND_INT_EN BIT(25)
239#define B_AX_PCIE_DBG_STE_INT_EN BIT(13)
240
241#define R_AX_PCIE_HISR00_V1 0x30B4
242#define B_AX_HCI_AXIDMA_INT BIT(29)
243#define B_AX_HC00ISR_IND_INT_V1 BIT(28)
244#define B_AX_HD1ISR_IND_INT_V1 BIT(27)
245#define B_AX_HD0ISR_IND_INT_V1 BIT(26)
246#define B_AX_HS1ISR_IND_INT BIT(25)
247#define B_AX_PCIE_DBG_STE_INT BIT(13)
248
249#define R_BE_PCIE_FRZ_CLK 0x3004
250#define B_BE_PCIE_FRZ_MAC_HW_RST BIT(31)
251#define B_BE_PCIE_FRZ_CFG_SPC_RST BIT(30)
252#define B_BE_PCIE_FRZ_ELBI_RST BIT(29)
253#define B_BE_PCIE_MAC_IS_ACTIVE BIT(28)
254#define B_BE_PCIE_FRZ_RTK_HW_RST BIT(27)
255#define B_BE_PCIE_FRZ_REG_RST BIT(26)
256#define B_BE_PCIE_FRZ_ANA_RST BIT(25)
257#define B_BE_PCIE_FRZ_WLAN_RST BIT(24)
258#define B_BE_PCIE_FRZ_FLR_RST BIT(23)
259#define B_BE_PCIE_FRZ_RET_NON_STKY_RST BIT(22)
260#define B_BE_PCIE_FRZ_RET_STKY_RST BIT(21)
261#define B_BE_PCIE_FRZ_NON_STKY_RST BIT(20)
262#define B_BE_PCIE_FRZ_STKY_RST BIT(19)
263#define B_BE_PCIE_FRZ_RET_CORE_RST BIT(18)
264#define B_BE_PCIE_FRZ_PWR_RST BIT(17)
265#define B_BE_PCIE_FRZ_PERST_RST BIT(16)
266#define B_BE_PCIE_FRZ_PHY_ALOAD BIT(15)
267#define B_BE_PCIE_FRZ_PHY_HW_RST BIT(14)
268#define B_BE_PCIE_DBG_CLK BIT(4)
269#define B_BE_PCIE_EN_CLK BIT(3)
270#define B_BE_PCIE_DBI_ACLK_ACT BIT(2)
271#define B_BE_PCIE_S1_ACLK_ACT BIT(1)
272#define B_BE_PCIE_EN_AUX_CLK BIT(0)
273
274#define R_BE_PCIE_PS_CTRL 0x3008
275#define B_BE_RSM_L0S_EN BIT(8)
276#define B_BE_CMAC_EXIT_L1_EN BIT(7)
277#define B_BE_DMAC0_EXIT_L1_EN BIT(6)
278#define B_BE_FORCE_L0 BIT(5)
279#define B_BE_DBI_RO_WR_DISABLE BIT(4)
280#define B_BE_SEL_XFER_PENDING BIT(3)
281#define B_BE_SEL_REQ_ENTR_L1 BIT(2)
282#define B_BE_PCIE_EN_SWENT_L23 BIT(1)
283#define B_BE_SEL_REQ_EXIT_L1 BIT(0)
284
285#define R_BE_PCIE_MIX_CFG 0x300C
286#define B_BE_L1SS_TIMEOUT_CTRL BIT(18)
287#define B_BE_ASPM_CTRL_L1 BIT(17)
288#define B_BE_ASPM_CTRL_L0 BIT(16)
289#define B_BE_XFER_PENDING_FW BIT(11)
290#define B_BE_XFER_PENDING BIT(10)
291#define B_BE_REQ_EXIT_L1 BIT(9)
292#define B_BE_REQ_ENTR_L1 BIT(8)
293#define B_BE_L1SUB_ENABLE BIT(0)
294
295#define R_BE_L1_CLK_CTRL 0x3010
296#define B_BE_RAS_SD_HOLD_LTSSM BIT(12)
297#define B_BE_CLK_REQ_N BIT(1)
298#define B_BE_CLK_PM_EN BIT(0)
299
300#define R_BE_PCIE_LAT_CTRL 0x3044
301#define B_BE_ELBI_PHY_REMAP_MASK GENMASK(29, 24)
302#define B_BE_SYS_SUS_L12_EN BIT(17)
303#define B_BE_MDIO_S_EN BIT(16)
304#define B_BE_SYM_AUX_CLK_SEL BIT(15)
305#define B_BE_RTK_LDO_POWER_LATENCY_MASK GENMASK(11, 10)
306#define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8)
307#define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4)
308#define B_BE_RTK_PM_SEL_OPT BIT(1)
309#define B_BE_CLK_REQ_SEL BIT(0)
310
311#define R_BE_PCIE_HIMR0 0x30B0
312#define B_BE_PCIE_HB1_IND_INTA_IMR BIT(31)
313#define B_BE_PCIE_HB0_IND_INTA_IMR BIT(30)
314#define B_BE_HCI_AXIDMA_INTA_IMR BIT(29)
315#define B_BE_HC0_IND_INTA_IMR BIT(28)
316#define B_BE_HD1_IND_INTA_IMR BIT(27)
317#define B_BE_HD0_IND_INTA_IMR BIT(26)
318#define B_BE_HS1_IND_INTA_IMR BIT(25)
319#define B_BE_HS0_IND_INTA_IMR BIT(24)
320#define B_BE_PCIE_HOTRST_INT_EN BIT(16)
321#define B_BE_PCIE_FLR_INT_EN BIT(15)
322#define B_BE_PCIE_PERST_INT_EN BIT(14)
323#define B_BE_PCIE_DBG_STE_INT_EN BIT(13)
324#define B_BE_HB1_IND_INT_EN0 BIT(9)
325#define B_BE_HB0_IND_INT_EN0 BIT(8)
326#define B_BE_HC1_IND_INT_EN0 BIT(7)
327#define B_BE_HCI_AXIDMA_INT_EN0 BIT(5)
328#define B_BE_HC0_IND_INT_EN0 BIT(4)
329#define B_BE_HD1_IND_INT_EN0 BIT(3)
330#define B_BE_HD0_IND_INT_EN0 BIT(2)
331#define B_BE_HS1_IND_INT_EN0 BIT(1)
332#define B_BE_HS0_IND_INT_EN0 BIT(0)
333
334#define R_BE_PCIE_HISR 0x30B4
335#define B_BE_PCIE_HOTRST_INT BIT(16)
336#define B_BE_PCIE_FLR_INT BIT(15)
337#define B_BE_PCIE_PERST_INT BIT(14)
338#define B_BE_PCIE_DBG_STE_INT BIT(13)
339#define B_BE_HB1IMR_IND BIT(9)
340#define B_BE_HB0IMR_IND BIT(8)
341#define B_BE_HC1ISR_IND_INT BIT(7)
342#define B_BE_HCI_AXIDMA_INT BIT(5)
343#define B_BE_HC0ISR_IND_INT BIT(4)
344#define B_BE_HD1ISR_IND_INT BIT(3)
345#define B_BE_HD0ISR_IND_INT BIT(2)
346#define B_BE_HS1ISR_IND_INT BIT(1)
347#define B_BE_HS0ISR_IND_INT BIT(0)
348
349#define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
350#define B_BE_PCIE_RX_RX1P1_IMR0_V1 BIT(23)
351#define B_BE_PCIE_RX_RX0P1_IMR0_V1 BIT(22)
352#define B_BE_PCIE_RX_ROQ1_IMR0_V1 BIT(21)
353#define B_BE_PCIE_RX_RPQ1_IMR0_V1 BIT(20)
354#define B_BE_PCIE_RX_RX1P2_IMR0_V1 BIT(19)
355#define B_BE_PCIE_RX_ROQ0_IMR0_V1 BIT(18)
356#define B_BE_PCIE_RX_RPQ0_IMR0_V1 BIT(17)
357#define B_BE_PCIE_RX_RX0P2_IMR0_V1 BIT(16)
358#define B_BE_PCIE_TX_CH14_IMR0 BIT(14)
359#define B_BE_PCIE_TX_CH13_IMR0 BIT(13)
360#define B_BE_PCIE_TX_CH12_IMR0 BIT(12)
361#define B_BE_PCIE_TX_CH11_IMR0 BIT(11)
362#define B_BE_PCIE_TX_CH10_IMR0 BIT(10)
363#define B_BE_PCIE_TX_CH9_IMR0 BIT(9)
364#define B_BE_PCIE_TX_CH8_IMR0 BIT(8)
365#define B_BE_PCIE_TX_CH7_IMR0 BIT(7)
366#define B_BE_PCIE_TX_CH6_IMR0 BIT(6)
367#define B_BE_PCIE_TX_CH5_IMR0 BIT(5)
368#define B_BE_PCIE_TX_CH4_IMR0 BIT(4)
369#define B_BE_PCIE_TX_CH3_IMR0 BIT(3)
370#define B_BE_PCIE_TX_CH2_IMR0 BIT(2)
371#define B_BE_PCIE_TX_CH1_IMR0 BIT(1)
372#define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
373
374#define R_BE_PCIE_DMA_ISR 0x30BC
375#define B_BE_PCIE_RX_RX1P1_ISR_V1 BIT(23)
376#define B_BE_PCIE_RX_RX0P1_ISR_V1 BIT(22)
377#define B_BE_PCIE_RX_ROQ1_ISR_V1 BIT(21)
378#define B_BE_PCIE_RX_RPQ1_ISR_V1 BIT(20)
379#define B_BE_PCIE_RX_RX1P2_ISR_V1 BIT(19)
380#define B_BE_PCIE_RX_ROQ0_ISR_V1 BIT(18)
381#define B_BE_PCIE_RX_RPQ0_ISR_V1 BIT(17)
382#define B_BE_PCIE_RX_RX0P2_ISR_V1 BIT(16)
383#define B_BE_PCIE_TX_CH14_ISR BIT(14)
384#define B_BE_PCIE_TX_CH13_ISR BIT(13)
385#define B_BE_PCIE_TX_CH12_ISR BIT(12)
386#define B_BE_PCIE_TX_CH11_ISR BIT(11)
387#define B_BE_PCIE_TX_CH10_ISR BIT(10)
388#define B_BE_PCIE_TX_CH9_ISR BIT(9)
389#define B_BE_PCIE_TX_CH8_ISR BIT(8)
390#define B_BE_PCIE_TX_CH7_ISR BIT(7)
391#define B_BE_PCIE_TX_CH6_ISR BIT(6)
392#define B_BE_PCIE_TX_CH5_ISR BIT(5)
393#define B_BE_PCIE_TX_CH4_ISR BIT(4)
394#define B_BE_PCIE_TX_CH3_ISR BIT(3)
395#define B_BE_PCIE_TX_CH2_ISR BIT(2)
396#define B_BE_PCIE_TX_CH1_ISR BIT(1)
397#define B_BE_PCIE_TX_CH0_ISR BIT(0)
398
399#define R_BE_HAXI_HIMR00 0xB0B0
400#define B_BE_RDU_CH5_INT_IMR_V1 BIT(30)
401#define B_BE_RDU_CH4_INT_IMR_V1 BIT(29)
402#define B_BE_RDU_CH3_INT_IMR_V1 BIT(28)
403#define B_BE_RDU_CH2_INT_IMR_V1 BIT(27)
404#define B_BE_RDU_CH1_INT_IMR_V1 BIT(26)
405#define B_BE_RDU_CH0_INT_IMR_V1 BIT(25)
406#define B_BE_RXDMA_STUCK_INT_EN_V1 BIT(24)
407#define B_BE_TXDMA_STUCK_INT_EN_V1 BIT(23)
408#define B_BE_TXDMA_CH14_INT_EN_V1 BIT(22)
409#define B_BE_TXDMA_CH13_INT_EN_V1 BIT(21)
410#define B_BE_TXDMA_CH12_INT_EN_V1 BIT(20)
411#define B_BE_TXDMA_CH11_INT_EN_V1 BIT(19)
412#define B_BE_TXDMA_CH10_INT_EN_V1 BIT(18)
413#define B_BE_TXDMA_CH9_INT_EN_V1 BIT(17)
414#define B_BE_TXDMA_CH8_INT_EN_V1 BIT(16)
415#define B_BE_TXDMA_CH7_INT_EN_V1 BIT(15)
416#define B_BE_TXDMA_CH6_INT_EN_V1 BIT(14)
417#define B_BE_TXDMA_CH5_INT_EN_V1 BIT(13)
418#define B_BE_TXDMA_CH4_INT_EN_V1 BIT(12)
419#define B_BE_TXDMA_CH3_INT_EN_V1 BIT(11)
420#define B_BE_TXDMA_CH2_INT_EN_V1 BIT(10)
421#define B_BE_TXDMA_CH1_INT_EN_V1 BIT(9)
422#define B_BE_TXDMA_CH0_INT_EN_V1 BIT(8)
423#define B_BE_RX1P1DMA_INT_EN_V1 BIT(7)
424#define B_BE_RX0P1DMA_INT_EN_V1 BIT(6)
425#define B_BE_RO1DMA_INT_EN BIT(5)
426#define B_BE_RP1DMA_INT_EN BIT(4)
427#define B_BE_RX1DMA_INT_EN BIT(3)
428#define B_BE_RO0DMA_INT_EN BIT(2)
429#define B_BE_RP0DMA_INT_EN BIT(1)
430#define B_BE_RX0DMA_INT_EN BIT(0)
431
432#define R_BE_HAXI_HISR00 0xB0B4
433#define B_BE_RDU_CH6_INT BIT(28)
434#define B_BE_RDU_CH5_INT BIT(27)
435#define B_BE_RDU_CH4_INT BIT(26)
436#define B_BE_RDU_CH2_INT BIT(25)
437#define B_BE_RDU_CH1_INT BIT(24)
438#define B_BE_RDU_CH0_INT BIT(23)
439#define B_BE_RXDMA_STUCK_INT BIT(22)
440#define B_BE_TXDMA_STUCK_INT BIT(21)
441#define B_BE_TXDMA_CH14_INT BIT(20)
442#define B_BE_TXDMA_CH13_INT BIT(19)
443#define B_BE_TXDMA_CH12_INT BIT(18)
444#define B_BE_TXDMA_CH11_INT BIT(17)
445#define B_BE_TXDMA_CH10_INT BIT(16)
446#define B_BE_TXDMA_CH9_INT BIT(15)
447#define B_BE_TXDMA_CH8_INT BIT(14)
448#define B_BE_TXDMA_CH7_INT BIT(13)
449#define B_BE_TXDMA_CH6_INT BIT(12)
450#define B_BE_TXDMA_CH5_INT BIT(11)
451#define B_BE_TXDMA_CH4_INT BIT(10)
452#define B_BE_TXDMA_CH3_INT BIT(9)
453#define B_BE_TXDMA_CH2_INT BIT(8)
454#define B_BE_TXDMA_CH1_INT BIT(7)
455#define B_BE_TXDMA_CH0_INT BIT(6)
456#define B_BE_RPQ1DMA_INT BIT(5)
457#define B_BE_RX1P1DMA_INT BIT(4)
458#define B_BE_RX1DMA_INT BIT(3)
459#define B_BE_RPQ0DMA_INT BIT(2)
460#define B_BE_RX0P1DMA_INT BIT(1)
461#define B_BE_RX0DMA_INT BIT(0)
462
463/* TX/RX */
464#define R_AX_DRV_FW_HSK_0 0x01B0
465#define R_AX_DRV_FW_HSK_1 0x01B4
466#define R_AX_DRV_FW_HSK_2 0x01B8
467#define R_AX_DRV_FW_HSK_3 0x01BC
468#define R_AX_DRV_FW_HSK_4 0x01C0
469#define R_AX_DRV_FW_HSK_5 0x01C4
470#define R_AX_DRV_FW_HSK_6 0x01C8
471#define R_AX_DRV_FW_HSK_7 0x01CC
472
473#define R_AX_RXQ_RXBD_IDX 0x1050
474#define R_AX_RPQ_RXBD_IDX 0x1054
475#define R_AX_ACH0_TXBD_IDX 0x1058
476#define R_AX_ACH1_TXBD_IDX 0x105C
477#define R_AX_ACH2_TXBD_IDX 0x1060
478#define R_AX_ACH3_TXBD_IDX 0x1064
479#define R_AX_ACH4_TXBD_IDX 0x1068
480#define R_AX_ACH5_TXBD_IDX 0x106C
481#define R_AX_ACH6_TXBD_IDX 0x1070
482#define R_AX_ACH7_TXBD_IDX 0x1074
483#define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */
484#define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
485#define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
486#define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
487#define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */
488#define R_AX_CH10_TXBD_IDX_V1 0x11D0
489#define R_AX_CH11_TXBD_IDX_V1 0x11D4
490#define R_AX_RXQ_RXBD_IDX_V1 0x1218
491#define R_AX_RPQ_RXBD_IDX_V1 0x121C
492#define TXBD_HW_IDX_MASK GENMASK(27, 16)
493#define TXBD_HOST_IDX_MASK GENMASK(11, 0)
494
495#define R_AX_ACH0_TXBD_DESA_L 0x1110
496#define R_AX_ACH0_TXBD_DESA_H 0x1114
497#define R_AX_ACH1_TXBD_DESA_L 0x1118
498#define R_AX_ACH1_TXBD_DESA_H 0x111C
499#define R_AX_ACH2_TXBD_DESA_L 0x1120
500#define R_AX_ACH2_TXBD_DESA_H 0x1124
501#define R_AX_ACH3_TXBD_DESA_L 0x1128
502#define R_AX_ACH3_TXBD_DESA_H 0x112C
503#define R_AX_ACH4_TXBD_DESA_L 0x1130
504#define R_AX_ACH4_TXBD_DESA_H 0x1134
505#define R_AX_ACH5_TXBD_DESA_L 0x1138
506#define R_AX_ACH5_TXBD_DESA_H 0x113C
507#define R_AX_ACH6_TXBD_DESA_L 0x1140
508#define R_AX_ACH6_TXBD_DESA_H 0x1144
509#define R_AX_ACH7_TXBD_DESA_L 0x1148
510#define R_AX_ACH7_TXBD_DESA_H 0x114C
511#define R_AX_CH8_TXBD_DESA_L 0x1150
512#define R_AX_CH8_TXBD_DESA_H 0x1154
513#define R_AX_CH9_TXBD_DESA_L 0x1158
514#define R_AX_CH9_TXBD_DESA_H 0x115C
515#define R_AX_CH10_TXBD_DESA_L 0x1358
516#define R_AX_CH10_TXBD_DESA_H 0x135C
517#define R_AX_CH11_TXBD_DESA_L 0x1360
518#define R_AX_CH11_TXBD_DESA_H 0x1364
519#define R_AX_CH12_TXBD_DESA_L 0x1160
520#define R_AX_CH12_TXBD_DESA_H 0x1164
521#define R_AX_RXQ_RXBD_DESA_L 0x1100
522#define R_AX_RXQ_RXBD_DESA_H 0x1104
523#define R_AX_RPQ_RXBD_DESA_L 0x1108
524#define R_AX_RPQ_RXBD_DESA_H 0x110C
525#define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
526#define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
527#define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
528#define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
529#define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
530#define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
531#define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
532#define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
533#define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
534#define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
535#define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
536#define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
537#define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
538#define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
539#define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
540#define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
541#define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
542#define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
543#define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
544#define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
545#define R_AX_CH8_TXBD_DESA_L_V1 0x1270
546#define R_AX_CH8_TXBD_DESA_H_V1 0x1274
547#define R_AX_CH9_TXBD_DESA_L_V1 0x1278
548#define R_AX_CH9_TXBD_DESA_H_V1 0x127C
549#define R_AX_CH12_TXBD_DESA_L_V1 0x1280
550#define R_AX_CH12_TXBD_DESA_H_V1 0x1284
551#define R_AX_CH10_TXBD_DESA_L_V1 0x1458
552#define R_AX_CH10_TXBD_DESA_H_V1 0x145C
553#define R_AX_CH11_TXBD_DESA_L_V1 0x1460
554#define R_AX_CH11_TXBD_DESA_H_V1 0x1464
555#define B_AX_DESC_NUM_MSK GENMASK(11, 0)
556
557#define R_AX_RXQ_RXBD_NUM 0x1020
558#define R_AX_RPQ_RXBD_NUM 0x1022
559#define R_AX_ACH0_TXBD_NUM 0x1024
560#define R_AX_ACH1_TXBD_NUM 0x1026
561#define R_AX_ACH2_TXBD_NUM 0x1028
562#define R_AX_ACH3_TXBD_NUM 0x102A
563#define R_AX_ACH4_TXBD_NUM 0x102C
564#define R_AX_ACH5_TXBD_NUM 0x102E
565#define R_AX_ACH6_TXBD_NUM 0x1030
566#define R_AX_ACH7_TXBD_NUM 0x1032
567#define R_AX_CH8_TXBD_NUM 0x1034
568#define R_AX_CH9_TXBD_NUM 0x1036
569#define R_AX_CH10_TXBD_NUM 0x1338
570#define R_AX_CH11_TXBD_NUM 0x133A
571#define R_AX_CH12_TXBD_NUM 0x1038
572#define R_AX_RXQ_RXBD_NUM_V1 0x1210
573#define R_AX_RPQ_RXBD_NUM_V1 0x1212
574#define R_AX_CH10_TXBD_NUM_V1 0x1438
575#define R_AX_CH11_TXBD_NUM_V1 0x143A
576
577#define R_AX_ACH0_BDRAM_CTRL 0x1200
578#define R_AX_ACH1_BDRAM_CTRL 0x1204
579#define R_AX_ACH2_BDRAM_CTRL 0x1208
580#define R_AX_ACH3_BDRAM_CTRL 0x120C
581#define R_AX_ACH4_BDRAM_CTRL 0x1210
582#define R_AX_ACH5_BDRAM_CTRL 0x1214
583#define R_AX_ACH6_BDRAM_CTRL 0x1218
584#define R_AX_ACH7_BDRAM_CTRL 0x121C
585#define R_AX_CH8_BDRAM_CTRL 0x1220
586#define R_AX_CH9_BDRAM_CTRL 0x1224
587#define R_AX_CH10_BDRAM_CTRL 0x1320
588#define R_AX_CH11_BDRAM_CTRL 0x1324
589#define R_AX_CH12_BDRAM_CTRL 0x1228
590#define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
591#define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
592#define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
593#define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
594#define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
595#define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
596#define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
597#define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
598#define R_AX_CH8_BDRAM_CTRL_V1 0x1320
599#define R_AX_CH9_BDRAM_CTRL_V1 0x1324
600#define R_AX_CH12_BDRAM_CTRL_V1 0x1328
601#define R_AX_CH10_BDRAM_CTRL_V1 0x1420
602#define R_AX_CH11_BDRAM_CTRL_V1 0x1424
603#define BDRAM_SIDX_MASK GENMASK(7, 0)
604#define BDRAM_MAX_MASK GENMASK(15, 8)
605#define BDRAM_MIN_MASK GENMASK(23, 16)
606
607#define R_AX_PCIE_INIT_CFG1 0x1000
608#define B_AX_PCIE_RXRST_KEEP_REG BIT(23)
609#define B_AX_PCIE_TXRST_KEEP_REG BIT(22)
610#define B_AX_PCIE_PERST_KEEP_REG BIT(21)
611#define B_AX_PCIE_FLR_KEEP_REG BIT(20)
612#define B_AX_PCIE_TRAIN_KEEP_REG BIT(19)
613#define B_AX_RXBD_MODE BIT(18)
614#define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14)
615#define B_AX_RXHCI_EN BIT(13)
616#define B_AX_LATENCY_CONTROL BIT(12)
617#define B_AX_TXHCI_EN BIT(11)
618#define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8)
619#define B_AX_TX_TRUNC_MODE BIT(5)
620#define B_AX_RX_TRUNC_MODE BIT(4)
621#define B_AX_RST_BDRAM BIT(3)
622#define B_AX_DIS_RXDMA_PRE BIT(2)
623
624#define R_AX_TXDMA_ADDR_H 0x10F0
625#define R_AX_RXDMA_ADDR_H 0x10F4
626
627#define R_AX_PCIE_DMA_STOP1 0x1010
628#define B_AX_STOP_PCIEIO BIT(20)
629#define B_AX_STOP_WPDMA BIT(19)
630#define B_AX_STOP_CH12 BIT(18)
631#define B_AX_STOP_CH9 BIT(17)
632#define B_AX_STOP_CH8 BIT(16)
633#define B_AX_STOP_ACH7 BIT(15)
634#define B_AX_STOP_ACH6 BIT(14)
635#define B_AX_STOP_ACH5 BIT(13)
636#define B_AX_STOP_ACH4 BIT(12)
637#define B_AX_STOP_ACH3 BIT(11)
638#define B_AX_STOP_ACH2 BIT(10)
639#define B_AX_STOP_ACH1 BIT(9)
640#define B_AX_STOP_ACH0 BIT(8)
641#define B_AX_STOP_RPQ BIT(1)
642#define B_AX_STOP_RXQ BIT(0)
643#define B_AX_TX_STOP1_ALL GENMASK(18, 8)
644#define B_AX_TX_STOP1_MASK (B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
645 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
646 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | \
647 B_AX_STOP_ACH6 | B_AX_STOP_ACH7 | \
648 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
649 B_AX_STOP_CH12)
650#define B_AX_TX_STOP1_MASK_V1 (B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
651 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
652 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
653 B_AX_STOP_CH12)
654
655#define R_AX_PCIE_DMA_STOP2 0x1310
656#define B_AX_STOP_CH11 BIT(1)
657#define B_AX_STOP_CH10 BIT(0)
658#define B_AX_TX_STOP2_ALL GENMASK(1, 0)
659
660#define R_AX_TXBD_RWPTR_CLR1 0x1014
661#define B_AX_CLR_CH12_IDX BIT(10)
662#define B_AX_CLR_CH9_IDX BIT(9)
663#define B_AX_CLR_CH8_IDX BIT(8)
664#define B_AX_CLR_ACH7_IDX BIT(7)
665#define B_AX_CLR_ACH6_IDX BIT(6)
666#define B_AX_CLR_ACH5_IDX BIT(5)
667#define B_AX_CLR_ACH4_IDX BIT(4)
668#define B_AX_CLR_ACH3_IDX BIT(3)
669#define B_AX_CLR_ACH2_IDX BIT(2)
670#define B_AX_CLR_ACH1_IDX BIT(1)
671#define B_AX_CLR_ACH0_IDX BIT(0)
672#define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)
673
674#define R_AX_RXBD_RWPTR_CLR 0x1018
675#define B_AX_CLR_RPQ_IDX BIT(1)
676#define B_AX_CLR_RXQ_IDX BIT(0)
677#define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
678
679#define R_AX_TXBD_RWPTR_CLR2 0x1314
680#define B_AX_CLR_CH11_IDX BIT(1)
681#define B_AX_CLR_CH10_IDX BIT(0)
682#define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
683
684#define R_AX_PCIE_DMA_BUSY1 0x101C
685#define B_AX_PCIEIO_RX_BUSY BIT(22)
686#define B_AX_PCIEIO_TX_BUSY BIT(21)
687#define B_AX_PCIEIO_BUSY BIT(20)
688#define B_AX_WPDMA_BUSY BIT(19)
689#define B_AX_CH12_BUSY BIT(18)
690#define B_AX_CH9_BUSY BIT(17)
691#define B_AX_CH8_BUSY BIT(16)
692#define B_AX_ACH7_BUSY BIT(15)
693#define B_AX_ACH6_BUSY BIT(14)
694#define B_AX_ACH5_BUSY BIT(13)
695#define B_AX_ACH4_BUSY BIT(12)
696#define B_AX_ACH3_BUSY BIT(11)
697#define B_AX_ACH2_BUSY BIT(10)
698#define B_AX_ACH1_BUSY BIT(9)
699#define B_AX_ACH0_BUSY BIT(8)
700#define B_AX_RPQ_BUSY BIT(1)
701#define B_AX_RXQ_BUSY BIT(0)
702#define DMA_BUSY1_CHECK (B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
703 B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
704 B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
705 B_AX_CH9_BUSY | B_AX_CH12_BUSY)
706#define DMA_BUSY1_CHECK_V1 (B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
707 B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
708 B_AX_CH12_BUSY)
709
710#define R_AX_PCIE_DMA_BUSY2 0x131C
711#define B_AX_CH11_BUSY BIT(1)
712#define B_AX_CH10_BUSY BIT(0)
713
714#define R_BE_HAXI_DMA_STOP1 0xB010
715#define B_BE_STOP_WPDMA BIT(31)
716#define B_BE_STOP_CH14 BIT(14)
717#define B_BE_STOP_CH13 BIT(13)
718#define B_BE_STOP_CH12 BIT(12)
719#define B_BE_STOP_CH11 BIT(11)
720#define B_BE_STOP_CH10 BIT(10)
721#define B_BE_STOP_CH9 BIT(9)
722#define B_BE_STOP_CH8 BIT(8)
723#define B_BE_STOP_CH7 BIT(7)
724#define B_BE_STOP_CH6 BIT(6)
725#define B_BE_STOP_CH5 BIT(5)
726#define B_BE_STOP_CH4 BIT(4)
727#define B_BE_STOP_CH3 BIT(3)
728#define B_BE_STOP_CH2 BIT(2)
729#define B_BE_STOP_CH1 BIT(1)
730#define B_BE_STOP_CH0 BIT(0)
731#define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
732 B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
733 B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
734 B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
735 B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
736 B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
737 B_BE_STOP_CH12)
738
739#define R_BE_CH0_TXBD_NUM_V1 0xB030
740#define R_BE_CH1_TXBD_NUM_V1 0xB032
741#define R_BE_CH2_TXBD_NUM_V1 0xB034
742#define R_BE_CH3_TXBD_NUM_V1 0xB036
743#define R_BE_CH4_TXBD_NUM_V1 0xB038
744#define R_BE_CH5_TXBD_NUM_V1 0xB03A
745#define R_BE_CH6_TXBD_NUM_V1 0xB03C
746#define R_BE_CH7_TXBD_NUM_V1 0xB03E
747#define R_BE_CH8_TXBD_NUM_V1 0xB040
748#define R_BE_CH9_TXBD_NUM_V1 0xB042
749#define R_BE_CH10_TXBD_NUM_V1 0xB044
750#define R_BE_CH11_TXBD_NUM_V1 0xB046
751#define R_BE_CH12_TXBD_NUM_V1 0xB048
752#define R_BE_CH13_TXBD_NUM_V1 0xB04C
753#define R_BE_CH14_TXBD_NUM_V1 0xB04E
754
755#define R_BE_RXQ0_RXBD_NUM_V1 0xB050
756#define R_BE_RPQ0_RXBD_NUM_V1 0xB052
757
758#define R_BE_CH0_TXBD_IDX_V1 0xB100
759#define R_BE_CH1_TXBD_IDX_V1 0xB104
760#define R_BE_CH2_TXBD_IDX_V1 0xB108
761#define R_BE_CH3_TXBD_IDX_V1 0xB10C
762#define R_BE_CH4_TXBD_IDX_V1 0xB110
763#define R_BE_CH5_TXBD_IDX_V1 0xB114
764#define R_BE_CH6_TXBD_IDX_V1 0xB118
765#define R_BE_CH7_TXBD_IDX_V1 0xB11C
766#define R_BE_CH8_TXBD_IDX_V1 0xB120
767#define R_BE_CH9_TXBD_IDX_V1 0xB124
768#define R_BE_CH10_TXBD_IDX_V1 0xB128
769#define R_BE_CH11_TXBD_IDX_V1 0xB12C
770#define R_BE_CH12_TXBD_IDX_V1 0xB130
771#define R_BE_CH13_TXBD_IDX_V1 0xB134
772#define R_BE_CH14_TXBD_IDX_V1 0xB138
773
774#define R_BE_RXQ0_RXBD_IDX_V1 0xB160
775#define R_BE_RPQ0_RXBD_IDX_V1 0xB164
776
777#define R_BE_CH0_TXBD_DESA_L_V1 0xB200
778#define R_BE_CH0_TXBD_DESA_H_V1 0xB204
779#define R_BE_CH1_TXBD_DESA_L_V1 0xB208
780#define R_BE_CH1_TXBD_DESA_H_V1 0xB20C
781#define R_BE_CH2_TXBD_DESA_L_V1 0xB210
782#define R_BE_CH2_TXBD_DESA_H_V1 0xB214
783#define R_BE_CH3_TXBD_DESA_L_V1 0xB218
784#define R_BE_CH3_TXBD_DESA_H_V1 0xB21C
785#define R_BE_CH4_TXBD_DESA_L_V1 0xB220
786#define R_BE_CH4_TXBD_DESA_H_V1 0xB224
787#define R_BE_CH5_TXBD_DESA_L_V1 0xB228
788#define R_BE_CH5_TXBD_DESA_H_V1 0xB22C
789#define R_BE_CH6_TXBD_DESA_L_V1 0xB230
790#define R_BE_CH6_TXBD_DESA_H_V1 0xB234
791#define R_BE_CH7_TXBD_DESA_L_V1 0xB238
792#define R_BE_CH7_TXBD_DESA_H_V1 0xB23C
793#define R_BE_CH8_TXBD_DESA_L_V1 0xB240
794#define R_BE_CH8_TXBD_DESA_H_V1 0xB244
795#define R_BE_CH9_TXBD_DESA_L_V1 0xB248
796#define R_BE_CH9_TXBD_DESA_H_V1 0xB24C
797#define R_BE_CH10_TXBD_DESA_L_V1 0xB250
798#define R_BE_CH10_TXBD_DESA_H_V1 0xB254
799#define R_BE_CH11_TXBD_DESA_L_V1 0xB258
800#define R_BE_CH11_TXBD_DESA_H_V1 0xB25C
801#define R_BE_CH12_TXBD_DESA_L_V1 0xB260
802#define R_BE_CH12_TXBD_DESA_H_V1 0xB264
803#define R_BE_CH13_TXBD_DESA_L_V1 0xB268
804#define R_BE_CH13_TXBD_DESA_H_V1 0xB26C
805#define R_BE_CH14_TXBD_DESA_L_V1 0xB270
806#define R_BE_CH14_TXBD_DESA_H_V1 0xB274
807
808#define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300
809#define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304
810#define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
811#define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
812
813/* Configure */
814#define R_AX_PCIE_INIT_CFG2 0x1004
815#define B_AX_WD_ITVL_IDLE GENMASK(27, 24)
816#define B_AX_WD_ITVL_ACT GENMASK(19, 16)
817#define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)
818
819#define R_AX_PCIE_PS_CTRL 0x1008
820#define B_AX_L1OFF_PWR_OFF_EN BIT(5)
821
822#define R_AX_INT_MIT_RX 0x10D4
823#define B_AX_RXMIT_RXP2_SEL BIT(19)
824#define B_AX_RXMIT_RXP1_SEL BIT(18)
825#define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16)
826#define AX_RXTIMER_UNIT_64US 0
827#define AX_RXTIMER_UNIT_128US 1
828#define AX_RXTIMER_UNIT_256US 2
829#define AX_RXTIMER_UNIT_512US 3
830#define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8)
831#define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)
832
833#define R_AX_DBG_ERR_FLAG_V1 0x1104
834
835#define R_AX_INT_MIT_RX_V1 0x1184
836#define B_AX_RXMIT_RXP2_SEL_V1 BIT(19)
837#define B_AX_RXMIT_RXP1_SEL_V1 BIT(18)
838#define B_AX_MIT_RXTIMER_UNIT_MASK GENMASK(17, 16)
839#define B_AX_MIT_RXCOUNTER_MATCH_MASK GENMASK(15, 8)
840#define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)
841
842#define R_AX_DBG_ERR_FLAG 0x11C4
843#define B_AX_PCIE_RPQ_FULL BIT(29)
844#define B_AX_PCIE_RXQ_FULL BIT(28)
845#define B_AX_CPL_STATUS_MASK GENMASK(27, 25)
846#define B_AX_RX_STUCK BIT(22)
847#define B_AX_TX_STUCK BIT(21)
848#define B_AX_PCIEDBG_TXERR0 BIT(16)
849#define B_AX_PCIE_RXP1_ERR0 BIT(4)
850#define B_AX_PCIE_TXBD_LEN0 BIT(1)
851#define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
852
853#define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
854#define B_AX_CLR_CH11_IDX BIT(1)
855#define B_AX_CLR_CH10_IDX BIT(0)
856
857#define R_AX_LBC_WATCHDOG 0x11D8
858#define B_AX_LBC_TIMER GENMASK(7, 4)
859#define B_AX_LBC_FLAG BIT(1)
860#define B_AX_LBC_EN BIT(0)
861
862#define R_AX_RXBD_RWPTR_CLR_V1 0x1200
863#define B_AX_CLR_RPQ_IDX BIT(1)
864#define B_AX_CLR_RXQ_IDX BIT(0)
865
866#define R_AX_HAXI_EXP_CTRL 0x1204
867#define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)
868
869#define R_AX_PCIE_EXP_CTRL 0x13F0
870#define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20)
871#define B_AX_MAX_TAG_NUM GENMASK(18, 16)
872#define B_AX_SIC_EN_FORCE_CLKREQ BIT(4)
873
874#define R_AX_PCIE_RX_PREF_ADV 0x13F4
875#define B_AX_RXDMA_PREF_ADV_EN BIT(0)
876
877#define R_AX_PCIE_HRPWM_V1 0x30C0
878#define R_AX_PCIE_CRPWM 0x30C4
879
880#define R_AX_LBC_WATCHDOG_V1 0x30D8
881
882#define R_BE_PCIE_HRPWM 0x30C0
883#define R_BE_PCIE_CRPWM 0x30C4
884
885#define R_BE_L1_2_CTRL_HCILDO 0x3110
886#define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
887
888#define R_BE_PL1_DBG_INFO 0x3120
889#define B_BE_END_PL1_CNT_MASK GENMASK(23, 16)
890#define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)
891
892#define R_BE_PCIE_MIT0_TMR 0x3330
893#define B_BE_PCIE_MIT0_RX_TMR_MASK GENMASK(5, 4)
894#define BE_MIT0_TMR_UNIT_1MS 0
895#define BE_MIT0_TMR_UNIT_2MS 1
896#define BE_MIT0_TMR_UNIT_4MS 2
897#define BE_MIT0_TMR_UNIT_8MS 3
898#define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
899
900#define R_BE_PCIE_MIT0_CNT 0x3334
901#define B_BE_PCIE_RX_MIT0_CNT_MASK GENMASK(31, 24)
902#define B_BE_PCIE_TX_MIT0_CNT_MASK GENMASK(23, 16)
903#define B_BE_PCIE_RX_MIT0_TMR_CNT_MASK GENMASK(15, 8)
904#define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)
905
906#define R_BE_PCIE_MIT_CH_EN 0x3338
907#define B_BE_PCIE_MIT_RX1P1_EN BIT(23)
908#define B_BE_PCIE_MIT_RX0P1_EN BIT(22)
909#define B_BE_PCIE_MIT_ROQ1_EN BIT(21)
910#define B_BE_PCIE_MIT_RPQ1_EN BIT(20)
911#define B_BE_PCIE_MIT_RX1P2_EN BIT(19)
912#define B_BE_PCIE_MIT_ROQ0_EN BIT(18)
913#define B_BE_PCIE_MIT_RPQ0_EN BIT(17)
914#define B_BE_PCIE_MIT_RX0P2_EN BIT(16)
915#define B_BE_PCIE_MIT_TXCH14_EN BIT(14)
916#define B_BE_PCIE_MIT_TXCH13_EN BIT(13)
917#define B_BE_PCIE_MIT_TXCH12_EN BIT(12)
918#define B_BE_PCIE_MIT_TXCH11_EN BIT(11)
919#define B_BE_PCIE_MIT_TXCH10_EN BIT(10)
920#define B_BE_PCIE_MIT_TXCH9_EN BIT(9)
921#define B_BE_PCIE_MIT_TXCH8_EN BIT(8)
922#define B_BE_PCIE_MIT_TXCH7_EN BIT(7)
923#define B_BE_PCIE_MIT_TXCH6_EN BIT(6)
924#define B_BE_PCIE_MIT_TXCH5_EN BIT(5)
925#define B_BE_PCIE_MIT_TXCH4_EN BIT(4)
926#define B_BE_PCIE_MIT_TXCH3_EN BIT(3)
927#define B_BE_PCIE_MIT_TXCH2_EN BIT(2)
928#define B_BE_PCIE_MIT_TXCH1_EN BIT(1)
929#define B_BE_PCIE_MIT_TXCH0_EN BIT(0)
930
931#define R_BE_SER_PL1_CTRL 0x34A8
932#define B_BE_PL1_SER_PL1_EN BIT(31)
933#define B_BE_PL1_IGNORE_HOT_RST BIT(30)
934#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
935#define B_BE_PL1_TIMER_CLEAR BIT(0)
936
937#define R_BE_REG_PL1_MASK 0x34B0
938#define B_BE_SER_PCLKREQ_ACK_MASK BIT(5)
939#define B_BE_SER_PM_CLK_MASK BIT(4)
940#define B_BE_SER_LTSSM_IMR BIT(3)
941#define B_BE_SER_PM_MASTER_IMR BIT(2)
942#define B_BE_SER_L1SUB_IMR BIT(1)
943#define B_BE_SER_PMU_IMR BIT(0)
944
945#define R_BE_REG_PL1_ISR 0x34B4
946
947#define R_BE_RX_APPEND_MODE 0x8920
948#define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16)
949#define B_BE_APPEND_LEN_MASK GENMASK(15, 0)
950
951#define R_BE_TXBD_RWPTR_CLR1 0xB014
952#define B_BE_CLR_CH14_IDX BIT(14)
953#define B_BE_CLR_CH13_IDX BIT(13)
954#define B_BE_CLR_CH12_IDX BIT(12)
955#define B_BE_CLR_CH11_IDX BIT(11)
956#define B_BE_CLR_CH10_IDX BIT(10)
957#define B_BE_CLR_CH9_IDX BIT(9)
958#define B_BE_CLR_CH8_IDX BIT(8)
959#define B_BE_CLR_CH7_IDX BIT(7)
960#define B_BE_CLR_CH6_IDX BIT(6)
961#define B_BE_CLR_CH5_IDX BIT(5)
962#define B_BE_CLR_CH4_IDX BIT(4)
963#define B_BE_CLR_CH3_IDX BIT(3)
964#define B_BE_CLR_CH2_IDX BIT(2)
965#define B_BE_CLR_CH1_IDX BIT(1)
966#define B_BE_CLR_CH0_IDX BIT(0)
967
968#define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
969#define B_BE_CLR_ROQ1_IDX_V1 BIT(5)
970#define B_BE_CLR_RPQ1_IDX_V1 BIT(4)
971#define B_BE_CLR_RXQ1_IDX_V1 BIT(3)
972#define B_BE_CLR_ROQ0_IDX BIT(2)
973#define B_BE_CLR_RPQ0_IDX BIT(1)
974#define B_BE_CLR_RXQ0_IDX BIT(0)
975
976#define R_BE_HAXI_DMA_BUSY1 0xB01C
977#define B_BE_HAXI_MST_BUSY BIT(31)
978#define B_BE_HAXI_RX_IDLE BIT(25)
979#define B_BE_HAXI_TX_IDLE BIT(24)
980#define B_BE_ROQ1_BUSY_V1 BIT(21)
981#define B_BE_RPQ1_BUSY_V1 BIT(20)
982#define B_BE_RXQ1_BUSY_V1 BIT(19)
983#define B_BE_ROQ0_BUSY_V1 BIT(18)
984#define B_BE_RPQ0_BUSY_V1 BIT(17)
985#define B_BE_RXQ0_BUSY_V1 BIT(16)
986#define B_BE_WPDMA_BUSY BIT(15)
987#define B_BE_CH14_BUSY BIT(14)
988#define B_BE_CH13_BUSY BIT(13)
989#define B_BE_CH12_BUSY BIT(12)
990#define B_BE_CH11_BUSY BIT(11)
991#define B_BE_CH10_BUSY BIT(10)
992#define B_BE_CH9_BUSY BIT(9)
993#define B_BE_CH8_BUSY BIT(8)
994#define B_BE_CH7_BUSY BIT(7)
995#define B_BE_CH6_BUSY BIT(6)
996#define B_BE_CH5_BUSY BIT(5)
997#define B_BE_CH4_BUSY BIT(4)
998#define B_BE_CH3_BUSY BIT(3)
999#define B_BE_CH2_BUSY BIT(2)
1000#define B_BE_CH1_BUSY BIT(1)
1001#define B_BE_CH0_BUSY BIT(0)
1002#define DMA_BUSY1_CHECK_BE (B_BE_CH0_BUSY | B_BE_CH1_BUSY | B_BE_CH2_BUSY | \
1003 B_BE_CH3_BUSY | B_BE_CH4_BUSY | B_BE_CH5_BUSY | \
1004 B_BE_CH6_BUSY | B_BE_CH7_BUSY | B_BE_CH8_BUSY | \
1005 B_BE_CH9_BUSY | B_BE_CH10_BUSY | B_BE_CH11_BUSY | \
1006 B_BE_CH12_BUSY | B_BE_CH13_BUSY | B_BE_CH14_BUSY)
1007
1008#define R_BE_HAXI_EXP_CTRL_V1 0xB020
1009#define B_BE_R_NO_SEC_ACCESS BIT(31)
1010#define B_BE_FORCE_EN_DMA_RX_GCLK BIT(5)
1011#define B_BE_FORCE_EN_DMA_TX_GCLK BIT(4)
1012#define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)
1013
1014#define RTW89_PCI_TXBD_NUM_MAX 256
1015#define RTW89_PCI_RXBD_NUM_MAX 256
1016#define RTW89_PCI_TXWD_NUM_MAX 512
1017#define RTW89_PCI_TXWD_PAGE_SIZE 128
1018#define RTW89_PCI_ADDRINFO_MAX 4
1019#define RTW89_PCI_RX_BUF_SIZE (11454 + 40) /* +40 for rtw89_rxdesc_long_v2 */
1020
1021#define RTW89_PCI_POLL_BDRAM_RST_CNT 100
1022#define RTW89_PCI_MULTITAG 8
1023
1024/* PCIE CFG register */
1025#define RTW89_PCIE_CAPABILITY_SPEED 0x7C
1026#define RTW89_PCIE_SUPPORT_GEN_MASK GENMASK(3, 0)
1027#define RTW89_PCIE_L1_STS_V1 0x80
1028#define RTW89_BCFG_LINK_SPEED_MASK GENMASK(19, 16)
1029#define RTW89_PCIE_GEN1_SPEED 0x01
1030#define RTW89_PCIE_GEN2_SPEED 0x02
1031#define RTW89_PCIE_PHY_RATE 0x82
1032#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
1033#define RTW89_PCIE_LINK_CHANGE_SPEED 0xA0
1034#define RTW89_PCIE_L1SS_STS_V1 0x0168
1035#define RTW89_PCIE_BIT_ASPM_L11 BIT(3)
1036#define RTW89_PCIE_BIT_ASPM_L12 BIT(2)
1037#define RTW89_PCIE_BIT_PCI_L11 BIT(1)
1038#define RTW89_PCIE_BIT_PCI_L12 BIT(0)
1039#define RTW89_PCIE_ASPM_CTRL 0x070F
1040#define RTW89_L1DLY_MASK GENMASK(5, 3)
1041#define RTW89_L0DLY_MASK GENMASK(2, 0)
1042#define RTW89_PCIE_TIMER_CTRL 0x0718
1043#define RTW89_PCIE_BIT_L1SUB BIT(5)
1044#define RTW89_PCIE_L1_CTRL 0x0719
1045#define RTW89_PCIE_BIT_CLK BIT(4)
1046#define RTW89_PCIE_BIT_L1 BIT(3)
1047#define RTW89_PCIE_CLK_CTRL 0x0725
1048#define RTW89_PCIE_FTS 0x080C
1049#define RTW89_PCIE_POLLING_BIT BIT(17)
1050#define RTW89_PCIE_RST_MSTATE 0x0B48
1051#define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0)
1052
1053#define INTF_INTGRA_MINREF_V1 90
1054#define INTF_INTGRA_HOSTREF_V1 100
1055
1056enum rtw89_pcie_phy {
1057 PCIE_PHY_GEN1,
1058 PCIE_PHY_GEN2,
1059 PCIE_PHY_GEN1_UNDEFINE = 0x7F,
1060};
1061
1062enum rtw89_pcie_l0sdly {
1063 PCIE_L0SDLY_1US = 0,
1064 PCIE_L0SDLY_2US = 1,
1065 PCIE_L0SDLY_3US = 2,
1066 PCIE_L0SDLY_4US = 3,
1067 PCIE_L0SDLY_5US = 4,
1068 PCIE_L0SDLY_6US = 5,
1069 PCIE_L0SDLY_7US = 6,
1070};
1071
1072enum rtw89_pcie_l1dly {
1073 PCIE_L1DLY_16US = 4,
1074 PCIE_L1DLY_32US = 5,
1075 PCIE_L1DLY_64US = 6,
1076 PCIE_L1DLY_HW_INFI = 7,
1077};
1078
1079enum rtw89_pcie_clkdly_hw {
1080 PCIE_CLKDLY_HW_0 = 0,
1081 PCIE_CLKDLY_HW_30US = 0x1,
1082 PCIE_CLKDLY_HW_50US = 0x2,
1083 PCIE_CLKDLY_HW_100US = 0x3,
1084 PCIE_CLKDLY_HW_150US = 0x4,
1085 PCIE_CLKDLY_HW_200US = 0x5,
1086};
1087
1088enum rtw89_pcie_clkdly_hw_v1 {
1089 PCIE_CLKDLY_HW_V1_0 = 0,
1090 PCIE_CLKDLY_HW_V1_16US = 0x1,
1091 PCIE_CLKDLY_HW_V1_32US = 0x2,
1092 PCIE_CLKDLY_HW_V1_64US = 0x3,
1093 PCIE_CLKDLY_HW_V1_80US = 0x4,
1094 PCIE_CLKDLY_HW_V1_96US = 0x5,
1095};
1096
1097enum mac_ax_bd_trunc_mode {
1098 MAC_AX_BD_NORM,
1099 MAC_AX_BD_TRUNC,
1100 MAC_AX_BD_DEF = 0xFE
1101};
1102
1103enum mac_ax_rxbd_mode {
1104 MAC_AX_RXBD_PKT,
1105 MAC_AX_RXBD_SEP,
1106 MAC_AX_RXBD_DEF = 0xFE
1107};
1108
1109enum mac_ax_tag_mode {
1110 MAC_AX_TAG_SGL,
1111 MAC_AX_TAG_MULTI,
1112 MAC_AX_TAG_DEF = 0xFE
1113};
1114
1115enum mac_ax_tx_burst {
1116 MAC_AX_TX_BURST_16B = 0,
1117 MAC_AX_TX_BURST_32B = 1,
1118 MAC_AX_TX_BURST_64B = 2,
1119 MAC_AX_TX_BURST_V1_64B = 0,
1120 MAC_AX_TX_BURST_128B = 3,
1121 MAC_AX_TX_BURST_V1_128B = 1,
1122 MAC_AX_TX_BURST_256B = 4,
1123 MAC_AX_TX_BURST_V1_256B = 2,
1124 MAC_AX_TX_BURST_512B = 5,
1125 MAC_AX_TX_BURST_1024B = 6,
1126 MAC_AX_TX_BURST_2048B = 7,
1127 MAC_AX_TX_BURST_DEF = 0xFE
1128};
1129
1130enum mac_ax_rx_burst {
1131 MAC_AX_RX_BURST_16B = 0,
1132 MAC_AX_RX_BURST_32B = 1,
1133 MAC_AX_RX_BURST_64B = 2,
1134 MAC_AX_RX_BURST_V1_64B = 0,
1135 MAC_AX_RX_BURST_128B = 3,
1136 MAC_AX_RX_BURST_V1_128B = 1,
1137 MAC_AX_RX_BURST_V1_256B = 0,
1138 MAC_AX_RX_BURST_DEF = 0xFE
1139};
1140
1141enum mac_ax_wd_dma_intvl {
1142 MAC_AX_WD_DMA_INTVL_0S,
1143 MAC_AX_WD_DMA_INTVL_256NS,
1144 MAC_AX_WD_DMA_INTVL_512NS,
1145 MAC_AX_WD_DMA_INTVL_768NS,
1146 MAC_AX_WD_DMA_INTVL_1US,
1147 MAC_AX_WD_DMA_INTVL_1_5US,
1148 MAC_AX_WD_DMA_INTVL_2US,
1149 MAC_AX_WD_DMA_INTVL_4US,
1150 MAC_AX_WD_DMA_INTVL_8US,
1151 MAC_AX_WD_DMA_INTVL_16US,
1152 MAC_AX_WD_DMA_INTVL_DEF = 0xFE
1153};
1154
1155enum mac_ax_multi_tag_num {
1156 MAC_AX_TAG_NUM_1,
1157 MAC_AX_TAG_NUM_2,
1158 MAC_AX_TAG_NUM_3,
1159 MAC_AX_TAG_NUM_4,
1160 MAC_AX_TAG_NUM_5,
1161 MAC_AX_TAG_NUM_6,
1162 MAC_AX_TAG_NUM_7,
1163 MAC_AX_TAG_NUM_8,
1164 MAC_AX_TAG_NUM_DEF = 0xFE
1165};
1166
1167enum mac_ax_lbc_tmr {
1168 MAC_AX_LBC_TMR_8US = 0,
1169 MAC_AX_LBC_TMR_16US,
1170 MAC_AX_LBC_TMR_32US,
1171 MAC_AX_LBC_TMR_64US,
1172 MAC_AX_LBC_TMR_128US,
1173 MAC_AX_LBC_TMR_256US,
1174 MAC_AX_LBC_TMR_512US,
1175 MAC_AX_LBC_TMR_1MS,
1176 MAC_AX_LBC_TMR_2MS,
1177 MAC_AX_LBC_TMR_4MS,
1178 MAC_AX_LBC_TMR_8MS,
1179 MAC_AX_LBC_TMR_DEF = 0xFE
1180};
1181
1182enum mac_ax_pcie_func_ctrl {
1183 MAC_AX_PCIE_DISABLE = 0,
1184 MAC_AX_PCIE_ENABLE = 1,
1185 MAC_AX_PCIE_DEFAULT = 0xFE,
1186 MAC_AX_PCIE_IGNORE = 0xFF
1187};
1188
1189enum mac_ax_io_rcy_tmr {
1190 MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
1191 MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
1192 MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
1193 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
1194};
1195
1196enum rtw89_pci_intr_mask_cfg {
1197 RTW89_PCI_INTR_MASK_RESET,
1198 RTW89_PCI_INTR_MASK_NORMAL,
1199 RTW89_PCI_INTR_MASK_LOW_POWER,
1200 RTW89_PCI_INTR_MASK_RECOVERY_START,
1201 RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE,
1202};
1203
1204struct rtw89_pci_isrs;
1205struct rtw89_pci;
1206
1207struct rtw89_pci_bd_idx_addr {
1208 u32 tx_bd_addrs[RTW89_TXCH_NUM];
1209 u32 rx_bd_addrs[RTW89_RXCH_NUM];
1210};
1211
1212struct rtw89_pci_ch_dma_addr {
1213 u32 num;
1214 u32 idx;
1215 u32 bdram;
1216 u32 desa_l;
1217 u32 desa_h;
1218};
1219
1220struct rtw89_pci_ch_dma_addr_set {
1221 struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];
1222 struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];
1223};
1224
1225struct rtw89_pci_bd_ram {
1226 u8 start_idx;
1227 u8 max_num;
1228 u8 min_num;
1229};
1230
1231struct rtw89_pci_gen_def {
1232 u32 isr_rdu;
1233 u32 isr_halt_c2h;
1234 u32 isr_wdt_timeout;
1235 struct rtw89_reg2_def isr_clear_rpq;
1236 struct rtw89_reg2_def isr_clear_rxq;
1237
1238 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
1239 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
1240 int (*mac_post_init)(struct rtw89_dev *rtwdev);
1241
1242 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
1243 int (*rst_bdram)(struct rtw89_dev *rtwdev);
1244
1245 int (*lv1rst_stop_dma)(struct rtw89_dev *rtwdev);
1246 int (*lv1rst_start_dma)(struct rtw89_dev *rtwdev);
1247
1248 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
1249 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
1250 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
1251
1252 void (*aspm_set)(struct rtw89_dev *rtwdev, bool enable);
1253 void (*clkreq_set)(struct rtw89_dev *rtwdev, bool enable);
1254 void (*l1ss_set)(struct rtw89_dev *rtwdev, bool enable);
1255};
1256
1257struct rtw89_pci_info {
1258 const struct rtw89_pci_gen_def *gen_def;
1259 enum mac_ax_bd_trunc_mode txbd_trunc_mode;
1260 enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
1261 enum mac_ax_rxbd_mode rxbd_mode;
1262 enum mac_ax_tag_mode tag_mode;
1263 enum mac_ax_tx_burst tx_burst;
1264 enum mac_ax_rx_burst rx_burst;
1265 enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
1266 enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
1267 enum mac_ax_multi_tag_num multi_tag_num;
1268 enum mac_ax_pcie_func_ctrl lbc_en;
1269 enum mac_ax_lbc_tmr lbc_tmr;
1270 enum mac_ax_pcie_func_ctrl autok_en;
1271 enum mac_ax_pcie_func_ctrl io_rcy_en;
1272 enum mac_ax_io_rcy_tmr io_rcy_tmr;
1273 bool rx_ring_eq_is_full;
1274 bool check_rx_tag;
1275
1276 u32 init_cfg_reg;
1277 u32 txhci_en_bit;
1278 u32 rxhci_en_bit;
1279 u32 rxbd_mode_bit;
1280 u32 exp_ctrl_reg;
1281 u32 max_tag_num_mask;
1282 u32 rxbd_rwptr_clr_reg;
1283 u32 txbd_rwptr_clr2_reg;
1284 struct rtw89_reg_def dma_io_stop;
1285 struct rtw89_reg_def dma_stop1;
1286 struct rtw89_reg_def dma_stop2;
1287 struct rtw89_reg_def dma_busy1;
1288 u32 dma_busy2_reg;
1289 u32 dma_busy3_reg;
1290
1291 u32 rpwm_addr;
1292 u32 cpwm_addr;
1293 u32 mit_addr;
1294 u32 tx_dma_ch_mask;
1295 const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
1296 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
1297 const struct rtw89_pci_bd_ram (*bd_ram_table)[RTW89_TXCH_NUM];
1298
1299 int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
1300 u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
1301 void *txaddr_info_addr, u32 total_len,
1302 dma_addr_t dma, u8 *add_info_nr);
1303 void (*config_intr_mask)(struct rtw89_dev *rtwdev);
1304 void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1305 void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1306 void (*recognize_intrs)(struct rtw89_dev *rtwdev,
1307 struct rtw89_pci *rtwpci,
1308 struct rtw89_pci_isrs *isrs);
1309};
1310
1311struct rtw89_pci_tx_data {
1312 dma_addr_t dma;
1313};
1314
1315struct rtw89_pci_rx_info {
1316 dma_addr_t dma;
1317 u32 fs:1, ls:1, tag:13, len:14;
1318};
1319
1320#define RTW89_PCI_TXBD_OPTION_LS BIT(14)
1321
1322struct rtw89_pci_tx_bd_32 {
1323 __le16 length;
1324 __le16 option;
1325 __le32 dma;
1326} __packed;
1327
1328#define RTW89_PCI_TXWP_VALID BIT(15)
1329
1330struct rtw89_pci_tx_wp_info {
1331 __le16 seq0;
1332 __le16 seq1;
1333 __le16 seq2;
1334 __le16 seq3;
1335} __packed;
1336
1337#define RTW89_PCI_ADDR_MSDU_LS BIT(15)
1338#define RTW89_PCI_ADDR_LS BIT(14)
1339#define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6))
1340#define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
1341
1342struct rtw89_pci_tx_addr_info_32 {
1343 __le16 length;
1344 __le16 option;
1345 __le32 dma;
1346} __packed;
1347
1348#define RTW89_TXADDR_INFO_NR_V1 10
1349
1350struct rtw89_pci_tx_addr_info_32_v1 {
1351 __le16 length_opt;
1352#define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)
1353#define B_PCIADDR_HIGH_SEL_V1_MASK GENMASK(14, 11)
1354#define B_PCIADDR_LS_V1_MASK BIT(15)
1355#define TXADDR_INFO_LENTHG_V1_MAX ALIGN_DOWN(BIT(11) - 1, 4)
1356 __le16 dma_low_lsb;
1357 __le16 dma_low_msb;
1358} __packed;
1359
1360#define RTW89_PCI_RPP_POLLUTED BIT(31)
1361#define RTW89_PCI_RPP_SEQ GENMASK(30, 16)
1362#define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13)
1363#define RTW89_TX_DONE 0x0
1364#define RTW89_TX_RETRY_LIMIT 0x1
1365#define RTW89_TX_LIFE_TIME 0x2
1366#define RTW89_TX_MACID_DROP 0x3
1367#define RTW89_PCI_RPP_QSEL GENMASK(12, 8)
1368#define RTW89_PCI_RPP_MACID GENMASK(7, 0)
1369
1370struct rtw89_pci_rpp_fmt {
1371 __le32 dword;
1372} __packed;
1373
1374struct rtw89_pci_rx_bd_32 {
1375 __le16 buf_size;
1376 __le16 rsvd;
1377 __le32 dma;
1378} __packed;
1379
1380#define RTW89_PCI_RXBD_FS BIT(15)
1381#define RTW89_PCI_RXBD_LS BIT(14)
1382#define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)
1383#define RTW89_PCI_RXBD_TAG GENMASK(28, 16)
1384
1385struct rtw89_pci_rxbd_info {
1386 __le32 dword;
1387};
1388
1389struct rtw89_pci_tx_wd {
1390 struct list_head list;
1391 struct sk_buff_head queue;
1392
1393 void *vaddr;
1394 dma_addr_t paddr;
1395 u32 len;
1396 u32 seq;
1397};
1398
1399struct rtw89_pci_dma_ring {
1400 void *head;
1401 u8 desc_size;
1402 dma_addr_t dma;
1403
1404 struct rtw89_pci_ch_dma_addr addr;
1405
1406 u32 len;
1407 u32 wp; /* host idx */
1408 u32 rp; /* hw idx */
1409};
1410
1411struct rtw89_pci_tx_wd_ring {
1412 void *head;
1413 dma_addr_t dma;
1414
1415 struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];
1416 struct list_head free_pages;
1417
1418 u32 page_size;
1419 u32 page_num;
1420 u32 curr_num;
1421};
1422
1423#define RTW89_RX_TAG_MAX 0x1fff
1424
1425struct rtw89_pci_tx_ring {
1426 struct rtw89_pci_tx_wd_ring wd_ring;
1427 struct rtw89_pci_dma_ring bd_ring;
1428 struct list_head busy_pages;
1429 u8 txch;
1430 bool dma_enabled;
1431 u16 tag; /* range from 0x0001 ~ 0x1fff */
1432
1433 u64 tx_cnt;
1434 u64 tx_acked;
1435 u64 tx_retry_lmt;
1436 u64 tx_life_time;
1437 u64 tx_mac_id_drop;
1438};
1439
1440struct rtw89_pci_rx_ring {
1441 struct rtw89_pci_dma_ring bd_ring;
1442 struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];
1443 u32 buf_sz;
1444 struct sk_buff *diliver_skb;
1445 struct rtw89_rx_desc_info diliver_desc;
1446 u32 target_rx_tag:13;
1447};
1448
1449struct rtw89_pci_isrs {
1450 u32 ind_isrs;
1451 u32 halt_c2h_isrs;
1452 u32 isrs[2];
1453};
1454
1455struct rtw89_pci {
1456 struct pci_dev *pdev;
1457
1458 /* protect HW irq related registers */
1459 spinlock_t irq_lock;
1460 /* protect TRX resources (exclude RXQ) */
1461 spinlock_t trx_lock;
1462 bool running;
1463 bool low_power;
1464 bool under_recovery;
1465 struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];
1466 struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];
1467 struct sk_buff_head h2c_queue;
1468 struct sk_buff_head h2c_release_queue;
1469 DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM);
1470
1471 u32 ind_intrs;
1472 u32 halt_c2h_intrs;
1473 u32 intrs[2];
1474 void __iomem *mmap;
1475};
1476
1477static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)
1478{
1479 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1480
1481 BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) >
1482 sizeof(info->status.status_driver_data));
1483
1484 return (struct rtw89_pci_rx_info *)skb->cb;
1485}
1486
1487static inline struct rtw89_pci_rx_bd_32 *
1488RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)
1489{
1490 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
1491 u8 *head = bd_ring->head;
1492 u32 desc_size = bd_ring->desc_size;
1493 u32 offset = idx * desc_size;
1494
1495 return (struct rtw89_pci_rx_bd_32 *)(head + offset);
1496}
1497
1498static inline void
1499rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)
1500{
1501 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
1502
1503 bd_ring->wp += cnt;
1504
1505 if (bd_ring->wp >= bd_ring->len)
1506 bd_ring->wp -= bd_ring->len;
1507}
1508
1509static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)
1510{
1511 struct rtw89_tx_skb_data *data = RTW89_TX_SKB_CB(skb);
1512
1513 return (struct rtw89_pci_tx_data *)data->hci_priv;
1514}
1515
1516static inline struct rtw89_pci_tx_bd_32 *
1517rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)
1518{
1519 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1520 struct rtw89_pci_tx_bd_32 *tx_bd, *head;
1521
1522 head = bd_ring->head;
1523 tx_bd = head + bd_ring->wp;
1524
1525 return tx_bd;
1526}
1527
1528static inline struct rtw89_pci_tx_wd *
1529rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)
1530{
1531 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1532 struct rtw89_pci_tx_wd *txwd;
1533
1534 txwd = list_first_entry_or_null(&wd_ring->free_pages,
1535 struct rtw89_pci_tx_wd, list);
1536 if (!txwd)
1537 return NULL;
1538
1539 list_del_init(entry: &txwd->list);
1540 txwd->len = 0;
1541 wd_ring->curr_num--;
1542
1543 return txwd;
1544}
1545
1546static inline void
1547rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,
1548 struct rtw89_pci_tx_wd *txwd)
1549{
1550 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1551
1552 memset(txwd->vaddr, 0, wd_ring->page_size);
1553 list_add_tail(new: &txwd->list, head: &wd_ring->free_pages);
1554 wd_ring->curr_num++;
1555}
1556
1557static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)
1558{
1559 return val == 0xffffffff || val == 0xeaeaeaea;
1560}
1561
1562extern const struct dev_pm_ops rtw89_pm_ops;
1563extern const struct dev_pm_ops rtw89_pm_ops_be;
1564extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;
1565extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;
1566extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be;
1567extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM];
1568extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM];
1569extern const struct rtw89_pci_gen_def rtw89_pci_gen_ax;
1570extern const struct rtw89_pci_gen_def rtw89_pci_gen_be;
1571
1572struct pci_device_id;
1573
1574int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
1575void rtw89_pci_remove(struct pci_dev *pdev);
1576void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev);
1577int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
1578int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
1579int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en);
1580u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
1581 void *txaddr_info_addr, u32 total_len,
1582 dma_addr_t dma, u8 *add_info_nr);
1583u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
1584 void *txaddr_info_addr, u32 total_len,
1585 dma_addr_t dma, u8 *add_info_nr);
1586void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
1587void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
1588void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1589void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev);
1590void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1591void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1592void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1593void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1594void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1595void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1596void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
1597 struct rtw89_pci *rtwpci,
1598 struct rtw89_pci_isrs *isrs);
1599void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
1600 struct rtw89_pci *rtwpci,
1601 struct rtw89_pci_isrs *isrs);
1602void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev,
1603 struct rtw89_pci *rtwpci,
1604 struct rtw89_pci_isrs *isrs);
1605
1606static inline
1607u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,
1608 void *txaddr_info_addr, u32 total_len,
1609 dma_addr_t dma, u8 *add_info_nr)
1610{
1611 const struct rtw89_pci_info *info = rtwdev->pci_info;
1612
1613 return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len,
1614 dma, add_info_nr);
1615}
1616
1617static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev,
1618 enum rtw89_pci_intr_mask_cfg cfg)
1619{
1620 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1621 const struct rtw89_pci_info *info = rtwdev->pci_info;
1622
1623 switch (cfg) {
1624 default:
1625 case RTW89_PCI_INTR_MASK_RESET:
1626 rtwpci->low_power = false;
1627 rtwpci->under_recovery = false;
1628 break;
1629 case RTW89_PCI_INTR_MASK_NORMAL:
1630 rtwpci->low_power = false;
1631 break;
1632 case RTW89_PCI_INTR_MASK_LOW_POWER:
1633 rtwpci->low_power = true;
1634 break;
1635 case RTW89_PCI_INTR_MASK_RECOVERY_START:
1636 rtwpci->under_recovery = true;
1637 break;
1638 case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE:
1639 rtwpci->under_recovery = false;
1640 break;
1641 }
1642
1643 rtw89_debug(rtwdev, mask: RTW89_DBG_HCI,
1644 fmt: "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n",
1645 rtwpci->low_power, rtwpci->under_recovery);
1646
1647 info->config_intr_mask(rtwdev);
1648}
1649
1650static inline
1651void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1652{
1653 const struct rtw89_pci_info *info = rtwdev->pci_info;
1654
1655 info->enable_intr(rtwdev, rtwpci);
1656}
1657
1658static inline
1659void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1660{
1661 const struct rtw89_pci_info *info = rtwdev->pci_info;
1662
1663 info->disable_intr(rtwdev, rtwpci);
1664}
1665
1666static inline
1667void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev,
1668 struct rtw89_pci *rtwpci,
1669 struct rtw89_pci_isrs *isrs)
1670{
1671 const struct rtw89_pci_info *info = rtwdev->pci_info;
1672
1673 info->recognize_intrs(rtwdev, rtwpci, isrs);
1674}
1675
1676static inline int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
1677{
1678 const struct rtw89_pci_info *info = rtwdev->pci_info;
1679 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1680
1681 return gen_def->mac_pre_init(rtwdev);
1682}
1683
1684static inline int rtw89_pci_ops_mac_pre_deinit(struct rtw89_dev *rtwdev)
1685{
1686 const struct rtw89_pci_info *info = rtwdev->pci_info;
1687 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1688
1689 if (!gen_def->mac_pre_deinit)
1690 return 0;
1691
1692 return gen_def->mac_pre_deinit(rtwdev);
1693}
1694
1695static inline int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev)
1696{
1697 const struct rtw89_pci_info *info = rtwdev->pci_info;
1698 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1699
1700 return gen_def->mac_post_init(rtwdev);
1701}
1702
1703static inline void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev)
1704{
1705 const struct rtw89_pci_info *info = rtwdev->pci_info;
1706 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1707
1708 gen_def->clr_idx_all(rtwdev);
1709}
1710
1711static inline int rtw89_pci_reset_bdram(struct rtw89_dev *rtwdev)
1712{
1713 const struct rtw89_pci_info *info = rtwdev->pci_info;
1714 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1715
1716 return gen_def->rst_bdram(rtwdev);
1717}
1718
1719static inline void rtw89_pci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
1720{
1721 const struct rtw89_pci_info *info = rtwdev->pci_info;
1722 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1723
1724 return gen_def->ctrl_txdma_ch(rtwdev, enable);
1725}
1726
1727static inline void rtw89_pci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
1728{
1729 const struct rtw89_pci_info *info = rtwdev->pci_info;
1730 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1731
1732 return gen_def->ctrl_txdma_fw_ch(rtwdev, enable);
1733}
1734
1735static inline int rtw89_pci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
1736{
1737 const struct rtw89_pci_info *info = rtwdev->pci_info;
1738 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1739
1740 return gen_def->poll_txdma_ch_idle(rtwdev);
1741}
1742#endif
1743

source code of linux/drivers/net/wireless/realtek/rtw89/pci.h