1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* Copyright(c) 2019-2020 Realtek Corporation |
3 | */ |
4 | |
5 | #ifndef __RTW89_REG_H__ |
6 | #define __RTW89_REG_H__ |
7 | |
8 | #define R_AX_SYS_WL_EFUSE_CTRL 0x000A |
9 | #define B_AX_AUTOLOAD_SUS BIT(5) |
10 | |
11 | #define R_AX_SYS_ISO_CTRL 0x0000 |
12 | #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14) |
13 | #define B_AX_PWC_EV2EF_B15 BIT(15) |
14 | #define B_AX_PWC_EV2EF_B14 BIT(14) |
15 | #define B_AX_ISO_EB2CORE BIT(8) |
16 | |
17 | #define R_AX_SYS_FUNC_EN 0x0002 |
18 | #define B_AX_FEN_BB_GLB_RSTN BIT(1) |
19 | #define B_AX_FEN_BBRSTB BIT(0) |
20 | |
21 | #define R_AX_SYS_PW_CTRL 0x0004 |
22 | #define B_AX_SOP_ASWRM BIT(31) |
23 | #define B_AX_SOP_PWMM_DSWR BIT(29) |
24 | #define B_AX_XTAL_OFF_A_DIE BIT(22) |
25 | #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18) |
26 | #define B_AX_RDY_SYSPWR BIT(17) |
27 | #define B_AX_EN_WLON BIT(16) |
28 | #define B_AX_APDM_HPDN BIT(15) |
29 | #define B_AX_PSUS_OFF_CAPC_EN BIT(14) |
30 | #define B_AX_AFSM_PCIE_SUS_EN BIT(12) |
31 | #define B_AX_AFSM_WLSUS_EN BIT(11) |
32 | #define B_AX_APFM_SWLPS BIT(10) |
33 | #define B_AX_APFM_OFFMAC BIT(9) |
34 | #define B_AX_APFN_ONMAC BIT(8) |
35 | |
36 | #define R_AX_SYS_CLK_CTRL 0x0008 |
37 | #define B_AX_CPU_CLK_EN BIT(14) |
38 | |
39 | #define R_AX_SYS_SWR_CTRL1 0x0010 |
40 | #define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10) |
41 | |
42 | #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018 |
43 | #define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6) |
44 | #define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5) |
45 | |
46 | #define R_AX_RSV_CTRL 0x001C |
47 | #define B_AX_R_DIS_PRST BIT(6) |
48 | #define B_AX_WLOCK_1C_BIT6 BIT(5) |
49 | |
50 | #define R_AX_AFE_LDO_CTRL 0x0020 |
51 | #define B_AX_AON_OFF_PC_EN BIT(23) |
52 | |
53 | #define R_AX_EFUSE_CTRL_1 0x0038 |
54 | #define B_AX_EF_PGPD_MASK GENMASK(30, 28) |
55 | #define B_AX_EF_RDT BIT(27) |
56 | #define B_AX_EF_VDDQST_MASK GENMASK(26, 24) |
57 | #define B_AX_EF_PGTS_MASK GENMASK(23, 20) |
58 | #define B_AX_EF_PD_DIS BIT(11) |
59 | #define B_AX_EF_POR BIT(10) |
60 | #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8) |
61 | |
62 | #define R_AX_EFUSE_CTRL 0x0030 |
63 | #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30) |
64 | #define B_AX_EF_RDY BIT(29) |
65 | #define B_AX_EF_COMP_RESULT BIT(28) |
66 | #define B_AX_EF_ADDR_MASK GENMASK(26, 16) |
67 | #define B_AX_EF_DATA_MASK GENMASK(15, 0) |
68 | |
69 | #define R_AX_EFUSE_CTRL_1_V1 0x0038 |
70 | #define B_AX_EF_ENT BIT(31) |
71 | #define B_AX_EF_BURST BIT(19) |
72 | #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16) |
73 | #define B_AX_EF_TROW_EN BIT(15) |
74 | #define B_AX_EF_ERR_FLAG BIT(14) |
75 | #define B_AX_EF_DSB_EN BIT(11) |
76 | #define B_AX_PCIE_CALIB_EN_V1 BIT(12) |
77 | #define B_AX_WDT_WAKE_PCIE_EN BIT(10) |
78 | #define B_AX_WDT_WAKE_USB_EN BIT(9) |
79 | |
80 | #define R_AX_GPIO_MUXCFG 0x0040 |
81 | #define B_AX_BOOT_MODE BIT(19) |
82 | #define B_AX_WL_EECS_EXT_32K_SEL BIT(18) |
83 | #define B_AX_WL_SEC_BONDING_OPT_STS BIT(17) |
84 | #define B_AX_SECSIC_SEL BIT(16) |
85 | #define B_AX_ENHTP BIT(14) |
86 | #define B_AX_BT_AOD_GPIO3 BIT(13) |
87 | #define B_AX_ENSIC BIT(12) |
88 | #define B_AX_SIC_SWRST BIT(11) |
89 | #define B_AX_PO_WIFI_PTA_PINS BIT(10) |
90 | #define B_AX_PO_BT_PTA_PINS BIT(9) |
91 | #define B_AX_ENUARTTX BIT(8) |
92 | #define B_AX_BTMODE_MASK GENMASK(7, 6) |
93 | #define MAC_AX_BT_MODE_0_3 0 |
94 | #define MAC_AX_BT_MODE_2 2 |
95 | #define MAC_AX_RTK_MODE 0 |
96 | #define MAC_AX_CSR_MODE 1 |
97 | #define B_AX_ENBT BIT(5) |
98 | #define B_AX_EROM_EN BIT(4) |
99 | #define B_AX_ENUARTRX BIT(2) |
100 | #define B_AX_GPIOSEL_MASK GENMASK(1, 0) |
101 | |
102 | #define R_AX_DBG_CTRL 0x0058 |
103 | #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30) |
104 | #define B_AX_DBG_SEL1_16BIT BIT(27) |
105 | #define B_AX_DBG_SEL1 GENMASK(23, 16) |
106 | #define B_AX_DBG_SEL0_4BIT GENMASK(15, 14) |
107 | #define B_AX_DBG_SEL0_16BIT BIT(11) |
108 | #define B_AX_DBG_SEL0 GENMASK(7, 0) |
109 | |
110 | #define R_AX_SYS_SDIO_CTRL 0x0070 |
111 | #define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15) |
112 | #define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14) |
113 | #define B_AX_PCIE_FORCE_PWR_NGAT BIT(13) |
114 | #define B_AX_PCIE_CALIB_EN_V1 BIT(12) |
115 | #define B_AX_PCIE_AUXCLK_GATE BIT(11) |
116 | #define B_AX_LTE_MUX_CTRL_PATH BIT(26) |
117 | |
118 | #define R_AX_HCI_OPT_CTRL 0x0074 |
119 | #define BIT_WAKE_CTRL_V1 BIT(23) |
120 | #define BIT_WAKE_CTRL BIT(5) |
121 | |
122 | #define R_AX_HCI_BG_CTRL 0x0078 |
123 | #define B_AX_IBX_EN_VALUE BIT(15) |
124 | #define B_AX_IB_EN_VALUE BIT(14) |
125 | #define B_AX_FORCED_IB_EN BIT(4) |
126 | #define B_AX_EN_REGBG BIT(3) |
127 | #define B_AX_R_AX_BG_LPF BIT(2) |
128 | #define B_AX_R_AX_BG GENMASK(1, 0) |
129 | |
130 | #define R_AX_HCI_LDO_CTRL 0x007A |
131 | #define B_AX_R_AX_VADJ_MASK GENMASK(3, 0) |
132 | |
133 | #define R_AX_PLATFORM_ENABLE 0x0088 |
134 | #define B_AX_AXIDMA_EN BIT(3) |
135 | #define B_AX_APB_WRAP_EN BIT(2) |
136 | #define B_AX_WCPU_EN BIT(1) |
137 | #define B_AX_PLATFORM_EN BIT(0) |
138 | |
139 | #define R_AX_WLLPS_CTRL 0x0090 |
140 | #define B_AX_LPSOP_ASWRM BIT(17) |
141 | #define B_AX_LPSOP_DSWRM BIT(9) |
142 | #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1) |
143 | #define SW_LPS_OPTION 0x0001A0B2 |
144 | |
145 | #define R_AX_SCOREBOARD 0x00AC |
146 | #define B_AX_TOGGLE BIT(31) |
147 | #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24) |
148 | #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0) |
149 | #define B_MAC_AX_BTGS1_NOTIFY BIT(0) |
150 | #define MAC_AX_NOTIFY_TP_MAJOR 0x81 |
151 | #define MAC_AX_NOTIFY_PWR_MAJOR 0x80 |
152 | |
153 | #define R_AX_DBG_PORT_SEL 0x00C0 |
154 | #define B_AX_DEBUG_ST_MASK GENMASK(31, 0) |
155 | |
156 | #define R_AX_PMC_DBG_CTRL2 0x00CC |
157 | #define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2) |
158 | |
159 | #define R_AX_PCIE_MIO_INTF 0x00E4 |
160 | #define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16) |
161 | #define B_AX_PCIE_MIO_BYIOREG BIT(13) |
162 | #define B_AX_PCIE_MIO_RE BIT(12) |
163 | #define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8) |
164 | #define MIO_WRITE_BYTE_ALL 0xF |
165 | #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0) |
166 | #define MIO_ADDR_PAGE_MASK GENMASK(12, 8) |
167 | |
168 | #define R_AX_PCIE_MIO_INTD 0x00E8 |
169 | #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0) |
170 | |
171 | #define R_AX_SYS_CFG1 0x00F0 |
172 | #define B_AX_CHIP_VER_MASK GENMASK(15, 12) |
173 | |
174 | #define R_AX_SYS_STATUS1 0x00F4 |
175 | #define B_AX_SEL_0XC0_MASK GENMASK(17, 16) |
176 | #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3) |
177 | #define MAC_AX_HCI_SEL_SDIO_UART 0 |
178 | #define MAC_AX_HCI_SEL_MULTI_USB 1 |
179 | #define MAC_AX_HCI_SEL_PCIE_UART 2 |
180 | #define MAC_AX_HCI_SEL_PCIE_USB 3 |
181 | #define MAC_AX_HCI_SEL_MULTI_SDIO 4 |
182 | |
183 | #define R_AX_HALT_H2C_CTRL 0x0160 |
184 | #define R_AX_HALT_H2C 0x0168 |
185 | #define B_AX_HALT_H2C_TRIGGER BIT(0) |
186 | #define R_AX_HALT_C2H_CTRL 0x0164 |
187 | #define R_AX_HALT_C2H 0x016C |
188 | |
189 | #define R_AX_WCPU_FW_CTRL 0x01E0 |
190 | #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5) |
191 | #define B_AX_FWDL_PATH_RDY BIT(2) |
192 | #define B_AX_H2C_PATH_RDY BIT(1) |
193 | #define B_AX_WCPU_FWDL_EN BIT(0) |
194 | |
195 | #define R_AX_RPWM 0x01E4 |
196 | #define R_AX_PCIE_HRPWM 0x10C0 |
197 | #define PS_RPWM_TOGGLE BIT(15) |
198 | #define PS_RPWM_ACK BIT(14) |
199 | #define PS_RPWM_SEQ_NUM GENMASK(13, 12) |
200 | #define PS_RPWM_NOTIFY_WAKE BIT(8) |
201 | #define PS_RPWM_STATE 0x7 |
202 | #define RPWM_SEQ_NUM_MAX 3 |
203 | #define PS_CPWM_SEQ_NUM GENMASK(13, 12) |
204 | #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8) |
205 | #define PS_CPWM_STATE GENMASK(2, 0) |
206 | #define CPWM_SEQ_NUM_MAX 3 |
207 | |
208 | #define R_AX_BOOT_REASON 0x01E6 |
209 | #define B_AX_BOOT_REASON_MASK GENMASK(2, 0) |
210 | |
211 | #define R_AX_LDM 0x01E8 |
212 | #define B_AX_EN_32K BIT(31) |
213 | |
214 | #define R_AX_UDM0 0x01F0 |
215 | #define R_AX_UDM1 0x01F4 |
216 | #define B_AX_UDM1_MASK GENMASK(31, 16) |
217 | #define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12) |
218 | #define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8) |
219 | #define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4) |
220 | #define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0) |
221 | #define R_AX_UDM2 0x01F8 |
222 | #define R_AX_UDM3 0x01FC |
223 | |
224 | #define R_AX_SPS_DIG_ON_CTRL0 0x0200 |
225 | #define B_AX_VREFPFM_L_MASK GENMASK(25, 22) |
226 | #define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17) |
227 | #define B_AX_OCP_L1_MASK GENMASK(15, 13) |
228 | #define B_AX_VOL_L1_MASK GENMASK(3, 0) |
229 | |
230 | #define R_AX_SPSLDO_ON_CTRL1 0x0204 |
231 | #define B_AX_FPWMDELAY BIT(3) |
232 | |
233 | #define R_AX_LDO_AON_CTRL0 0x0218 |
234 | #define B_AX_PD_REGU_L BIT(16) |
235 | |
236 | #define R_AX_SPSANA_ON_CTRL1 0x0224 |
237 | |
238 | #define R_AX_WLAN_XTAL_SI_CTRL 0x0270 |
239 | #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31) |
240 | #define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30) |
241 | #define B_AX_WL_XTAL_GNT BIT(29) |
242 | #define B_AX_BT_XTAL_GNT BIT(28) |
243 | #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24) |
244 | #define XTAL_SI_NORMAL_WRITE 0x00 |
245 | #define XTAL_SI_NORMAL_READ 0x01 |
246 | #define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16) |
247 | #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8) |
248 | #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0) |
249 | |
250 | #define R_AX_WLAN_XTAL_SI_CONFIG 0x0274 |
251 | #define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0) |
252 | |
253 | #define R_AX_XTAL_ON_CTRL0 0x0280 |
254 | #define B_AX_XTAL_SC_LPS BIT(31) |
255 | #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17) |
256 | #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10) |
257 | #define B_AX_XTAL_SC_MASK GENMASK(6, 0) |
258 | |
259 | #define R_AX_XTAL_ON_CTRL3 0x028C |
260 | #define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24) |
261 | #define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16) |
262 | #define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8) |
263 | #define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0) |
264 | |
265 | #define R_AX_GPIO0_7_FUNC_SEL 0x02D0 |
266 | |
267 | #define R_AX_EECS_EESK_FUNC_SEL 0x02D8 |
268 | #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4) |
269 | |
270 | #define R_AX_GPIO16_23_FUNC_SEL 0x02D8 |
271 | #define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4) |
272 | #define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0) |
273 | |
274 | #define R_AX_LED1_FUNC_SEL 0x02DC |
275 | #define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24) |
276 | #define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1 |
277 | |
278 | #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 |
279 | #define B_AX_LED1_PULL_LOW_EN BIT(18) |
280 | #define B_AX_EESK_PULL_LOW_EN BIT(17) |
281 | #define B_AX_EECS_PULL_LOW_EN BIT(16) |
282 | |
283 | #define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 |
284 | #define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19) |
285 | #define B_AX_GPIO10_PULL_LOW_EN BIT(10) |
286 | |
287 | #define R_AX_WLRF_CTRL 0x02F0 |
288 | #define B_AX_AFC_AFEDIG BIT(17) |
289 | #define B_AX_WLRF1_CTRL_7 BIT(15) |
290 | #define B_AX_WLRF1_CTRL_1 BIT(9) |
291 | #define B_AX_WLRF_CTRL_7 BIT(7) |
292 | #define B_AX_WLRF_CTRL_1 BIT(1) |
293 | |
294 | #define R_AX_IC_PWR_STATE 0x03F0 |
295 | #define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16) |
296 | #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8) |
297 | #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6) |
298 | #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4) |
299 | #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2) |
300 | #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0) |
301 | |
302 | #define R_AX_SPS_DIG_OFF_CTRL0 0x0400 |
303 | #define B_AX_C3_L1_MASK GENMASK(5, 4) |
304 | #define B_AX_C1_L1_MASK GENMASK(1, 0) |
305 | |
306 | #define R_AX_AFE_OFF_CTRL1 0x0444 |
307 | #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24) |
308 | #define B_AX_S1_LDO2PWRCUT_F BIT(23) |
309 | #define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21) |
310 | |
311 | #define R_AX_SEC_CTRL 0x0C00 |
312 | #define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16) |
313 | |
314 | #define R_AX_FILTER_MODEL_ADDR 0x0C04 |
315 | |
316 | #define R_AX_HAXI_INIT_CFG1 0x1000 |
317 | #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28) |
318 | #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24) |
319 | #define B_AX_DMA_MODE_MASK GENMASK(19, 18) |
320 | #define DMA_MOD_PCIE_1B 0x0 |
321 | #define DMA_MOD_PCIE_4B 0x1 |
322 | #define DMA_MOD_USB 0x2 |
323 | #define DMA_MOD_SDIO 0x3 |
324 | #define B_AX_STOP_AXI_MST BIT(17) |
325 | #define B_AX_HAXI_RST_KEEP_REG BIT(16) |
326 | #define B_AX_RXHCI_EN_V1 BIT(15) |
327 | #define B_AX_RXBD_MODE_V1 BIT(14) |
328 | #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8) |
329 | #define B_AX_TXHCI_EN_V1 BIT(7) |
330 | #define B_AX_FLUSH_AXI_MST BIT(4) |
331 | #define B_AX_RST_BDRAM BIT(3) |
332 | #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0) |
333 | |
334 | #define R_AX_HAXI_DMA_STOP1 0x1010 |
335 | #define B_AX_STOP_WPDMA BIT(19) |
336 | #define B_AX_STOP_CH12 BIT(18) |
337 | #define B_AX_STOP_CH9 BIT(17) |
338 | #define B_AX_STOP_CH8 BIT(16) |
339 | #define B_AX_STOP_ACH7 BIT(15) |
340 | #define B_AX_STOP_ACH6 BIT(14) |
341 | #define B_AX_STOP_ACH5 BIT(13) |
342 | #define B_AX_STOP_ACH4 BIT(12) |
343 | #define B_AX_STOP_ACH3 BIT(11) |
344 | #define B_AX_STOP_ACH2 BIT(10) |
345 | #define B_AX_STOP_ACH1 BIT(9) |
346 | #define B_AX_STOP_ACH0 BIT(8) |
347 | |
348 | #define R_AX_HAXI_DMA_BUSY1 0x101C |
349 | #define B_AX_HAXIIO_BUSY BIT(20) |
350 | #define B_AX_WPDMA_BUSY BIT(19) |
351 | #define B_AX_CH12_BUSY BIT(18) |
352 | #define B_AX_CH9_BUSY BIT(17) |
353 | #define B_AX_CH8_BUSY BIT(16) |
354 | #define B_AX_ACH7_BUSY BIT(15) |
355 | #define B_AX_ACH6_BUSY BIT(14) |
356 | #define B_AX_ACH5_BUSY BIT(13) |
357 | #define B_AX_ACH4_BUSY BIT(12) |
358 | #define B_AX_ACH3_BUSY BIT(11) |
359 | #define B_AX_ACH2_BUSY BIT(10) |
360 | #define B_AX_ACH1_BUSY BIT(9) |
361 | #define B_AX_ACH0_BUSY BIT(8) |
362 | |
363 | #define R_AX_PCIE_DBG_CTRL 0x11C0 |
364 | #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16) |
365 | #define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13) |
366 | #define B_AX_MRD_TIMEOUT_EN BIT(10) |
367 | #define B_AX_ASFF_FULL_NO_STK BIT(1) |
368 | #define B_AX_EN_STUCK_DBG BIT(0) |
369 | |
370 | #define R_AX_HAXI_DMA_STOP2 0x11C0 |
371 | #define B_AX_STOP_CH11 BIT(1) |
372 | #define B_AX_STOP_CH10 BIT(0) |
373 | |
374 | #define R_AX_HAXI_DMA_BUSY2 0x11C8 |
375 | #define B_AX_CH11_BUSY BIT(1) |
376 | #define B_AX_CH10_BUSY BIT(0) |
377 | |
378 | #define R_AX_HAXI_DMA_BUSY3 0x1208 |
379 | #define B_AX_RPQ_BUSY BIT(1) |
380 | #define B_AX_RXQ_BUSY BIT(0) |
381 | |
382 | #define R_AX_LTR_DEC_CTRL 0x1600 |
383 | #define B_AX_LTR_IDX_DRV_VLD BIT(16) |
384 | #define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14) |
385 | #define B_AX_LTR_IDX_FW_VLD BIT(13) |
386 | #define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11) |
387 | #define B_AX_LTR_IDX_HW_VLD BIT(10) |
388 | #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8) |
389 | #define B_AX_LTR_REQ_DRV BIT(7) |
390 | #define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5) |
391 | #define PCIE_LTR_IDX_IDLE 3 |
392 | #define B_AX_LTR_DRV_DEC_EN BIT(4) |
393 | #define B_AX_LTR_FW_DEC_EN BIT(3) |
394 | #define B_AX_LTR_HW_DEC_EN BIT(2) |
395 | #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0) |
396 | #define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN) |
397 | |
398 | #define R_AX_LTR_LATENCY_IDX0 0x1604 |
399 | #define R_AX_LTR_LATENCY_IDX1 0x1608 |
400 | #define R_AX_LTR_LATENCY_IDX2 0x160C |
401 | #define R_AX_LTR_LATENCY_IDX3 0x1610 |
402 | |
403 | #define R_AX_HCI_FC_CTRL_V1 0x1700 |
404 | #define R_AX_CH_PAGE_CTRL_V1 0x1704 |
405 | |
406 | #define R_AX_ACH0_PAGE_CTRL_V1 0x1710 |
407 | #define R_AX_ACH1_PAGE_CTRL_V1 0x1714 |
408 | #define R_AX_ACH2_PAGE_CTRL_V1 0x1718 |
409 | #define R_AX_ACH3_PAGE_CTRL_V1 0x171C |
410 | #define R_AX_ACH4_PAGE_CTRL_V1 0x1720 |
411 | #define R_AX_ACH5_PAGE_CTRL_V1 0x1724 |
412 | #define R_AX_ACH6_PAGE_CTRL_V1 0x1728 |
413 | #define R_AX_ACH7_PAGE_CTRL_V1 0x172C |
414 | #define R_AX_CH8_PAGE_CTRL_V1 0x1730 |
415 | #define R_AX_CH9_PAGE_CTRL_V1 0x1734 |
416 | #define R_AX_CH10_PAGE_CTRL_V1 0x1738 |
417 | #define R_AX_CH11_PAGE_CTRL_V1 0x173C |
418 | |
419 | #define R_AX_ACH0_PAGE_INFO_V1 0x1750 |
420 | #define R_AX_ACH1_PAGE_INFO_V1 0x1754 |
421 | #define R_AX_ACH2_PAGE_INFO_V1 0x1758 |
422 | #define R_AX_ACH3_PAGE_INFO_V1 0x175C |
423 | #define R_AX_ACH4_PAGE_INFO_V1 0x1760 |
424 | #define R_AX_ACH5_PAGE_INFO_V1 0x1764 |
425 | #define R_AX_ACH6_PAGE_INFO_V1 0x1768 |
426 | #define R_AX_ACH7_PAGE_INFO_V1 0x176C |
427 | #define R_AX_CH8_PAGE_INFO_V1 0x1770 |
428 | #define R_AX_CH9_PAGE_INFO_V1 0x1774 |
429 | #define R_AX_CH10_PAGE_INFO_V1 0x1778 |
430 | #define R_AX_CH11_PAGE_INFO_V1 0x177C |
431 | #define R_AX_CH12_PAGE_INFO_V1 0x1780 |
432 | |
433 | #define R_AX_PUB_PAGE_INFO3_V1 0x178C |
434 | #define R_AX_PUB_PAGE_CTRL1_V1 0x1790 |
435 | #define R_AX_PUB_PAGE_CTRL2_V1 0x1794 |
436 | #define R_AX_PUB_PAGE_INFO1_V1 0x1798 |
437 | #define R_AX_PUB_PAGE_INFO2_V1 0x179C |
438 | #define R_AX_WP_PAGE_CTRL1_V1 0x17A0 |
439 | #define R_AX_WP_PAGE_CTRL2_V1 0x17A4 |
440 | #define R_AX_WP_PAGE_INFO1_V1 0x17A8 |
441 | |
442 | #define R_AX_H2CREG_DATA0_V1 0x7140 |
443 | #define R_AX_H2CREG_DATA1_V1 0x7144 |
444 | #define R_AX_H2CREG_DATA2_V1 0x7148 |
445 | #define R_AX_H2CREG_DATA3_V1 0x714C |
446 | #define R_AX_C2HREG_DATA0_V1 0x7150 |
447 | #define R_AX_C2HREG_DATA1_V1 0x7154 |
448 | #define R_AX_C2HREG_DATA2_V1 0x7158 |
449 | #define R_AX_C2HREG_DATA3_V1 0x715C |
450 | #define R_AX_H2CREG_CTRL_V1 0x7160 |
451 | #define R_AX_C2HREG_CTRL_V1 0x7164 |
452 | |
453 | #define R_AX_HCI_FUNC_EN_V1 0x7880 |
454 | |
455 | #define R_AX_PHYREG_SET 0x8040 |
456 | #define PHYREG_SET_ALL_CYCLE 0x8 |
457 | #define PHYREG_SET_XYN_CYCLE 0xE |
458 | |
459 | #define R_AX_HD0IMR 0x8110 |
460 | #define B_AX_WDT_PTFM_INT_EN BIT(5) |
461 | #define B_AX_CPWM_INT_EN BIT(2) |
462 | #define B_AX_GT3_INT_EN BIT(1) |
463 | #define B_AX_C2H_INT_EN BIT(0) |
464 | #define R_AX_HD0ISR 0x8114 |
465 | #define B_AX_C2H_INT BIT(0) |
466 | |
467 | #define R_AX_H2CREG_DATA0 0x8140 |
468 | #define R_AX_H2CREG_DATA1 0x8144 |
469 | #define R_AX_H2CREG_DATA2 0x8148 |
470 | #define R_AX_H2CREG_DATA3 0x814C |
471 | #define R_AX_C2HREG_DATA0 0x8150 |
472 | #define R_AX_C2HREG_DATA1 0x8154 |
473 | #define R_AX_C2HREG_DATA2 0x8158 |
474 | #define R_AX_C2HREG_DATA3 0x815C |
475 | #define R_AX_H2CREG_CTRL 0x8160 |
476 | #define B_AX_H2CREG_TRIGGER BIT(0) |
477 | #define R_AX_C2HREG_CTRL 0x8164 |
478 | #define B_AX_C2HREG_TRIGGER BIT(0) |
479 | #define R_AX_CPWM 0x8170 |
480 | |
481 | #define R_AX_HCI_FUNC_EN 0x8380 |
482 | #define B_AX_HCI_RXDMA_EN BIT(1) |
483 | #define B_AX_HCI_TXDMA_EN BIT(0) |
484 | |
485 | #define R_AX_BOOT_DBG 0x83F0 |
486 | |
487 | #define R_AX_DMAC_FUNC_EN 0x8400 |
488 | #define B_AX_DMAC_CRPRT BIT(31) |
489 | #define B_AX_MAC_FUNC_EN BIT(30) |
490 | #define B_AX_DMAC_FUNC_EN BIT(29) |
491 | #define B_AX_MPDU_PROC_EN BIT(28) |
492 | #define B_AX_WD_RLS_EN BIT(27) |
493 | #define B_AX_DLE_WDE_EN BIT(26) |
494 | #define B_AX_TXPKT_CTRL_EN BIT(25) |
495 | #define B_AX_STA_SCH_EN BIT(24) |
496 | #define B_AX_DLE_PLE_EN BIT(23) |
497 | #define B_AX_PKT_BUF_EN BIT(22) |
498 | #define B_AX_DMAC_TBL_EN BIT(21) |
499 | #define B_AX_PKT_IN_EN BIT(20) |
500 | #define B_AX_DLE_CPUIO_EN BIT(19) |
501 | #define B_AX_DISPATCHER_EN BIT(18) |
502 | #define B_AX_BBRPT_EN BIT(17) |
503 | #define B_AX_MAC_SEC_EN BIT(16) |
504 | #define B_AX_DMACREG_GCKEN BIT(15) |
505 | #define B_AX_MAC_UN_EN BIT(15) |
506 | #define B_AX_H_AXIDMA_EN BIT(14) |
507 | |
508 | #define R_AX_DMAC_CLK_EN 0x8404 |
509 | #define B_AX_WD_RLS_CLK_EN BIT(27) |
510 | #define B_AX_DLE_WDE_CLK_EN BIT(26) |
511 | #define B_AX_TXPKT_CTRL_CLK_EN BIT(25) |
512 | #define B_AX_STA_SCH_CLK_EN BIT(24) |
513 | #define B_AX_DLE_PLE_CLK_EN BIT(23) |
514 | #define B_AX_PKT_IN_CLK_EN BIT(20) |
515 | #define B_AX_DLE_CPUIO_CLK_EN BIT(19) |
516 | #define B_AX_DISPATCHER_CLK_EN BIT(18) |
517 | #define B_AX_BBRPT_CLK_EN BIT(17) |
518 | #define B_AX_MAC_SEC_CLK_EN BIT(16) |
519 | #define B_AX_AXIDMA_CLK_EN BIT(9) |
520 | |
521 | #define PCI_LTR_IDLE_TIMER_1US 0 |
522 | #define PCI_LTR_IDLE_TIMER_10US 1 |
523 | #define PCI_LTR_IDLE_TIMER_100US 2 |
524 | #define PCI_LTR_IDLE_TIMER_200US 3 |
525 | #define PCI_LTR_IDLE_TIMER_400US 4 |
526 | #define PCI_LTR_IDLE_TIMER_800US 5 |
527 | #define PCI_LTR_IDLE_TIMER_1_6MS 6 |
528 | #define PCI_LTR_IDLE_TIMER_3_2MS 7 |
529 | #define PCI_LTR_IDLE_TIMER_R_ERR 0xFD |
530 | #define PCI_LTR_IDLE_TIMER_DEF 0xFE |
531 | #define PCI_LTR_IDLE_TIMER_IGNORE 0xFF |
532 | |
533 | #define PCI_LTR_SPC_10US 0 |
534 | #define PCI_LTR_SPC_100US 1 |
535 | #define PCI_LTR_SPC_500US 2 |
536 | #define PCI_LTR_SPC_1MS 3 |
537 | #define PCI_LTR_SPC_R_ERR 0xFD |
538 | #define PCI_LTR_SPC_DEF 0xFE |
539 | #define PCI_LTR_SPC_IGNORE 0xFF |
540 | |
541 | #define R_AX_LTR_CTRL_0 0x8410 |
542 | #define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12) |
543 | #define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) |
544 | #define B_AX_LTR_WD_NOEMP_CHK BIT(6) |
545 | #define B_AX_APP_LTR_ACT BIT(5) |
546 | #define B_AX_APP_LTR_IDLE BIT(4) |
547 | #define B_AX_LTR_EN BIT(1) |
548 | #define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1) |
549 | #define B_AX_LTR_HW_EN BIT(0) |
550 | |
551 | #define R_AX_LTR_CTRL_1 0x8414 |
552 | #define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16) |
553 | #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0) |
554 | |
555 | #define R_AX_LTR_IDLE_LATENCY 0x8418 |
556 | |
557 | #define R_AX_LTR_ACTIVE_LATENCY 0x841C |
558 | |
559 | #define R_AX_SER_DBG_INFO 0x8424 |
560 | #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28) |
561 | |
562 | #define R_AX_DLE_EMPTY0 0x8430 |
563 | #define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) |
564 | #define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) |
565 | #define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) |
566 | #define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23) |
567 | #define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) |
568 | #define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) |
569 | #define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) |
570 | #define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) |
571 | #define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) |
572 | #define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) |
573 | #define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16) |
574 | #define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) |
575 | #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) |
576 | #define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) |
577 | #define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7) |
578 | #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) |
579 | #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) |
580 | #define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) |
581 | #define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) |
582 | #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) |
583 | |
584 | #define R_AX_DLE_EMPTY1 0x8434 |
585 | #define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20) |
586 | #define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19) |
587 | #define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18) |
588 | #define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17) |
589 | #define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16) |
590 | #define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5) |
591 | #define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4) |
592 | #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3) |
593 | #define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2) |
594 | #define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1) |
595 | #define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0) |
596 | |
597 | #define R_AX_DMAC_ERR_IMR 0x8520 |
598 | #define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10) |
599 | #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9) |
600 | #define B_AX_DISPATCH_ERR_INT_EN BIT(8) |
601 | #define B_AX_PKTIN_ERR_INT_EN BIT(7) |
602 | #define B_AX_PLE_DLE_ERR_INT_EN BIT(6) |
603 | #define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5) |
604 | #define B_AX_WDE_DLE_ERR_INT_EN BIT(4) |
605 | #define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3) |
606 | #define B_AX_MPDU_ERR_INT_EN BIT(2) |
607 | #define B_AX_WSEC_ERR_INT_EN BIT(1) |
608 | #define B_AX_WDRLS_ERR_INT_EN BIT(0) |
609 | #define DMAC_ERR_IMR_EN GENMASK(31, 0) |
610 | #define DMAC_ERR_IMR_DIS 0 |
611 | |
612 | #define R_AX_DMAC_ERR_ISR 0x8524 |
613 | #define B_AX_HAXIDMA_ERR_FLAG BIT(14) |
614 | #define B_AX_PAXIDMA_ERR_FLAG BIT(13) |
615 | #define B_AX_HCI_BUF_ERR_FLAG BIT(12) |
616 | #define B_AX_BBRPT_ERR_FLAG BIT(11) |
617 | #define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) |
618 | #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) |
619 | #define B_AX_DISPATCH_ERR_FLAG BIT(8) |
620 | #define B_AX_PKTIN_ERR_FLAG BIT(7) |
621 | #define B_AX_PLE_DLE_ERR_FLAG BIT(6) |
622 | #define B_AX_TXPKTCTRL_ERR_FLAG BIT(5) |
623 | #define B_AX_WDE_DLE_ERR_FLAG BIT(4) |
624 | #define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3) |
625 | #define B_AX_MPDU_ERR_FLAG BIT(2) |
626 | #define B_AX_WSEC_ERR_FLAG BIT(1) |
627 | #define B_AX_WDRLS_ERR_FLAG BIT(0) |
628 | |
629 | #define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800 |
630 | #define B_AX_PL_PAGE_128B_SEL BIT(9) |
631 | #define B_AX_WD_PAGE_64B_SEL BIT(8) |
632 | #define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804 |
633 | #define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808 |
634 | #define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C |
635 | #define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810 |
636 | #define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0) |
637 | |
638 | #define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850 |
639 | #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31) |
640 | #define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30) |
641 | #define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29) |
642 | #define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) |
643 | #define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27) |
644 | #define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26) |
645 | #define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25) |
646 | #define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24) |
647 | #define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21) |
648 | #define B_AX_HDT_RES_ERR_INT_EN BIT(20) |
649 | #define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19) |
650 | #define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18) |
651 | #define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17) |
652 | #define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16) |
653 | #define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15) |
654 | #define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14) |
655 | #define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13) |
656 | #define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12) |
657 | #define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11) |
658 | #define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10) |
659 | #define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9) |
660 | #define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8) |
661 | #define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7) |
662 | #define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6) |
663 | #define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5) |
664 | #define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4) |
665 | #define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3) |
666 | #define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2) |
667 | #define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1) |
668 | #define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0) |
669 | #define B_AX_HOST_DISP_IMR_CLR (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \ |
670 | B_AX_HDT_CHANNEL_ID_ERR_INT_EN | \ |
671 | B_AX_HDT_PKT_FAIL_DBG_INT_EN | \ |
672 | B_AX_HDT_PERMU_OVERFLOW_INT_EN | \ |
673 | B_AX_HDT_PERMU_UNDERFLOW_INT_EN | \ |
674 | B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \ |
675 | B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \ |
676 | B_AX_HDT_OFFSET_UNMATCH_INT_EN | \ |
677 | B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \ |
678 | B_AX_HDT_WD_CHK_ERR_INT_EN | \ |
679 | B_AX_HDT_PRE_COST_ERR_INT_EN | \ |
680 | B_AX_HDT_TXPKTSIZE_ERR_INT_EN | \ |
681 | B_AX_HDT_TCP_CHK_ERR_INT_EN | \ |
682 | B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | \ |
683 | B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | \ |
684 | B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | \ |
685 | B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | \ |
686 | B_AX_HDT_FLOW_CTRL_ERR_INT_EN | \ |
687 | B_AX_HDT_NULLPKT_ERR_INT_EN | \ |
688 | B_AX_HDT_BURST_NUM_ERR_INT_EN | \ |
689 | B_AX_HDT_RXAGG_CFG_ERR_INT_EN | \ |
690 | B_AX_HDT_SHIFT_EN_ERR_INT_EN | \ |
691 | B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \ |
692 | B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \ |
693 | B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | \ |
694 | B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | \ |
695 | B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \ |
696 | B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN) |
697 | #define B_AX_HOST_DISP_IMR_SET (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \ |
698 | B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \ |
699 | B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \ |
700 | B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \ |
701 | B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \ |
702 | B_AX_HDT_DMA_PROCESS_ERR_INT_EN) |
703 | |
704 | #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31) |
705 | #define B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30) |
706 | #define B_AX_HR_CHKSUM_FSM_ERR_INT_EN BIT(29) |
707 | #define B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) |
708 | #define B_AX_HR_DMA_PROCESS_ERR_INT_EN BIT(27) |
709 | #define B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26) |
710 | #define B_AX_HR_SHIFT_EN_ERR_INT_EN BIT(25) |
711 | #define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24) |
712 | #define B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN BIT(23) |
713 | #define B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22) |
714 | #define B_AX_HT_ILL_CH_ERR_INT_EN BIT(20) |
715 | #define B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18) |
716 | #define B_AX_HT_WD_LEN_OVER_ERR_INT_EN BIT(17) |
717 | #define B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16) |
718 | #define B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15) |
719 | #define B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14) |
720 | #define B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13) |
721 | #define B_AX_HT_CHKSUM_FSM_ERR_INT_EN BIT(12) |
722 | #define B_AX_HT_TXPKTSIZE_ERR_INT_EN BIT(11) |
723 | #define B_AX_HT_PRE_SUB_ERR_INT_EN BIT(10) |
724 | #define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9) |
725 | #define B_AX_HT_CHANNEL_DMA_ERR_INT_EN BIT(8) |
726 | #define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7) |
727 | #define B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) |
728 | #define B_AX_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5) |
729 | #define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) |
730 | #define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) |
731 | #define B_AX_HT_PKT_FAIL_ERR_INT_EN BIT(2) |
732 | #define B_AX_HT_CH_ID_ERR_INT_EN BIT(1) |
733 | #define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0) |
734 | #define B_AX_HOST_DISP_IMR_CLR_V1 (B_AX_HT_EP_CH_DIFF_ERR_INT_EN | \ |
735 | B_AX_HT_CH_ID_ERR_INT_EN | \ |
736 | B_AX_HT_PKT_FAIL_ERR_INT_EN | \ |
737 | B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ |
738 | B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ |
739 | B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \ |
740 | B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \ |
741 | B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN | \ |
742 | B_AX_HT_CHANNEL_DMA_ERR_INT_EN | \ |
743 | B_AX_HT_WD_CHKSUM_ERR_INT_EN | \ |
744 | B_AX_HT_PRE_SUB_ERR_INT_EN | \ |
745 | B_AX_HT_TXPKTSIZE_ERR_INT_EN | \ |
746 | B_AX_HT_CHKSUM_FSM_ERR_INT_EN | \ |
747 | B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN | \ |
748 | B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN | \ |
749 | B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ |
750 | B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ |
751 | B_AX_HT_WD_LEN_OVER_ERR_INT_EN | \ |
752 | B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN | \ |
753 | B_AX_HT_ILL_CH_ERR_INT_EN | \ |
754 | B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN | \ |
755 | B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN | \ |
756 | B_AX_HR_AGG_CFG_ERR_INT_EN | \ |
757 | B_AX_HR_SHIFT_EN_ERR_INT_EN | \ |
758 | B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ |
759 | B_AX_HR_DMA_PROCESS_ERR_INT_EN | \ |
760 | B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN | \ |
761 | B_AX_HR_CHKSUM_FSM_ERR_INT_EN | \ |
762 | B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN | \ |
763 | B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN) |
764 | #define B_AX_HOST_DISP_IMR_SET_V1 (B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \ |
765 | B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \ |
766 | B_AX_HT_ILL_CH_ERR_INT_EN | \ |
767 | B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ |
768 | B_AX_HR_DMA_PROCESS_ERR_INT_EN) |
769 | |
770 | #define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854 |
771 | #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31) |
772 | #define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30) |
773 | #define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29) |
774 | #define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) |
775 | #define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27) |
776 | #define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26) |
777 | #define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25) |
778 | #define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24) |
779 | #define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20) |
780 | #define B_AX_CPU_RESP_ERR_INT_EN BIT(19) |
781 | #define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18) |
782 | #define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17) |
783 | #define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16) |
784 | #define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15) |
785 | #define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14) |
786 | #define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13) |
787 | #define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12) |
788 | #define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11) |
789 | #define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10) |
790 | #define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9) |
791 | #define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8) |
792 | #define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) |
793 | #define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6) |
794 | #define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5) |
795 | #define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4) |
796 | #define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3) |
797 | #define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2) |
798 | #define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1) |
799 | #define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0) |
800 | #define B_AX_CPU_DISP_IMR_CLR (B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | \ |
801 | B_AX_CPU_PKT_FAIL_DBG_INT_EN | \ |
802 | B_AX_CPU_CHANNEL_ID_ERR_INT_EN | \ |
803 | B_AX_CPU_PERMU_OVERFLOW_INT_EN | \ |
804 | B_AX_CPU_PERMU_UNDERFLOW_INT_EN | \ |
805 | B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \ |
806 | B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \ |
807 | B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | \ |
808 | B_AX_CPU_OFFSET_UNMATCH_INT_EN | \ |
809 | B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | \ |
810 | B_AX_CPU_WD_CHK_ERR_INT_EN | \ |
811 | B_AX_CPU_PRE_COST_ERR_INT_EN | \ |
812 | B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | \ |
813 | B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | \ |
814 | B_AX_CPU_F2P_QSEL_ERR_INT_EN | \ |
815 | B_AX_CPU_F2P_SEQ_ERR_INT_EN | \ |
816 | B_AX_CPU_FLOW_CTRL_ERR_INT_EN | \ |
817 | B_AX_CPU_NULLPKT_ERR_INT_EN | \ |
818 | B_AX_CPU_BURST_NUM_ERR_INT_EN | \ |
819 | B_AX_CPU_RXAGG_CFG_ERR_INT_EN | \ |
820 | B_AX_CPU_SHIFT_EN_ERR_INT_EN | \ |
821 | B_AX_CPU_TOTAL_LEN_ERR_INT_EN | \ |
822 | B_AX_CPU_DMA_PROCESS_ERR_INT_EN | \ |
823 | B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | \ |
824 | B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | \ |
825 | B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | \ |
826 | B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN) |
827 | #define B_AX_CPU_DISP_IMR_SET (B_AX_CPU_PKT_FAIL_DBG_INT_EN | \ |
828 | B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \ |
829 | B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \ |
830 | B_AX_CPU_TOTAL_LEN_ERR_INT_EN) |
831 | |
832 | #define B_AX_CR_PLD_LEN_ERR_INT_EN BIT(30) |
833 | #define B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29) |
834 | #define B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28) |
835 | #define B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27) |
836 | #define B_AX_CR_DMA_PROCESS_ERR_INT_EN BIT(26) |
837 | #define B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25) |
838 | #define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24) |
839 | #define B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22) |
840 | #define B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21) |
841 | #define B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20) |
842 | #define B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19) |
843 | #define B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17) |
844 | #define B_AX_CT_WD_LEN_OVER_ERR_INT_EN BIT(16) |
845 | #define B_AX_CT_F2P_SEQ_ERR_INT_EN BIT(15) |
846 | #define B_AX_CT_F2P_QSEL_ERR_INT_EN BIT(14) |
847 | #define B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13) |
848 | #define B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12) |
849 | #define B_AX_CT_PRE_SUB_ERR_INT_EN BIT(11) |
850 | #define B_AX_CT_WD_CHKSUM_ERR_INT_EN BIT(10) |
851 | #define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9) |
852 | #define B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8) |
853 | #define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) |
854 | #define B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) |
855 | #define B_AX_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5) |
856 | #define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) |
857 | #define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) |
858 | #define B_AX_CT_CH_ID_ERR_INT_EN BIT(2) |
859 | #define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0) |
860 | #define B_AX_CPU_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \ |
861 | B_AX_CT_CH_ID_ERR_INT_EN | \ |
862 | B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ |
863 | B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ |
864 | B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \ |
865 | B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \ |
866 | B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN | \ |
867 | B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN | \ |
868 | B_AX_CT_CHANNEL_DMA_ERR_INT_EN | \ |
869 | B_AX_CT_WD_CHKSUM_ERR_INT_EN | \ |
870 | B_AX_CT_PRE_SUB_ERR_INT_EN | \ |
871 | B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ |
872 | B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ |
873 | B_AX_CT_F2P_QSEL_ERR_INT_EN | \ |
874 | B_AX_CT_F2P_SEQ_ERR_INT_EN | \ |
875 | B_AX_CT_WD_LEN_OVER_ERR_INT_EN | \ |
876 | B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \ |
877 | B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN | \ |
878 | B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN | \ |
879 | B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN | \ |
880 | B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN | \ |
881 | B_AX_CR_SHIFT_EN_ERR_INT_EN | \ |
882 | B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \ |
883 | B_AX_CR_DMA_PROCESS_ERR_INT_EN | \ |
884 | B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN | \ |
885 | B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \ |
886 | B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN | \ |
887 | B_AX_CR_PLD_LEN_ERR_INT_EN) |
888 | #define B_AX_CPU_DISP_IMR_SET_V1 (B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \ |
889 | B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \ |
890 | B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \ |
891 | B_AX_CR_DMA_PROCESS_ERR_INT_EN | \ |
892 | B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \ |
893 | B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN) |
894 | |
895 | #define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858 |
896 | #define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29) |
897 | #define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28) |
898 | #define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27) |
899 | #define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26) |
900 | #define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25) |
901 | #define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24) |
902 | #define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17) |
903 | #define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16) |
904 | #define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12) |
905 | #define B_AX_PLE_RESP_ERR_INT_EN BIT(11) |
906 | #define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10) |
907 | #define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9) |
908 | #define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8) |
909 | #define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4) |
910 | #define B_AX_WDE_RESP_ERR_INT_EN BIT(3) |
911 | #define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2) |
912 | #define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1) |
913 | #define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0) |
914 | #define B_AX_OTHER_DISP_IMR_CLR (B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | \ |
915 | B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | \ |
916 | B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | \ |
917 | B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | \ |
918 | B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | \ |
919 | B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | \ |
920 | B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \ |
921 | B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \ |
922 | B_AX_PLE_OUTPUT_ERR_INT_EN | \ |
923 | B_AX_PLE_RESP_ERR_INT_EN | \ |
924 | B_AX_PLE_BURST_NUM_ERR_INT_EN | \ |
925 | B_AX_PLE_NULL_PKT_ERR_INT_EN | \ |
926 | B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \ |
927 | B_AX_WDE_OUTPUT_ERR_INT_EN | \ |
928 | B_AX_WDE_RESP_ERR_INT_EN | \ |
929 | B_AX_WDE_BURST_NUM_ERR_INT_EN | \ |
930 | B_AX_WDE_NULL_PKT_ERR_INT_EN | \ |
931 | B_AX_WDE_FLOW_CTRL_ERR_INT_EN) |
932 | |
933 | #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31) |
934 | #define B_AX_REUSE_EN_ERR_INT_EN BIT(30) |
935 | #define B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29) |
936 | #define B_AX_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28) |
937 | #define B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27) |
938 | #define B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26) |
939 | #define B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25) |
940 | #define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24) |
941 | #define B_AX_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23) |
942 | #define B_AX_REUSE_PKT_CNT_ERR_INT_EN BIT(22) |
943 | #define B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21) |
944 | #define B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20) |
945 | #define B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19) |
946 | #define B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18) |
947 | #define B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17) |
948 | #define B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16) |
949 | #define B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15) |
950 | #define B_AX_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14) |
951 | #define B_AX_PLE_RESPOSE_ERR_INT_EN BIT(11) |
952 | #define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7) |
953 | #define B_AX_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6) |
954 | #define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3) |
955 | #define B_AX_OTHER_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \ |
956 | B_AX_WDE_FLOW_CTRL_ERR_INT_EN | \ |
957 | B_AX_WDE_NULL_PKT_ERR_INT_EN | \ |
958 | B_AX_WDE_BURST_NUM_ERR_INT_EN | \ |
959 | B_AX_WDE_RESPONSE_ERR_INT_EN | \ |
960 | B_AX_WDE_OUTPUT_ERR_INT_EN | \ |
961 | B_AX_HDR_RX_TIMEOUT_ERR_INT_EN | \ |
962 | B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN | \ |
963 | B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \ |
964 | B_AX_PLE_NULL_PKT_ERR_INT_EN | \ |
965 | B_AX_PLE_BURST_NUM_ERR_INT_EN | \ |
966 | B_AX_PLE_RESPOSE_ERR_INT_EN | \ |
967 | B_AX_PLE_OUTPUT_ERR_INT_EN | \ |
968 | B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \ |
969 | B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \ |
970 | B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN | \ |
971 | B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN | \ |
972 | B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \ |
973 | B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \ |
974 | B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \ |
975 | B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \ |
976 | B_AX_REUSE_PKT_CNT_ERR_INT_EN | \ |
977 | B_AX_REUSE_SIZE_ZERO_ERR_INT_EN | \ |
978 | B_AX_STF_CMD_OVERFLOW_ERR_INT_EN | \ |
979 | B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN | \ |
980 | B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN | \ |
981 | B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN | \ |
982 | B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \ |
983 | B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN | \ |
984 | B_AX_REUSE_EN_ERR_INT_EN | \ |
985 | B_AX_REUSE_SIZE_ERR_INT_EN) |
986 | #define B_AX_OTHER_DISP_IMR_SET_V1 (B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \ |
987 | B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \ |
988 | B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \ |
989 | B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \ |
990 | B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \ |
991 | B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \ |
992 | B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \ |
993 | B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN) |
994 | |
995 | #define R_AX_DISPATCHER_DBG_PORT 0x8860 |
996 | #define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8) |
997 | #define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4) |
998 | #define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0) |
999 | |
1000 | #define R_AX_RX_FUNCTION_STOP 0x8920 |
1001 | #define B_AX_HDR_RX_STOP BIT(0) |
1002 | |
1003 | #define R_AX_HCI_FC_CTRL 0x8A00 |
1004 | #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10) |
1005 | #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8) |
1006 | #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6) |
1007 | #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4) |
1008 | #define B_AX_HCI_FC_CH12_EN BIT(3) |
1009 | #define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1) |
1010 | #define B_AX_HCI_FC_EN BIT(0) |
1011 | |
1012 | #define R_AX_CH_PAGE_CTRL 0x8A04 |
1013 | #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16) |
1014 | #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0) |
1015 | |
1016 | #define B_AX_MAX_PG_MASK GENMASK(28, 16) |
1017 | #define B_AX_MIN_PG_MASK GENMASK(12, 0) |
1018 | #define B_AX_GRP BIT(31) |
1019 | #define R_AX_ACH0_PAGE_CTRL 0x8A10 |
1020 | #define R_AX_ACH1_PAGE_CTRL 0x8A14 |
1021 | #define R_AX_ACH2_PAGE_CTRL 0x8A18 |
1022 | #define R_AX_ACH3_PAGE_CTRL 0x8A1C |
1023 | #define R_AX_ACH4_PAGE_CTRL 0x8A20 |
1024 | #define R_AX_ACH5_PAGE_CTRL 0x8A24 |
1025 | #define R_AX_ACH6_PAGE_CTRL 0x8A28 |
1026 | #define R_AX_ACH7_PAGE_CTRL 0x8A2C |
1027 | #define R_AX_CH8_PAGE_CTRL 0x8A30 |
1028 | #define R_AX_CH9_PAGE_CTRL 0x8A34 |
1029 | #define R_AX_CH10_PAGE_CTRL 0x8A38 |
1030 | #define R_AX_CH11_PAGE_CTRL 0x8A3C |
1031 | |
1032 | #define B_AX_AVAL_PG_MASK GENMASK(27, 16) |
1033 | #define B_AX_USE_PG_MASK GENMASK(12, 0) |
1034 | #define R_AX_ACH0_PAGE_INFO 0x8A50 |
1035 | #define R_AX_ACH1_PAGE_INFO 0x8A54 |
1036 | #define R_AX_ACH2_PAGE_INFO 0x8A58 |
1037 | #define R_AX_ACH3_PAGE_INFO 0x8A5C |
1038 | #define R_AX_ACH4_PAGE_INFO 0x8A60 |
1039 | #define R_AX_ACH5_PAGE_INFO 0x8A64 |
1040 | #define R_AX_ACH6_PAGE_INFO 0x8A68 |
1041 | #define R_AX_ACH7_PAGE_INFO 0x8A6C |
1042 | #define R_AX_CH8_PAGE_INFO 0x8A70 |
1043 | #define R_AX_CH9_PAGE_INFO 0x8A74 |
1044 | #define R_AX_CH10_PAGE_INFO 0x8A78 |
1045 | #define R_AX_CH11_PAGE_INFO 0x8A7C |
1046 | #define R_AX_CH12_PAGE_INFO 0x8A80 |
1047 | |
1048 | #define R_AX_PUB_PAGE_INFO3 0x8A8C |
1049 | #define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16) |
1050 | #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0) |
1051 | |
1052 | #define R_AX_PUB_PAGE_CTRL1 0x8A90 |
1053 | #define B_AX_PUBPG_G1_MASK GENMASK(28, 16) |
1054 | #define B_AX_PUBPG_G0_MASK GENMASK(12, 0) |
1055 | |
1056 | #define R_AX_PUB_PAGE_CTRL2 0x8A94 |
1057 | #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0) |
1058 | |
1059 | #define R_AX_PUB_PAGE_INFO1 0x8A98 |
1060 | #define B_AX_G1_USE_PG_MASK GENMASK(28, 16) |
1061 | #define B_AX_G0_USE_PG_MASK GENMASK(12, 0) |
1062 | |
1063 | #define R_AX_PUB_PAGE_INFO2 0x8A9C |
1064 | #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0) |
1065 | |
1066 | #define R_AX_WP_PAGE_CTRL1 0x8AA0 |
1067 | #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16) |
1068 | #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0) |
1069 | |
1070 | #define R_AX_WP_PAGE_CTRL2 0x8AA4 |
1071 | #define B_AX_WP_THRD_MASK GENMASK(12, 0) |
1072 | |
1073 | #define R_AX_WP_PAGE_INFO1 0x8AA8 |
1074 | #define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16) |
1075 | |
1076 | #define R_AX_WDE_PKTBUF_CFG 0x8C08 |
1077 | #define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8) |
1078 | #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0) |
1079 | #define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) |
1080 | |
1081 | #define R_AX_WDE_ERRFLAG_MSG 0x8C30 |
1082 | #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0) |
1083 | |
1084 | #define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34 |
1085 | #define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31) |
1086 | #define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24) |
1087 | #define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16) |
1088 | #define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2) |
1089 | #define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1) |
1090 | #define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0) |
1091 | |
1092 | #define R_AX_WDE_ERR_IMR 0x8C38 |
1093 | #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) |
1094 | #define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) |
1095 | #define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) |
1096 | #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) |
1097 | #define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) |
1098 | #define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) |
1099 | #define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) |
1100 | #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) |
1101 | #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) |
1102 | #define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) |
1103 | #define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13) |
1104 | #define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12) |
1105 | #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) |
1106 | #define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6) |
1107 | #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5) |
1108 | #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) |
1109 | #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3) |
1110 | #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) |
1111 | #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) |
1112 | #define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0) |
1113 | #define B_AX_WDE_IMR_CLR (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ |
1114 | B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
1115 | B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
1116 | B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \ |
1117 | B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
1118 | B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \ |
1119 | B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \ |
1120 | B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ |
1121 | B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ |
1122 | B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ |
1123 | B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ |
1124 | B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1125 | B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1126 | B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ |
1127 | B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ |
1128 | B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1129 | B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ |
1130 | B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ |
1131 | B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN) |
1132 | #define B_AX_WDE_IMR_SET (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ |
1133 | B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
1134 | B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
1135 | B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \ |
1136 | B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
1137 | B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \ |
1138 | B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \ |
1139 | B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ |
1140 | B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ |
1141 | B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ |
1142 | B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ |
1143 | B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1144 | B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1145 | B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ |
1146 | B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ |
1147 | B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1148 | B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ |
1149 | B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ |
1150 | B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN) |
1151 | |
1152 | #define B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) |
1153 | #define B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28) |
1154 | #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) |
1155 | #define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) |
1156 | #define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) |
1157 | #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) |
1158 | #define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) |
1159 | #define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) |
1160 | #define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) |
1161 | #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) |
1162 | #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) |
1163 | #define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) |
1164 | #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) |
1165 | #define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) |
1166 | #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) |
1167 | #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) |
1168 | #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) |
1169 | #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) |
1170 | #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) |
1171 | #define B_AX_WDE_BUFREQ_SIZELMT_INT_EN BIT(2) |
1172 | #define B_AX_WDE_BUFREQ_SIZE0_INT_EN BIT(1) |
1173 | #define B_AX_WDE_IMR_CLR_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ |
1174 | B_AX_WDE_BUFREQ_SIZE0_INT_EN | \ |
1175 | B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \ |
1176 | B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ |
1177 | B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ |
1178 | B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ |
1179 | B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ |
1180 | B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \ |
1181 | B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ |
1182 | B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ |
1183 | B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ |
1184 | B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ |
1185 | B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ |
1186 | B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1187 | B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1188 | B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ |
1189 | B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ |
1190 | B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1191 | B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ |
1192 | B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ |
1193 | B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \ |
1194 | B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \ |
1195 | B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \ |
1196 | B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN) |
1197 | #define B_AX_WDE_IMR_SET_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ |
1198 | B_AX_WDE_BUFREQ_SIZE0_INT_EN | \ |
1199 | B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \ |
1200 | B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ |
1201 | B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ |
1202 | B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ |
1203 | B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ |
1204 | B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \ |
1205 | B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ |
1206 | B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ |
1207 | B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ |
1208 | B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ |
1209 | B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ |
1210 | B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1211 | B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1212 | B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ |
1213 | B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ |
1214 | B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1215 | B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ |
1216 | B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ |
1217 | B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \ |
1218 | B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \ |
1219 | B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \ |
1220 | B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN) |
1221 | |
1222 | #define R_AX_WDE_ERR_ISR 0x8C3C |
1223 | #define B_AX_WDE_DATCHN_RRDY_ERR BIT(27) |
1224 | #define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26) |
1225 | #define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25) |
1226 | #define B_AX_WDE_DATCHN_ARBT_ERR BIT(24) |
1227 | #define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19) |
1228 | #define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18) |
1229 | #define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17) |
1230 | #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16) |
1231 | #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15) |
1232 | #define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14) |
1233 | #define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13) |
1234 | #define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12) |
1235 | #define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7) |
1236 | #define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6) |
1237 | #define B_AX_WDE_GETNPG_STRPG_ERR BIT(5) |
1238 | #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4) |
1239 | #define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3) |
1240 | #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2) |
1241 | #define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1) |
1242 | #define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0) |
1243 | |
1244 | #define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16) |
1245 | #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0) |
1246 | #define R_AX_WDE_QTA0_CFG 0x8C40 |
1247 | #define R_AX_WDE_QTA1_CFG 0x8C44 |
1248 | #define R_AX_WDE_QTA2_CFG 0x8C48 |
1249 | #define R_AX_WDE_QTA3_CFG 0x8C4C |
1250 | #define R_AX_WDE_QTA4_CFG 0x8C50 |
1251 | |
1252 | #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0) |
1253 | #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0) |
1254 | #define B_AX_DLE_FREE_TAILPG GENMASK(27, 16) |
1255 | #define B_AX_DLE_USE_PGNUM GENMASK(27, 16) |
1256 | #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0) |
1257 | #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0) |
1258 | |
1259 | #define R_AX_WDE_INI_STATUS 0x8D00 |
1260 | #define B_AX_WDE_Q_MGN_INI_RDY BIT(1) |
1261 | #define B_AX_WDE_BUF_MGN_INI_RDY BIT(0) |
1262 | #define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY) |
1263 | #define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10 |
1264 | #define B_AX_WDE_DFI_ACTIVE BIT(31) |
1265 | #define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16) |
1266 | #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0) |
1267 | #define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14 |
1268 | #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0) |
1269 | |
1270 | #define R_AX_PLE_PKTBUF_CFG 0x9008 |
1271 | #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8) |
1272 | #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0) |
1273 | #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16) |
1274 | |
1275 | #define R_AX_PLE_DBGERR_LOCKEN 0x9020 |
1276 | #define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7) |
1277 | #define B_AX_PLE_LOCKEN_DLEPIF06 BIT(6) |
1278 | #define B_AX_PLE_LOCKEN_DLEPIF05 BIT(5) |
1279 | #define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4) |
1280 | #define B_AX_PLE_LOCKEN_DLEPIF03 BIT(3) |
1281 | #define B_AX_PLE_LOCKEN_DLEPIF02 BIT(2) |
1282 | #define B_AX_PLE_LOCKEN_DLEPIF01 BIT(1) |
1283 | #define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0) |
1284 | |
1285 | #define R_AX_PLE_DBGERR_STS 0x9024 |
1286 | #define B_AX_PLE_LOCKON_DLEPIF07 BIT(7) |
1287 | #define B_AX_PLE_LOCKON_DLEPIF06 BIT(6) |
1288 | #define B_AX_PLE_LOCKON_DLEPIF05 BIT(5) |
1289 | #define B_AX_PLE_LOCKON_DLEPIF04 BIT(4) |
1290 | #define B_AX_PLE_LOCKON_DLEPIF03 BIT(3) |
1291 | #define B_AX_PLE_LOCKON_DLEPIF02 BIT(2) |
1292 | #define B_AX_PLE_LOCKON_DLEPIF01 BIT(1) |
1293 | #define B_AX_PLE_LOCKON_DLEPIF00 BIT(0) |
1294 | |
1295 | #define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034 |
1296 | #define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31) |
1297 | #define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24) |
1298 | #define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16) |
1299 | #define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2) |
1300 | #define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1) |
1301 | #define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0) |
1302 | |
1303 | #define R_AX_PLE_ERRFLAG_MSG 0x9030 |
1304 | #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0) |
1305 | #define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) |
1306 | #define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28) |
1307 | #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) |
1308 | #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) |
1309 | #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) |
1310 | #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) |
1311 | #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) |
1312 | #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) |
1313 | #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) |
1314 | #define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2) |
1315 | #define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1) |
1316 | #define B_AX_PLE_DATCHN_CAMREQ_ERR BIT(29) |
1317 | #define B_AX_PLE_DATCHN_ADRERR_ERR BIT(28) |
1318 | #define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9) |
1319 | #define B_AX_PLE_GETNPG_PGOFST_ERR_V1 BIT(8) |
1320 | #define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7) |
1321 | #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_V1 BIT(6) |
1322 | #define B_AX_PLE_BUFRTN_SIZE_ERR_V1 BIT(5) |
1323 | #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4) |
1324 | #define B_AX_PLE_BUFREQ_UNAVAL_ERR_V1 BIT(3) |
1325 | #define B_AX_PLE_BUFREQ_SIZELMT_ERR BIT(2) |
1326 | #define B_AX_PLE_BUFREQ_SIZE0_ERR BIT(1) |
1327 | |
1328 | #define R_AX_PLE_ERR_IMR 0x9038 |
1329 | #define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27) |
1330 | #define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26) |
1331 | #define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25) |
1332 | #define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24) |
1333 | #define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) |
1334 | #define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18) |
1335 | #define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17) |
1336 | #define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) |
1337 | #define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) |
1338 | #define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14) |
1339 | #define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13) |
1340 | #define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12) |
1341 | #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) |
1342 | #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6) |
1343 | #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5) |
1344 | #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) |
1345 | #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3) |
1346 | #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) |
1347 | #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) |
1348 | #define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0) |
1349 | #define B_AX_PLE_IMR_CLR (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ |
1350 | B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
1351 | B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
1352 | B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \ |
1353 | B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
1354 | B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | \ |
1355 | B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \ |
1356 | B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ |
1357 | B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ |
1358 | B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ |
1359 | B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ |
1360 | B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1361 | B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1362 | B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ |
1363 | B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ |
1364 | B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1365 | B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ |
1366 | B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ |
1367 | B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN) |
1368 | #define B_AX_PLE_IMR_SET (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ |
1369 | B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
1370 | B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
1371 | B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \ |
1372 | B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
1373 | B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \ |
1374 | B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ |
1375 | B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ |
1376 | B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ |
1377 | B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ |
1378 | B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1379 | B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1380 | B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ |
1381 | B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ |
1382 | B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1383 | B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ |
1384 | B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ |
1385 | B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN) |
1386 | |
1387 | #define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) |
1388 | #define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28) |
1389 | #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) |
1390 | #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) |
1391 | #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) |
1392 | #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) |
1393 | #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) |
1394 | #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) |
1395 | #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) |
1396 | #define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2) |
1397 | #define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1) |
1398 | #define B_AX_PLE_IMR_CLR_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ |
1399 | B_AX_PLE_BUFREQ_SIZE0_INT_EN | \ |
1400 | B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \ |
1401 | B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ |
1402 | B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ |
1403 | B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ |
1404 | B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ |
1405 | B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \ |
1406 | B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ |
1407 | B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ |
1408 | B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ |
1409 | B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ |
1410 | B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ |
1411 | B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1412 | B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1413 | B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ |
1414 | B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ |
1415 | B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1416 | B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ |
1417 | B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ |
1418 | B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \ |
1419 | B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \ |
1420 | B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \ |
1421 | B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN) |
1422 | #define B_AX_PLE_IMR_SET_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ |
1423 | B_AX_PLE_BUFREQ_SIZE0_INT_EN | \ |
1424 | B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \ |
1425 | B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ |
1426 | B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ |
1427 | B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ |
1428 | B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ |
1429 | B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \ |
1430 | B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ |
1431 | B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ |
1432 | B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ |
1433 | B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ |
1434 | B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ |
1435 | B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
1436 | B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
1437 | B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ |
1438 | B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ |
1439 | B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ |
1440 | B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ |
1441 | B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ |
1442 | B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \ |
1443 | B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \ |
1444 | B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \ |
1445 | B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN) |
1446 | |
1447 | #define R_AX_PLE_ERR_FLAG_ISR 0x903C |
1448 | #define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16) |
1449 | #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0) |
1450 | #define R_AX_PLE_QTA0_CFG 0x9040 |
1451 | #define R_AX_PLE_QTA1_CFG 0x9044 |
1452 | #define R_AX_PLE_QTA2_CFG 0x9048 |
1453 | #define R_AX_PLE_QTA3_CFG 0x904C |
1454 | #define R_AX_PLE_QTA4_CFG 0x9050 |
1455 | #define R_AX_PLE_QTA5_CFG 0x9054 |
1456 | #define R_AX_PLE_QTA6_CFG 0x9058 |
1457 | #define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16) |
1458 | #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0) |
1459 | #define R_AX_PLE_QTA7_CFG 0x905C |
1460 | #define B_AX_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16) |
1461 | #define B_AX_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0) |
1462 | #define R_AX_PLE_QTA8_CFG 0x9060 |
1463 | #define R_AX_PLE_QTA9_CFG 0x9064 |
1464 | #define R_AX_PLE_QTA10_CFG 0x9068 |
1465 | #define R_AX_PLE_QTA11_CFG 0x906C |
1466 | |
1467 | #define R_AX_PLE_INI_STATUS 0x9100 |
1468 | #define B_AX_PLE_Q_MGN_INI_RDY BIT(1) |
1469 | #define B_AX_PLE_BUF_MGN_INI_RDY BIT(0) |
1470 | #define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY) |
1471 | #define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110 |
1472 | #define B_AX_PLE_DFI_ACTIVE BIT(31) |
1473 | #define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) |
1474 | #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0) |
1475 | #define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114 |
1476 | #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0) |
1477 | |
1478 | #define R_AX_WDRLS_CFG 0x9408 |
1479 | #define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8) |
1480 | #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0) |
1481 | |
1482 | #define R_AX_RLSRPT0_CFG0 0x9410 |
1483 | #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24) |
1484 | #define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16) |
1485 | #define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8) |
1486 | #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0) |
1487 | |
1488 | #define R_AX_RLSRPT0_CFG1 0x9414 |
1489 | #define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16) |
1490 | #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0) |
1491 | |
1492 | #define R_AX_WDRLS_ERR_IMR 0x9430 |
1493 | #define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) |
1494 | #define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) |
1495 | #define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) |
1496 | #define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) |
1497 | #define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) |
1498 | #define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) |
1499 | #define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) |
1500 | #define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) |
1501 | #define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) |
1502 | #define B_AX_WDRLS_IMR_EN_CLR (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ |
1503 | B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ |
1504 | B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ |
1505 | B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ |
1506 | B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ |
1507 | B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ |
1508 | B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ |
1509 | B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ |
1510 | B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) |
1511 | #define B_AX_WDRLS_IMR_SET (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ |
1512 | B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ |
1513 | B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ |
1514 | B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ |
1515 | B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ |
1516 | B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ |
1517 | B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ |
1518 | B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) |
1519 | #define B_AX_WDRLS_IMR_SET_V1 (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ |
1520 | B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ |
1521 | B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ |
1522 | B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ |
1523 | B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ |
1524 | B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ |
1525 | B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ |
1526 | B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ |
1527 | B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) |
1528 | |
1529 | #define R_AX_WDRLS_ERR_ISR 0x9434 |
1530 | |
1531 | #define R_AX_BBRPT_COM_ERR_IMR 0x9608 |
1532 | #define B_AX_BBRPT_COM_HANG_EN BIT(1) |
1533 | #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) |
1534 | |
1535 | #define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C |
1536 | #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16) |
1537 | #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) |
1538 | |
1539 | #define R_AX_BBRPT_COM_ERR_ISR 0x960C |
1540 | #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0) |
1541 | |
1542 | #define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C |
1543 | #define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7) |
1544 | #define B_AX_BBPRT_CHIF_NULL_ERR_V1 BIT(6) |
1545 | #define B_AX_BBPRT_CHIF_LEFT2_ERR_V1 BIT(5) |
1546 | #define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4) |
1547 | #define B_AX_BBPRT_CHIF_HDRL_ERR_V1 BIT(3) |
1548 | #define B_AX_BBPRT_CHIF_BOVF_ERR_V1 BIT(2) |
1549 | #define B_AX_BBPRT_CHIF_OVF_ERR_V1 BIT(1) |
1550 | #define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0) |
1551 | |
1552 | #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628 |
1553 | #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) |
1554 | #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) |
1555 | #define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) |
1556 | #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) |
1557 | #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) |
1558 | #define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) |
1559 | #define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) |
1560 | #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) |
1561 | #define R_AX_BBRPT_CHINFO_IMR_SET_V1 (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \ |
1562 | B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \ |
1563 | B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \ |
1564 | B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \ |
1565 | B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \ |
1566 | B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \ |
1567 | B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \ |
1568 | B_AX_BBPRT_CHIF_TO_ERR_INT_EN) |
1569 | |
1570 | #define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C |
1571 | #define B_AX_BBPRT_CHIF_TO_ERR BIT(23) |
1572 | #define B_AX_BBPRT_CHIF_NULL_ERR BIT(22) |
1573 | #define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21) |
1574 | #define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20) |
1575 | #define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19) |
1576 | #define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18) |
1577 | #define B_AX_BBPRT_CHIF_OVF_ERR BIT(17) |
1578 | #define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16) |
1579 | #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) |
1580 | #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) |
1581 | #define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) |
1582 | #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) |
1583 | #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) |
1584 | #define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) |
1585 | #define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) |
1586 | #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) |
1587 | #define B_AX_BBRPT_CHINFO_IMR_CLR (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \ |
1588 | B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \ |
1589 | B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \ |
1590 | B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \ |
1591 | B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \ |
1592 | B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \ |
1593 | B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \ |
1594 | B_AX_BBPRT_CHIF_TO_ERR_INT_EN) |
1595 | |
1596 | #define R_AX_BBRPT_DFS_ERR_IMR 0x9638 |
1597 | #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) |
1598 | |
1599 | #define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C |
1600 | #define B_AX_BBRPT_DFS_TO_ERR BIT(16) |
1601 | #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) |
1602 | |
1603 | #define R_AX_BBRPT_DFS_ERR_ISR 0x963C |
1604 | #define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0) |
1605 | |
1606 | #define R_AX_LA_ERRFLAG 0x966C |
1607 | #define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16) |
1608 | #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0) |
1609 | |
1610 | #define R_AX_WD_BUF_REQ 0x9800 |
1611 | #define R_AX_PL_BUF_REQ 0x9820 |
1612 | #define B_AX_WD_BUF_REQ_EXEC BIT(31) |
1613 | #define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16) |
1614 | #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0) |
1615 | |
1616 | #define R_AX_WD_BUF_STATUS 0x9804 |
1617 | #define R_AX_PL_BUF_STATUS 0x9824 |
1618 | #define B_AX_WD_BUF_STAT_DONE BIT(31) |
1619 | #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0) |
1620 | #define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0) |
1621 | |
1622 | #define R_AX_WD_CPUQ_OP_0 0x9810 |
1623 | #define R_AX_PL_CPUQ_OP_0 0x9830 |
1624 | #define B_AX_WD_CPUQ_OP_EXEC BIT(31) |
1625 | #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) |
1626 | #define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16) |
1627 | #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) |
1628 | |
1629 | #define R_AX_WD_CPUQ_OP_1 0x9814 |
1630 | #define R_AX_PL_CPUQ_OP_1 0x9834 |
1631 | #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22) |
1632 | #define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16) |
1633 | #define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6) |
1634 | #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0) |
1635 | |
1636 | #define R_AX_WD_CPUQ_OP_2 0x9818 |
1637 | #define R_AX_PL_CPUQ_OP_2 0x9838 |
1638 | #define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) |
1639 | #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) |
1640 | |
1641 | #define R_AX_WD_CPUQ_OP_STATUS 0x981C |
1642 | #define R_AX_PL_CPUQ_OP_STATUS 0x983C |
1643 | #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31) |
1644 | #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0) |
1645 | |
1646 | #define R_AX_CPUIO_ERR_IMR 0x9840 |
1647 | #define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12) |
1648 | #define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8) |
1649 | #define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4) |
1650 | #define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0) |
1651 | #define B_AX_CPUIO_IMR_CLR (B_AX_WDEBUF_OP_ERR_INT_EN | \ |
1652 | B_AX_WDEQUE_OP_ERR_INT_EN | \ |
1653 | B_AX_PLEBUF_OP_ERR_INT_EN | \ |
1654 | B_AX_PLEQUE_OP_ERR_INT_EN) |
1655 | #define B_AX_CPUIO_IMR_SET (B_AX_WDEBUF_OP_ERR_INT_EN | \ |
1656 | B_AX_WDEQUE_OP_ERR_INT_EN | \ |
1657 | B_AX_PLEBUF_OP_ERR_INT_EN | \ |
1658 | B_AX_PLEQUE_OP_ERR_INT_EN) |
1659 | |
1660 | #define R_AX_CPUIO_ERR_ISR 0x9844 |
1661 | |
1662 | #define R_AX_SEC_ERR_IMR_ISR 0x991C |
1663 | |
1664 | #define R_AX_PKTIN_SETTING 0x9A00 |
1665 | #define B_AX_WD_ADDR_INFO_LENGTH BIT(1) |
1666 | |
1667 | #define R_AX_PKTIN_ERR_IMR 0x9A20 |
1668 | #define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0) |
1669 | |
1670 | #define R_AX_PKTIN_ERR_ISR 0x9A24 |
1671 | |
1672 | #define R_AX_MPDU_TX_ERR_ISR 0x9BF0 |
1673 | #define R_AX_MPDU_TX_ERR_IMR 0x9BF4 |
1674 | #define B_AX_TX_KSRCH_ERR_EN BIT(9) |
1675 | #define B_AX_TX_NW_TYPE_ERR_EN BIT(8) |
1676 | #define B_AX_TX_LLC_PRE_ERR_EN BIT(7) |
1677 | #define B_AX_TX_ETH_TYPE_ERR_EN BIT(6) |
1678 | #define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5) |
1679 | #define B_AX_TX_OFFSET_ERR_INT_EN BIT(4) |
1680 | #define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3) |
1681 | #define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2) |
1682 | #define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1) |
1683 | #define B_AX_MPDU_TX_IMR_SET_V1 (B_AX_TX_GET_ERRPKTID_INT_EN | \ |
1684 | B_AX_TX_NXT_ERRPKTID_INT_EN | \ |
1685 | B_AX_TX_MPDU_SIZE_ZERO_INT_EN | \ |
1686 | B_AX_TX_HDR3_SIZE_ERR_INT_EN | \ |
1687 | B_AX_TX_ETH_TYPE_ERR_EN | \ |
1688 | B_AX_TX_NW_TYPE_ERR_EN | \ |
1689 | B_AX_TX_KSRCH_ERR_EN) |
1690 | |
1691 | #define R_AX_MPDU_PROC 0x9C00 |
1692 | #define B_AX_A_ICV_ERR BIT(1) |
1693 | #define B_AX_APPEND_FCS BIT(0) |
1694 | |
1695 | #define R_AX_ACTION_FWD0 0x9C04 |
1696 | #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95 |
1697 | |
1698 | #define R_AX_ACTION_FWD1 0x9C08 |
1699 | |
1700 | #define R_AX_TF_FWD 0x9C14 |
1701 | #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55 |
1702 | |
1703 | #define R_AX_HW_RPT_FWD 0x9C18 |
1704 | #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0) |
1705 | #define RTW89_PRPT_DEST_HOST 1 |
1706 | #define RTW89_PRPT_DEST_WLCPU 2 |
1707 | |
1708 | #define R_AX_CUT_AMSDU_CTRL 0x9C40 |
1709 | #define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0 |
1710 | |
1711 | #define R_AX_WOW_CTRL 0x9C50 |
1712 | #define B_AX_WOW_WOWEN BIT(1) |
1713 | |
1714 | #define R_AX_MPDU_RX_ERR_ISR 0x9CF0 |
1715 | #define R_AX_MPDU_RX_ERR_IMR 0x9CF4 |
1716 | #define B_AX_RPT_ERR_INT_EN BIT(3) |
1717 | #define B_AX_MHDRLEN_ERR_INT_EN BIT(1) |
1718 | #define B_AX_GETPKTID_ERR_INT_EN BIT(0) |
1719 | #define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN |
1720 | |
1721 | #define R_AX_SEC_ENG_CTRL 0x9D00 |
1722 | #define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16) |
1723 | #define B_AX_TX_PARTIAL_MODE BIT(11) |
1724 | #define B_AX_CLK_EN_CGCMP BIT(10) |
1725 | #define B_AX_CLK_EN_WAPI BIT(9) |
1726 | #define B_AX_CLK_EN_WEP_TKIP BIT(8) |
1727 | #define B_AX_BMC_MGNT_DEC BIT(5) |
1728 | #define B_AX_UC_MGNT_DEC BIT(4) |
1729 | #define B_AX_MC_DEC BIT(3) |
1730 | #define B_AX_BC_DEC BIT(2) |
1731 | #define B_AX_SEC_RX_DEC BIT(1) |
1732 | #define B_AX_SEC_TX_ENC BIT(0) |
1733 | |
1734 | #define R_AX_SEC_MPDU_PROC 0x9D04 |
1735 | #define B_AX_APPEND_ICV BIT(1) |
1736 | #define B_AX_APPEND_MIC BIT(0) |
1737 | |
1738 | #define R_AX_SEC_CAM_ACCESS 0x9D10 |
1739 | #define R_AX_SEC_CAM_RDATA 0x9D14 |
1740 | #define R_AX_SEC_CAM_WDATA 0x9D18 |
1741 | |
1742 | #define R_AX_SEC_DEBUG 0x9D1C |
1743 | #define B_AX_IMR_ERROR BIT(3) |
1744 | |
1745 | #define R_AX_SEC_DEBUG1 0x9D1C |
1746 | #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30) |
1747 | #define AX_TX_TO_VAL 0x2 |
1748 | |
1749 | #define R_AX_SEC_TX_DEBUG 0x9D20 |
1750 | #define R_AX_SEC_RX_DEBUG 0x9D24 |
1751 | #define R_AX_SEC_TRX_PKT_CNT 0x9D28 |
1752 | |
1753 | #define R_AX_SEC_DEBUG2 0x9D28 |
1754 | #define B_AX_DBG_READ_SH 2 |
1755 | #define B_AX_DBG_READ_MSK 0x3fffffff |
1756 | |
1757 | #define R_AX_SEC_TRX_BLK_CNT 0x9D2C |
1758 | |
1759 | #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C |
1760 | #define B_AX_RX_HANG_IMR BIT(1) |
1761 | #define B_AX_TX_HANG_IMR BIT(0) |
1762 | |
1763 | #define R_AX_SEC_ERROR_FLAG 0x9D30 |
1764 | #define B_AX_RX_HANG_ERROR_V1 BIT(1) |
1765 | #define B_AX_TX_HANG_ERROR_V1 BIT(0) |
1766 | |
1767 | #define R_AX_SS_CTRL 0x9E10 |
1768 | #define B_AX_SS_INIT_DONE_1 BIT(31) |
1769 | #define B_AX_SS_WARM_INIT_FLG BIT(29) |
1770 | #define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28) |
1771 | #define B_AX_SS_EN BIT(0) |
1772 | |
1773 | #define R_AX_SS2FINFO_PATH 0x9E50 |
1774 | #define B_AX_SS_UL_REL BIT(31) |
1775 | #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24) |
1776 | #define B_AX_SS_REL_PORT_MASK GENMASK(18, 16) |
1777 | #define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8) |
1778 | #define SS2F_PATH_WLCPU 0x0A |
1779 | #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0) |
1780 | |
1781 | #define R_AX_SS_MACID_PAUSE_0 0x9EB0 |
1782 | #define B_AX_SS_MACID31_0_PAUSE_SH 0 |
1783 | #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0) |
1784 | |
1785 | #define R_AX_SS_MACID_PAUSE_1 0x9EB4 |
1786 | #define B_AX_SS_MACID63_32_PAUSE_SH 0 |
1787 | #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0) |
1788 | |
1789 | #define R_AX_SS_MACID_PAUSE_2 0x9EB8 |
1790 | #define B_AX_SS_MACID95_64_PAUSE_SH 0 |
1791 | #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0) |
1792 | |
1793 | #define R_AX_SS_MACID_PAUSE_3 0x9EBC |
1794 | #define B_AX_SS_MACID127_96_PAUSE_SH 0 |
1795 | #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0) |
1796 | |
1797 | #define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0 |
1798 | #define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2) |
1799 | #define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1) |
1800 | #define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0) |
1801 | #define B_AX_STA_SCHEDULER_IMR_SET (B_AX_SEARCH_HANG_TIMEOUT_INT_EN | \ |
1802 | B_AX_RPT_HANG_TIMEOUT_INT_EN | \ |
1803 | B_AX_PLE_B_PKTID_ERR_INT_EN) |
1804 | |
1805 | #define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4 |
1806 | |
1807 | #define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C |
1808 | #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25) |
1809 | #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24) |
1810 | #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19) |
1811 | #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18) |
1812 | #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17) |
1813 | #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16) |
1814 | #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) |
1815 | #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8) |
1816 | #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) |
1817 | #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) |
1818 | #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) |
1819 | #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0) |
1820 | #define B_AX_TXPKTCTL_IMR_B0_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ |
1821 | B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ |
1822 | B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \ |
1823 | B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \ |
1824 | B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ |
1825 | B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) |
1826 | #define B_AX_TXPKTCTL_IMR_B1_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ |
1827 | B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ |
1828 | B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \ |
1829 | B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \ |
1830 | B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ |
1831 | B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) |
1832 | #define B_AX_TXPKTCTL_IMR_B0_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ |
1833 | B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN) |
1834 | #define B_AX_TXPKTCTL_IMR_B1_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ |
1835 | B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ |
1836 | B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ |
1837 | B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) |
1838 | |
1839 | #define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C |
1840 | #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) |
1841 | #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) |
1842 | #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) |
1843 | #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) |
1844 | |
1845 | #define R_AX_DBG_FUN_INTF_CTL 0x9F30 |
1846 | #define B_AX_DFI_ACTIVE BIT(31) |
1847 | #define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16) |
1848 | #define B_AX_DFI_ADDR_MASK GENMASK(15, 0) |
1849 | #define R_AX_DBG_FUN_INTF_DATA 0x9F34 |
1850 | #define B_AX_DFI_DATA_MASK GENMASK(31, 0) |
1851 | |
1852 | #define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48 |
1853 | #define B_AX_B0_PRELD_FEN BIT(31) |
1854 | #define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16) |
1855 | #define PRELD_B0_ENT_NUM 10 |
1856 | #define PRELD_AMSDU_SIZE 52 |
1857 | #define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) |
1858 | #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) |
1859 | |
1860 | #define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C |
1861 | #define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) |
1862 | #define PRELD_NEXT_WND 1 |
1863 | #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) |
1864 | |
1865 | #define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78 |
1866 | #define B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(21) |
1867 | #define B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(20) |
1868 | #define B_AX_B0_IMR_ERR_MPDUIF_DATAERR BIT(18) |
1869 | #define B_AX_B0_IMR_ERR_MPDUINFO_RECFG BIT(16) |
1870 | #define B_AX_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11) |
1871 | #define B_AX_B0_IMR_ERR_CMDPSR_FRZTO BIT(10) |
1872 | #define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9) |
1873 | #define B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8) |
1874 | #define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3) |
1875 | #define B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD BIT(2) |
1876 | #define B_AX_B0_IMR_ERR_USRCTL_NOINIT BIT(1) |
1877 | #define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0) |
1878 | #define B_AX_TXPKTCTL_IMR_B0_CLR_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \ |
1879 | B_AX_B0_IMR_ERR_USRCTL_NOINIT | \ |
1880 | B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD | \ |
1881 | B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN | \ |
1882 | B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \ |
1883 | B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \ |
1884 | B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \ |
1885 | B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \ |
1886 | B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \ |
1887 | B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \ |
1888 | B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ |
1889 | B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG) |
1890 | #define B_AX_TXPKTCTL_IMR_B0_SET_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \ |
1891 | B_AX_B0_IMR_ERR_USRCTL_NOINIT | \ |
1892 | B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \ |
1893 | B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \ |
1894 | B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \ |
1895 | B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \ |
1896 | B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \ |
1897 | B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \ |
1898 | B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ |
1899 | B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG) |
1900 | |
1901 | #define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C |
1902 | #define B_AX_B0_ISR_ERR_PRELD_EVT3 BIT(23) |
1903 | #define B_AX_B0_ISR_ERR_PRELD_EVT2 BIT(22) |
1904 | #define B_AX_B0_ISR_ERR_PRELD_ENTNUMCFG BIT(21) |
1905 | #define B_AX_B0_ISR_ERR_PRELD_RLSPKTSZERR BIT(20) |
1906 | #define B_AX_B0_ISR_ERR_MPDUIF_ERR1 BIT(19) |
1907 | #define B_AX_B0_ISR_ERR_MPDUIF_DATAERR BIT(18) |
1908 | #define B_AX_B0_ISR_ERR_MPDUINFO_ERR1 BIT(17) |
1909 | #define B_AX_B0_ISR_ERR_MPDUINFO_RECFG BIT(16) |
1910 | #define B_AX_B0_ISR_ERR_CMDPSR_TBLSZ BIT(11) |
1911 | #define B_AX_B0_ISR_ERR_CMDPSR_FRZTO BIT(10) |
1912 | #define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9) |
1913 | #define B_AX_B0_ISR_ERR_CMDPSR_1STCMDERR BIT(8) |
1914 | #define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7) |
1915 | #define B_AX_B0_ISR_ERR_USRCTL_EVT6 BIT(6) |
1916 | #define B_AX_B0_ISR_ERR_USRCTL_EVT5 BIT(5) |
1917 | #define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4) |
1918 | #define B_AX_B0_ISR_ERR_USRCTL_RLSBMPLEN BIT(3) |
1919 | #define B_AX_B0_ISR_ERR_USRCTL_RDNRLSCMD BIT(2) |
1920 | #define B_AX_B0_ISR_ERR_USRCTL_NOINIT BIT(1) |
1921 | #define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0) |
1922 | |
1923 | #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88 |
1924 | #define B_AX_B1_PRELD_FEN BIT(31) |
1925 | #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16) |
1926 | #define PRELD_B1_ENT_NUM 4 |
1927 | #define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) |
1928 | #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) |
1929 | |
1930 | #define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C |
1931 | #define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) |
1932 | #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) |
1933 | |
1934 | #define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8 |
1935 | #define B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(21) |
1936 | #define B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(20) |
1937 | #define B_AX_B1_IMR_ERR_MPDUIF_DATAERR BIT(18) |
1938 | #define B_AX_B1_IMR_ERR_MPDUINFO_RECFG BIT(16) |
1939 | #define B_AX_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11) |
1940 | #define B_AX_B1_IMR_ERR_CMDPSR_FRZTO BIT(10) |
1941 | #define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9) |
1942 | #define B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8) |
1943 | #define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3) |
1944 | #define B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD BIT(2) |
1945 | #define B_AX_B1_IMR_ERR_USRCTL_NOINIT BIT(1) |
1946 | #define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0) |
1947 | #define B_AX_TXPKTCTL_IMR_B1_CLR_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \ |
1948 | B_AX_B1_IMR_ERR_USRCTL_NOINIT | \ |
1949 | B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD | \ |
1950 | B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN | \ |
1951 | B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \ |
1952 | B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \ |
1953 | B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \ |
1954 | B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \ |
1955 | B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \ |
1956 | B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \ |
1957 | B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ |
1958 | B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG) |
1959 | #define B_AX_TXPKTCTL_IMR_B1_SET_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \ |
1960 | B_AX_B1_IMR_ERR_USRCTL_NOINIT | \ |
1961 | B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \ |
1962 | B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \ |
1963 | B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \ |
1964 | B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \ |
1965 | B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \ |
1966 | B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \ |
1967 | B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ |
1968 | B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG) |
1969 | |
1970 | #define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC |
1971 | #define B_AX_B1_ISR_ERR_PRELD_EVT3 BIT(23) |
1972 | #define B_AX_B1_ISR_ERR_PRELD_EVT2 BIT(22) |
1973 | #define B_AX_B1_ISR_ERR_PRELD_ENTNUMCFG BIT(21) |
1974 | #define B_AX_B1_ISR_ERR_PRELD_RLSPKTSZERR BIT(20) |
1975 | #define B_AX_B1_ISR_ERR_MPDUIF_ERR1 BIT(19) |
1976 | #define B_AX_B1_ISR_ERR_MPDUIF_DATAERR BIT(18) |
1977 | #define B_AX_B1_ISR_ERR_MPDUINFO_ERR1 BIT(17) |
1978 | #define B_AX_B1_ISR_ERR_MPDUINFO_RECFG BIT(16) |
1979 | #define B_AX_B1_ISR_ERR_CMDPSR_TBLSZ BIT(11) |
1980 | #define B_AX_B1_ISR_ERR_CMDPSR_FRZTO BIT(10) |
1981 | #define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9) |
1982 | #define B_AX_B1_ISR_ERR_CMDPSR_1STCMDERR BIT(8) |
1983 | #define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7) |
1984 | #define B_AX_B1_ISR_ERR_USRCTL_EVT6 BIT(6) |
1985 | #define B_AX_B1_ISR_ERR_USRCTL_EVT5 BIT(5) |
1986 | #define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4) |
1987 | #define B_AX_B1_ISR_ERR_USRCTL_RLSBMPLEN BIT(3) |
1988 | #define B_AX_B1_ISR_ERR_USRCTL_RDNRLSCMD BIT(2) |
1989 | #define B_AX_B1_ISR_ERR_USRCTL_NOINIT BIT(1) |
1990 | #define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0) |
1991 | |
1992 | #define R_AX_AFE_CTRL1 0x0024 |
1993 | |
1994 | #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4) |
1995 | #define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3) |
1996 | #define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2) |
1997 | #define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1) |
1998 | #define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0) |
1999 | |
2000 | #define R_AX_SYS_ISO_CTRL_EXTEND 0x0080 |
2001 | #define B_AX_CMAC1_FEN BIT(30) |
2002 | #define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17) |
2003 | #define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16) |
2004 | #define B_AX_R_SYM_ISO_CMAC12PP BIT(5) |
2005 | |
2006 | #define R_AX_CMAC_REG_START 0xC000 |
2007 | |
2008 | #define R_AX_CMAC_FUNC_EN 0xC000 |
2009 | #define R_AX_CMAC_FUNC_EN_C1 0xE000 |
2010 | #define B_AX_CMAC_CRPRT BIT(31) |
2011 | #define B_AX_CMAC_EN BIT(30) |
2012 | #define B_AX_CMAC_TXEN BIT(29) |
2013 | #define B_AX_CMAC_RXEN BIT(28) |
2014 | #define B_AX_FORCE_CMACREG_GCKEN BIT(15) |
2015 | #define B_AX_PHYINTF_EN BIT(5) |
2016 | #define B_AX_CMAC_DMA_EN BIT(4) |
2017 | #define B_AX_PTCLTOP_EN BIT(3) |
2018 | #define B_AX_SCHEDULER_EN BIT(2) |
2019 | #define B_AX_TMAC_EN BIT(1) |
2020 | #define B_AX_RMAC_EN BIT(0) |
2021 | |
2022 | #define R_AX_CK_EN 0xC004 |
2023 | #define R_AX_CK_EN_C1 0xE004 |
2024 | #define B_AX_CMAC_ALLCKEN GENMASK(31, 0) |
2025 | #define B_AX_CMAC_CKEN BIT(30) |
2026 | #define B_AX_PHYINTF_CKEN BIT(5) |
2027 | #define B_AX_CMAC_DMA_CKEN BIT(4) |
2028 | #define B_AX_PTCLTOP_CKEN BIT(3) |
2029 | #define B_AX_SCHEDULER_CKEN BIT(2) |
2030 | #define B_AX_TMAC_CKEN BIT(1) |
2031 | #define B_AX_RMAC_CKEN BIT(0) |
2032 | |
2033 | #define R_AX_WMAC_RFMOD 0xC010 |
2034 | #define R_AX_WMAC_RFMOD_C1 0xE010 |
2035 | #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0) |
2036 | #define AX_WMAC_RFMOD_20M 0 |
2037 | #define AX_WMAC_RFMOD_40M 1 |
2038 | #define AX_WMAC_RFMOD_80M 2 |
2039 | #define AX_WMAC_RFMOD_160M 3 |
2040 | |
2041 | #define R_AX_GID_POSITION0 0xC070 |
2042 | #define R_AX_GID_POSITION0_C1 0xE070 |
2043 | #define R_AX_GID_POSITION1 0xC074 |
2044 | #define R_AX_GID_POSITION1_C1 0xE074 |
2045 | #define R_AX_GID_POSITION2 0xC078 |
2046 | #define R_AX_GID_POSITION2_C1 0xE078 |
2047 | #define R_AX_GID_POSITION3 0xC07C |
2048 | #define R_AX_GID_POSITION3_C1 0xE07C |
2049 | #define R_AX_GID_POSITION_EN0 0xC080 |
2050 | #define R_AX_GID_POSITION_EN0_C1 0xE080 |
2051 | #define R_AX_GID_POSITION_EN1 0xC084 |
2052 | #define R_AX_GID_POSITION_EN1_C1 0xE084 |
2053 | |
2054 | #define R_AX_TX_SUB_CARRIER_VALUE 0xC088 |
2055 | #define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088 |
2056 | #define B_AX_TXSC_80M_MASK GENMASK(11, 8) |
2057 | #define B_AX_TXSC_40M_MASK GENMASK(7, 4) |
2058 | #define B_AX_TXSC_20M_MASK GENMASK(3, 0) |
2059 | |
2060 | #define R_AX_PTCL_RRSR1 0xC090 |
2061 | #define R_AX_PTCL_RRSR1_C1 0xE090 |
2062 | #define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8) |
2063 | #define RRSR_OFDM_CCK_EN 3 |
2064 | #define B_AX_RSC_MASK GENMASK(7, 6) |
2065 | #define B_AX_RRSR_CCK_MASK GENMASK(3, 0) |
2066 | |
2067 | #define R_AX_CMAC_ERR_IMR 0xC160 |
2068 | #define R_AX_CMAC_ERR_IMR_C1 0xE160 |
2069 | #define B_AX_WMAC_TX_ERR_IND_EN BIT(7) |
2070 | #define B_AX_WMAC_RX_ERR_IND_EN BIT(6) |
2071 | #define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5) |
2072 | #define B_AX_PHYINTF_ERR_IND_EN BIT(4) |
2073 | #define B_AX_DMA_TOP_ERR_IND_EN BIT(3) |
2074 | #define B_AX_PTCL_TOP_ERR_IND_EN BIT(1) |
2075 | #define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0) |
2076 | #define CMAC0_ERR_IMR_EN GENMASK(31, 0) |
2077 | #define CMAC1_ERR_IMR_EN GENMASK(31, 0) |
2078 | #define CMAC0_ERR_IMR_DIS 0 |
2079 | #define CMAC1_ERR_IMR_DIS 0 |
2080 | |
2081 | #define R_AX_CMAC_ERR_ISR 0xC164 |
2082 | #define R_AX_CMAC_ERR_ISR_C1 0xE164 |
2083 | #define B_AX_WMAC_TX_ERR_IND BIT(7) |
2084 | #define B_AX_WMAC_RX_ERR_IND BIT(6) |
2085 | #define B_AX_TXPWR_CTRL_ERR_IND BIT(5) |
2086 | #define B_AX_PHYINTF_ERR_IND BIT(4) |
2087 | #define B_AX_DMA_TOP_ERR_IND BIT(3) |
2088 | #define B_AX_PTCL_TOP_ERR_IND BIT(1) |
2089 | #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0) |
2090 | |
2091 | #define R_AX_PORT0_TSF_SYNC 0xC2A0 |
2092 | #define R_AX_PORT0_TSF_SYNC_C1 0xE2A0 |
2093 | #define R_AX_PORT1_TSF_SYNC 0xC2A4 |
2094 | #define R_AX_PORT1_TSF_SYNC_C1 0xE2A4 |
2095 | #define R_AX_PORT2_TSF_SYNC 0xC2A8 |
2096 | #define R_AX_PORT2_TSF_SYNC_C1 0xE2A8 |
2097 | #define R_AX_PORT3_TSF_SYNC 0xC2AC |
2098 | #define R_AX_PORT3_TSF_SYNC_C1 0xE2AC |
2099 | #define R_AX_PORT4_TSF_SYNC 0xC2B0 |
2100 | #define R_AX_PORT4_TSF_SYNC_C1 0xE2B0 |
2101 | #define B_AX_SYNC_NOW BIT(30) |
2102 | #define B_AX_SYNC_ONCE BIT(29) |
2103 | #define B_AX_SYNC_AUTO BIT(28) |
2104 | #define B_AX_SYNC_PORT_SRC GENMASK(26, 24) |
2105 | #define B_AX_SYNC_PORT_OFFSET_SIGN BIT(18) |
2106 | #define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0) |
2107 | |
2108 | #define R_AX_MACID_SLEEP_0 0xC2C0 |
2109 | #define R_AX_MACID_SLEEP_0_C1 0xE2C0 |
2110 | #define B_AX_MACID31_0_SLEEP_SH 0 |
2111 | #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0) |
2112 | |
2113 | #define R_AX_MACID_SLEEP_1 0xC2C4 |
2114 | #define R_AX_MACID_SLEEP_1_C1 0xE2C4 |
2115 | #define B_AX_MACID63_32_SLEEP_SH 0 |
2116 | #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0) |
2117 | |
2118 | #define R_AX_MACID_SLEEP_2 0xC2C8 |
2119 | #define R_AX_MACID_SLEEP_2_C1 0xE2C8 |
2120 | #define B_AX_MACID95_64_SLEEP_SH 0 |
2121 | #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0) |
2122 | |
2123 | #define R_AX_MACID_SLEEP_3 0xC2CC |
2124 | #define R_AX_MACID_SLEEP_3_C1 0xE2CC |
2125 | #define B_AX_MACID127_96_SLEEP_SH 0 |
2126 | #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0) |
2127 | |
2128 | #define SCH_PREBKF_24US 0x18 |
2129 | #define R_AX_PREBKF_CFG_0 0xC338 |
2130 | #define R_AX_PREBKF_CFG_0_C1 0xE338 |
2131 | #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0) |
2132 | |
2133 | #define R_AX_PREBKF_CFG_1 0xC33C |
2134 | #define R_AX_PREBKF_CFG_1_C1 0xE33C |
2135 | #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24) |
2136 | #define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16) |
2137 | #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8) |
2138 | #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0) |
2139 | #define SIFS_MACTXEN_T1 0x47 |
2140 | #define SIFS_MACTXEN_T1_V1 0x41 |
2141 | |
2142 | #define R_AX_CCA_CFG_0 0xC340 |
2143 | #define R_AX_CCA_CFG_0_C1 0xE340 |
2144 | #define B_AX_BTCCA_BRK_TXOP_EN BIT(9) |
2145 | #define B_AX_BTCCA_EN BIT(5) |
2146 | #define B_AX_EDCCA_EN BIT(4) |
2147 | #define B_AX_SEC80_EN BIT(3) |
2148 | #define B_AX_SEC40_EN BIT(2) |
2149 | #define B_AX_SEC20_EN BIT(1) |
2150 | #define B_AX_CCA_EN BIT(0) |
2151 | |
2152 | #define R_AX_CTN_TXEN 0xC348 |
2153 | #define R_AX_CTN_TXEN_C1 0xE348 |
2154 | #define B_AX_CTN_TXEN_TWT_1 BIT(15) |
2155 | #define B_AX_CTN_TXEN_TWT_0 BIT(14) |
2156 | #define B_AX_CTN_TXEN_ULQ BIT(13) |
2157 | #define B_AX_CTN_TXEN_BCNQ BIT(12) |
2158 | #define B_AX_CTN_TXEN_HGQ BIT(11) |
2159 | #define B_AX_CTN_TXEN_CPUMGQ BIT(10) |
2160 | #define B_AX_CTN_TXEN_MGQ1 BIT(9) |
2161 | #define B_AX_CTN_TXEN_MGQ BIT(8) |
2162 | #define B_AX_CTN_TXEN_VO_1 BIT(7) |
2163 | #define B_AX_CTN_TXEN_VI_1 BIT(6) |
2164 | #define B_AX_CTN_TXEN_BK_1 BIT(5) |
2165 | #define B_AX_CTN_TXEN_BE_1 BIT(4) |
2166 | #define B_AX_CTN_TXEN_VO_0 BIT(3) |
2167 | #define B_AX_CTN_TXEN_VI_0 BIT(2) |
2168 | #define B_AX_CTN_TXEN_BK_0 BIT(1) |
2169 | #define B_AX_CTN_TXEN_BE_0 BIT(0) |
2170 | #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0) |
2171 | |
2172 | #define R_AX_MUEDCA_BE_PARAM_0 0xC350 |
2173 | #define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350 |
2174 | #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16) |
2175 | #define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8) |
2176 | #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0) |
2177 | |
2178 | #define R_AX_MUEDCA_BK_PARAM_0 0xC354 |
2179 | #define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354 |
2180 | #define R_AX_MUEDCA_VI_PARAM_0 0xC358 |
2181 | #define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358 |
2182 | #define R_AX_MUEDCA_VO_PARAM_0 0xC35C |
2183 | #define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C |
2184 | |
2185 | #define R_AX_MUEDCA_EN 0xC370 |
2186 | #define R_AX_MUEDCA_EN_C1 0xE370 |
2187 | #define B_AX_MUEDCA_WMM_SEL BIT(8) |
2188 | #define B_AX_SET_MUEDCATIMER_TF_0 BIT(4) |
2189 | #define B_AX_MUEDCA_EN_0 BIT(0) |
2190 | |
2191 | #define R_AX_CCA_CONTROL 0xC390 |
2192 | #define R_AX_CCA_CONTROL_C1 0xE390 |
2193 | #define B_AX_TB_CHK_TX_NAV BIT(31) |
2194 | #define B_AX_TB_CHK_BASIC_NAV BIT(30) |
2195 | #define B_AX_TB_CHK_BTCCA BIT(29) |
2196 | #define B_AX_TB_CHK_EDCCA BIT(28) |
2197 | #define B_AX_TB_CHK_CCA_S80 BIT(27) |
2198 | #define B_AX_TB_CHK_CCA_S40 BIT(26) |
2199 | #define B_AX_TB_CHK_CCA_S20 BIT(25) |
2200 | #define B_AX_TB_CHK_CCA_P20 BIT(24) |
2201 | #define B_AX_SIFS_CHK_BTCCA BIT(21) |
2202 | #define B_AX_SIFS_CHK_EDCCA BIT(20) |
2203 | #define B_AX_SIFS_CHK_CCA_S80 BIT(19) |
2204 | #define B_AX_SIFS_CHK_CCA_S40 BIT(18) |
2205 | #define B_AX_SIFS_CHK_CCA_S20 BIT(17) |
2206 | #define B_AX_SIFS_CHK_CCA_P20 BIT(16) |
2207 | #define B_AX_CTN_CHK_TXNAV BIT(8) |
2208 | #define B_AX_CTN_CHK_INTRA_NAV BIT(7) |
2209 | #define B_AX_CTN_CHK_BASIC_NAV BIT(6) |
2210 | #define B_AX_CTN_CHK_BTCCA BIT(5) |
2211 | #define B_AX_CTN_CHK_EDCCA BIT(4) |
2212 | #define B_AX_CTN_CHK_CCA_S80 BIT(3) |
2213 | #define B_AX_CTN_CHK_CCA_S40 BIT(2) |
2214 | #define B_AX_CTN_CHK_CCA_S20 BIT(1) |
2215 | #define B_AX_CTN_CHK_CCA_P20 BIT(0) |
2216 | |
2217 | #define R_AX_CTN_DRV_TXEN 0xC398 |
2218 | #define R_AX_CTN_DRV_TXEN_C1 0xE398 |
2219 | #define B_AX_CTN_TXEN_TWT_3 BIT(17) |
2220 | #define B_AX_CTN_TXEN_TWT_2 BIT(16) |
2221 | #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0) |
2222 | |
2223 | #define R_AX_SCHEDULE_ERR_IMR 0xC3E8 |
2224 | #define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8 |
2225 | #define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1) |
2226 | |
2227 | #define R_AX_SCHEDULE_ERR_ISR 0xC3EC |
2228 | #define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC |
2229 | |
2230 | #define R_AX_SCH_DBG_SEL 0xC3F4 |
2231 | #define R_AX_SCH_DBG_SEL_C1 0xE3F4 |
2232 | #define B_AX_SCH_DBG_EN BIT(16) |
2233 | #define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8) |
2234 | #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0) |
2235 | |
2236 | #define R_AX_SCH_DBG 0xC3F8 |
2237 | #define R_AX_SCH_DBG_C1 0xE3F8 |
2238 | #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0) |
2239 | |
2240 | #define R_AX_SCH_EXT_CTRL 0xC3FC |
2241 | #define R_AX_SCH_EXT_CTRL_C1 0xE3FC |
2242 | #define B_AX_PORT_RST_TSF_ADV BIT(1) |
2243 | |
2244 | #define R_AX_PORT_CFG_P0 0xC400 |
2245 | #define R_AX_PORT_CFG_P1 0xC440 |
2246 | #define R_AX_PORT_CFG_P2 0xC480 |
2247 | #define R_AX_PORT_CFG_P3 0xC4C0 |
2248 | #define R_AX_PORT_CFG_P4 0xC500 |
2249 | #define B_AX_BRK_SETUP BIT(16) |
2250 | #define B_AX_TBTT_UPD_SHIFT_SEL BIT(15) |
2251 | #define B_AX_BCN_DROP_ALLOW BIT(14) |
2252 | #define B_AX_TBTT_PROHIB_EN BIT(13) |
2253 | #define B_AX_BCNTX_EN BIT(12) |
2254 | #define B_AX_NET_TYPE_MASK GENMASK(11, 10) |
2255 | #define B_AX_BCN_FORCETX_EN BIT(9) |
2256 | #define B_AX_TXBCN_BTCCA_EN BIT(8) |
2257 | #define B_AX_BCNERR_CNT_EN BIT(7) |
2258 | #define B_AX_BCN_AGRES BIT(6) |
2259 | #define B_AX_TSFTR_RST BIT(5) |
2260 | #define B_AX_RX_BSSID_FIT_EN BIT(4) |
2261 | #define B_AX_TSF_UDT_EN BIT(3) |
2262 | #define B_AX_PORT_FUNC_EN BIT(2) |
2263 | #define B_AX_TXBCN_RPT_EN BIT(1) |
2264 | #define B_AX_RXBCN_RPT_EN BIT(0) |
2265 | |
2266 | #define R_AX_TBTT_PROHIB_P0 0xC404 |
2267 | #define R_AX_TBTT_PROHIB_P1 0xC444 |
2268 | #define R_AX_TBTT_PROHIB_P2 0xC484 |
2269 | #define R_AX_TBTT_PROHIB_P3 0xC4C4 |
2270 | #define R_AX_TBTT_PROHIB_P4 0xC504 |
2271 | #define B_AX_TBTT_HOLD_MASK GENMASK(27, 16) |
2272 | #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0) |
2273 | |
2274 | #define R_AX_BCN_AREA_P0 0xC408 |
2275 | #define R_AX_BCN_AREA_P1 0xC448 |
2276 | #define R_AX_BCN_AREA_P2 0xC488 |
2277 | #define R_AX_BCN_AREA_P3 0xC4C8 |
2278 | #define R_AX_BCN_AREA_P4 0xC508 |
2279 | #define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16) |
2280 | #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0) |
2281 | |
2282 | #define R_AX_BCNERLYINT_CFG_P0 0xC40C |
2283 | #define R_AX_BCNERLYINT_CFG_P1 0xC44C |
2284 | #define R_AX_BCNERLYINT_CFG_P2 0xC48C |
2285 | #define R_AX_BCNERLYINT_CFG_P3 0xC4CC |
2286 | #define R_AX_BCNERLYINT_CFG_P4 0xC50C |
2287 | #define B_AX_BCNERLY_MASK GENMASK(11, 0) |
2288 | |
2289 | #define R_AX_TBTTERLYINT_CFG_P0 0xC40E |
2290 | #define R_AX_TBTTERLYINT_CFG_P1 0xC44E |
2291 | #define R_AX_TBTTERLYINT_CFG_P2 0xC48E |
2292 | #define R_AX_TBTTERLYINT_CFG_P3 0xC4CE |
2293 | #define R_AX_TBTTERLYINT_CFG_P4 0xC50E |
2294 | #define B_AX_TBTTERLY_MASK GENMASK(11, 0) |
2295 | |
2296 | #define R_AX_TBTT_AGG_P0 0xC412 |
2297 | #define R_AX_TBTT_AGG_P1 0xC452 |
2298 | #define R_AX_TBTT_AGG_P2 0xC492 |
2299 | #define R_AX_TBTT_AGG_P3 0xC4D2 |
2300 | #define R_AX_TBTT_AGG_P4 0xC512 |
2301 | #define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8) |
2302 | |
2303 | #define R_AX_BCN_SPACE_CFG_P0 0xC414 |
2304 | #define R_AX_BCN_SPACE_CFG_P1 0xC454 |
2305 | #define R_AX_BCN_SPACE_CFG_P2 0xC494 |
2306 | #define R_AX_BCN_SPACE_CFG_P3 0xC4D4 |
2307 | #define R_AX_BCN_SPACE_CFG_P4 0xC514 |
2308 | #define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16) |
2309 | #define B_AX_BCN_SPACE_MASK GENMASK(15, 0) |
2310 | |
2311 | #define R_AX_BCN_FORCETX_P0 0xC418 |
2312 | #define R_AX_BCN_FORCETX_P1 0xC458 |
2313 | #define R_AX_BCN_FORCETX_P2 0xC498 |
2314 | #define R_AX_BCN_FORCETX_P3 0xC4D8 |
2315 | #define R_AX_BCN_FORCETX_P4 0xC518 |
2316 | #define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16) |
2317 | #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0) |
2318 | #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0) |
2319 | |
2320 | #define R_AX_BCN_ERR_CNT_P0 0xC420 |
2321 | #define R_AX_BCN_ERR_CNT_P1 0xC460 |
2322 | #define R_AX_BCN_ERR_CNT_P2 0xC4A0 |
2323 | #define R_AX_BCN_ERR_CNT_P3 0xC4E0 |
2324 | #define R_AX_BCN_ERR_CNT_P4 0xC520 |
2325 | #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24) |
2326 | #define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16) |
2327 | #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0) |
2328 | #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0) |
2329 | |
2330 | #define R_AX_BCN_ERR_FLAG_P0 0xC424 |
2331 | #define R_AX_BCN_ERR_FLAG_P1 0xC464 |
2332 | #define R_AX_BCN_ERR_FLAG_P2 0xC4A4 |
2333 | #define R_AX_BCN_ERR_FLAG_P3 0xC4E4 |
2334 | #define R_AX_BCN_ERR_FLAG_P4 0xC524 |
2335 | #define B_AX_BCN_ERR_FLAG_OTHERS BIT(6) |
2336 | #define B_AX_BCN_ERR_FLAG_MAC BIT(5) |
2337 | #define B_AX_BCN_ERR_FLAG_TXON BIT(4) |
2338 | #define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3) |
2339 | #define B_AX_BCN_ERR_FLAG_INVALID BIT(2) |
2340 | #define B_AX_BCN_ERR_FLAG_CMP BIT(1) |
2341 | #define B_AX_BCN_ERR_FLAG_LOCK BIT(0) |
2342 | |
2343 | #define R_AX_DTIM_CTRL_P0 0xC426 |
2344 | #define R_AX_DTIM_CTRL_P1 0xC466 |
2345 | #define R_AX_DTIM_CTRL_P2 0xC4A6 |
2346 | #define R_AX_DTIM_CTRL_P3 0xC4E6 |
2347 | #define R_AX_DTIM_CTRL_P4 0xC526 |
2348 | #define B_AX_DTIM_NUM_MASK GENMASK(15, 8) |
2349 | #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0) |
2350 | |
2351 | #define R_AX_TBTT_SHIFT_P0 0xC428 |
2352 | #define R_AX_TBTT_SHIFT_P1 0xC468 |
2353 | #define R_AX_TBTT_SHIFT_P2 0xC4A8 |
2354 | #define R_AX_TBTT_SHIFT_P3 0xC4E8 |
2355 | #define R_AX_TBTT_SHIFT_P4 0xC528 |
2356 | #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0) |
2357 | #define B_AX_TBTT_SHIFT_OFST_SIGN BIT(11) |
2358 | #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0) |
2359 | |
2360 | #define R_AX_BCN_CNT_TMR_P0 0xC434 |
2361 | #define R_AX_BCN_CNT_TMR_P1 0xC474 |
2362 | #define R_AX_BCN_CNT_TMR_P2 0xC4B4 |
2363 | #define R_AX_BCN_CNT_TMR_P3 0xC4F4 |
2364 | #define R_AX_BCN_CNT_TMR_P4 0xC534 |
2365 | #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0) |
2366 | |
2367 | #define R_AX_TSFTR_LOW_P0 0xC438 |
2368 | #define R_AX_TSFTR_LOW_P1 0xC478 |
2369 | #define R_AX_TSFTR_LOW_P2 0xC4B8 |
2370 | #define R_AX_TSFTR_LOW_P3 0xC4F8 |
2371 | #define R_AX_TSFTR_LOW_P4 0xC538 |
2372 | #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0) |
2373 | |
2374 | #define R_AX_TSFTR_HIGH_P0 0xC43C |
2375 | #define R_AX_TSFTR_HIGH_P1 0xC47C |
2376 | #define R_AX_TSFTR_HIGH_P2 0xC4BC |
2377 | #define R_AX_TSFTR_HIGH_P3 0xC4FC |
2378 | #define R_AX_TSFTR_HIGH_P4 0xC53C |
2379 | #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0) |
2380 | |
2381 | #define R_AX_BCN_DROP_ALL0 0xC560 |
2382 | #define R_AX_BCN_DROP_ALL0_C1 0xE560 |
2383 | #define B_AX_BCN_DROP_ALL_P4 BIT(4) |
2384 | #define B_AX_BCN_DROP_ALL_P3 BIT(3) |
2385 | #define B_AX_BCN_DROP_ALL_P2 BIT(2) |
2386 | #define B_AX_BCN_DROP_ALL_P1 BIT(1) |
2387 | #define B_AX_BCN_DROP_ALL_P0 BIT(0) |
2388 | |
2389 | #define R_AX_MBSSID_CTRL 0xC568 |
2390 | #define R_AX_MBSSID_CTRL_C1 0xE568 |
2391 | #define B_AX_P0MB_ALL_MASK GENMASK(23, 1) |
2392 | #define B_AX_P0MB_NUM_MASK GENMASK(19, 16) |
2393 | #define B_AX_P0MB15_EN BIT(15) |
2394 | #define B_AX_P0MB14_EN BIT(14) |
2395 | #define B_AX_P0MB13_EN BIT(13) |
2396 | #define B_AX_P0MB12_EN BIT(12) |
2397 | #define B_AX_P0MB11_EN BIT(11) |
2398 | #define B_AX_P0MB10_EN BIT(10) |
2399 | #define B_AX_P0MB9_EN BIT(9) |
2400 | #define B_AX_P0MB8_EN BIT(8) |
2401 | #define B_AX_P0MB7_EN BIT(7) |
2402 | #define B_AX_P0MB6_EN BIT(6) |
2403 | #define B_AX_P0MB5_EN BIT(5) |
2404 | #define B_AX_P0MB4_EN BIT(4) |
2405 | #define B_AX_P0MB3_EN BIT(3) |
2406 | #define B_AX_P0MB2_EN BIT(2) |
2407 | #define B_AX_P0MB1_EN BIT(1) |
2408 | |
2409 | #define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590 |
2410 | #define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590 |
2411 | #define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0 |
2412 | #define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0 |
2413 | |
2414 | #define R_AX_PTCL_COMMON_SETTING_0 0xC600 |
2415 | #define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600 |
2416 | #define B_AX_PCIE_MODE_MASK GENMASK(15, 14) |
2417 | #define B_AX_CPUMGQ_LIFETIME_EN BIT(8) |
2418 | #define B_AX_MGQ_LIFETIME_EN BIT(7) |
2419 | #define B_AX_LIFETIME_EN BIT(6) |
2420 | #define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4) |
2421 | #define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3) |
2422 | #define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2) |
2423 | #define B_AX_CMAC_TX_MODE_1 BIT(1) |
2424 | #define B_AX_CMAC_TX_MODE_0 BIT(0) |
2425 | |
2426 | #define R_AX_AMPDU_AGG_LIMIT 0xC610 |
2427 | #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24) |
2428 | #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) |
2429 | #define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) |
2430 | #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0) |
2431 | |
2432 | #define R_AX_AGG_LEN_HT_0 0xC614 |
2433 | #define R_AX_AGG_LEN_HT_0_C1 0xE614 |
2434 | #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) |
2435 | #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8) |
2436 | #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0) |
2437 | |
2438 | #define S_AX_CTS2S_TH_SEC_256B 1 |
2439 | #define R_AX_SIFS_SETTING 0xC624 |
2440 | #define R_AX_SIFS_SETTING_C1 0xE624 |
2441 | #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) |
2442 | #define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) |
2443 | #define B_AX_HW_CTS2SELF_EN BIT(16) |
2444 | #define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8 |
2445 | #define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) |
2446 | #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) |
2447 | #define S_AX_CTS2S_TH_1K 4 |
2448 | |
2449 | #define R_AX_TXRATE_CHK 0xC628 |
2450 | #define R_AX_TXRATE_CHK_C1 0xE628 |
2451 | #define B_AX_DEFT_RATE_MASK GENMASK(15, 7) |
2452 | #define B_AX_BAND_MODE BIT(4) |
2453 | #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2) |
2454 | #define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1) |
2455 | #define B_AX_CHECK_CCK_EN BIT(0) |
2456 | |
2457 | #define R_AX_TXCNT 0xC62C |
2458 | #define R_AX_TXCNT_C1 0xE62C |
2459 | #define B_AX_ADD_TXCNT_BY BIT(31) |
2460 | #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24) |
2461 | #define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16) |
2462 | |
2463 | #define R_AX_MBSSID_DROP_0 0xC63C |
2464 | #define R_AX_MBSSID_DROP_0_C1 0xE63C |
2465 | #define B_AX_GI_LTF_FB_SEL BIT(30) |
2466 | #define B_AX_RATE_SEL_MASK GENMASK(29, 24) |
2467 | #define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16) |
2468 | #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0) |
2469 | |
2470 | #define R_AX_PTCLRPT_FULL_HDL 0xC660 |
2471 | #define R_AX_PTCLRPT_FULL_HDL_C1 0xE660 |
2472 | #define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12) |
2473 | #define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9) |
2474 | #define B_AX_F2PCMD_RPT_EN BIT(8) |
2475 | #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6) |
2476 | #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4) |
2477 | #define FWD_TO_WLCPU 1 |
2478 | #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2) |
2479 | #define B_AX_F2PCMDRPT_FULL_DROP BIT(1) |
2480 | #define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0) |
2481 | |
2482 | #define R_AX_BT_PLT 0xC67C |
2483 | #define R_AX_BT_PLT_C1 0xE67C |
2484 | #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) |
2485 | #define B_AX_BT_PLT_RST BIT(9) |
2486 | #define B_AX_PLT_EN BIT(8) |
2487 | #define B_AX_RX_PLT_GNT_LTE_RX BIT(7) |
2488 | #define B_AX_RX_PLT_GNT_BT_RX BIT(6) |
2489 | #define B_AX_RX_PLT_GNT_BT_TX BIT(5) |
2490 | #define B_AX_RX_PLT_GNT_WL BIT(4) |
2491 | #define B_AX_TX_PLT_GNT_LTE_RX BIT(3) |
2492 | #define B_AX_TX_PLT_GNT_BT_RX BIT(2) |
2493 | #define B_AX_TX_PLT_GNT_BT_TX BIT(1) |
2494 | #define B_AX_TX_PLT_GNT_WL BIT(0) |
2495 | |
2496 | #define R_AX_PTCL_BSS_COLOR_0 0xC6A0 |
2497 | #define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0 |
2498 | #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24) |
2499 | #define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16) |
2500 | #define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8) |
2501 | #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0) |
2502 | |
2503 | #define R_AX_PTCL_BSS_COLOR_1 0xC6A4 |
2504 | #define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4 |
2505 | #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0) |
2506 | |
2507 | #define R_AX_PTCL_IMR0 0xC6C0 |
2508 | #define R_AX_PTCL_IMR0_C1 0xE6C0 |
2509 | #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31) |
2510 | #define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30) |
2511 | #define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29) |
2512 | #define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28) |
2513 | #define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27) |
2514 | #define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26) |
2515 | #define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25) |
2516 | #define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24) |
2517 | #define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23) |
2518 | #define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15) |
2519 | #define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14) |
2520 | #define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12) |
2521 | #define B_AX_Q_PKTID_ERR_INT_EN BIT(11) |
2522 | #define B_AX_D_PKTID_ERR_INT_EN BIT(10) |
2523 | #define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9) |
2524 | #define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8) |
2525 | #define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1) |
2526 | #define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) |
2527 | #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0) |
2528 | #define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \ |
2529 | B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \ |
2530 | B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \ |
2531 | B_AX_D_PKTID_ERR_INT_EN | \ |
2532 | B_AX_Q_PKTID_ERR_INT_EN | \ |
2533 | B_AX_BCNQ_ORDER_ERR_INT_EN | \ |
2534 | B_AX_TWTSP_QSEL_ERR_INT_EN | \ |
2535 | B_AX_F2PCMD_EMPTY_ERR_INT_EN | \ |
2536 | B_AX_TX_RECORD_PKTID_ERR_INT_EN | \ |
2537 | B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | \ |
2538 | B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | \ |
2539 | B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | \ |
2540 | B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | \ |
2541 | B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | \ |
2542 | B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | \ |
2543 | B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | \ |
2544 | B_AX_F2PCMD_PKTID_ERR_INT_EN) |
2545 | #define B_AX_PTCL_IMR_SET (B_AX_FSM_TIMEOUT_ERR_INT_EN | \ |
2546 | B_AX_TX_RECORD_PKTID_ERR_INT_EN | \ |
2547 | B_AX_F2PCMD_USER_ALLC_ERR_INT_EN) |
2548 | #define B_AX_PTCL_IMR_CLR_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \ |
2549 | B_AX_FSM_TIMEOUT_ERR_INT_EN) |
2550 | #define B_AX_PTCL_IMR_SET_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \ |
2551 | B_AX_FSM_TIMEOUT_ERR_INT_EN) |
2552 | |
2553 | #define R_AX_PTCL_ISR0 0xC6C4 |
2554 | #define R_AX_PTCL_ISR0_C1 0xE6C4 |
2555 | |
2556 | #define S_AX_PTCL_TO_2MS 0x3F |
2557 | #define R_AX_PTCL_FSM_MON 0xC6E8 |
2558 | #define R_AX_PTCL_FSM_MON_C1 0xE6E8 |
2559 | #define B_AX_PTCL_TX_ARB_TO_MODE BIT(6) |
2560 | #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) |
2561 | |
2562 | #define R_AX_PTCL_TX_CTN_SEL 0xC6EC |
2563 | #define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC |
2564 | #define B_AX_PTCL_TX_ON_STAT BIT(7) |
2565 | |
2566 | #define R_AX_PTCL_DBG_INFO 0xC6F0 |
2567 | #define R_AX_PTCL_DBG_INFO_C1 0xE6F0 |
2568 | #define B_AX_PTCL_DBG_INFO_MASK_BY_PORT(port) \ |
2569 | ({\ |
2570 | typeof(port) _port = (port); \ |
2571 | GENMASK((_port) * 2 + 1, (_port) * 2); \ |
2572 | }) |
2573 | |
2574 | #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0) |
2575 | #define R_AX_PTCL_DBG 0xC6F4 |
2576 | #define R_AX_PTCL_DBG_C1 0xE6F4 |
2577 | #define B_AX_PTCL_DBG_EN BIT(8) |
2578 | #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0) |
2579 | #define AX_PTCL_DBG_BCNQ_NUM0 8 |
2580 | #define AX_PTCL_DBG_BCNQ_NUM1 9 |
2581 | |
2582 | |
2583 | #define R_AX_DLE_CTRL 0xC800 |
2584 | #define R_AX_DLE_CTRL_C1 0xE800 |
2585 | #define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23) |
2586 | #define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15) |
2587 | #define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14) |
2588 | #define B_AX_DLE_IMR_CLR (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \ |
2589 | B_AX_RXDATA_FSM_HANG_ERROR_IMR | \ |
2590 | B_AX_NO_RESERVE_PAGE_ERR_IMR) |
2591 | #define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \ |
2592 | B_AX_RXDATA_FSM_HANG_ERROR_IMR) |
2593 | |
2594 | #define R_AX_RX_ERR_FLAG 0xC800 |
2595 | #define R_AX_RX_ERR_FLAG_C1 0xE800 |
2596 | #define B_AX_RX_GET_NO_PAGE_ERR BIT(31) |
2597 | #define B_AX_RX_GET_NULL_PKT_ERR BIT(30) |
2598 | #define B_AX_RX_RU0_FSM_HANG_ERR BIT(29) |
2599 | #define B_AX_RX_RU1_FSM_HANG_ERR BIT(28) |
2600 | #define B_AX_RX_RU2_FSM_HANG_ERR BIT(27) |
2601 | #define B_AX_RX_RU3_FSM_HANG_ERR BIT(26) |
2602 | #define B_AX_RX_RU4_FSM_HANG_ERR BIT(25) |
2603 | #define B_AX_RX_RU5_FSM_HANG_ERR BIT(24) |
2604 | #define B_AX_RX_RU6_FSM_HANG_ERR BIT(23) |
2605 | #define B_AX_RX_RU7_FSM_HANG_ERR BIT(22) |
2606 | #define B_AX_RX_RXSTS_FSM_HANG_ERR BIT(21) |
2607 | #define B_AX_RX_CSI_FSM_HANG_ERR BIT(20) |
2608 | #define B_AX_RX_TXRPT_FSM_HANG_ERR BIT(19) |
2609 | #define B_AX_RX_F2PCMD_FSM_HANG_ERR BIT(18) |
2610 | #define B_AX_RX_RU0_ZERO_LEN_ERR BIT(17) |
2611 | #define B_AX_RX_RU1_ZERO_LEN_ERR BIT(16) |
2612 | #define B_AX_RX_RU2_ZERO_LEN_ERR BIT(15) |
2613 | #define B_AX_RX_RU3_ZERO_LEN_ERR BIT(14) |
2614 | #define B_AX_RX_RU4_ZERO_LEN_ERR BIT(13) |
2615 | #define B_AX_RX_RU5_ZERO_LEN_ERR BIT(12) |
2616 | #define B_AX_RX_RU6_ZERO_LEN_ERR BIT(11) |
2617 | #define B_AX_RX_RU7_ZERO_LEN_ERR BIT(10) |
2618 | #define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9) |
2619 | #define B_AX_RX_CSI_ZERO_LEN_ERR BIT(8) |
2620 | #define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7) |
2621 | #define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG BIT(6) |
2622 | #define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG BIT(5) |
2623 | #define B_AX_PLE_WD_OPT_FSM_HANG BIT(4) |
2624 | #define B_AX_PLE_ENQ_FSM_HANG BIT(3) |
2625 | #define B_AX_RXDATA_ENQUE_ORDER_ERR BIT(2) |
2626 | #define B_AX_RXSTS_ENQUE_ORDER_ERR BIT(1) |
2627 | #define B_AX_RX_CSI_PKT_NUM_ERR BIT(0) |
2628 | |
2629 | #define R_AX_RXDMA_CTRL_0 0xC804 |
2630 | #define R_AX_RXDMA_CTRL_0_C1 0xE804 |
2631 | #define B_AX_RXDMA_DBGOUT_EN BIT(31) |
2632 | #define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29) |
2633 | #define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25) |
2634 | #define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21) |
2635 | #define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19) |
2636 | #define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13) |
2637 | #define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10) |
2638 | #define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9) |
2639 | #define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7) |
2640 | #define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6) |
2641 | #define B_AX_RXSTS_PTR_FULL_MODE BIT(5) |
2642 | #define B_AX_CSI_PTR_FULL_MODE BIT(4) |
2643 | #define B_AX_RU3_PTR_FULL_MODE BIT(3) |
2644 | #define B_AX_RU2_PTR_FULL_MODE BIT(2) |
2645 | #define B_AX_RU1_PTR_FULL_MODE BIT(1) |
2646 | #define B_AX_RU0_PTR_FULL_MODE BIT(0) |
2647 | #define RX_FULL_MODE (B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | \ |
2648 | B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \ |
2649 | B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE) |
2650 | |
2651 | #define R_AX_RX_CTRL0 0xC808 |
2652 | #define R_AX_RX_CTRL0_C1 0xE808 |
2653 | #define B_AX_DLE_CLOCK_FORCE_V1 BIT(31) |
2654 | #define B_AX_TXDMA_CLOCK_FORCE_V1 BIT(30) |
2655 | #define B_AX_RXDMA_CLOCK_FORCE_V1 BIT(29) |
2656 | #define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24) |
2657 | #define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18) |
2658 | #define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15) |
2659 | #define B_AX_RXDMA_DIS_CSI_RELEASE_V1 BIT(14) |
2660 | #define B_AX_CSI_PTR_FULL_MODE_V1 BIT(13) |
2661 | #define B_AX_RXDATA_PTR_FULL_MODE BIT(12) |
2662 | #define B_AX_RXSTS_PTR_FULL_MODE_V1 BIT(11) |
2663 | #define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8) |
2664 | #define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5) |
2665 | #define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2) |
2666 | #define B_AX_ORDER_FIFO_MASK GENMASK(1, 0) |
2667 | |
2668 | #define R_AX_RX_CTRL1 0xC80C |
2669 | #define R_AX_RX_CTRL1_C1 0xE80C |
2670 | #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31) |
2671 | #define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25) |
2672 | #define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24) |
2673 | #define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18) |
2674 | #define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_EN BIT(17) |
2675 | #define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11) |
2676 | #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_EN BIT(10) |
2677 | #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4) |
2678 | #define B_AX_ORDER_FIFO_OUT BIT(3) |
2679 | #define B_AX_ORDER_FIFO_EMPTY BIT(2) |
2680 | #define B_AX_DBG_SEL_MASK GENMASK(1, 0) |
2681 | |
2682 | #define R_AX_RX_CTRL2 0xC810 |
2683 | #define R_AX_RX_CTRL2_C1 0xE810 |
2684 | #define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30) |
2685 | #define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28) |
2686 | #define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26) |
2687 | #define B_AX_DLE_ENQ_STATE_V1 BIT(25) |
2688 | #define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19) |
2689 | #define B_AX_MACRX_CS_MASK GENMASK(18, 14) |
2690 | #define B_AX_RXSTS_CS_MASK GENMASK(13, 9) |
2691 | #define B_AX_ERR_INDICATOR BIT(5) |
2692 | #define B_AX_TXRPT_CS_MASK GENMASK(4, 0) |
2693 | |
2694 | #define R_AX_RXDMA_PKT_INFO_0 0xC814 |
2695 | #define R_AX_RXDMA_PKT_INFO_1 0xC818 |
2696 | #define R_AX_RXDMA_PKT_INFO_2 0xC81C |
2697 | |
2698 | #define R_AX_RX_ERR_FLAG_IMR 0xC804 |
2699 | #define R_AX_RX_ERR_FLAG_IMR_C1 0xE804 |
2700 | #define B_AX_RX_GET_NULL_PKT_ERR_MSK BIT(30) |
2701 | #define B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK BIT(29) |
2702 | #define B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK BIT(28) |
2703 | #define B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK BIT(27) |
2704 | #define B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK BIT(26) |
2705 | #define B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK BIT(25) |
2706 | #define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24) |
2707 | #define B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK BIT(23) |
2708 | #define B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK BIT(22) |
2709 | #define B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK BIT(21) |
2710 | #define B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK BIT(20) |
2711 | #define B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK BIT(19) |
2712 | #define B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK BIT(18) |
2713 | #define B_AX_RX_RU0_ZERO_LEN_ERR_MSK BIT(17) |
2714 | #define B_AX_RX_RU1_ZERO_LEN_ERR_MSK BIT(16) |
2715 | #define B_AX_RX_RU2_ZERO_LEN_ERR_MSK BIT(15) |
2716 | #define B_AX_RX_RU3_ZERO_LEN_ERR_MSK BIT(14) |
2717 | #define B_AX_RX_RU4_ZERO_LEN_ERR_MSK BIT(13) |
2718 | #define B_AX_RX_RU5_ZERO_LEN_ERR_MSK BIT(12) |
2719 | #define B_AX_RX_RU6_ZERO_LEN_ERR_MSK BIT(11) |
2720 | #define B_AX_RX_RU7_ZERO_LEN_ERR_MSK BIT(10) |
2721 | #define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9) |
2722 | #define B_AX_RX_CSI_ZERO_LEN_ERR_MSK BIT(8) |
2723 | #define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7) |
2724 | #define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG_MSK BIT(6) |
2725 | #define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG_MSK BIT(5) |
2726 | #define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4) |
2727 | #define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3) |
2728 | #define B_AX_RXDATA_ENQUE_ORDER_ERR_MSK BIT(2) |
2729 | #define B_AX_RXSTS_ENQUE_ORDER_ERR_MSK BIT(1) |
2730 | #define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0) |
2731 | #define B_AX_RX_ERR_IMR_CLR_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \ |
2732 | B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \ |
2733 | B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \ |
2734 | B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \ |
2735 | B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \ |
2736 | B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \ |
2737 | B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \ |
2738 | B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \ |
2739 | B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \ |
2740 | B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \ |
2741 | B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \ |
2742 | B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \ |
2743 | B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \ |
2744 | B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \ |
2745 | B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \ |
2746 | B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \ |
2747 | B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \ |
2748 | B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \ |
2749 | B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \ |
2750 | B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \ |
2751 | B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \ |
2752 | B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \ |
2753 | B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \ |
2754 | B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \ |
2755 | B_AX_RX_GET_NULL_PKT_ERR_MSK) |
2756 | #define B_AX_RX_ERR_IMR_SET_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \ |
2757 | B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \ |
2758 | B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \ |
2759 | B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \ |
2760 | B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \ |
2761 | B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \ |
2762 | B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \ |
2763 | B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \ |
2764 | B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \ |
2765 | B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \ |
2766 | B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \ |
2767 | B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \ |
2768 | B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \ |
2769 | B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \ |
2770 | B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \ |
2771 | B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \ |
2772 | B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \ |
2773 | B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \ |
2774 | B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \ |
2775 | B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \ |
2776 | B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \ |
2777 | B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \ |
2778 | B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \ |
2779 | B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \ |
2780 | B_AX_RX_GET_NULL_PKT_ERR_MSK) |
2781 | |
2782 | #define R_AX_TX_ERR_FLAG_IMR 0xC870 |
2783 | #define R_AX_TX_ERR_FLAG_IMR_C1 0xE870 |
2784 | #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31) |
2785 | #define B_AX_TX_RU1_FSM_HANG_ERR_MSK BIT(30) |
2786 | #define B_AX_TX_RU2_FSM_HANG_ERR_MSK BIT(29) |
2787 | #define B_AX_TX_RU3_FSM_HANG_ERR_MSK BIT(28) |
2788 | #define B_AX_TX_RU4_FSM_HANG_ERR_MSK BIT(27) |
2789 | #define B_AX_TX_RU5_FSM_HANG_ERR_MSK BIT(26) |
2790 | #define B_AX_TX_RU6_FSM_HANG_ERR_MSK BIT(25) |
2791 | #define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24) |
2792 | #define B_AX_TX_RU8_FSM_HANG_ERR_MSK BIT(23) |
2793 | #define B_AX_TX_RU9_FSM_HANG_ERR_MSK BIT(22) |
2794 | #define B_AX_TX_RU10_FSM_HANG_ERR_MSK BIT(21) |
2795 | #define B_AX_TX_RU11_FSM_HANG_ERR_MSK BIT(20) |
2796 | #define B_AX_TX_RU12_FSM_HANG_ERR_MSK BIT(19) |
2797 | #define B_AX_TX_RU13_FSM_HANG_ERR_MSK BIT(18) |
2798 | #define B_AX_TX_RU14_FSM_HANG_ERR_MSK BIT(17) |
2799 | #define B_AX_TX_RU15_FSM_HANG_ERR_MSK BIT(16) |
2800 | #define B_AX_TX_CSI_FSM_HANG_ERR_MSK BIT(15) |
2801 | #define B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK BIT(14) |
2802 | #define B_AX_TX_ERR_IMR_CLR_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \ |
2803 | B_AX_TX_CSI_FSM_HANG_ERR_MSK | \ |
2804 | B_AX_TX_RU7_FSM_HANG_ERR_MSK | \ |
2805 | B_AX_TX_RU6_FSM_HANG_ERR_MSK | \ |
2806 | B_AX_TX_RU5_FSM_HANG_ERR_MSK | \ |
2807 | B_AX_TX_RU4_FSM_HANG_ERR_MSK | \ |
2808 | B_AX_TX_RU3_FSM_HANG_ERR_MSK | \ |
2809 | B_AX_TX_RU2_FSM_HANG_ERR_MSK | \ |
2810 | B_AX_TX_RU1_FSM_HANG_ERR_MSK | \ |
2811 | B_AX_TX_RU0_FSM_HANG_ERR_MSK) |
2812 | #define B_AX_TX_ERR_IMR_SET_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \ |
2813 | B_AX_TX_CSI_FSM_HANG_ERR_MSK | \ |
2814 | B_AX_TX_RU7_FSM_HANG_ERR_MSK | \ |
2815 | B_AX_TX_RU6_FSM_HANG_ERR_MSK | \ |
2816 | B_AX_TX_RU5_FSM_HANG_ERR_MSK | \ |
2817 | B_AX_TX_RU4_FSM_HANG_ERR_MSK | \ |
2818 | B_AX_TX_RU3_FSM_HANG_ERR_MSK | \ |
2819 | B_AX_TX_RU2_FSM_HANG_ERR_MSK | \ |
2820 | B_AX_TX_RU1_FSM_HANG_ERR_MSK | \ |
2821 | B_AX_TX_RU0_FSM_HANG_ERR_MSK) |
2822 | |
2823 | #define R_AX_TCR0 0xCA00 |
2824 | #define R_AX_TCR0_C1 0xEA00 |
2825 | #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24) |
2826 | #define B_AX_TCR_UDF_EN BIT(23) |
2827 | #define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16) |
2828 | #define TCR_UDF_THSD 0x6 |
2829 | #define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10) |
2830 | #define B_AX_TCR_VHTSIGA1_TXPS BIT(9) |
2831 | #define B_AX_TCR_PLCP_ERRHDL_EN BIT(8) |
2832 | #define B_AX_TCR_PADSEL BIT(7) |
2833 | #define B_AX_TCR_MASK_SIGBCRC BIT(6) |
2834 | #define B_AX_TCR_SR_VAL15_ALLOW BIT(5) |
2835 | #define B_AX_TCR_EN_EOF BIT(4) |
2836 | #define B_AX_TCR_EN_SCRAM_INC BIT(3) |
2837 | #define B_AX_TCR_EN_20MST BIT(2) |
2838 | #define B_AX_TCR_CRC BIT(1) |
2839 | #define B_AX_TCR_DISGCLK BIT(0) |
2840 | |
2841 | #define R_AX_TCR1 0xCA04 |
2842 | #define R_AX_TCR1_C1 0xEA04 |
2843 | #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28) |
2844 | #define B_AX_TCR_CCK_LOCK_CLK BIT(27) |
2845 | #define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26) |
2846 | #define B_AX_TCR_USTIME GENMASK(23, 16) |
2847 | #define B_AX_TCR_SMOOTH_VAL BIT(15) |
2848 | #define B_AX_TCR_SMOOTH_CTRL BIT(14) |
2849 | #define B_AX_CS_REQ_VAL BIT(13) |
2850 | #define B_AX_CS_REQ_SEL BIT(12) |
2851 | #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8) |
2852 | #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0) |
2853 | |
2854 | #define R_AX_MD_TSFT_STMP_CTL 0xCA08 |
2855 | #define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08 |
2856 | #define B_AX_TSFT_OFS_MASK GENMASK(31, 16) |
2857 | #define B_AX_STMP_THSD_MASK GENMASK(15, 8) |
2858 | #define B_AX_UPD_HGQMD BIT(1) |
2859 | #define B_AX_UPD_TIMIE BIT(0) |
2860 | |
2861 | #define R_AX_PPWRBIT_SETTING 0xCA0C |
2862 | #define R_AX_PPWRBIT_SETTING_C1 0xEA0C |
2863 | |
2864 | #define R_AX_TXD_FIFO_CTRL 0xCA1C |
2865 | #define R_AX_TXD_FIFO_CTRL_C1 0xEA1C |
2866 | #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24) |
2867 | #define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16) |
2868 | #define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12) |
2869 | #define TXDFIFO_HIGH_MCS_THRE 0x7 |
2870 | #define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8) |
2871 | #define TXDFIFO_LOW_MCS_THRE 0x7 |
2872 | #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4) |
2873 | #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0) |
2874 | |
2875 | #define R_AX_MACTX_DBG_SEL_CNT 0xCA20 |
2876 | #define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20 |
2877 | #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24) |
2878 | #define B_AX_MACTX_DMA_CNT GENMASK(23, 16) |
2879 | #define B_AX_LENGTH_ERR_FLAG_U3 BIT(11) |
2880 | #define B_AX_LENGTH_ERR_FLAG_U2 BIT(10) |
2881 | #define B_AX_LENGTH_ERR_FLAG_U1 BIT(9) |
2882 | #define B_AX_LENGTH_ERR_FLAG_U0 BIT(8) |
2883 | #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0) |
2884 | |
2885 | #define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4 |
2886 | #define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4 |
2887 | #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0) |
2888 | |
2889 | #define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8 |
2890 | #define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8 |
2891 | #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0) |
2892 | |
2893 | #define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC |
2894 | #define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC |
2895 | #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0) |
2896 | |
2897 | #define R_AX_RSP_CHK_SIG 0xCC00 |
2898 | #define R_AX_RSP_CHK_SIG_C1 0xEC00 |
2899 | #define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) |
2900 | #define B_AX_RSP_TBPPDU_CHK_PWR BIT(29) |
2901 | #define B_AX_RSP_CHK_BASIC_NAV BIT(21) |
2902 | #define B_AX_RSP_CHK_INTRA_NAV BIT(20) |
2903 | #define B_AX_RSP_CHK_TXNAV BIT(19) |
2904 | #define B_AX_TXDATA_END_PS_OPT BIT(18) |
2905 | #define B_AX_CHECK_SOUNDING_SEQ BIT(17) |
2906 | #define B_AX_RXBA_IGNOREA2 BIT(16) |
2907 | #define B_AX_ACKTO_CCK_MASK GENMASK(15, 8) |
2908 | #define B_AX_ACKTO_MASK GENMASK(7, 0) |
2909 | |
2910 | #define R_AX_TRXPTCL_RESP_0 0xCC04 |
2911 | #define R_AX_TRXPTCL_RESP_0_C1 0xEC04 |
2912 | #define B_AX_WMAC_RESP_STBC_EN BIT(31) |
2913 | #define B_AX_WMAC_RXFTM_TXACK_SC BIT(30) |
2914 | #define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29) |
2915 | #define B_AX_RSP_CHK_SEC_CCA_80 BIT(28) |
2916 | #define B_AX_RSP_CHK_SEC_CCA_40 BIT(27) |
2917 | #define B_AX_RSP_CHK_SEC_CCA_20 BIT(26) |
2918 | #define B_AX_RSP_CHK_BTCCA BIT(25) |
2919 | #define B_AX_RSP_CHK_EDCCA BIT(24) |
2920 | #define B_AX_RSP_CHK_CCA BIT(23) |
2921 | #define B_AX_WMAC_LDPC_EN BIT(22) |
2922 | #define B_AX_WMAC_SGIEN BIT(21) |
2923 | #define B_AX_WMAC_SPLCPEN BIT(20) |
2924 | #define B_AX_WMAC_BESP_EARLY_TXBA BIT(17) |
2925 | #define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8) |
2926 | #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) |
2927 | #define WMAC_SPEC_SIFS_OFDM_52A 0x15 |
2928 | #define WMAC_SPEC_SIFS_OFDM_52B 0x11 |
2929 | #define WMAC_SPEC_SIFS_OFDM_52C 0x11 |
2930 | #define WMAC_SPEC_SIFS_CCK 0xA |
2931 | |
2932 | #define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08 |
2933 | #define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08 |
2934 | #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31) |
2935 | #define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28) |
2936 | #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24) |
2937 | #define B_AX_NESS_MASK GENMASK(23, 22) |
2938 | #define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21) |
2939 | #define B_AX_WMAC_RESP_DCM_EN BIT(20) |
2940 | #define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16) |
2941 | #define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12) |
2942 | #define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10) |
2943 | #define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9) |
2944 | #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0) |
2945 | |
2946 | #define R_AX_MAC_LOOPBACK 0xCC20 |
2947 | #define R_AX_MAC_LOOPBACK_C1 0xEC20 |
2948 | #define B_AX_MACLBK_EN BIT(0) |
2949 | |
2950 | #define R_AX_WMAC_NAV_CTL 0xCC80 |
2951 | #define R_AX_WMAC_NAV_CTL_C1 0xEC80 |
2952 | #define B_AX_WMAC_NAV_UPPER_EN BIT(26) |
2953 | #define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18) |
2954 | #define B_AX_WMAC_PLCP_UP_NAV_EN BIT(17) |
2955 | #define B_AX_WMAC_TF_UP_NAV_EN BIT(16) |
2956 | #define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8) |
2957 | #define NAV_12MS 0xBC |
2958 | #define NAV_25MS 0xC4 |
2959 | #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0) |
2960 | |
2961 | #define R_AX_RXTRIG_TEST_USER_2 0xCCB0 |
2962 | #define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0 |
2963 | #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24) |
2964 | #define B_AX_RXTRIG_RU26_DIS BIT(21) |
2965 | #define B_AX_RXTRIG_FCSCHK_EN BIT(20) |
2966 | #define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) |
2967 | #define B_AX_RXTRIG_EN BIT(16) |
2968 | #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) |
2969 | |
2970 | #define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC |
2971 | #define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC |
2972 | #define B_AX_WMAC_MODE BIT(22) |
2973 | #define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16) |
2974 | #define B_AX_RMAC_FTM BIT(8) |
2975 | #define B_AX_RMAC_CSI BIT(7) |
2976 | #define B_AX_TMAC_MIMO_CTRL BIT(6) |
2977 | #define B_AX_TMAC_RXTB BIT(5) |
2978 | #define B_AX_TMAC_HWSIGB_GEN BIT(4) |
2979 | #define B_AX_TMAC_TXPLCP BIT(3) |
2980 | #define B_AX_TMAC_RESP BIT(2) |
2981 | #define B_AX_TMAC_TXCTL BIT(1) |
2982 | #define B_AX_TMAC_MACTX BIT(0) |
2983 | #define B_AX_TMAC_IMR_CLR_V1 (B_AX_TMAC_MACTX | \ |
2984 | B_AX_TMAC_TXCTL | \ |
2985 | B_AX_TMAC_RESP | \ |
2986 | B_AX_TMAC_TXPLCP | \ |
2987 | B_AX_TMAC_HWSIGB_GEN | \ |
2988 | B_AX_TMAC_RXTB | \ |
2989 | B_AX_TMAC_MIMO_CTRL | \ |
2990 | B_AX_RMAC_CSI | \ |
2991 | B_AX_RMAC_FTM) |
2992 | #define B_AX_TMAC_IMR_SET_V1 (B_AX_TMAC_MACTX | \ |
2993 | B_AX_TMAC_TXCTL | \ |
2994 | B_AX_TMAC_RESP | \ |
2995 | B_AX_TMAC_TXPLCP | \ |
2996 | B_AX_TMAC_HWSIGB_GEN | \ |
2997 | B_AX_TMAC_RXTB | \ |
2998 | B_AX_TMAC_MIMO_CTRL | \ |
2999 | B_AX_RMAC_FTM) |
3000 | |
3001 | #define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0 |
3002 | #define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0 |
3003 | #define B_AX_FTM_ERROR_FLAG_CLR BIT(8) |
3004 | #define B_AX_CSI_ERROR_FLAG_CLR BIT(7) |
3005 | #define B_AX_MIMOCTRL_ERROR_FLAG_CLR BIT(6) |
3006 | #define B_AX_RXTB_ERROR_FLAG_CLR BIT(5) |
3007 | #define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4) |
3008 | #define B_AX_TXPLCP_ERROR_FLAG_CLR BIT(3) |
3009 | #define B_AX_RESP_ERROR_FLAG_CLR BIT(2) |
3010 | #define B_AX_TXCTL_ERROR_FLAG_CLR BIT(1) |
3011 | #define B_AX_MACTX_ERROR_FLAG_CLR BIT(0) |
3012 | |
3013 | #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0 |
3014 | #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0 |
3015 | #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0) |
3016 | |
3017 | #define R_AX_WMAC_TX_TF_INFO_1 0xCCD4 |
3018 | #define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4 |
3019 | #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0) |
3020 | |
3021 | #define R_AX_WMAC_TX_TF_INFO_2 0xCCD8 |
3022 | #define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8 |
3023 | #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0) |
3024 | |
3025 | #define R_AX_TMAC_ERR_IMR_ISR 0xCCEC |
3026 | #define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC |
3027 | #define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19) |
3028 | #define B_AX_TMAC_RESP_ERR_CLR BIT(18) |
3029 | #define B_AX_TMAC_TXCTL_ERR_CLR BIT(17) |
3030 | #define B_AX_TMAC_MACTX_ERR_CLR BIT(16) |
3031 | #define B_AX_TMAC_TXPLCP_ERR BIT(14) |
3032 | #define B_AX_TMAC_RESP_ERR BIT(13) |
3033 | #define B_AX_TMAC_TXCTL_ERR BIT(12) |
3034 | #define B_AX_TMAC_MACTX_ERR BIT(11) |
3035 | #define B_AX_TMAC_TXPLCP_INT_EN BIT(10) |
3036 | #define B_AX_TMAC_RESP_INT_EN BIT(9) |
3037 | #define B_AX_TMAC_TXCTL_INT_EN BIT(8) |
3038 | #define B_AX_TMAC_MACTX_INT_EN BIT(7) |
3039 | #define B_AX_WMAC_INT_MODE BIT(6) |
3040 | #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0) |
3041 | #define B_AX_TMAC_IMR_CLR (B_AX_TMAC_MACTX_INT_EN | \ |
3042 | B_AX_TMAC_TXCTL_INT_EN | \ |
3043 | B_AX_TMAC_RESP_INT_EN | \ |
3044 | B_AX_TMAC_TXPLCP_INT_EN) |
3045 | #define B_AX_TMAC_IMR_SET (B_AX_TMAC_MACTX_INT_EN | \ |
3046 | B_AX_TMAC_TXCTL_INT_EN | \ |
3047 | B_AX_TMAC_RESP_INT_EN | \ |
3048 | B_AX_TMAC_TXPLCP_INT_EN) |
3049 | |
3050 | #define R_AX_DBGSEL_TRXPTCL 0xCCF4 |
3051 | #define R_AX_DBGSEL_TRXPTCL_C1 0xECF4 |
3052 | #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0) |
3053 | |
3054 | #define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8 |
3055 | #define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8 |
3056 | #define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16) |
3057 | #define B_AX_CSI_ON_TIMEOUT_EN BIT(5) |
3058 | #define B_AX_STS_ON_TIMEOUT_EN BIT(4) |
3059 | #define B_AX_DATA_ON_TIMEOUT_EN BIT(3) |
3060 | #define B_AX_OFDM_CCA_TIMEOUT_EN BIT(2) |
3061 | #define B_AX_CCK_CCA_TIMEOUT_EN BIT(1) |
3062 | #define B_AX_PHY_TXON_TIMEOUT_EN BIT(0) |
3063 | #define B_AX_PHYINFO_IMR_CLR_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \ |
3064 | B_AX_CCK_CCA_TIMEOUT_EN | \ |
3065 | B_AX_OFDM_CCA_TIMEOUT_EN | \ |
3066 | B_AX_DATA_ON_TIMEOUT_EN | \ |
3067 | B_AX_STS_ON_TIMEOUT_EN | \ |
3068 | B_AX_CSI_ON_TIMEOUT_EN) |
3069 | #define B_AX_PHYINFO_IMR_SET_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \ |
3070 | B_AX_CCK_CCA_TIMEOUT_EN | \ |
3071 | B_AX_OFDM_CCA_TIMEOUT_EN | \ |
3072 | B_AX_DATA_ON_TIMEOUT_EN | \ |
3073 | B_AX_STS_ON_TIMEOUT_EN | \ |
3074 | B_AX_CSI_ON_TIMEOUT_EN) |
3075 | |
3076 | #define R_AX_PHYINFO_ERR_IMR 0xCCFC |
3077 | #define R_AX_PHYINFO_ERR_IMR_C1 0xECFC |
3078 | #define B_AX_CSI_ON_TIMEOUT BIT(29) |
3079 | #define B_AX_STS_ON_TIMEOUT BIT(28) |
3080 | #define B_AX_DATA_ON_TIMEOUT BIT(27) |
3081 | #define B_AX_OFDM_CCA_TIMEOUT BIT(26) |
3082 | #define B_AX_CCK_CCA_TIMEOUT BIT(25) |
3083 | #define B_AXC_PHY_TXON_TIMEOUT BIT(24) |
3084 | #define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21) |
3085 | #define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20) |
3086 | #define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19) |
3087 | #define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18) |
3088 | #define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17) |
3089 | #define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16) |
3090 | #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0) |
3091 | #define B_AX_PHYINFO_IMR_EN_ALL (B_AX_PHY_TXON_TIMEOUT_INT_EN | \ |
3092 | B_AX_CCK_CCA_TIMEOUT_INT_EN | \ |
3093 | B_AX_OFDM_CCA_TIMEOUT_INT_EN | \ |
3094 | B_AX_DATA_ON_TIMEOUT_INT_EN | \ |
3095 | B_AX_STS_ON_TIMEOUT_INT_EN | \ |
3096 | B_AX_CSI_ON_TIMEOUT_INT_EN) |
3097 | |
3098 | #define R_AX_PHYINFO_ERR_ISR 0xCCFC |
3099 | #define R_AX_PHYINFO_ERR_ISR_C1 0xECFC |
3100 | |
3101 | #define R_AX_BFMER_CTRL_0 0xCD78 |
3102 | #define R_AX_BFMER_CTRL_0_C1 0xED78 |
3103 | #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24) |
3104 | #define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16) |
3105 | #define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8) |
3106 | #define B_AX_BFMER_NDP_BFEN BIT(2) |
3107 | #define B_AX_BFMER_VHT_BFPRT_CHK BIT(0) |
3108 | |
3109 | #define R_AX_BFMEE_RESP_OPTION 0xCD80 |
3110 | #define R_AX_BFMEE_RESP_OPTION_C1 0xED80 |
3111 | #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24) |
3112 | #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20) |
3113 | #define BFRP_RX_STANDBY_TIMER_KEEP 0x0 |
3114 | #define BFRP_RX_STANDBY_TIMER_RELEASE 0x1 |
3115 | #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17) |
3116 | #define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16) |
3117 | #define BFRP_RX_STANDBY_TIMER 0x0 |
3118 | #define NDP_RX_STANDBY_TIMER 0xFF |
3119 | #define B_AX_BFMEE_HE_NDPA_EN BIT(2) |
3120 | #define B_AX_BFMEE_VHT_NDPA_EN BIT(1) |
3121 | #define B_AX_BFMEE_HT_NDPA_EN BIT(0) |
3122 | |
3123 | #define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88 |
3124 | #define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88 |
3125 | #define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94 |
3126 | #define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94 |
3127 | #define B_AX_BFMEE_CSISEQ_SEL BIT(29) |
3128 | #define B_AX_BFMEE_BFPARAM_SEL BIT(28) |
3129 | #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) |
3130 | #define B_AX_BFMEE_BF_PORT_SEL BIT(23) |
3131 | #define B_AX_BFMEE_USE_NSTS BIT(22) |
3132 | #define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21) |
3133 | #define B_AX_BFMEE_CSI_GID_SEL BIT(20) |
3134 | #define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18) |
3135 | #define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17) |
3136 | #define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16) |
3137 | #define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15) |
3138 | #define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14) |
3139 | #define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13) |
3140 | #define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12) |
3141 | #define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) |
3142 | #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) |
3143 | #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) |
3144 | #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) |
3145 | #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) |
3146 | |
3147 | #define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C |
3148 | #define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C |
3149 | #define CSI_RRSC_BMAP 0x29292911 |
3150 | |
3151 | #define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90 |
3152 | #define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90 |
3153 | #define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16) |
3154 | #define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8) |
3155 | #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0) |
3156 | #define CSI_INIT_RATE_HE 0x3 |
3157 | #define CSI_INIT_RATE_VHT 0x3 |
3158 | #define CSI_INIT_RATE_HT 0x3 |
3159 | |
3160 | #define R_AX_RCR 0xCE00 |
3161 | #define R_AX_RCR_C1 0xEE00 |
3162 | #define B_AX_STOP_RX_IN BIT(11) |
3163 | #define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8) |
3164 | #define B_AX_CH_EN_MASK GENMASK(3, 0) |
3165 | |
3166 | #define R_AX_DLK_PROTECT_CTL 0xCE02 |
3167 | #define R_AX_DLK_PROTECT_CTL_C1 0xEE02 |
3168 | #define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) |
3169 | #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) |
3170 | |
3171 | #define R_AX_PLCP_HDR_FLTR 0xCE04 |
3172 | #define R_AX_PLCP_HDR_FLTR_C1 0xEE04 |
3173 | #define B_AX_DIS_CHK_MIN_LEN BIT(8) |
3174 | #define B_AX_HE_SIGB_CRC_CHK BIT(6) |
3175 | #define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5) |
3176 | #define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4) |
3177 | #define B_AX_SIGA_CRC_CHK BIT(3) |
3178 | #define B_AX_LSIG_PARITY_CHK_EN BIT(2) |
3179 | #define B_AX_CCK_SIG_CHK BIT(1) |
3180 | #define B_AX_CCK_CRC_CHK BIT(0) |
3181 | |
3182 | #define R_AX_RX_FLTR_OPT 0xCE20 |
3183 | #define R_AX_RX_FLTR_OPT_C1 0xEE20 |
3184 | #define B_AX_UID_FILTER_MASK GENMASK(31, 24) |
3185 | #define B_AX_UNSPT_FILTER_SH 22 |
3186 | #define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22) |
3187 | #define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) |
3188 | #define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f |
3189 | #define B_AX_A_FTM_REQ BIT(14) |
3190 | #define B_AX_A_ERR_PKT BIT(13) |
3191 | #define B_AX_A_UNSUP_PKT BIT(12) |
3192 | #define B_AX_A_CRC32_ERR BIT(11) |
3193 | #define B_AX_A_PWR_MGNT BIT(10) |
3194 | #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8) |
3195 | #define B_AX_A_BCN_CHK_EN BIT(7) |
3196 | #define B_AX_A_MC_LIST_CAM_MATCH BIT(6) |
3197 | #define B_AX_A_BC_CAM_MATCH BIT(5) |
3198 | #define B_AX_A_UC_CAM_MATCH BIT(4) |
3199 | #define B_AX_A_MC BIT(3) |
3200 | #define B_AX_A_BC BIT(2) |
3201 | #define B_AX_A_A1_MATCH BIT(1) |
3202 | #define B_AX_SNIFFER_MODE BIT(0) |
3203 | #define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC | \ |
3204 | B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH | \ |
3205 | B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ | \ |
3206 | u32_encode_bits(3, B_AX_UID_FILTER_MASK) | \ |
3207 | B_AX_A_BCN_CHK_EN) |
3208 | #define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK) |
3209 | |
3210 | #define R_AX_CTRL_FLTR 0xCE24 |
3211 | #define R_AX_CTRL_FLTR_C1 0xEE24 |
3212 | #define R_AX_MGNT_FLTR 0xCE28 |
3213 | #define R_AX_MGNT_FLTR_C1 0xEE28 |
3214 | #define R_AX_DATA_FLTR 0xCE2C |
3215 | #define R_AX_DATA_FLTR_C1 0xEE2C |
3216 | #define RX_FLTR_FRAME_DROP 0x00000000 |
3217 | #define RX_FLTR_FRAME_TO_HOST 0x55555555 |
3218 | #define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA |
3219 | |
3220 | #define R_AX_ADDR_CAM_CTRL 0xCE34 |
3221 | #define R_AX_ADDR_CAM_CTRL_C1 0xEE34 |
3222 | #define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16) |
3223 | #define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) |
3224 | #define B_AX_ADDR_CAM_CLR BIT(8) |
3225 | #define B_AX_ADDR_CAM_A2_B0_CHK BIT(2) |
3226 | #define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1) |
3227 | #define B_AX_ADDR_CAM_EN BIT(0) |
3228 | |
3229 | #define R_AX_RESPBA_CAM_CTRL 0xCE3C |
3230 | #define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C |
3231 | #define B_AX_SSN_SEL BIT(2) |
3232 | #define B_AX_BACAM_RST_MASK GENMASK(1, 0) |
3233 | #define S_AX_BACAM_RST_ALL 2 |
3234 | |
3235 | #define R_AX_PPDU_STAT 0xCE40 |
3236 | #define R_AX_PPDU_STAT_C1 0xEE40 |
3237 | #define B_AX_PPDU_STAT_RPT_TRIG BIT(8) |
3238 | #define B_AX_PPDU_STAT_RPT_CRC32 BIT(5) |
3239 | #define B_AX_PPDU_STAT_RPT_A1M BIT(4) |
3240 | #define B_AX_APP_PLCP_HDR_RPT BIT(3) |
3241 | #define B_AX_APP_RX_CNT_RPT BIT(2) |
3242 | #define B_AX_APP_MAC_INFO_RPT BIT(1) |
3243 | #define B_AX_PPDU_STAT_RPT_EN BIT(0) |
3244 | |
3245 | #define R_AX_RX_SR_CTRL 0xCE4A |
3246 | #define R_AX_RX_SR_CTRL_C1 0xEE4A |
3247 | #define B_AX_SR_EN BIT(0) |
3248 | |
3249 | #define R_AX_BSSID_SRC_CTRL 0xCE4B |
3250 | #define R_AX_BSSID_SRC_CTRL_C1 0xEE4B |
3251 | #define B_AX_BSSID_MATCH BIT(3) |
3252 | #define B_AX_PARTIAL_AID_MATCH BIT(2) |
3253 | #define B_AX_BSSCOLOR_MATCH BIT(1) |
3254 | #define B_AX_PLCP_SRC_EN BIT(0) |
3255 | |
3256 | #define R_AX_CSIRPT_OPTION 0xCE64 |
3257 | #define R_AX_CSIRPT_OPTION_C1 0xEE64 |
3258 | #define B_AX_CSIPRT_HESU_AID_EN BIT(25) |
3259 | #define B_AX_CSIPRT_VHTSU_AID_EN BIT(24) |
3260 | |
3261 | #define R_AX_RX_STATE_MONITOR 0xCEF0 |
3262 | #define R_AX_RX_STATE_MONITOR_C1 0xEEF0 |
3263 | #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0) |
3264 | #define B_AX_STATE_CUR_MASK GENMASK(31, 16) |
3265 | #define B_AX_STATE_NXT_MASK GENMASK(13, 8) |
3266 | #define B_AX_STATE_UPD BIT(7) |
3267 | #define B_AX_STATE_SEL_MASK GENMASK(4, 0) |
3268 | |
3269 | #define R_AX_RMAC_ERR_ISR 0xCEF4 |
3270 | #define R_AX_RMAC_ERR_ISR_C1 0xEEF4 |
3271 | #define B_AX_RXERR_INTPS_EN BIT(31) |
3272 | #define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19) |
3273 | #define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18) |
3274 | #define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17) |
3275 | #define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16) |
3276 | #define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15) |
3277 | #define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14) |
3278 | #define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13) |
3279 | #define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12) |
3280 | #define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7) |
3281 | #define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6) |
3282 | #define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5) |
3283 | #define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4) |
3284 | #define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3) |
3285 | #define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2) |
3286 | #define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1) |
3287 | #define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0) |
3288 | #define B_AX_RMAC_IMR_CLR (B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | \ |
3289 | B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | \ |
3290 | B_AX_RMAC_DMA_TIMEOUT_INT_EN | \ |
3291 | B_AX_RMAC_CCA_TIMEOUT_INT_EN | \ |
3292 | B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | \ |
3293 | B_AX_RMAC_CSI_TIMEOUT_INT_EN | \ |
3294 | B_AX_RMAC_RX_TIMEOUT_INT_EN | \ |
3295 | B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN) |
3296 | #define B_AX_RMAC_IMR_SET (B_AX_RMAC_DMA_TIMEOUT_INT_EN | \ |
3297 | B_AX_RMAC_CSI_TIMEOUT_INT_EN | \ |
3298 | B_AX_RMAC_RX_TIMEOUT_INT_EN | \ |
3299 | B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN) |
3300 | |
3301 | #define R_AX_RX_ERR_IMR 0xCEF8 |
3302 | #define R_AX_RX_ERR_IMR_C1 0xEEF8 |
3303 | #define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9) |
3304 | #define B_AX_RX_ERR_STS_ACT_TO_MSK BIT(8) |
3305 | #define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7) |
3306 | #define B_AX_RX_ERR_ACT_TO_MSK BIT(6) |
3307 | #define B_AX_CSI_DATAON_ASSERT_TO_MSK BIT(5) |
3308 | #define B_AX_DATAON_ASSERT_TO_MSK BIT(4) |
3309 | #define B_AX_CCA_ASSERT_TO_MSK BIT(3) |
3310 | #define B_AX_RX_ERR_DMA_TO_MSK BIT(2) |
3311 | #define B_AX_RX_ERR_DATA_TO_MSK BIT(1) |
3312 | #define B_AX_RX_ERR_CCA_TO_MSK BIT(0) |
3313 | #define B_AX_RMAC_IMR_CLR_V1 (B_AX_RX_ERR_CCA_TO_MSK | \ |
3314 | B_AX_RX_ERR_DATA_TO_MSK | \ |
3315 | B_AX_RX_ERR_DMA_TO_MSK | \ |
3316 | B_AX_CCA_ASSERT_TO_MSK | \ |
3317 | B_AX_DATAON_ASSERT_TO_MSK | \ |
3318 | B_AX_CSI_DATAON_ASSERT_TO_MSK | \ |
3319 | B_AX_RX_ERR_ACT_TO_MSK | \ |
3320 | B_AX_RX_ERR_CSI_ACT_TO_MSK | \ |
3321 | B_AX_RX_ERR_STS_ACT_TO_MSK | \ |
3322 | B_AX_RX_ERR_TRIG_ACT_TO_MSK) |
3323 | #define B_AX_RMAC_IMR_SET_V1 (B_AX_RX_ERR_CCA_TO_MSK | \ |
3324 | B_AX_RX_ERR_DATA_TO_MSK | \ |
3325 | B_AX_RX_ERR_DMA_TO_MSK | \ |
3326 | B_AX_CCA_ASSERT_TO_MSK | \ |
3327 | B_AX_DATAON_ASSERT_TO_MSK | \ |
3328 | B_AX_CSI_DATAON_ASSERT_TO_MSK | \ |
3329 | B_AX_RX_ERR_ACT_TO_MSK | \ |
3330 | B_AX_RX_ERR_CSI_ACT_TO_MSK | \ |
3331 | B_AX_RX_ERR_STS_ACT_TO_MSK | \ |
3332 | B_AX_RX_ERR_TRIG_ACT_TO_MSK) |
3333 | |
3334 | #define R_AX_RMAC_PLCP_MON 0xCEF8 |
3335 | #define R_AX_RMAC_PLCP_MON_C1 0xEEF8 |
3336 | #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0) |
3337 | #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28) |
3338 | #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0) |
3339 | |
3340 | #define R_AX_RX_DEBUG_SELECT 0xCEFC |
3341 | #define R_AX_RX_DEBUG_SELECT_C1 0xEEFC |
3342 | #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0) |
3343 | |
3344 | #define R_AX_PWR_RATE_CTRL 0xD200 |
3345 | #define R_AX_PWR_RATE_CTRL_C1 0xF200 |
3346 | #define B_AX_PWR_REF GENMASK(27, 10) |
3347 | #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) |
3348 | #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0) |
3349 | |
3350 | #define R_AX_PWR_RATE_OFST_CTRL 0xD204 |
3351 | #define R_AX_PWR_COEXT_CTRL 0xD220 |
3352 | #define B_AX_TXAGC_BT_EN BIT(1) |
3353 | #define B_AX_TXAGC_BT_MASK GENMASK(11, 3) |
3354 | |
3355 | #define R_AX_PWR_SWING_OTHER_CTRL0 0xD230 |
3356 | #define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230 |
3357 | #define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0) |
3358 | |
3359 | #define R_AX_PWR_UL_CTRL0 0xD240 |
3360 | #define R_AX_PWR_UL_CTRL2 0xD248 |
3361 | #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0) |
3362 | #define B_AX_PWR_UL_CTRL2_MASK 0x07700007 |
3363 | |
3364 | #define R_AX_PWR_NORM_FORCE1 0xD260 |
3365 | #define R_AX_PWR_NORM_FORCE1_C1 0xF260 |
3366 | #define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29) |
3367 | #define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24) |
3368 | #define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23) |
3369 | #define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22) |
3370 | #define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21) |
3371 | #define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20) |
3372 | #define B_AX_FORCE_BT_GRANT_EN BIT(19) |
3373 | #define B_AX_FORCE_BT_GRANT_VALUE BIT(18) |
3374 | #define B_AX_FORCE_RX_LTE_EN BIT(17) |
3375 | #define B_AX_FORCE_RX_LTE_VALUE BIT(16) |
3376 | #define B_AX_FORCE_TXBF_EN_EN BIT(15) |
3377 | #define B_AX_FORCE_TXBF_EN_VALUE BIT(14) |
3378 | #define B_AX_FORCE_TXSC_EN BIT(13) |
3379 | #define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9) |
3380 | #define B_AX_FORCE_NTX_EN BIT(6) |
3381 | #define B_AX_FORCE_NTX_VALUE BIT(5) |
3382 | #define B_AX_FORCE_PWR_MODE_EN BIT(3) |
3383 | #define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0) |
3384 | |
3385 | #define R_AX_PWR_UL_TB_CTRL 0xD288 |
3386 | #define B_AX_PWR_UL_TB_CTRL_EN BIT(31) |
3387 | #define R_AX_PWR_UL_TB_1T 0xD28C |
3388 | #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0) |
3389 | #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0) |
3390 | #define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24) |
3391 | #define R_AX_PWR_UL_TB_2T 0xD290 |
3392 | #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) |
3393 | #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0) |
3394 | #define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24) |
3395 | #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 |
3396 | #define R_AX_PWR_BY_RATE_TABLE6 0xD2D8 |
3397 | #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 |
3398 | #define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0 |
3399 | #define R_AX_PWR_BY_RATE_1SS_MAX R_AX_PWR_BY_RATE_TABLE6 |
3400 | #define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10 |
3401 | #define R_AX_PWR_LMT_TABLE0 0xD2EC |
3402 | #define R_AX_PWR_LMT_TABLE9 0xD310 |
3403 | #define R_AX_PWR_LMT_TABLE19 0xD338 |
3404 | #define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0 |
3405 | #define R_AX_PWR_LMT_1SS_MAX R_AX_PWR_LMT_TABLE9 |
3406 | #define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19 |
3407 | #define R_AX_PWR_RU_LMT_TABLE0 0xD33C |
3408 | #define R_AX_PWR_RU_LMT_TABLE5 0xD350 |
3409 | #define R_AX_PWR_RU_LMT_TABLE11 0xD368 |
3410 | #define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0 |
3411 | #define R_AX_PWR_RU_LMT_1SS_MAX R_AX_PWR_RU_LMT_TABLE5 |
3412 | #define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11 |
3413 | #define R_AX_PWR_MACID_LMT_TABLE0 0xD36C |
3414 | #define R_AX_PWR_MACID_LMT_TABLE127 0xD568 |
3415 | |
3416 | #define R_AX_PATH_COM0 0xD800 |
3417 | #define AX_PATH_COM0_DFVAL 0x00000000 |
3418 | #define AX_PATH_COM0_PATHA 0x08889880 |
3419 | #define AX_PATH_COM0_PATHB 0x11111900 |
3420 | #define AX_PATH_COM0_PATHAB 0x19999980 |
3421 | #define R_AX_PATH_COM1 0xD804 |
3422 | #define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28) |
3423 | #define AX_PATH_COM1_DFVAL 0x00000000 |
3424 | #define AX_PATH_COM1_PATHA 0x13111111 |
3425 | #define AX_PATH_COM1_PATHB 0x23222222 |
3426 | #define AX_PATH_COM1_PATHAB 0x33333333 |
3427 | #define R_AX_PATH_COM2 0xD808 |
3428 | #define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4) |
3429 | #define AX_PATH_COM2_DFVAL 0x00000000 |
3430 | #define AX_PATH_COM2_PATHA 0x01209313 |
3431 | #define AX_PATH_COM2_PATHB 0x01209323 |
3432 | #define AX_PATH_COM2_PATHAB 0x01209333 |
3433 | #define R_AX_PATH_COM3 0xD80C |
3434 | #define AX_PATH_COM3_DFVAL 0x49249249 |
3435 | #define R_AX_PATH_COM4 0xD810 |
3436 | #define AX_PATH_COM4_DFVAL 0x1C9C9C49 |
3437 | #define R_AX_PATH_COM5 0xD814 |
3438 | #define AX_PATH_COM5_DFVAL 0x39393939 |
3439 | #define R_AX_PATH_COM6 0xD818 |
3440 | #define AX_PATH_COM6_DFVAL 0x39393939 |
3441 | #define R_AX_PATH_COM7 0xD81C |
3442 | #define AX_PATH_COM7_DFVAL 0x39393939 |
3443 | #define AX_PATH_COM7_PATHA 0x39393939 |
3444 | #define AX_PATH_COM7_PATHB 0x39383939 |
3445 | #define AX_PATH_COM7_PATHAB 0x39393939 |
3446 | #define R_AX_PATH_COM8 0xD820 |
3447 | #define AX_PATH_COM8_DFVAL 0x00000000 |
3448 | #define AX_PATH_COM8_PATHA 0x00003939 |
3449 | #define AX_PATH_COM8_PATHB 0x00003938 |
3450 | #define AX_PATH_COM8_PATHAB 0x00003939 |
3451 | #define R_AX_PATH_COM9 0xD824 |
3452 | #define AX_PATH_COM9_DFVAL 0x000007C0 |
3453 | #define R_AX_PATH_COM10 0xD828 |
3454 | #define AX_PATH_COM10_DFVAL 0xE0000000 |
3455 | #define R_AX_PATH_COM11 0xD82C |
3456 | #define AX_PATH_COM11_DFVAL 0x00000000 |
3457 | #define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848 |
3458 | #define B_P80_AT_HIGH_FREQ_BB_WRP BIT(28) |
3459 | #define R_AX_TSSI_CTRL_HEAD 0xD908 |
3460 | #define R_AX_BANDEDGE_CFG 0xD94C |
3461 | #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30) |
3462 | #define R_AX_TSSI_CTRL_TAIL 0xD95C |
3463 | |
3464 | #define R_AX_TXPWR_IMR 0xD9E0 |
3465 | #define R_AX_TXPWR_IMR_C1 0xF9E0 |
3466 | #define R_AX_TXPWR_ISR 0xD9E4 |
3467 | #define R_AX_TXPWR_ISR_C1 0xF9E4 |
3468 | |
3469 | #define R_AX_BTC_CFG 0xDA00 |
3470 | #define B_AX_BTC_EN BIT(31) |
3471 | #define B_AX_EN_EXT_BT_PINMUX BIT(29) |
3472 | #define B_AX_BTC_RST BIT(28) |
3473 | #define B_AX_BTC_DBG_SRC_SEL BIT(27) |
3474 | #define B_AX_BTC_MODE_MASK GENMASK(25, 24) |
3475 | #define B_AX_INV_WL_ACT2 BIT(17) |
3476 | #define B_AX_BTG_LNA1_GAIN_SEL BIT(16) |
3477 | #define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8) |
3478 | #define B_AX_IGN_GNT_BT2_RX BIT(7) |
3479 | #define B_AX_IGN_GNT_BT2_TX BIT(6) |
3480 | #define B_AX_IGN_GNT_BT2 BIT(5) |
3481 | #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3) |
3482 | #define B_AX_DIS_BTC_CLK_G BIT(2) |
3483 | #define B_AX_GNT_WL_RX_CTRL BIT(1) |
3484 | #define B_AX_WL_SRC BIT(0) |
3485 | |
3486 | #define R_AX_RTK_MODE_CFG_V1 0xDA04 |
3487 | #define R_AX_RTK_MODE_CFG_V1_C1 0xFA04 |
3488 | #define B_AX_BT_BLE_EN_V1 BIT(24) |
3489 | #define B_AX_BT_ULTRA_EN BIT(16) |
3490 | #define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14) |
3491 | #define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12) |
3492 | #define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10) |
3493 | #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8) |
3494 | #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0) |
3495 | |
3496 | #define R_AX_WL_PRI_MSK 0xDA10 |
3497 | #define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8) |
3498 | |
3499 | #define R_AX_BT_CNT_CFG 0xDA10 |
3500 | #define R_AX_BT_CNT_CFG_C1 0xFA10 |
3501 | #define B_AX_BT_CNT_RST_V1 BIT(1) |
3502 | #define B_AX_BT_CNT_EN BIT(0) |
3503 | |
3504 | #define R_BTC_BT_CNT_HIGH 0xDA14 |
3505 | #define R_BTC_BT_CNT_LOW 0xDA18 |
3506 | |
3507 | #define R_AX_BTC_FUNC_EN 0xDA20 |
3508 | #define R_AX_BTC_FUNC_EN_C1 0xFA20 |
3509 | #define B_AX_PTA_WL_TX_EN BIT(1) |
3510 | #define B_AX_PTA_EDCCA_EN BIT(0) |
3511 | |
3512 | #define R_BTC_COEX_WL_REQ 0xDA24 |
3513 | #define R_BTC_COEX_WL_REQ_BE 0xE324 |
3514 | #define B_BTC_TX_NULL_HI BIT(23) |
3515 | #define B_BTC_TX_BCN_HI BIT(22) |
3516 | #define B_BTC_TX_TRI_HI BIT(17) |
3517 | #define B_BTC_RSP_ACK_HI BIT(10) |
3518 | #define B_BTC_PRI_MASK_TX_TIME GENMASK(4, 3) |
3519 | #define B_BTC_PRI_MASK_RX_TIME_V1 GENMASK(2, 1) |
3520 | |
3521 | #define R_BTC_BREAK_TABLE 0xDA2C |
3522 | #define BTC_BREAK_PARAM 0xf0ffffff |
3523 | |
3524 | #define R_BTC_BT_COEX_MSK_TABLE 0xDA30 |
3525 | #define B_BTC_PRI_MASK_RXCCK_V1 BIT(28) |
3526 | #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) |
3527 | |
3528 | #define R_AX_BT_COEX_CFG_2 0xDA34 |
3529 | #define R_AX_BT_COEX_CFG_2_C1 0xFA34 |
3530 | #define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12) |
3531 | #define B_AX_GNT_BT_POLARITY BIT(8) |
3532 | #define B_AX_TIMER_MASK GENMASK(7, 0) |
3533 | #define MAC_AX_CSR_RATE 80 |
3534 | |
3535 | #define R_AX_CSR_MODE 0xDA40 |
3536 | #define R_AX_CSR_MODE_C1 0xFA40 |
3537 | #define B_AX_BT_CNT_RST BIT(16) |
3538 | #define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12) |
3539 | #define MAC_AX_CSR_DELAY 0 |
3540 | #define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8) |
3541 | #define MAC_AX_CSR_TRX_TO 4 |
3542 | #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4) |
3543 | #define MAC_AX_CSR_PRI_TO 5 |
3544 | #define B_AX_WL_ACT_MSK BIT(3) |
3545 | #define B_AX_STATIS_BT_EN BIT(2) |
3546 | #define B_AX_WL_ACT_MASK_ENABLE BIT(1) |
3547 | #define B_AX_ENHANCED_BT BIT(0) |
3548 | |
3549 | #define R_AX_BT_BREAK_TABLE 0xDA44 |
3550 | |
3551 | #define R_AX_BT_STAST_HIGH 0xDA44 |
3552 | #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16) |
3553 | #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0) |
3554 | #define R_AX_BT_STAST_LOW 0xDA48 |
3555 | #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0) |
3556 | #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16) |
3557 | |
3558 | #define R_AX_GNT_SW_CTRL 0xDA48 |
3559 | #define R_AX_GNT_SW_CTRL_C1 0xFA48 |
3560 | #define B_AX_WL_ACT2_VAL BIT(21) |
3561 | #define B_AX_WL_ACT2_SWCTRL BIT(20) |
3562 | #define B_AX_WL_ACT_VAL BIT(19) |
3563 | #define B_AX_WL_ACT_SWCTRL BIT(18) |
3564 | #define B_AX_GNT_BT_RX_VAL BIT(17) |
3565 | #define B_AX_GNT_BT_RX_SWCTRL BIT(16) |
3566 | #define B_AX_GNT_BT_TX_VAL BIT(15) |
3567 | #define B_AX_GNT_BT_TX_SWCTRL BIT(14) |
3568 | #define B_AX_GNT_WL_RX_VAL BIT(13) |
3569 | #define B_AX_GNT_WL_RX_SWCTRL BIT(12) |
3570 | #define B_AX_GNT_WL_TX_VAL BIT(11) |
3571 | #define B_AX_GNT_WL_TX_SWCTRL BIT(10) |
3572 | #define B_AX_GNT_BT_RFC_S1_VAL BIT(9) |
3573 | #define B_AX_GNT_BT_RFC_S1_SWCTRL BIT(8) |
3574 | #define B_AX_GNT_WL_RFC_S1_VAL BIT(7) |
3575 | #define B_AX_GNT_WL_RFC_S1_SWCTRL BIT(6) |
3576 | #define B_AX_GNT_BT_RFC_S0_VAL BIT(5) |
3577 | #define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4) |
3578 | #define B_AX_GNT_WL_RFC_S0_VAL BIT(3) |
3579 | #define B_AX_GNT_WL_RFC_S0_SWCTRL BIT(2) |
3580 | #define B_AX_GNT_WL_BB_VAL BIT(1) |
3581 | #define B_AX_GNT_WL_BB_SWCTRL BIT(0) |
3582 | |
3583 | #define R_AX_GNT_VAL 0x0054 |
3584 | #define B_AX_GNT_BT_RFC_S1_STA BIT(5) |
3585 | #define B_AX_GNT_WL_RFC_S1_STA BIT(4) |
3586 | #define B_AX_GNT_BT_RFC_S0_STA BIT(3) |
3587 | #define B_AX_GNT_WL_RFC_S0_STA BIT(2) |
3588 | |
3589 | #define R_AX_GNT_VAL_V1 0xDA4C |
3590 | #define B_AX_GNT_BT_RFC_S1 BIT(4) |
3591 | #define B_AX_GNT_BT_RFC_S0 BIT(3) |
3592 | #define B_AX_GNT_WL_RFC_S1 BIT(2) |
3593 | #define B_AX_GNT_WL_RFC_S0 BIT(1) |
3594 | |
3595 | #define R_AX_TDMA_MODE 0xDA4C |
3596 | #define R_AX_TDMA_MODE_C1 0xFA4C |
3597 | #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16) |
3598 | #define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8) |
3599 | #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6) |
3600 | #define B_AX_TDMA_BT_START_NOTIFY BIT(5) |
3601 | #define B_AX_ENABLE_TDMA_FW_MODE BIT(4) |
3602 | #define B_AX_ENABLE_PTA_TDMA_MODE BIT(3) |
3603 | #define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) |
3604 | #define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) |
3605 | #define B_AX_RTK_BT_ENABLE BIT(0) |
3606 | |
3607 | #define R_AX_BT_COEX_CFG_5 0xDA6C |
3608 | #define R_AX_BT_COEX_CFG_5_C1 0xFA6C |
3609 | #define B_AX_BT_TIME_MASK GENMASK(31, 6) |
3610 | #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0) |
3611 | #define MAC_AX_RTK_RATE 5 |
3612 | |
3613 | #define R_AX_LTE_CTRL 0xDAF0 |
3614 | #define R_AX_LTE_WDATA 0xDAF4 |
3615 | #define R_AX_LTE_RDATA 0xDAF8 |
3616 | |
3617 | #define R_AX_MACID_ANT_TABLE 0xDC00 |
3618 | #define R_AX_MACID_ANT_TABLE_LAST 0xDDFC |
3619 | |
3620 | #define CMAC1_START_ADDR_AX 0xE000 |
3621 | #define CMAC1_END_ADDR_AX 0xFFFF |
3622 | #define R_AX_CMAC_REG_END 0xFFFF |
3623 | |
3624 | #define R_AX_LTE_SW_CFG_1 0x0038 |
3625 | #define R_AX_LTE_SW_CFG_1_C1 0x2038 |
3626 | #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31) |
3627 | #define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30) |
3628 | #define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29) |
3629 | #define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28) |
3630 | #define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27) |
3631 | #define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26) |
3632 | #define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25) |
3633 | #define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24) |
3634 | #define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19) |
3635 | #define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18) |
3636 | #define B_AX_LTE_PATTERN_2_EN BIT(17) |
3637 | #define B_AX_LTE_PATTERN_1_EN BIT(16) |
3638 | #define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15) |
3639 | #define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14) |
3640 | #define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13) |
3641 | #define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12) |
3642 | #define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11) |
3643 | #define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10) |
3644 | #define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9) |
3645 | #define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8) |
3646 | #define B_AX_LTECOEX_FUN_EN BIT(7) |
3647 | #define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6) |
3648 | #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4) |
3649 | #define B_AX_LTECOEX_UART_MUX BIT(3) |
3650 | #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0) |
3651 | |
3652 | #define R_AX_LTE_SW_CFG_2 0x003C |
3653 | #define R_AX_LTE_SW_CFG_2_C1 0x203C |
3654 | #define B_AX_WL_RX_CTRL BIT(8) |
3655 | #define B_AX_GNT_WL_RX_SW_VAL BIT(7) |
3656 | #define B_AX_GNT_WL_RX_SW_CTRL BIT(6) |
3657 | #define B_AX_GNT_WL_TX_SW_VAL BIT(5) |
3658 | #define B_AX_GNT_WL_TX_SW_CTRL BIT(4) |
3659 | #define B_AX_GNT_BT_RX_SW_VAL BIT(3) |
3660 | #define B_AX_GNT_BT_RX_SW_CTRL BIT(2) |
3661 | #define B_AX_GNT_BT_TX_SW_VAL BIT(1) |
3662 | #define B_AX_GNT_BT_TX_SW_CTRL BIT(0) |
3663 | |
3664 | #define R_BE_SYS_ISO_CTRL 0x0000 |
3665 | #define B_BE_PWC_EV2EF_B BIT(15) |
3666 | #define B_BE_PWC_EV2EF_S BIT(14) |
3667 | #define B_BE_PA33V_EN BIT(13) |
3668 | #define B_BE_PA12V_EN BIT(12) |
3669 | #define B_BE_PAOOBS33V_EN BIT(11) |
3670 | #define B_BE_PAOOBS12V_EN BIT(10) |
3671 | #define B_BE_ISO_RFDIO BIT(9) |
3672 | #define B_BE_ISO_EB2CORE BIT(8) |
3673 | #define B_BE_ISO_DIOE BIT(7) |
3674 | #define B_BE_ISO_WLPON2PP BIT(6) |
3675 | #define B_BE_ISO_IP2MAC_WA02PP BIT(5) |
3676 | #define B_BE_ISO_PD2CORE BIT(4) |
3677 | #define B_BE_ISO_PA2PCIE BIT(3) |
3678 | #define B_BE_ISO_PAOOBS2PCIE BIT(1) |
3679 | #define B_BE_ISO_WD2PP BIT(0) |
3680 | |
3681 | #define R_BE_SYS_PW_CTRL 0x0004 |
3682 | #define B_BE_SOP_ASWRM BIT(31) |
3683 | #define B_BE_SOP_EASWR BIT(30) |
3684 | #define B_BE_SOP_PWMM_DSWR BIT(29) |
3685 | #define B_BE_SOP_EDSWR BIT(28) |
3686 | #define B_BE_SOP_ACKF BIT(27) |
3687 | #define B_BE_SOP_ERCK BIT(26) |
3688 | #define B_BE_SOP_ANA_CLK_DIVISION_2 BIT(25) |
3689 | #define B_BE_SOP_EXTL BIT(24) |
3690 | #define B_BE_SOP_OFF_CAPC_EN BIT(23) |
3691 | #define B_BE_XTAL_OFF_A_DIE BIT(22) |
3692 | #define B_BE_ROP_SWPR BIT(21) |
3693 | #define B_BE_DIS_HW_LPLDM BIT(20) |
3694 | #define B_BE_DIS_HW_LPURLDO BIT(19) |
3695 | #define B_BE_DIS_WLBT_PDNSUSEN_SOPC BIT(18) |
3696 | #define B_BE_RDY_SYSPWR BIT(17) |
3697 | #define B_BE_EN_WLON BIT(16) |
3698 | #define B_BE_APDM_HPDN BIT(15) |
3699 | #define B_BE_PSUS_OFF_CAPC_EN BIT(14) |
3700 | #define B_BE_AFSM_PCIE_SUS_EN BIT(12) |
3701 | #define B_BE_AFSM_WLSUS_EN BIT(11) |
3702 | #define B_BE_APFM_SWLPS BIT(10) |
3703 | #define B_BE_APFM_OFFMAC BIT(9) |
3704 | #define B_BE_APFN_ONMAC BIT(8) |
3705 | #define B_BE_CHIP_PDN_EN BIT(7) |
3706 | #define B_BE_RDY_MACDIS BIT(6) |
3707 | |
3708 | #define R_BE_SYS_CLK_CTRL 0x0008 |
3709 | #define B_BE_CPU_CLK_EN BIT(14) |
3710 | #define B_BE_SYMR_BE_CLK_EN BIT(13) |
3711 | #define B_BE_MAC_CLK_EN BIT(11) |
3712 | #define B_BE_EXT_32K_EN BIT(8) |
3713 | #define B_BE_WL_CLK_TEST BIT(7) |
3714 | #define B_BE_LOADER_CLK_EN BIT(5) |
3715 | #define B_BE_ANA_CLK_DIVISION_2 BIT(1) |
3716 | #define B_BE_CNTD16V_EN BIT(0) |
3717 | |
3718 | #define R_BE_SYS_WL_EFUSE_CTRL 0x000A |
3719 | #define B_BE_OTP_B_PWC_RPT BIT(15) |
3720 | #define B_BE_OTP_S_PWC_RPT BIT(14) |
3721 | #define B_BE_OTP_ISO_RPT BIT(13) |
3722 | #define B_BE_OTP_BURST_RPT BIT(12) |
3723 | #define B_BE_OTP_AUTOLOAD_RPT BIT(11) |
3724 | #define B_BE_AUTOLOAD_DIS_A_DIE BIT(6) |
3725 | #define B_BE_AUTOLOAD_SUS BIT(5) |
3726 | #define B_BE_AUTOLOAD_DIS BIT(4) |
3727 | |
3728 | #define R_BE_SYS_PAGE_CLK_GATED 0x000C |
3729 | #define B_BE_USB_APHY_PC_DLP_OP BIT(27) |
3730 | #define B_BE_PCIE_APHY_PC_DLP_OP BIT(26) |
3731 | #define B_BE_UPHY_POWER_READY_CHK BIT(25) |
3732 | #define B_BE_CPHY_POWER_READY_CHK BIT(24) |
3733 | #define B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK GENMASK(23, 22) |
3734 | #define B_BE_SYM_PRST_DEBUNC_SEL BIT(21) |
3735 | #define B_BE_CPHY_AUXCLK_OP BIT(20) |
3736 | #define B_BE_SOP_OFFUA_PC BIT(19) |
3737 | #define B_BE_SOP_OFFPOOBS_PC BIT(18) |
3738 | #define B_BE_PCIE_LAN1_MASK BIT(17) |
3739 | #define B_BE_PCIE_LAN0_MASK BIT(16) |
3740 | #define B_BE_DIS_CLK_REGF_GATE BIT(15) |
3741 | #define B_BE_DIS_CLK_REGE_GATE BIT(14) |
3742 | #define B_BE_DIS_CLK_REGD_GATE BIT(13) |
3743 | #define B_BE_DIS_CLK_REGC_GATE BIT(12) |
3744 | #define B_BE_DIS_CLK_REGB_GATE BIT(11) |
3745 | #define B_BE_DIS_CLK_REGA_GATE BIT(10) |
3746 | #define B_BE_DIS_CLK_REG9_GATE BIT(9) |
3747 | #define B_BE_DIS_CLK_REG8_GATE BIT(8) |
3748 | #define B_BE_DIS_CLK_REG7_GATE BIT(7) |
3749 | #define B_BE_DIS_CLK_REG6_GATE BIT(6) |
3750 | #define B_BE_DIS_CLK_REG5_GATE BIT(5) |
3751 | #define B_BE_DIS_CLK_REG4_GATE BIT(4) |
3752 | #define B_BE_DIS_CLK_REG3_GATE BIT(3) |
3753 | #define B_BE_DIS_CLK_REG2_GATE BIT(2) |
3754 | #define B_BE_DIS_CLK_REG1_GATE BIT(1) |
3755 | #define B_BE_DIS_CLK_REG0_GATE BIT(0) |
3756 | |
3757 | #define R_BE_ANAPAR_POW_MAC 0x0016 |
3758 | #define B_BE_POW_PC_LDO_PORT1 BIT(3) |
3759 | #define B_BE_POW_PC_LDO_PORT0 BIT(2) |
3760 | #define B_BE_POW_PLL_V1 BIT(1) |
3761 | #define B_BE_POW_POWER_CUT_POW_LDO BIT(0) |
3762 | |
3763 | #define R_BE_SYS_ADIE_PAD_PWR_CTRL 0x0018 |
3764 | #define B_BE_SYM_PADPDN_WL_RFC1_1P3 BIT(6) |
3765 | #define B_BE_SYM_PADPDN_WL_RFC0_1P3 BIT(5) |
3766 | |
3767 | #define R_BE_RSV_CTRL 0x001C |
3768 | #define B_BE_HR_BE_DBG GENMASK(23, 12) |
3769 | #define B_BE_R_SYM_DIS_PCIE_FLR BIT(9) |
3770 | #define B_BE_R_EN_HRST_PWRON BIT(8) |
3771 | #define B_BE_LOCK_ALL_EN BIT(7) |
3772 | #define B_BE_R_DIS_PRST BIT(6) |
3773 | #define B_BE_WLOCK_1C_BIT6 BIT(5) |
3774 | #define B_BE_WLOCK_40 BIT(4) |
3775 | #define B_BE_WLOCK_08 BIT(3) |
3776 | #define B_BE_WLOCK_04 BIT(2) |
3777 | #define B_BE_WLOCK_00 BIT(1) |
3778 | #define B_BE_WLOCK_ALL BIT(0) |
3779 | |
3780 | #define R_BE_AFE_LDO_CTRL 0x0020 |
3781 | #define B_BE_FORCE_MACBBBT_PWR_ON BIT(31) |
3782 | #define B_BE_R_SYM_WLPOFF_P4_PC_EN BIT(28) |
3783 | #define B_BE_R_SYM_WLPOFF_P3_PC_EN BIT(27) |
3784 | #define B_BE_R_SYM_WLPOFF_P2_PC_EN BIT(26) |
3785 | #define B_BE_R_SYM_WLPOFF_P1_PC_EN BIT(25) |
3786 | #define B_BE_R_SYM_WLPOFF_PC_EN BIT(24) |
3787 | #define B_BE_AON_OFF_PC_EN BIT(23) |
3788 | #define B_BE_R_SYM_WLPON_P3_PC_EN BIT(21) |
3789 | #define B_BE_R_SYM_WLPON_P2_PC_EN BIT(20) |
3790 | #define B_BE_R_SYM_WLPON_P1_PC_EN BIT(19) |
3791 | #define B_BE_R_SYM_WLPON_PC_EN BIT(18) |
3792 | #define B_BE_R_SYM_WLBBPON1_P1_PC_EN BIT(15) |
3793 | #define B_BE_R_SYM_WLBBPON1_PC_EN BIT(14) |
3794 | #define B_BE_R_SYM_WLBBPON_P1_PC_EN BIT(13) |
3795 | #define B_BE_R_SYM_WLBBPON_PC_EN BIT(12) |
3796 | #define B_BE_R_SYM_DIS_WPHYBBOFF_PC BIT(10) |
3797 | #define B_BE_R_SYM_WLBBOFF1_P4_PC_EN BIT(9) |
3798 | #define B_BE_R_SYM_WLBBOFF1_P3_PC_EN BIT(8) |
3799 | #define B_BE_R_SYM_WLBBOFF1_P2_PC_EN BIT(7) |
3800 | #define B_BE_R_SYM_WLBBOFF1_P1_PC_EN BIT(6) |
3801 | #define B_BE_R_SYM_WLBBOFF1_PC_EN BIT(5) |
3802 | #define B_BE_R_SYM_WLBBOFF_P4_PC_EN BIT(4) |
3803 | #define B_BE_R_SYM_WLBBOFF_P3_PC_EN BIT(3) |
3804 | #define B_BE_R_SYM_WLBBOFF_P2_PC_EN BIT(2) |
3805 | #define B_BE_R_SYM_WLBBOFF_P1_PC_EN BIT(1) |
3806 | #define B_BE_R_SYM_WLBBOFF_PC_EN BIT(0) |
3807 | |
3808 | #define R_BE_AFE_CTRL1 0x0024 |
3809 | #define B_BE_R_SYM_WLCMAC0_P4_PC_EN BIT(28) |
3810 | #define B_BE_R_SYM_WLCMAC0_P3_PC_EN BIT(27) |
3811 | #define B_BE_R_SYM_WLCMAC0_P2_PC_EN BIT(26) |
3812 | #define B_BE_R_SYM_WLCMAC0_P1_PC_EN BIT(25) |
3813 | #define B_BE_R_SYM_WLCMAC0_PC_EN BIT(24) |
3814 | #define B_BE_DATAMEM_PC3_EN BIT(23) |
3815 | #define B_BE_DATAMEM_PC2_EN BIT(22) |
3816 | #define B_BE_DATAMEM_PC1_EN BIT(21) |
3817 | #define B_BE_DATAMEM_PC_EN BIT(20) |
3818 | #define B_BE_DMEM7_PC_EN BIT(19) |
3819 | #define B_BE_DMEM6_PC_EN BIT(18) |
3820 | #define B_BE_DMEM5_PC_EN BIT(17) |
3821 | #define B_BE_DMEM4_PC_EN BIT(16) |
3822 | #define B_BE_DMEM3_PC_EN BIT(15) |
3823 | #define B_BE_DMEM2_PC_EN BIT(14) |
3824 | #define B_BE_DMEM1_PC_EN BIT(13) |
3825 | #define B_BE_IMEM4_PC_EN BIT(12) |
3826 | #define B_BE_IMEM3_PC_EN BIT(11) |
3827 | #define B_BE_IMEM2_PC_EN BIT(10) |
3828 | #define B_BE_IMEM1_PC_EN BIT(9) |
3829 | #define B_BE_IMEM0_PC_EN BIT(8) |
3830 | #define B_BE_R_SYM_WLCMAC1_P4_PC_EN BIT(4) |
3831 | #define B_BE_R_SYM_WLCMAC1_P3_PC_EN BIT(3) |
3832 | #define B_BE_R_SYM_WLCMAC1_P2_PC_EN BIT(2) |
3833 | #define B_BE_R_SYM_WLCMAC1_P1_PC_EN BIT(1) |
3834 | #define B_BE_R_SYM_WLCMAC1_PC_EN BIT(0) |
3835 | #define B_BE_AFE_CTRL1_SET (B_BE_R_SYM_WLCMAC1_PC_EN | \ |
3836 | B_BE_R_SYM_WLCMAC1_P1_PC_EN | \ |
3837 | B_BE_R_SYM_WLCMAC1_P2_PC_EN | \ |
3838 | B_BE_R_SYM_WLCMAC1_P3_PC_EN | \ |
3839 | B_BE_R_SYM_WLCMAC1_P4_PC_EN) |
3840 | |
3841 | #define R_BE_EFUSE_CTRL 0x0030 |
3842 | #define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30) |
3843 | #define B_BE_EF_RDY BIT(29) |
3844 | #define B_BE_EF_COMP_RESULT BIT(28) |
3845 | #define B_BE_EF_ADDR_MASK GENMASK(15, 0) |
3846 | |
3847 | #define R_BE_EFUSE_CTRL_1_V1 0x0034 |
3848 | #define B_BE_EF_DATA_MASK GENMASK(31, 0) |
3849 | |
3850 | #define R_BE_WL_BT_PWR_CTRL 0x0068 |
3851 | #define B_BE_ISO_BD2PP BIT(31) |
3852 | #define B_BE_LDOV12B_EN BIT(30) |
3853 | #define B_BE_CKEN_BT BIT(29) |
3854 | #define B_BE_FEN_BT BIT(28) |
3855 | #define B_BE_BTCPU_BOOTSEL BIT(27) |
3856 | #define B_BE_SPI_SPEEDUP BIT(26) |
3857 | #define B_BE_BT_LDO_MODE BIT(25) |
3858 | #define B_BE_ISO_BTPON2PP BIT(22) |
3859 | #define B_BE_BT_FUNC_EN BIT(18) |
3860 | #define B_BE_BT_HWPDN_SL BIT(17) |
3861 | #define B_BE_BT_DISN_EN BIT(16) |
3862 | #define B_BE_SDM_SRC_SEL BIT(12) |
3863 | #define B_BE_ISO_BA2PP BIT(11) |
3864 | #define B_BE_BT_AFE_LDO_EN BIT(10) |
3865 | #define B_BE_BT_AFE_PLL_EN BIT(9) |
3866 | #define B_BE_WLAN_32K_SEL BIT(6) |
3867 | #define B_BE_WL_DRV_EXIST_IDX BIT(5) |
3868 | #define B_BE_DOP_EHPAD BIT(4) |
3869 | #define B_BE_WL_FUNC_EN BIT(2) |
3870 | #define B_BE_WL_HWPDN_SL BIT(1) |
3871 | #define B_BE_WL_HWPDN_EN BIT(0) |
3872 | |
3873 | #define R_BE_SYS_SDIO_CTRL 0x0070 |
3874 | #define B_BE_MCM_FLASH_EN BIT(28) |
3875 | #define B_BE_PCIE_SEC_LOAD BIT(26) |
3876 | #define B_BE_PCIE_SER_RSTB BIT(25) |
3877 | #define B_BE_PCIE_SEC_LOAD_CLR BIT(24) |
3878 | #define B_BE_SDIO_CMD_SW_RST BIT(20) |
3879 | #define B_BE_SDIO_INT_POLARITY BIT(19) |
3880 | #define B_BE_SDIO_OFF_EN BIT(17) |
3881 | #define B_BE_SDIO_ON_EN BIT(16) |
3882 | #define B_BE_PCIE_DIS_L2__CTRL_LDO_HCI BIT(15) |
3883 | #define B_BE_PCIE_DIS_L2_RTK_PERST BIT(14) |
3884 | #define B_BE_PCIE_FORCE_PWR_NGAT BIT(13) |
3885 | #define B_BE_PCIE_FORCE_IBX_EN BIT(12) |
3886 | #define B_BE_PCIE_AUXCLK_GATE BIT(11) |
3887 | #define B_BE_PCIE_WAIT_TIMEOUT_EVENT BIT(10) |
3888 | #define B_BE_PCIE_WAIT_TIME BIT(9) |
3889 | #define B_BE_L1OFF_TO_L0_RESUME_EVT BIT(8) |
3890 | #define B_BE_USBA_FORCE_PWR_NGAT BIT(7) |
3891 | #define B_BE_USBD_FORCE_PWR_NGAT BIT(6) |
3892 | #define B_BE_BT_CTRL_USB_PWR BIT(5) |
3893 | #define B_BE_USB_D_STATE_HOLD BIT(4) |
3894 | #define B_BE_R_BE_FORCE_DP BIT(3) |
3895 | #define B_BE_R_BE_DP_MODE BIT(2) |
3896 | #define B_BE_RES_USB_MASS_STORAGE_DESC BIT(1) |
3897 | #define B_BE_USB_WAIT_TIME BIT(0) |
3898 | |
3899 | #define R_BE_HCI_OPT_CTRL 0x0074 |
3900 | #define B_BE_HCI_WLAN_IO_ST BIT(31) |
3901 | #define B_BE_HCI_WLAN_IO_EN BIT(28) |
3902 | #define B_BE_HAXIDMA_IO_ST BIT(27) |
3903 | #define B_BE_HAXIDMA_BACKUP_RESTORE_ST BIT(26) |
3904 | #define B_BE_HAXIDMA_IO_EN BIT(24) |
3905 | #define B_BE_EN_PCIE_WAKE BIT(23) |
3906 | #define B_BE_SDIO_PAD_H3L1 BIT(22) |
3907 | #define B_BE_USBMAC_ANACLK_SW BIT(21) |
3908 | #define B_BE_PCIE_CPHY_CCK_XTAL_SEL BIT(20) |
3909 | #define B_BE_SDIO_DATA_PAD_SMT BIT(19) |
3910 | #define B_BE_SDIO_PAD_E5 BIT(18) |
3911 | #define B_BE_FORCE_PCIE_AUXCLK BIT(17) |
3912 | #define B_BE_HCI_LA_ADDR_MAP BIT(16) |
3913 | #define B_BE_HCI_LA_GLO_RST BIT(15) |
3914 | #define B_BE_USB3_SUS_DIS BIT(14) |
3915 | #define B_BE_NOPWR_CTRL_SEL BIT(13) |
3916 | #define B_BE_USB_HOST_PWR_OFF_EN BIT(12) |
3917 | #define B_BE_SYM_LPS_BLOCK_EN BIT(11) |
3918 | #define B_BE_USB_LPM_ACT_EN BIT(10) |
3919 | #define B_BE_USB_LPM_NY BIT(9) |
3920 | #define B_BE_USB2_SUS_DIS BIT(8) |
3921 | #define B_BE_SDIO_PAD_E_MASK GENMASK(7, 5) |
3922 | #define B_BE_USB_LPPLL_EN BIT(4) |
3923 | #define B_BE_USB1_1_USB2_0_DECISION BIT(3) |
3924 | #define B_BE_ROP_SW15 BIT(2) |
3925 | #define B_BE_PCI_CKRDY_OPT BIT(1) |
3926 | #define B_BE_PCI_VAUX_EN BIT(0) |
3927 | |
3928 | #define R_BE_SYS_ISO_CTRL_EXTEND 0x0080 |
3929 | #define B_BE_R_SYM_ISO_DMEM62PP BIT(29) |
3930 | #define B_BE_R_SYM_ISO_DMEM52PP BIT(28) |
3931 | #define B_BE_R_SYM_ISO_DMEM42PP BIT(27) |
3932 | #define B_BE_R_SYM_ISO_DMEM32PP BIT(26) |
3933 | #define B_BE_R_SYM_ISO_DMEM22PP BIT(25) |
3934 | #define B_BE_R_SYM_ISO_DMEM12PP BIT(24) |
3935 | #define B_BE_R_SYM_ISO_IMEM42PP BIT(22) |
3936 | #define B_BE_R_SYM_ISO_IMEM32PP BIT(21) |
3937 | #define B_BE_R_SYM_ISO_IMEM22PP BIT(20) |
3938 | #define B_BE_R_SYM_ISO_IMEM12PP BIT(19) |
3939 | #define B_BE_R_SYM_ISO_IMEM02PP BIT(18) |
3940 | #define B_BE_R_SYM_ISO_AON_OFF2PP BIT(15) |
3941 | #define B_BE_R_SYM_PWC_HCILA BIT(13) |
3942 | #define B_BE_R_SYM_PWC_PD12V BIT(12) |
3943 | #define B_BE_R_SYM_PWC_UD12V BIT(11) |
3944 | #define B_BE_R_SYM_PWC_BTBRG BIT(10) |
3945 | #define B_BE_R_SYM_LDOBTSDIO_EN BIT(9) |
3946 | #define B_BE_R_SYM_LDOSPDIO_EN BIT(8) |
3947 | #define B_BE_R_SYM_ISO_HCILA BIT(4) |
3948 | #define B_BE_R_SYM_ISO_BTBRG2PP BIT(2) |
3949 | #define B_BE_R_SYM_ISO_BTSDIO2PP BIT(1) |
3950 | #define B_BE_R_SYM_ISO_SPDIO2PP BIT(0) |
3951 | |
3952 | #define R_BE_FEN_RST_ENABLE 0x0084 |
3953 | #define B_BE_R_SYM_FEN_WLMACOFF BIT(31) |
3954 | #define B_BE_R_SYM_ISO_WA12PP BIT(28) |
3955 | #define B_BE_R_SYM_ISO_CMAC12PP BIT(25) |
3956 | #define B_BE_R_SYM_ISO_CMAC02PP BIT(24) |
3957 | #define B_BE_R_SYM_ISO_ADDA_P32PP BIT(23) |
3958 | #define B_BE_R_SYM_ISO_ADDA_P22PP BIT(22) |
3959 | #define B_BE_R_SYM_ISO_ADDA_P12PP BIT(21) |
3960 | #define B_BE_R_SYM_ISO_ADDA_P02PP BIT(20) |
3961 | #define B_BE_CMAC1_FEN BIT(17) |
3962 | #define B_BE_CMAC0_FEN BIT(16) |
3963 | #define B_BE_SYM_ISO_BBPON12PP BIT(13) |
3964 | #define B_BE_SYM_ISO_BB12PP BIT(12) |
3965 | #define B_BE_BOOT_RDY1 BIT(10) |
3966 | #define B_BE_FEN_BB1_IP_RSTN BIT(9) |
3967 | #define B_BE_FEN_BB1PLAT_RSTB BIT(8) |
3968 | #define B_BE_SYM_ISO_BBPON02PP BIT(5) |
3969 | #define B_BE_SYM_ISO_BB02PP BIT(4) |
3970 | #define B_BE_BOOT_RDY0 BIT(2) |
3971 | #define B_BE_FEN_BB_IP_RSTN BIT(1) |
3972 | #define B_BE_FEN_BBPLAT_RSTB BIT(0) |
3973 | |
3974 | #define R_BE_PLATFORM_ENABLE 0x0088 |
3975 | #define B_BE_HOLD_AFTER_RESET BIT(11) |
3976 | #define B_BE_SYM_WLPLT_MEM_MUX_EN BIT(10) |
3977 | #define B_BE_WCPU_WARM_EN BIT(9) |
3978 | #define B_BE_SPIC_EN BIT(8) |
3979 | #define B_BE_UART_EN BIT(7) |
3980 | #define B_BE_IDDMA_EN BIT(6) |
3981 | #define B_BE_IPSEC_EN BIT(5) |
3982 | #define B_BE_HIOE_EN BIT(4) |
3983 | #define B_BE_APB_WRAP_EN BIT(2) |
3984 | #define B_BE_WCPU_EN BIT(1) |
3985 | #define B_BE_PLATFORM_EN BIT(0) |
3986 | |
3987 | #define R_BE_WLLPS_CTRL 0x0090 |
3988 | #define B_BE_LPSOP_BBMEMDS BIT(30) |
3989 | #define B_BE_LPSOP_BBOFF BIT(29) |
3990 | #define B_BE_LPSOP_MACOFF BIT(28) |
3991 | #define B_BE_LPSOP_OFF_CAPC_EN BIT(27) |
3992 | #define B_BE_LPSOP_MEM_DS BIT(26) |
3993 | #define B_BE_LPSOP_XTALM_LPS BIT(23) |
3994 | #define B_BE_LPSOP_XTAL BIT(22) |
3995 | #define B_BE_LPSOP_ACLK_DIV_2 BIT(21) |
3996 | #define B_BE_LPSOP_ACLK_SEL BIT(20) |
3997 | #define B_BE_LPSOP_ASWRM BIT(17) |
3998 | #define B_BE_LPSOP_ASWR BIT(16) |
3999 | #define B_BE_LPSOP_DSWR_ADJ_MASK GENMASK(15, 12) |
4000 | #define B_BE_LPSOP_DSWRSD BIT(10) |
4001 | #define B_BE_LPSOP_DSWRM BIT(9) |
4002 | #define B_BE_LPSOP_DSWR BIT(8) |
4003 | #define B_BE_LPSOP_OLD_ADJ_MASK GENMASK(7, 4) |
4004 | #define B_BE_FORCE_LEAVE_LPS BIT(3) |
4005 | #define B_BE_LPSOP_OLDSD BIT(2) |
4006 | #define B_BE_DIS_WLBT_LPSEN_LOPC BIT(1) |
4007 | #define B_BE_WL_LPS_EN BIT(0) |
4008 | |
4009 | #define R_BE_WLRESUME_CTRL 0x0094 |
4010 | #define B_BE_LPSROP_DMEM5_RSU_EN BIT(31) |
4011 | #define B_BE_LPSROP_DMEM4_RSU_EN BIT(30) |
4012 | #define B_BE_LPSROP_DMEM3_RSU_EN BIT(29) |
4013 | #define B_BE_LPSROP_DMEM2_RSU_EN BIT(28) |
4014 | #define B_BE_LPSROP_DMEM1_RSU_EN BIT(27) |
4015 | #define B_BE_LPSROP_DMEM0_RSU_EN BIT(26) |
4016 | #define B_BE_LPSROP_IMEM5_RSU_EN BIT(25) |
4017 | #define B_BE_LPSROP_IMEM4_RSU_EN BIT(24) |
4018 | #define B_BE_LPSROP_IMEM3_RSU_EN BIT(23) |
4019 | #define B_BE_LPSROP_IMEM2_RSU_EN BIT(22) |
4020 | #define B_BE_LPSROP_IMEM1_RSU_EN BIT(21) |
4021 | #define B_BE_LPSROP_IMEM0_RSU_EN BIT(20) |
4022 | #define B_BE_LPSROP_BB1_W_BB0 BIT(14) |
4023 | #define B_BE_LPSROP_CMAC1 BIT(13) |
4024 | #define B_BE_LPSROP_CMAC0 BIT(12) |
4025 | #define B_BE_LPSROP_XTALM BIT(11) |
4026 | #define B_BE_LPSROP_PLLM BIT(10) |
4027 | #define B_BE_LPSROP_HIOE BIT(9) |
4028 | #define B_BE_LPSROP_CPU BIT(8) |
4029 | #define B_BE_LPSROP_LOWPWRPLL BIT(7) |
4030 | #define B_BE_LPSROP_DSWRSD_SEL_MASK GENMASK(5, 4) |
4031 | |
4032 | #define R_BE_EFUSE_CTRL_2_V1 0x00A4 |
4033 | #define B_BE_EF_ENT BIT(31) |
4034 | #define B_BE_EF_TCOLUMN_EN BIT(29) |
4035 | #define B_BE_BT_OTP_PWC_DIS BIT(28) |
4036 | #define B_BE_EF_RDT BIT(27) |
4037 | #define B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL BIT(24) |
4038 | #define B_BE_EF_PGTS_MASK GENMASK(23, 20) |
4039 | #define B_BE_EF_BURST BIT(19) |
4040 | #define B_BE_EF_TEST_SEL_MASK GENMASK(18, 16) |
4041 | #define B_BE_EF_TROW_EN BIT(15) |
4042 | #define B_BE_EF_ERR_FLAG BIT(14) |
4043 | #define B_BE_EF_FBURST_DIS BIT(13) |
4044 | #define B_BE_EF_HT_SEL BIT(12) |
4045 | #define B_BE_EF_DSB_EN BIT(11) |
4046 | #define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0) |
4047 | |
4048 | #define R_BE_PMC_DBG_CTRL2 0x00CC |
4049 | #define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24) |
4050 | #define B_BE_DIS_IOWRAP_TIMEOUT BIT(16) |
4051 | #define B_BE_STOP_WL_PMC BIT(9) |
4052 | #define B_BE_STOP_SYM_PMC BIT(8) |
4053 | #define B_BE_SYM_REG_PCIE_WRMSK BIT(7) |
4054 | #define B_BE_BT_ACCESS_WL_PAGE0 BIT(6) |
4055 | #define B_BE_R_BE_RST_WLPMC BIT(5) |
4056 | #define B_BE_R_BE_RST_PD12N BIT(4) |
4057 | #define B_BE_SYSON_DIS_WLR_BE_WRMSK BIT(3) |
4058 | #define B_BE_SYSON_DIS_PMCR_BE_WRMSK BIT(2) |
4059 | #define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0) |
4060 | |
4061 | #define R_BE_MEM_PWR_CTRL 0x00D0 |
4062 | #define B_BE_DMEM5_WLMCU_DS BIT(31) |
4063 | #define B_BE_DMEM4_WLMCU_DS BIT(30) |
4064 | #define B_BE_DMEM3_WLMCU_DS BIT(29) |
4065 | #define B_BE_DMEM2_WLMCU_DS BIT(28) |
4066 | #define B_BE_DMEM1_WLMCU_DS BIT(27) |
4067 | #define B_BE_DMEM0_WLMCU_DS BIT(26) |
4068 | #define B_BE_IMEM5_WLMCU_DS BIT(25) |
4069 | #define B_BE_IMEM4_WLMCU_DS BIT(24) |
4070 | #define B_BE_IMEM3_WLMCU_DS BIT(23) |
4071 | #define B_BE_IMEM2_WLMCU_DS BIT(22) |
4072 | #define B_BE_IMEM1_WLMCU_DS BIT(21) |
4073 | #define B_BE_IMEM0_WLMCU_DS BIT(20) |
4074 | #define B_BE_MEM_BBMCU1_DS BIT(19) |
4075 | #define B_BE_MEM_BBMCU0_DS_V1 BIT(17) |
4076 | #define B_BE_MEM_BT_DS BIT(10) |
4077 | #define B_BE_MEM_SDIO_LS BIT(9) |
4078 | #define B_BE_MEM_SDIO_DS BIT(8) |
4079 | #define B_BE_MEM_USB_LS BIT(7) |
4080 | #define B_BE_MEM_USB_DS BIT(6) |
4081 | #define B_BE_MEM_PCI_LS BIT(5) |
4082 | #define B_BE_MEM_PCI_DS BIT(4) |
4083 | #define B_BE_MEM_WLMAC_LS BIT(3) |
4084 | |
4085 | #define R_BE_PCIE_MIO_INTF 0x00E4 |
4086 | #define B_BE_AON_MIO_EPHY_1K_SEL_MASK GENMASK(29, 24) |
4087 | #define B_BE_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16) |
4088 | #define B_BE_PCIE_MIO_ASIF BIT(15) |
4089 | #define B_BE_PCIE_MIO_BYIOREG BIT(13) |
4090 | #define B_BE_PCIE_MIO_RE BIT(12) |
4091 | #define B_BE_PCIE_MIO_WE_MASK GENMASK(11, 8) |
4092 | #define B_BE_PCIE_MIO_ADDR_MASK GENMASK(7, 0) |
4093 | |
4094 | #define R_BE_PCIE_MIO_INTD 0x00E8 |
4095 | #define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0) |
4096 | |
4097 | #define R_BE_HALT_H2C_CTRL 0x0160 |
4098 | #define B_BE_HALT_H2C_TRIGGER BIT(0) |
4099 | |
4100 | #define R_BE_HALT_C2H_CTRL 0x0164 |
4101 | #define B_BE_HALT_C2H_TRIGGER BIT(0) |
4102 | |
4103 | #define R_BE_HALT_H2C 0x0168 |
4104 | #define B_BE_HALT_H2C_MASK GENMASK(31, 0) |
4105 | |
4106 | #define R_BE_HALT_C2H 0x016C |
4107 | #define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28) |
4108 | #define B_BE_ERROR_CODE_MASK GENMASK(15, 0) |
4109 | |
4110 | #define R_BE_SYS_CFG5 0x0170 |
4111 | #define B_BE_WDT_DATACPU_WAKE_PCIE_EN BIT(12) |
4112 | #define B_BE_WDT_DATACPU_WAKE_USB_EN BIT(11) |
4113 | #define B_BE_WDT_WAKE_PCIE_EN BIT(10) |
4114 | #define B_BE_WDT_WAKE_USB_EN BIT(9) |
4115 | #define B_BE_SYM_DIS_HC_ACCESS_MAC BIT(8) |
4116 | #define B_BE_LPS_STATUS BIT(3) |
4117 | #define B_BE_HCI_TXDMA_BUSY BIT(2) |
4118 | |
4119 | #define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184 |
4120 | |
4121 | #define R_BE_FWS1IMR 0x0198 |
4122 | #define B_BE_FS_RPWM_INT_EN_V1 BIT(24) |
4123 | #define B_BE_PCIE_HOTRST_EN BIT(22) |
4124 | #define B_BE_PCIE_SER_TIMEOUT_INDIC_EN BIT(21) |
4125 | #define B_BE_PCIE_RXI300_SLVTOUT_INDIC_EN BIT(20) |
4126 | #define B_BE_AON_PCIE_FLR_INT_EN BIT(19) |
4127 | #define B_BE_PCIE_ERR_INDIC_INT_EN BIT(18) |
4128 | #define B_BE_SDIO_ERR_INDIC_INT_EN BIT(17) |
4129 | #define B_BE_USB_ERR_INDIC_INT_EN BIT(16) |
4130 | #define B_BE_FS_GPIO27_INT_EN BIT(11) |
4131 | #define B_BE_FS_GPIO26_INT_EN BIT(10) |
4132 | #define B_BE_FS_GPIO25_INT_EN BIT(9) |
4133 | #define B_BE_FS_GPIO24_INT_EN BIT(8) |
4134 | #define B_BE_FS_GPIO23_INT_EN BIT(7) |
4135 | #define B_BE_FS_GPIO22_INT_EN BIT(6) |
4136 | #define B_BE_FS_GPIO21_INT_EN BIT(5) |
4137 | #define B_BE_FS_GPIO20_INT_EN BIT(4) |
4138 | #define B_BE_FS_GPIO19_INT_EN BIT(3) |
4139 | #define B_BE_FS_GPIO18_INT_EN BIT(2) |
4140 | #define B_BE_FS_GPIO17_INT_EN BIT(1) |
4141 | #define B_BE_FS_GPIO16_INT_EN BIT(0) |
4142 | |
4143 | #define R_BE_HIMR0 0x01A0 |
4144 | #define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25) |
4145 | #define B_BE_HALT_D2H_INT_EN BIT(24) |
4146 | #define B_BE_WDT_TIMEOUT_INT_EN BIT(22) |
4147 | #define B_BE_HALT_C2H_INT_EN BIT(21) |
4148 | #define B_BE_RON_INT_EN BIT(20) |
4149 | #define B_BE_PDNINT_EN BIT(19) |
4150 | #define B_BE_SPSANA_OCP_INT_EN BIT(18) |
4151 | #define B_BE_SPS_OCP_INT_EN BIT(17) |
4152 | #define B_BE_BTON_STS_UPDATE_INT_EN BIT(16) |
4153 | #define B_BE_GPIOF_INT_EN BIT(15) |
4154 | #define B_BE_GPIOE_INT_EN BIT(14) |
4155 | #define B_BE_GPIOD_INT_EN BIT(13) |
4156 | #define B_BE_GPIOC_INT_EN BIT(12) |
4157 | #define B_BE_GPIOB_INT_EN BIT(11) |
4158 | #define B_BE_GPIOA_INT_EN BIT(10) |
4159 | #define B_BE_GPIO9_INT_EN BIT(9) |
4160 | #define B_BE_GPIO8_INT_EN BIT(8) |
4161 | #define B_BE_GPIO7_INT_EN BIT(7) |
4162 | #define B_BE_GPIO6_INT_EN BIT(6) |
4163 | #define B_BE_GPIO5_INT_EN BIT(5) |
4164 | #define B_BE_GPIO4_INT_EN BIT(4) |
4165 | #define B_BE_GPIO3_INT_EN BIT(3) |
4166 | #define B_BE_GPIO2_INT_EN BIT(2) |
4167 | #define B_BE_GPIO1_INT_EN BIT(1) |
4168 | #define B_BE_GPIO0_INT_EN BIT(0) |
4169 | |
4170 | #define R_BE_HISR0 0x01A4 |
4171 | #define B_BE_WDT_DATACPU_TIMEOUT_INT BIT(25) |
4172 | #define B_BE_HALT_D2H_INT BIT(24) |
4173 | #define B_BE_WDT_TIMEOUT_INT BIT(22) |
4174 | #define B_BE_HALT_C2H_INT BIT(21) |
4175 | #define B_BE_RON_INT BIT(20) |
4176 | #define B_BE_PDNINT BIT(19) |
4177 | #define B_BE_SPSANA_OCP_INT BIT(18) |
4178 | #define B_BE_SPS_OCP_INT BIT(17) |
4179 | #define B_BE_BTON_STS_UPDATE_INT BIT(16) |
4180 | #define B_BE_GPIOF_INT BIT(15) |
4181 | #define B_BE_GPIOE_INT BIT(14) |
4182 | #define B_BE_GPIOD_INT BIT(13) |
4183 | #define B_BE_GPIOC_INT BIT(12) |
4184 | #define B_BE_GPIOB_INT BIT(11) |
4185 | #define B_BE_GPIOA_INT BIT(10) |
4186 | #define B_BE_GPIO9_INT BIT(9) |
4187 | #define B_BE_GPIO8_INT BIT(8) |
4188 | #define B_BE_GPIO7_INT BIT(7) |
4189 | #define B_BE_GPIO6_INT BIT(6) |
4190 | #define B_BE_GPIO5_INT BIT(5) |
4191 | #define B_BE_GPIO4_INT BIT(4) |
4192 | #define B_BE_GPIO3_INT BIT(3) |
4193 | #define B_BE_GPIO2_INT BIT(2) |
4194 | #define B_BE_GPIO1_INT BIT(1) |
4195 | #define B_BE_GPIO0_INT BIT(0) |
4196 | |
4197 | #define R_BE_WCPU_FW_CTRL 0x01E0 |
4198 | #define B_BE_RUN_ENV_MASK GENMASK(31, 30) |
4199 | #define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26) |
4200 | #define B_BE_WDT_PLT_RST_EN BIT(17) |
4201 | #define B_BE_FW_SEC_AUTH_DONE BIT(14) |
4202 | #define B_BE_FW_CPU_UTIL_STS_EN BIT(13) |
4203 | #define B_BE_BBMCU1_FWDL_EN BIT(12) |
4204 | #define B_BE_BBMCU0_FWDL_EN BIT(11) |
4205 | #define B_BE_DATACPU_FWDL_EN BIT(10) |
4206 | #define B_BE_WLANCPU_FWDL_EN BIT(9) |
4207 | #define B_BE_WCPU_ROM_CUT_GET BIT(8) |
4208 | #define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4) |
4209 | #define B_BE_FW_BOOT_MODE_MASK GENMASK(3, 2) |
4210 | #define B_BE_H2C_PATH_RDY BIT(1) |
4211 | #define B_BE_DLFW_PATH_RDY BIT(0) |
4212 | |
4213 | #define R_BE_BOOT_REASON 0x01E6 |
4214 | #define B_BE_BOOT_REASON_MASK GENMASK(2, 0) |
4215 | |
4216 | #define R_BE_LDM 0x01E8 |
4217 | #define B_BE_EN_32K BIT(31) |
4218 | #define B_BE_LDM_MASK GENMASK(30, 0) |
4219 | |
4220 | #define R_BE_UDM0 0x01F0 |
4221 | #define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28) |
4222 | #define B_BE_UDM0_TX_RPT_CNT_MASK GENMASK(27, 24) |
4223 | #define B_BE_UDM0_FS_CODE_MASK GENMASK(23, 8) |
4224 | #define B_BE_NULL_POINTER_INDC BIT(7) |
4225 | #define B_BE_ROM_ASSERT_INDC BIT(6) |
4226 | #define B_BE_RAM_ASSERT_INDC BIT(5) |
4227 | #define B_BE_FW_IMAGE_TYPE BIT(4) |
4228 | #define B_BE_UDM0_TRAP_LOOP_CTRL BIT(2) |
4229 | #define B_BE_UDM0_SEND_HALTC2H_CTRL BIT(1) |
4230 | #define B_BE_UDM0_DBG_MODE_CTRL BIT(0) |
4231 | |
4232 | #define R_BE_UDM1 0x01F4 |
4233 | #define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16) |
4234 | #define B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12) |
4235 | #define B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8) |
4236 | #define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4) |
4237 | #define B_BE_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0) |
4238 | |
4239 | #define R_BE_UDM2 0x01F8 |
4240 | #define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0) |
4241 | |
4242 | #define R_BE_AFE_ON_CTRL0 0x0240 |
4243 | #define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29) |
4244 | #define B_BE_REG_LPF_R2_MASK GENMASK(28, 24) |
4245 | #define B_BE_REG_LPF_C3_MASK GENMASK(23, 21) |
4246 | #define B_BE_REG_LPF_C2_MASK GENMASK(20, 18) |
4247 | #define B_BE_REG_LPF_C1_MASK GENMASK(17, 15) |
4248 | #define B_BE_REG_CP_ICPX2 BIT(14) |
4249 | #define B_BE_REG_CP_ICP_SEL_FAST_MASK GENMASK(13, 10) |
4250 | #define B_BE_REG_CP_ICP_SEL_MASK GENMASK(9, 6) |
4251 | #define B_BE_REG_IB_PI_MASK GENMASK(5, 4) |
4252 | #define B_BE_REG_CK_DEBUG_BT BIT(3) |
4253 | #define B_BE_EN_PC_LDO BIT(2) |
4254 | #define B_BE_LDO_VSEL_MASK GENMASK(1, 0) |
4255 | |
4256 | #define R_BE_AFE_ON_CTRL1 0x0244 |
4257 | #define B_BE_REG_CK_MON_SEL_MASK GENMASK(31, 29) |
4258 | #define B_BE_REG_CK_MON_CK960M_EN BIT(28) |
4259 | #define B_BE_REG_XTAL_FREQ_SEL BIT(27) |
4260 | #define B_BE_REG_XTAL_EDGE_SEL BIT(26) |
4261 | #define B_BE_REG_VCO_KVCO BIT(25) |
4262 | #define B_BE_REG_SDM_EDGE_SEL BIT(24) |
4263 | #define B_BE_REG_SDM_CK_SEL BIT(23) |
4264 | #define B_BE_REG_SDM_CK_GATED BIT(22) |
4265 | #define B_BE_REG_PFD_RESET_GATED BIT(21) |
4266 | #define B_BE_REG_LPF_R3_FAST_MASK GENMASK(20, 16) |
4267 | #define B_BE_REG_LPF_R2_FAST_MASK GENMASK(15, 11) |
4268 | #define B_BE_REG_LPF_C3_FAST_MASK GENMASK(10, 8) |
4269 | #define B_BE_REG_LPF_C2_FAST_MASK GENMASK(7, 5) |
4270 | #define B_BE_REG_LPF_C1_FAST_MASK GENMASK(4, 2) |
4271 | #define B_BE_REG_LPF_R3_4_MASK GENMASK(1, 0) |
4272 | |
4273 | #define R_BE_AFE_ON_CTRL3 0x024C |
4274 | #define B_BE_LDO_VSEL_DA_1_MASK GENMASK(31, 30) |
4275 | #define B_BE_LDO_VSEL_DA_0_MASK GENMASK(29, 28) |
4276 | #define B_BE_LDO_VSEL_D2S_1_MASK GENMASK(27, 26) |
4277 | #define B_BE_LDO_VSEL_D2S_0_MASK GENMASK(25, 24) |
4278 | #define B_BE_LDO_VSEL_BUF_MASK GENMASK(23, 22) |
4279 | #define B_BE_REG_R2_L_MASK GENMASK(21, 19) |
4280 | #define B_BE_REG_R1_L_MASK GENMASK(18, 16) |
4281 | #define B_BE_REG_CK_DEBUG_BT_MON BIT(15) |
4282 | #define B_BE_REG_BT_CLK_BUF_POWER BIT(14) |
4283 | #define B_BE_REG_BG_OUT_BTADC_V1 BIT(13) |
4284 | #define B_BE_REG_SEL_V18 BIT(11) |
4285 | #define B_BE_REG_FRAC_EN BIT(10) |
4286 | #define B_BE_REG_CK1920M_EN BIT(9) |
4287 | #define B_BE_REG_CK1280M_EN BIT(8) |
4288 | #define B_BE_REG_12LDO_SEL_MASK GENMASK(7, 6) |
4289 | #define B_BE_REG_09LDO_SEL_MASK GENMASK(5, 4) |
4290 | #define B_BE_REG_VC_TH BIT(3) |
4291 | #define B_BE_REG_VC_TL BIT(2) |
4292 | #define B_BE_REG_CK40M_EN BIT(1) |
4293 | #define B_BE_REG_CK640M_EN BIT(0) |
4294 | |
4295 | #define R_BE_WLAN_XTAL_SI_CTRL 0x0270 |
4296 | #define B_BE_WL_XTAL_SI_CMD_POLL BIT(31) |
4297 | #define B_BE_WL_XTAL_SI_CHIPID_MASK GENMASK(30, 28) |
4298 | #define B_BE_WL_XTAL_SI_MODE_MASK GENMASK(25, 24) |
4299 | #define B_BE_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16) |
4300 | #define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8) |
4301 | #define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0) |
4302 | |
4303 | #define R_BE_IC_PWR_STATE 0x03F0 |
4304 | #define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16) |
4305 | #define MAC_AX_SYS_ACT 0x220 |
4306 | #define B_BE_WLMAC_PWR_STE_MASK GENMASK(9, 8) |
4307 | #define B_BE_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6) |
4308 | #define B_BE_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4) |
4309 | #define B_BE_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2) |
4310 | #define B_BE_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0) |
4311 | |
4312 | #define R_BE_WLCPU_PORT_PC 0x03FC |
4313 | |
4314 | #define R_BE_DCPU_PLATFORM_ENABLE 0x0888 |
4315 | #define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10) |
4316 | #define B_BE_DCPU_WARM_EN BIT(9) |
4317 | #define B_BE_DCPU_UART_EN BIT(7) |
4318 | #define B_BE_DCPU_IDDMA_EN BIT(6) |
4319 | #define B_BE_DCPU_APB_WRAP_EN BIT(2) |
4320 | #define B_BE_DCPU_EN BIT(1) |
4321 | #define B_BE_DCPU_PLATFORM_EN BIT(0) |
4322 | |
4323 | #define R_BE_PL_AXIDMA_IDCT_MSK 0x0910 |
4324 | #define B_BE_PL_AXIDMA_RRESP_ERR_MASK BIT(6) |
4325 | #define B_BE_PL_AXIDMA_BRESP_ERR_MASK BIT(5) |
4326 | #define B_BE_PL_AXIDMA_FC_ERR_MASK BIT(4) |
4327 | #define B_BE_PL_AXIDMA_TXBD_LEN0_MASK BIT(3) |
4328 | #define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR_MASK BIT(2) |
4329 | #define B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK BIT(1) |
4330 | #define B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK BIT(0) |
4331 | #define B_BE_PL_AXIDMA_IDCT_MSK_CLR (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \ |
4332 | B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \ |
4333 | B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \ |
4334 | B_BE_PL_AXIDMA_FC_ERR_MASK | \ |
4335 | B_BE_PL_AXIDMA_BRESP_ERR_MASK | \ |
4336 | B_BE_PL_AXIDMA_RRESP_ERR_MASK) |
4337 | #define B_BE_PL_AXIDMA_IDCT_MSK_SET (B_BE_PL_AXIDMA_TXBD_TX_STUCK_MASK | \ |
4338 | B_BE_PL_AXIDMA_TXBD_RX_STUCK_MASK | \ |
4339 | B_BE_PL_AXIDMA_TXBD_LEN0_MASK | \ |
4340 | B_BE_PL_AXIDMA_FC_ERR_MASK) |
4341 | |
4342 | #define R_BE_PL_AXIDMA_IDCT 0x0914 |
4343 | #define B_BE_PL_AXIDMA_RRESP_ERR BIT(6) |
4344 | #define B_BE_PL_AXIDMA_BRESP_ERR BIT(5) |
4345 | #define B_BE_PL_AXIDMA_FC_ERR BIT(4) |
4346 | #define B_BE_PL_AXIDMA_TXBD_LEN0 BIT(3) |
4347 | #define B_BE_PL_AXIDMA_TXBD_4KBOUD_LENERR BIT(2) |
4348 | #define B_BE_PL_AXIDMA_TXBD_RX_STUCK BIT(1) |
4349 | #define B_BE_PL_AXIDMA_TXBD_TX_STUCK BIT(0) |
4350 | |
4351 | #define R_BE_FILTER_MODEL_ADDR 0x0C04 |
4352 | |
4353 | #define R_BE_WLAN_WDT 0x3050 |
4354 | #define B_BE_WLAN_WDT_TIMEOUT BIT(31) |
4355 | #define B_BE_WLAN_WDT_TIMER_CLEAR BIT(4) |
4356 | #define B_BE_WLAN_WDT_BYPASS BIT(1) |
4357 | #define B_BE_WLAN_WDT_ENABLE BIT(0) |
4358 | |
4359 | #define R_BE_AXIDMA_WDT 0x305C |
4360 | #define B_BE_AXIDMA_WDT_TIMEOUT BIT(31) |
4361 | #define B_BE_AXIDMA_WDT_TIMER_CLEAR BIT(4) |
4362 | #define B_BE_AXIDMA_WDT_BYPASS BIT(1) |
4363 | #define B_BE_AXIDMA_WDT_ENABLE BIT(0) |
4364 | |
4365 | #define R_BE_AON_WDT 0x3068 |
4366 | #define B_BE_AON_WDT_TIMEOUT BIT(31) |
4367 | #define B_BE_AON_WDT_TIMER_CLEAR BIT(4) |
4368 | #define B_BE_AON_WDT_BYPASS BIT(1) |
4369 | #define B_BE_AON_WDT_ENABLE BIT(0) |
4370 | |
4371 | #define R_BE_AON_WDT_TMR 0x306C |
4372 | #define R_BE_MDIO_WDT_TMR 0x3090 |
4373 | #define R_BE_LA_MODE_WDT_TMR 0x309C |
4374 | #define R_BE_WDT_AR_TMR 0x3144 |
4375 | #define R_BE_WDT_AW_TMR 0x3150 |
4376 | #define R_BE_WLAN_WDT_TMR 0x3054 |
4377 | #define R_BE_WDT_W_TMR 0x315C |
4378 | #define R_BE_AXIDMA_WDT_TMR 0x3060 |
4379 | #define R_BE_WDT_B_TMR 0x3164 |
4380 | #define R_BE_WDT_R_TMR 0x316C |
4381 | #define R_BE_LOCAL_WDT_TMR 0x3084 |
4382 | |
4383 | #define R_BE_LOCAL_WDT 0x3080 |
4384 | #define B_BE_LOCAL_WDT_TIMEOUT BIT(31) |
4385 | #define B_BE_LOCAL_WDT_TIMER_CLEAR BIT(4) |
4386 | #define B_BE_LOCAL_WDT_BYPASS BIT(1) |
4387 | #define B_BE_LOCAL_WDT_ENABLE BIT(0) |
4388 | |
4389 | #define R_BE_MDIO_WDT 0x308C |
4390 | #define B_BE_MDIO_WDT_TIMEOUT BIT(31) |
4391 | #define B_BE_MDIO_WDT_TIMER_CLEAR BIT(4) |
4392 | #define B_BE_MDIO_WDT_BYPASS BIT(1) |
4393 | #define B_BE_MDIO_WDT_ENABLE BIT(0) |
4394 | |
4395 | #define R_BE_LA_MODE_WDT 0x3098 |
4396 | #define B_BE_LA_MODE_WDT_TIMEOUT BIT(31) |
4397 | #define B_BE_LA_MODE_WDT_TIMER_CLEAR BIT(4) |
4398 | #define B_BE_LA_MODE_WDT_BYPASS BIT(1) |
4399 | #define B_BE_LA_MODE_WDT_ENABLE BIT(0) |
4400 | |
4401 | #define R_BE_WDT_AR 0x3140 |
4402 | #define B_BE_WDT_AR_TIMEOUT BIT(31) |
4403 | #define B_BE_WDT_AR_TIMER_CLEAR BIT(4) |
4404 | #define B_BE_WDT_AR_BYPASS BIT(1) |
4405 | #define B_BE_WDT_AR_ENABLE BIT(0) |
4406 | |
4407 | #define R_BE_WDT_AW 0x314C |
4408 | #define B_BE_WDT_AW_TIMEOUT BIT(31) |
4409 | #define B_BE_WDT_AW_TIMER_CLEAR BIT(4) |
4410 | #define B_BE_WDT_AW_BYPASS BIT(1) |
4411 | #define B_BE_WDT_AW_ENABLE BIT(0) |
4412 | |
4413 | #define R_BE_WDT_W 0x3158 |
4414 | #define B_BE_WDT_W_TIMEOUT BIT(31) |
4415 | #define B_BE_WDT_W_TIMER_CLEAR BIT(4) |
4416 | #define B_BE_WDT_W_BYPASS BIT(1) |
4417 | #define B_BE_WDT_W_ENABLE BIT(0) |
4418 | |
4419 | #define R_BE_WDT_B 0x3160 |
4420 | #define B_BE_WDT_B_TIMEOUT BIT(31) |
4421 | #define B_BE_WDT_B_TIMER_CLEAR BIT(4) |
4422 | #define B_BE_WDT_B_BYPASS BIT(1) |
4423 | #define B_BE_WDT_B_ENABLE BIT(0) |
4424 | |
4425 | #define R_BE_WDT_R 0x3168 |
4426 | #define B_BE_WDT_R_TIMEOUT BIT(31) |
4427 | #define B_BE_WDT_R_TIMER_CLEAR BIT(4) |
4428 | #define B_BE_WDT_R_BYPASS BIT(1) |
4429 | #define B_BE_WDT_R_ENABLE BIT(0) |
4430 | |
4431 | #define R_BE_LTR_DECISION_CTRL_V1 0x3610 |
4432 | #define B_BE_ENABLE_LTR_CTL_DECISION BIT(31) |
4433 | #define B_BE_LAT_LTR_IDX_DRV_VLD_V1 BIT(24) |
4434 | #define B_BE_LAT_LTR_IDX_DRV_V1_MASK GENMASK(23, 22) |
4435 | #define B_BE_LAT_LTR_IDX_FW_VLD_V1 BIT(21) |
4436 | #define B_BE_LAT_LTR_IDX_FW_V1_MASK GENMASK(20, 19) |
4437 | #define B_BE_LAT_LTR_IDX_HW_VLD_V1 BIT(18) |
4438 | #define B_BE_LAT_LTR_IDX_HW_V1_MASK GENMASK(17, 16) |
4439 | #define B_BE_LTR_IDX_DRV_V1_MASK GENMASK(15, 14) |
4440 | #define B_BE_LTR_REQ_DRV_V1 BIT(13) |
4441 | #define B_BE_LTR_IDX_DISABLE_V1_MASK GENMASK(9, 8) |
4442 | #define B_BE_LTR_EN_PORT_V1_MASK GENMASK(6, 4) |
4443 | #define B_BE_LTR_DRV_DEC_EN_V1 BIT(6) |
4444 | #define B_BE_LTR_FW_DEC_EN_V1 BIT(5) |
4445 | #define B_BE_LTR_HW_DEC_EN_V1 BIT(4) |
4446 | #define B_BE_LTR_SPACE_IDX_MASK GENMASK(1, 0) |
4447 | |
4448 | #define R_BE_LTR_LATENCY_IDX0_V1 0x3614 |
4449 | #define R_BE_LTR_LATENCY_IDX1_V1 0x3618 |
4450 | #define R_BE_LTR_LATENCY_IDX2_V1 0x361C |
4451 | #define R_BE_LTR_LATENCY_IDX3_V1 0x3620 |
4452 | |
4453 | #define R_BE_H2CREG_DATA0 0x7140 |
4454 | #define R_BE_H2CREG_DATA1 0x7144 |
4455 | #define R_BE_H2CREG_DATA2 0x7148 |
4456 | #define R_BE_H2CREG_DATA3 0x714C |
4457 | #define R_BE_C2HREG_DATA0 0x7150 |
4458 | #define R_BE_C2HREG_DATA1 0x7154 |
4459 | #define R_BE_C2HREG_DATA2 0x7158 |
4460 | #define R_BE_C2HREG_DATA3 0x715C |
4461 | #define R_BE_H2CREG_CTRL 0x7160 |
4462 | #define B_BE_H2CREG_TRIGGER BIT(0) |
4463 | #define R_BE_C2HREG_CTRL 0x7164 |
4464 | #define B_BE_C2HREG_TRIGGER BIT(0) |
4465 | |
4466 | #define R_BE_HCI_FUNC_EN 0x7880 |
4467 | #define B_BE_HCI_CR_PROTECT BIT(31) |
4468 | #define B_BE_HCI_TRXBUF_EN BIT(2) |
4469 | #define B_BE_HCI_RXDMA_EN BIT(1) |
4470 | #define B_BE_HCI_TXDMA_EN BIT(0) |
4471 | |
4472 | #define R_BE_DBG_WOW_READY 0x815E |
4473 | #define B_BE_DBG_WOW_READY GENMASK(7, 0) |
4474 | |
4475 | #define R_BE_DMAC_FUNC_EN 0x8400 |
4476 | #define B_BE_DMAC_CRPRT BIT(31) |
4477 | #define B_BE_MAC_FUNC_EN BIT(30) |
4478 | #define B_BE_DMAC_FUNC_EN BIT(29) |
4479 | #define B_BE_MPDU_PROC_EN BIT(28) |
4480 | #define B_BE_WD_RLS_EN BIT(27) |
4481 | #define B_BE_DLE_WDE_EN BIT(26) |
4482 | #define B_BE_TXPKT_CTRL_EN BIT(25) |
4483 | #define B_BE_STA_SCH_EN BIT(24) |
4484 | #define B_BE_DLE_PLE_EN BIT(23) |
4485 | #define B_BE_PKT_BUF_EN BIT(22) |
4486 | #define B_BE_DMAC_TBL_EN BIT(21) |
4487 | #define B_BE_PKT_IN_EN BIT(20) |
4488 | #define B_BE_DLE_CPUIO_EN BIT(19) |
4489 | #define B_BE_DISPATCHER_EN BIT(18) |
4490 | #define B_BE_BBRPT_EN BIT(17) |
4491 | #define B_BE_MAC_SEC_EN BIT(16) |
4492 | #define B_BE_DMACREG_GCKEN BIT(15) |
4493 | #define B_BE_H_AXIDMA_EN BIT(14) |
4494 | #define B_BE_DMAC_MLO_EN BIT(11) |
4495 | #define B_BE_PLRLS_EN BIT(10) |
4496 | #define B_BE_P_AXIDMA_EN BIT(9) |
4497 | #define B_BE_DLE_DATACPUIO_EN BIT(8) |
4498 | #define B_BE_LTR_CTL_EN BIT(7) |
4499 | |
4500 | #define R_BE_DMAC_CLK_EN 0x8404 |
4501 | #define B_BE_MAC_CKEN BIT(30) |
4502 | #define B_BE_DMAC_CKEN BIT(29) |
4503 | #define B_BE_MPDU_CKEN BIT(28) |
4504 | #define B_BE_WD_RLS_CLK_EN BIT(27) |
4505 | #define B_BE_DLE_WDE_CLK_EN BIT(26) |
4506 | #define B_BE_TXPKT_CTRL_CLK_EN BIT(25) |
4507 | #define B_BE_STA_SCH_CLK_EN BIT(24) |
4508 | #define B_BE_DLE_PLE_CLK_EN BIT(23) |
4509 | #define B_BE_PKTBUF_CKEN BIT(22) |
4510 | #define B_BE_DMAC_TABLE_CLK_EN BIT(21) |
4511 | #define B_BE_PKT_IN_CLK_EN BIT(20) |
4512 | #define B_BE_DLE_CPUIO_CLK_EN BIT(19) |
4513 | #define B_BE_DISPATCHER_CLK_EN BIT(18) |
4514 | #define B_BE_BBRPT_CLK_EN BIT(17) |
4515 | #define B_BE_MAC_SEC_CLK_EN BIT(16) |
4516 | #define B_BE_H_AXIDMA_CKEN BIT(14) |
4517 | #define B_BE_DMAC_MLO_CKEN BIT(11) |
4518 | #define B_BE_PLRLS_CKEN BIT(10) |
4519 | #define B_BE_P_AXIDMA_CKEN BIT(9) |
4520 | #define B_BE_DLE_DATACPUIO_CKEN BIT(8) |
4521 | |
4522 | #define R_BE_LTR_CTRL_0 0x8410 |
4523 | #define B_BE_LTR_REQ_FW BIT(18) |
4524 | #define B_BE_LTR_IDX_FW_MASK GENMASK(17, 16) |
4525 | #define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) |
4526 | #define B_BE_LTR_WD_NOEMP_CHK BIT(1) |
4527 | #define B_BE_LTR_HW_EN BIT(0) |
4528 | |
4529 | #define R_BE_LTR_CFG_0 0x8414 |
4530 | #define B_BE_LTR_IDX_DISABLE_MASK GENMASK(17, 16) |
4531 | #define B_BE_LTR_IDX_IDLE_MASK GENMASK(15, 14) |
4532 | #define B_BE_LTR_IDX_ACTIVE_MASK GENMASK(13, 12) |
4533 | #define B_BE_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) |
4534 | #define B_BE_EN_LTR_CMAC_RX_USE_PG_CHK BIT(3) |
4535 | #define B_BE_EN_LTR_WD_NON_EMPTY_CHK BIT(2) |
4536 | #define B_BE_EN_LTR_HAXIDMA_TX_IDLE_CHK BIT(1) |
4537 | #define B_BE_EN_LTR_HAXIDMA_RX_IDLE_CHK BIT(0) |
4538 | |
4539 | #define R_BE_LTR_CFG_1 0x8418 |
4540 | #define B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK GENMASK(27, 16) |
4541 | #define B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK GENMASK(11, 0) |
4542 | |
4543 | #define R_BE_DMAC_TABLE_CTRL 0x8420 |
4544 | #define B_BE_HWAMSDU_PADDING_MODE BIT(31) |
4545 | #define B_BE_MACID_MPDU_PROCESSOR_OFFSET_MASK GENMASK(26, 16) |
4546 | #define B_BE_DMAC_ADDR_MODE BIT(12) |
4547 | #define B_BE_DMAC_CTRL_INFO_SER_IO BIT(11) |
4548 | #define B_BE_DMAC_CTRL_INFO_OFFSET_MASK GENMASK(10, 0) |
4549 | |
4550 | #define R_BE_SER_DBG_INFO 0x8424 |
4551 | #define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28) |
4552 | #define B_BE_SER_L1_COUNTER_MASK GENMASK(27, 24) |
4553 | #define B_BE_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16) |
4554 | #define B_BE_SER_L0_COUNTER_MASK GENMASK(8, 0) |
4555 | |
4556 | #define R_BE_DMAC_SYS_CR32B 0x842C |
4557 | #define B_BE_DMAC_BB_PHY1_MASK GENMASK(31, 16) |
4558 | #define B_BE_DMAC_BB_PHY0_MASK GENMASK(15, 0) |
4559 | #define B_BE_DMAC_BB_CTRL_39 BIT(31) |
4560 | #define B_BE_DMAC_BB_CTRL_38 BIT(30) |
4561 | #define B_BE_DMAC_BB_CTRL_37 BIT(29) |
4562 | #define B_BE_DMAC_BB_CTRL_36 BIT(28) |
4563 | #define B_BE_DMAC_BB_CTRL_35 BIT(27) |
4564 | #define B_BE_DMAC_BB_CTRL_34 BIT(26) |
4565 | #define B_BE_DMAC_BB_CTRL_33 BIT(25) |
4566 | #define B_BE_DMAC_BB_CTRL_32 BIT(24) |
4567 | #define B_BE_DMAC_BB_CTRL_31 BIT(23) |
4568 | #define B_BE_DMAC_BB_CTRL_30 BIT(22) |
4569 | #define B_BE_DMAC_BB_CTRL_29 BIT(21) |
4570 | #define B_BE_DMAC_BB_CTRL_28 BIT(20) |
4571 | #define B_BE_DMAC_BB_CTRL_27 BIT(19) |
4572 | #define B_BE_DMAC_BB_CTRL_26 BIT(18) |
4573 | #define B_BE_DMAC_BB_CTRL_25 BIT(17) |
4574 | #define B_BE_DMAC_BB_CTRL_24 BIT(16) |
4575 | #define B_BE_DMAC_BB_CTRL_23 BIT(15) |
4576 | #define B_BE_DMAC_BB_CTRL_22 BIT(14) |
4577 | #define B_BE_DMAC_BB_CTRL_21 BIT(13) |
4578 | #define B_BE_DMAC_BB_CTRL_20 BIT(12) |
4579 | #define B_BE_DMAC_BB_CTRL_19 BIT(11) |
4580 | #define B_BE_DMAC_BB_CTRL_18 BIT(10) |
4581 | #define B_BE_DMAC_BB_CTRL_17 BIT(9) |
4582 | #define B_BE_DMAC_BB_CTRL_16 BIT(8) |
4583 | #define B_BE_DMAC_BB_CTRL_15 BIT(7) |
4584 | #define B_BE_DMAC_BB_CTRL_14 BIT(6) |
4585 | #define B_BE_DMAC_BB_CTRL_13 BIT(5) |
4586 | #define B_BE_DMAC_BB_CTRL_12 BIT(4) |
4587 | #define B_BE_DMAC_BB_CTRL_11 BIT(3) |
4588 | #define B_BE_DMAC_BB_CTRL_10 BIT(2) |
4589 | #define B_BE_DMAC_BB_CTRL_9 BIT(1) |
4590 | #define B_BE_DMAC_BB_CTRL_8 BIT(0) |
4591 | |
4592 | #define R_BE_DLE_EMPTY0 0x8430 |
4593 | #define B_BE_PLE_EMPTY_QTA_DMAC_H2D BIT(27) |
4594 | #define B_BE_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) |
4595 | #define B_BE_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) |
4596 | #define B_BE_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) |
4597 | #define B_BE_PLE_EMPTY_QTA_DMAC_H2C BIT(23) |
4598 | #define B_BE_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) |
4599 | #define B_BE_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) |
4600 | #define B_BE_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) |
4601 | #define B_BE_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) |
4602 | #define B_BE_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) |
4603 | #define B_BE_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) |
4604 | #define B_BE_WDE_EMPTY_QTA_DMAC_HIF BIT(16) |
4605 | #define B_BE_WDE_EMPTY_QUE_CMAC_B1_HIQ BIT(15) |
4606 | #define B_BE_WDE_EMPTY_QUE_CMAC_B1_MBH BIT(14) |
4607 | #define B_BE_WDE_EMPTY_QUE_CMAC_B0_OTHERS BIT(13) |
4608 | #define B_BE_WDE_EMPTY_QUE_DMAC_MLO_ACQ BIT(12) |
4609 | #define B_BE_WDE_EMPTY_QUE_DMAC_MLO_MISC BIT(11) |
4610 | #define B_BE_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) |
4611 | #define B_BE_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) |
4612 | #define B_BE_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) |
4613 | #define B_BE_WDE_EMPTY_QUE_OTHERS BIT(7) |
4614 | #define B_BE_WDE_EMPTY_QUE_CMAC_WMM3 BIT(6) |
4615 | #define B_BE_WDE_EMPTY_QUE_CMAC_WMM2 BIT(5) |
4616 | #define B_BE_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) |
4617 | #define B_BE_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) |
4618 | #define B_BE_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) |
4619 | #define B_BE_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) |
4620 | #define B_BE_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) |
4621 | |
4622 | #define R_BE_DLE_EMPTY1 0x8434 |
4623 | #define B_BE_PLE_EMPTY_QTA_CMAC_DMA_TXRPT BIT(21) |
4624 | #define B_BE_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20) |
4625 | #define B_BE_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19) |
4626 | #define B_BE_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18) |
4627 | #define B_BE_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17) |
4628 | #define B_BE_PLE_EMPTY_QTA_DMAC_C2H BIT(16) |
4629 | #define B_BE_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5) |
4630 | #define B_BE_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4) |
4631 | #define B_BE_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3) |
4632 | #define B_BE_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2) |
4633 | #define B_BE_PLE_EMPTY_QUE_DMAC_HDP BIT(1) |
4634 | #define B_BE_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0) |
4635 | |
4636 | #define R_BE_SER_L1_DBG_CNT_0 0x8440 |
4637 | #define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24) |
4638 | #define B_BE_SER_L1_SEC_CNT_MASK GENMASK(23, 16) |
4639 | #define B_BE_SER_L1_MPDU_CNT_MASK GENMASK(15, 8) |
4640 | #define B_BE_SER_L1_STA_SCH_CNT_MASK GENMASK(7, 0) |
4641 | |
4642 | #define R_BE_SER_L1_DBG_CNT_1 0x8444 |
4643 | #define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24) |
4644 | #define B_BE_SER_L1_TXPKTCTRL_CNT_MASK GENMASK(23, 16) |
4645 | #define B_BE_SER_L1_PLE_CNT_MASK GENMASK(15, 8) |
4646 | #define B_BE_SER_L1_PKTIN_CNT_MASK GENMASK(7, 0) |
4647 | |
4648 | #define R_BE_SER_L1_DBG_CNT_2 0x8448 |
4649 | #define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24) |
4650 | #define B_BE_SER_L1_APB_BRIDGE_CNT_MASK GENMASK(23, 16) |
4651 | #define B_BE_SER_L1_DLE_W_CPUIO_CNT_MASK GENMASK(15, 8) |
4652 | #define B_BE_SER_L1_BBRPT_CNT_MASK GENMASK(7, 0) |
4653 | |
4654 | #define R_BE_SER_L1_DBG_CNT_3 0x844C |
4655 | #define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24) |
4656 | #define B_BE_SER_L1_P_AXIDMA_CNT_MASK GENMASK(23, 16) |
4657 | #define B_BE_SER_L1_H_AXIDMA_CNT_MASK GENMASK(15, 8) |
4658 | #define B_BE_SER_L1_MLO_ERR_CNT_MASK GENMASK(7, 0) |
4659 | |
4660 | #define R_BE_SER_L1_DBG_CNT_4 0x8450 |
4661 | #define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24) |
4662 | #define B_BE_SER_L1_DLE_D_CPUIO_CNT_MASK GENMASK(23, 16) |
4663 | |
4664 | #define R_BE_SER_L1_DBG_CNT_5 0x8454 |
4665 | #define B_BE_SER_L1_DBG_0_MASK GENMASK(31, 0) |
4666 | |
4667 | #define R_BE_SER_L1_DBG_CNT_6 0x8458 |
4668 | #define B_BE_SER_L1_DBG_1_MASK GENMASK(31, 0) |
4669 | |
4670 | #define R_BE_SER_L1_DBG_CNT_7 0x845C |
4671 | #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0) |
4672 | |
4673 | #define R_BE_DMAC_ERR_IMR 0x8520 |
4674 | #define B_BE_DMAC_NOTX_ERR_INT_EN BIT(21) |
4675 | #define B_BE_DMAC_NORX_ERR_INT_EN BIT(20) |
4676 | #define B_BE_DLE_DATACPUIO_ERR_INT_EN BIT(19) |
4677 | #define B_BE_PLRSL_ERR_INT_EN BIT(18) |
4678 | #define B_BE_MLO_ERR_INT_EN BIT(17) |
4679 | #define B_BE_DMAC_FW_ERR_INT_EN BIT(16) |
4680 | #define B_BE_H_AXIDMA_ERR_INT_EN BIT(14) |
4681 | #define B_BE_P_AXIDMA_ERR_INT_EN BIT(13) |
4682 | #define B_BE_HCI_BUF_ERR_INT_EN BIT(12) |
4683 | #define B_BE_BBRPT_ERR_INT_EN BIT(11) |
4684 | #define B_BE_DLE_CPUIO_ERR_INT_EN BIT(10) |
4685 | #define B_BE_APB_BRIDGE_ERR_INT_EN BIT(9) |
4686 | #define B_BE_DISPATCH_ERR_INT_EN BIT(8) |
4687 | #define B_BE_PKTIN_ERR_INT_EN BIT(7) |
4688 | #define B_BE_PLE_DLE_ERR_INT_EN BIT(6) |
4689 | #define B_BE_TXPKTCTRL_ERR_INT_EN BIT(5) |
4690 | #define B_BE_WDE_DLE_ERR_INT_EN BIT(4) |
4691 | #define B_BE_STA_SCHEDULER_ERR_INT_EN BIT(3) |
4692 | #define B_BE_MPDU_ERR_INT_EN BIT(2) |
4693 | #define B_BE_WSEC_ERR_INT_EN BIT(1) |
4694 | #define B_BE_WDRLS_ERR_INT_EN BIT(0) |
4695 | |
4696 | #define R_BE_DMAC_ERR_ISR 0x8524 |
4697 | #define B_BE_DLE_DATACPUIO_ERR_INT BIT(19) |
4698 | #define B_BE_PLRLS_ERR_INT BIT(18) |
4699 | #define B_BE_MLO_ERR_INT BIT(17) |
4700 | #define B_BE_DMAC_FW_ERR_IDCT BIT(16) |
4701 | #define B_BE_H_AXIDMA_ERR_INT BIT(14) |
4702 | #define B_BE_P_AXIDMA_ERR_INT BIT(13) |
4703 | #define B_BE_HCI_BUF_ERR_FLAG BIT(12) |
4704 | #define B_BE_BBRPT_ERR_FLAG BIT(11) |
4705 | #define B_BE_DLE_CPUIO_ERR_FLAG BIT(10) |
4706 | #define B_BE_APB_BRIDGE_ERR_FLAG BIT(9) |
4707 | #define B_BE_DISPATCH_ERR_FLAG BIT(8) |
4708 | #define B_BE_PKTIN_ERR_FLAG BIT(7) |
4709 | #define B_BE_PLE_DLE_ERR_FLAG BIT(6) |
4710 | #define B_BE_TXPKTCTRL_ERR_FLAG BIT(5) |
4711 | #define B_BE_WDE_DLE_ERR_FLAG BIT(4) |
4712 | #define B_BE_STA_SCHEDULER_ERR_FLAG BIT(3) |
4713 | #define B_BE_MPDU_ERR_FLAG BIT(2) |
4714 | #define B_BE_WSEC_ERR_FLAG BIT(1) |
4715 | #define B_BE_WDRLS_ERR_FLAG BIT(0) |
4716 | |
4717 | #define R_BE_DISP_ERROR_ISR0 0x8804 |
4718 | #define B_BE_REUSE_SIZE_ERR BIT(31) |
4719 | #define B_BE_REUSE_EN_ERR BIT(30) |
4720 | #define B_BE_STF_OQT_UNDERFLOW_ERR BIT(29) |
4721 | #define B_BE_STF_OQT_OVERFLOW_ERR BIT(28) |
4722 | #define B_BE_STF_WRFF_UNDERFLOW_ERR BIT(27) |
4723 | #define B_BE_STF_WRFF_OVERFLOW_ERR BIT(26) |
4724 | #define B_BE_STF_CMD_UNDERFLOW_ERR BIT(25) |
4725 | #define B_BE_STF_CMD_OVERFLOW_ERR BIT(24) |
4726 | #define B_BE_REUSE_SIZE_ZERO_ERR BIT(23) |
4727 | #define B_BE_REUSE_PKT_CNT_ERR BIT(22) |
4728 | #define B_BE_CDT_PTR_TIMEOUT_ERR BIT(21) |
4729 | #define B_BE_CDT_HCI_TIMEOUT_ERR BIT(20) |
4730 | #define B_BE_HDT_PTR_TIMEOUT_ERR BIT(19) |
4731 | #define B_BE_HDT_HCI_TIMEOUT_ERR BIT(18) |
4732 | #define B_BE_CDT_ADDR_INFO_LEN_ERR BIT(17) |
4733 | #define B_BE_HDT_ADDR_INFO_LEN_ERR BIT(16) |
4734 | #define B_BE_CDR_DMA_TIMEOUT_ERR BIT(15) |
4735 | #define B_BE_CDR_RX_TIMEOUT_ERR BIT(14) |
4736 | #define B_BE_PLE_OUTPUT_ERR BIT(12) |
4737 | #define B_BE_PLE_RESPOSE_ERR BIT(11) |
4738 | #define B_BE_PLE_BURST_NUM_ERR BIT(10) |
4739 | #define B_BE_PLE_NULL_PKT_ERR BIT(9) |
4740 | #define B_BE_PLE_FLOW_CTRL_ERR BIT(8) |
4741 | #define B_BE_HDR_DMA_TIMEOUT_ERR BIT(7) |
4742 | #define B_BE_HDR_RX_TIMEOUT_ERR BIT(6) |
4743 | #define B_BE_WDE_OUTPUT_ERR BIT(4) |
4744 | #define B_BE_WDE_RESPONSE_ERR BIT(3) |
4745 | #define B_BE_WDE_BURST_NUM_ERR BIT(2) |
4746 | #define B_BE_WDE_NULL_PKT_ERR BIT(1) |
4747 | #define B_BE_WDE_FLOW_CTRL_ERR BIT(0) |
4748 | |
4749 | #define R_BE_DISP_ERROR_ISR1 0x8808 |
4750 | #define B_BE_HR_WRFF_UNDERFLOW_ERR BIT(31) |
4751 | #define B_BE_HR_WRFF_OVERFLOW_ERR BIT(30) |
4752 | #define B_BE_HR_CHKSUM_FSM_ERR BIT(29) |
4753 | #define B_BE_HR_SHIFT_DMA_CFG_ERR BIT(28) |
4754 | #define B_BE_HR_DMA_PROCESS_ERR BIT(27) |
4755 | #define B_BE_HR_TOTAL_LEN_UNDER_ERR BIT(26) |
4756 | #define B_BE_HR_SHIFT_EN_ERR BIT(25) |
4757 | #define B_BE_HR_AGG_CFG_ERR BIT(24) |
4758 | #define B_BE_HR_PLD_LEN_ZERO_ERR BIT(22) |
4759 | #define B_BE_HT_ILL_CH_ERR BIT(20) |
4760 | #define B_BE_HT_ADDR_INFO_LEN_ERR BIT(18) |
4761 | #define B_BE_HT_WD_LEN_OVER_ERR BIT(17) |
4762 | #define B_BE_HT_PLD_CMD_UNDERFLOW_ERR BIT(16) |
4763 | #define B_BE_HT_PLD_CMD_OVERFLOW_ERR BIT(15) |
4764 | #define B_BE_HT_WRFF_UNDERFLOW_ERR BIT(14) |
4765 | #define B_BE_HT_WRFF_OVERFLOW_ERR BIT(13) |
4766 | #define B_BE_HT_CHKSUM_FSM_ERR BIT(12) |
4767 | #define B_BE_HT_NON_IDLE_PKT_STR_ERR BIT(11) |
4768 | #define B_BE_HT_PRE_SUB_BE_ERR BIT(10) |
4769 | #define B_BE_HT_WD_CHKSUM_ERR BIT(9) |
4770 | #define B_BE_HT_CHANNEL_DMA_ERR BIT(8) |
4771 | #define B_BE_HT_OFFSET_UNMATCH_ERR BIT(7) |
4772 | #define B_BE_HT_PAYLOAD_UNDER_ERR BIT(6) |
4773 | #define B_BE_HT_PAYLOAD_OVER_ERR BIT(5) |
4774 | #define B_BE_HT_PERMU_FF_UNDERFLOW_ERR BIT(4) |
4775 | #define B_BE_HT_PERMU_FF_OVERFLOW_ERR BIT(3) |
4776 | #define B_BE_HT_PKT_FAIL_ERR BIT(2) |
4777 | #define B_BE_HT_CH_ID_ERR BIT(1) |
4778 | #define B_BE_HT_EP_CH_DIFF_ERR BIT(0) |
4779 | |
4780 | #define R_BE_DISP_ERROR_ISR2 0x880C |
4781 | #define B_BE_CR_PLD_LEN_ERR BIT(30) |
4782 | #define B_BE_CR_WRFF_UNDERFLOW_ERR BIT(29) |
4783 | #define B_BE_CR_WRFF_OVERFLOW_ERR BIT(28) |
4784 | #define B_BE_CR_SHIFT_DMA_CFG_ERR BIT(27) |
4785 | #define B_BE_CR_DMA_PROCESS_ERR BIT(26) |
4786 | #define B_BE_CR_SHIFT_EN_ERR BIT(24) |
4787 | #define B_BE_REUSE_FIFO_B_UNDER_ERR BIT(22) |
4788 | #define B_BE_REUSE_FIFO_B_OVER_ERR BIT(21) |
4789 | #define B_BE_REUSE_FIFO_A_UNDER_ERR BIT(20) |
4790 | #define B_BE_REUSE_FIFO_A_OVER_ERR BIT(19) |
4791 | #define B_BE_CT_ADDR_INFO_LEN_MISS_ERR BIT(17) |
4792 | #define B_BE_CT_WD_LEN_OVER_ERR BIT(16) |
4793 | #define B_BE_CT_F2P_SEQ_ERR BIT(15) |
4794 | #define B_BE_CT_F2P_QSEL_ERR BIT(14) |
4795 | #define B_BE_CT_PLD_CMD_UNDERFLOW_ERR BIT(13) |
4796 | #define B_BE_CT_PLD_CMD_OVERFLOW_ERR BIT(12) |
4797 | #define B_BE_CT_PRE_SUB_ERR BIT(11) |
4798 | #define B_BE_CT_WD_CHKSUM_ERR BIT(10) |
4799 | #define B_BE_CT_CHANNEL_DMA_ERR BIT(9) |
4800 | #define B_BE_CT_OFFSET_UNMATCH_ERR BIT(8) |
4801 | #define B_BE_F2P_TOTAL_NUM_ERR BIT(7) |
4802 | #define B_BE_CT_PAYLOAD_UNDER_ERR BIT(6) |
4803 | #define B_BE_CT_PAYLOAD_OVER_ERR BIT(5) |
4804 | #define B_BE_CT_PERMU_FF_UNDERFLOW_ERR BIT(4) |
4805 | #define B_BE_CT_PERMU_FF_OVERFLOW_ERR BIT(3) |
4806 | #define B_BE_CT_CH_ID_ERR BIT(2) |
4807 | #define B_BE_CT_EP_CH_DIFF_ERR BIT(0) |
4808 | |
4809 | #define R_BE_DISP_OTHER_IMR 0x8870 |
4810 | #define B_BE_REUSE_SIZE_ERR_INT_EN BIT(31) |
4811 | #define B_BE_REUSE_EN_ERR_INT_EN BIT(30) |
4812 | #define B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29) |
4813 | #define B_BE_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28) |
4814 | #define B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27) |
4815 | #define B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26) |
4816 | #define B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25) |
4817 | #define B_BE_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24) |
4818 | #define B_BE_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23) |
4819 | #define B_BE_REUSE_PKT_CNT_ERR_INT_EN BIT(22) |
4820 | #define B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21) |
4821 | #define B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20) |
4822 | #define B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19) |
4823 | #define B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18) |
4824 | #define B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17) |
4825 | #define B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16) |
4826 | #define B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15) |
4827 | #define B_BE_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14) |
4828 | #define B_BE_PLE_OUTPUT_ERR_INT_EN BIT(12) |
4829 | #define B_BE_PLE_RESPOSE_ERR_INT_EN BIT(11) |
4830 | #define B_BE_PLE_BURST_NUM_ERR_INT_EN BIT(10) |
4831 | #define B_BE_PLE_NULL_PKT_ERR_INT_EN BIT(9) |
4832 | #define B_BE_PLE_FLOW_CTRL_ERR_INT_EN BIT(8) |
4833 | #define B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7) |
4834 | #define B_BE_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6) |
4835 | #define B_BE_WDE_OUTPUT_ERR_INT_EN BIT(4) |
4836 | #define B_BE_WDE_RESPONSE_ERR_INT_EN BIT(3) |
4837 | #define B_BE_WDE_BURST_NUM_ERR_INT_EN BIT(2) |
4838 | #define B_BE_WDE_NULL_PKT_ERR_INT_EN BIT(1) |
4839 | #define B_BE_WDE_FLOW_CTRL_ERR_INT_EN BIT(0) |
4840 | #define B_BE_DISP_OTHER_IMR_CLR (B_BE_WDE_FLOW_CTRL_ERR_INT_EN | \ |
4841 | B_BE_WDE_NULL_PKT_ERR_INT_EN | \ |
4842 | B_BE_WDE_BURST_NUM_ERR_INT_EN | \ |
4843 | B_BE_WDE_RESPONSE_ERR_INT_EN | \ |
4844 | B_BE_WDE_OUTPUT_ERR_INT_EN | \ |
4845 | B_BE_HDR_RX_TIMEOUT_ERR_INT_EN | \ |
4846 | B_BE_HDR_DMA_TIMEOUT_ERR_INT_EN | \ |
4847 | B_BE_PLE_FLOW_CTRL_ERR_INT_EN | \ |
4848 | B_BE_PLE_NULL_PKT_ERR_INT_EN | \ |
4849 | B_BE_PLE_BURST_NUM_ERR_INT_EN | \ |
4850 | B_BE_PLE_RESPOSE_ERR_INT_EN | \ |
4851 | B_BE_PLE_OUTPUT_ERR_INT_EN | \ |
4852 | B_BE_CDR_RX_TIMEOUT_ERR_INT_EN | \ |
4853 | B_BE_CDR_DMA_TIMEOUT_ERR_INT_EN | \ |
4854 | B_BE_HDT_ADDR_INFO_LEN_ERR_INT_EN | \ |
4855 | B_BE_CDT_ADDR_INFO_LEN_ERR_INT_EN | \ |
4856 | B_BE_HDT_HCI_TIMEOUT_ERR_INT_EN | \ |
4857 | B_BE_HDT_PTR_TIMEOUT_ERR_INT_EN | \ |
4858 | B_BE_CDT_HCI_TIMEOUT_ERR_INT_EN | \ |
4859 | B_BE_CDT_PTR_TIMEOUT_ERR_INT_EN | \ |
4860 | B_BE_REUSE_PKT_CNT_ERR_INT_EN | \ |
4861 | B_BE_REUSE_SIZE_ZERO_ERR_INT_EN | \ |
4862 | B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \ |
4863 | B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \ |
4864 | B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \ |
4865 | B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \ |
4866 | B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \ |
4867 | B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN | \ |
4868 | B_BE_REUSE_EN_ERR_INT_EN | \ |
4869 | B_BE_REUSE_SIZE_ERR_INT_EN) |
4870 | #define B_BE_DISP_OTHER_IMR_SET (B_BE_STF_CMD_OVERFLOW_ERR_INT_EN | \ |
4871 | B_BE_STF_CMD_UNDERFLOW_ERR_INT_EN | \ |
4872 | B_BE_STF_WRFF_OVERFLOW_ERR_INT_EN | \ |
4873 | B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \ |
4874 | B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \ |
4875 | B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN) |
4876 | |
4877 | #define R_BE_DISP_HOST_IMR 0x8874 |
4878 | #define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31) |
4879 | #define B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30) |
4880 | #define B_BE_HR_CHKSUM_FSM_ERR_INT_EN BIT(29) |
4881 | #define B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) |
4882 | #define B_BE_HR_DMA_PROCESS_ERR_INT_EN BIT(27) |
4883 | #define B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26) |
4884 | #define B_BE_HR_SHIFT_EN_ERR_INT_EN BIT(25) |
4885 | #define B_BE_HR_AGG_CFG_ERR_INT_EN BIT(24) |
4886 | #define B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22) |
4887 | #define B_BE_HT_ILL_CH_ERR_INT_EN BIT(20) |
4888 | #define B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18) |
4889 | #define B_BE_HT_WD_LEN_OVER_ERR_INT_EN BIT(17) |
4890 | #define B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16) |
4891 | #define B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15) |
4892 | #define B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14) |
4893 | #define B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13) |
4894 | #define B_BE_HT_CHKSUM_FSM_ERR_INT_EN BIT(12) |
4895 | #define B_BE_HT_NON_IDLE_PKT_STR_ERR_EN BIT(11) |
4896 | #define B_BE_HT_PRE_SUB_ERR_INT_EN BIT(10) |
4897 | #define B_BE_HT_WD_CHKSUM_ERR_INT_EN BIT(9) |
4898 | #define B_BE_HT_CHANNEL_DMA_ERR_INT_EN BIT(8) |
4899 | #define B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7) |
4900 | #define B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) |
4901 | #define B_BE_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5) |
4902 | #define B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) |
4903 | #define B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) |
4904 | #define B_BE_HT_PKT_FAIL_ERR_INT_EN BIT(2) |
4905 | #define B_BE_HT_CH_ID_ERR_INT_EN BIT(1) |
4906 | #define B_BE_HT_EP_CH_DIFF_ERR_INT_EN BIT(0) |
4907 | #define B_BE_DISP_HOST_IMR_CLR (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \ |
4908 | B_BE_HT_CH_ID_ERR_INT_EN | \ |
4909 | B_BE_HT_PKT_FAIL_ERR_INT_EN | \ |
4910 | B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ |
4911 | B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ |
4912 | B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \ |
4913 | B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \ |
4914 | B_BE_HT_OFFSET_UNMATCH_ERR_INT_EN | \ |
4915 | B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \ |
4916 | B_BE_HT_WD_CHKSUM_ERR_INT_EN | \ |
4917 | B_BE_HT_PRE_SUB_ERR_INT_EN | \ |
4918 | B_BE_HT_NON_IDLE_PKT_STR_ERR_EN | \ |
4919 | B_BE_HT_CHKSUM_FSM_ERR_INT_EN | \ |
4920 | B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \ |
4921 | B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \ |
4922 | B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ |
4923 | B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ |
4924 | B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \ |
4925 | B_BE_HT_ADDR_INFO_LEN_ERR_INT_EN | \ |
4926 | B_BE_HT_ILL_CH_ERR_INT_EN | \ |
4927 | B_BE_HR_PLD_LEN_ZERO_ERR_INT_EN | \ |
4928 | B_BE_HR_AGG_CFG_ERR_INT_EN | \ |
4929 | B_BE_HR_SHIFT_EN_ERR_INT_EN | \ |
4930 | B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ |
4931 | B_BE_HR_DMA_PROCESS_ERR_INT_EN | \ |
4932 | B_BE_HR_SHIFT_DMA_CFG_ERR_INT_EN | \ |
4933 | B_BE_HR_CHKSUM_FSM_ERR_INT_EN | \ |
4934 | B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \ |
4935 | B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN) |
4936 | #define B_BE_DISP_HOST_IMR_SET (B_BE_HT_EP_CH_DIFF_ERR_INT_EN | \ |
4937 | B_BE_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ |
4938 | B_BE_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ |
4939 | B_BE_HT_PAYLOAD_OVER_ERR_INT_EN | \ |
4940 | B_BE_HT_PAYLOAD_UNDER_ERR_INT_EN | \ |
4941 | B_BE_HT_CHANNEL_DMA_ERR_INT_EN | \ |
4942 | B_BE_HT_PRE_SUB_ERR_INT_EN | \ |
4943 | B_BE_HT_WRFF_OVERFLOW_ERR_INT_EN | \ |
4944 | B_BE_HT_WRFF_UNDERFLOW_ERR_INT_EN | \ |
4945 | B_BE_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ |
4946 | B_BE_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ |
4947 | B_BE_HT_WD_LEN_OVER_ERR_INT_EN | \ |
4948 | B_BE_HT_ILL_CH_ERR_INT_EN | \ |
4949 | B_BE_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ |
4950 | B_BE_HR_DMA_PROCESS_ERR_INT_EN | \ |
4951 | B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \ |
4952 | B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN) |
4953 | |
4954 | #define R_BE_DISP_CPU_IMR 0x8878 |
4955 | #define B_BE_CR_PLD_LEN_ERR_INT_EN BIT(30) |
4956 | #define B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29) |
4957 | #define B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28) |
4958 | #define B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27) |
4959 | #define B_BE_CR_DMA_PROCESS_ERR_INT_EN BIT(26) |
4960 | #define B_BE_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25) |
4961 | #define B_BE_CR_SHIFT_EN_ERR_INT_EN BIT(24) |
4962 | #define B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22) |
4963 | #define B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21) |
4964 | #define B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20) |
4965 | #define B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19) |
4966 | #define B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17) |
4967 | #define B_BE_CT_WD_LEN_OVER_ERR_INT_EN BIT(16) |
4968 | #define B_BE_CT_F2P_SEQ_ERR_INT_EN BIT(15) |
4969 | #define B_BE_CT_F2P_QSEL_ERR_INT_EN BIT(14) |
4970 | #define B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13) |
4971 | #define B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12) |
4972 | #define B_BE_CT_PRE_SUB_ERR_INT_EN BIT(11) |
4973 | #define B_BE_CT_WD_CHKSUM_ERR_INT_EN BIT(10) |
4974 | #define B_BE_CT_CHANNEL_DMA_ERR_INT_EN BIT(9) |
4975 | #define B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8) |
4976 | #define B_BE_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) |
4977 | #define B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) |
4978 | #define B_BE_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5) |
4979 | #define B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) |
4980 | #define B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) |
4981 | #define B_BE_CT_CH_ID_ERR_INT_EN BIT(2) |
4982 | #define B_BE_CT_PKT_FAIL_ERR_INT_EN BIT(1) |
4983 | #define B_BE_CT_EP_CH_DIFF_ERR_INT_EN BIT(0) |
4984 | #define B_BE_DISP_CPU_IMR_CLR (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \ |
4985 | B_BE_CT_CH_ID_ERR_INT_EN | \ |
4986 | B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ |
4987 | B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ |
4988 | B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \ |
4989 | B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \ |
4990 | B_BE_CT_OFFSET_UNMATCH_ERR_INT_EN | \ |
4991 | B_BE_CT_CHANNEL_DMA_ERR_INT_EN | \ |
4992 | B_BE_CT_WD_CHKSUM_ERR_INT_EN | \ |
4993 | B_BE_CT_PRE_SUB_ERR_INT_EN | \ |
4994 | B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ |
4995 | B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ |
4996 | B_BE_CT_F2P_QSEL_ERR_INT_EN | \ |
4997 | B_BE_CT_F2P_SEQ_ERR_INT_EN | \ |
4998 | B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \ |
4999 | B_BE_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \ |
5000 | B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \ |
5001 | B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \ |
5002 | B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \ |
5003 | B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \ |
5004 | B_BE_CR_SHIFT_EN_ERR_INT_EN | \ |
5005 | B_BE_CR_DMA_PROCESS_ERR_INT_EN | \ |
5006 | B_BE_CR_SHIFT_DMA_CFG_ERR_INT_EN | \ |
5007 | B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \ |
5008 | B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN | \ |
5009 | B_BE_CR_PLD_LEN_ERR_INT_EN) |
5010 | #define B_BE_DISP_CPU_IMR_SET (B_BE_CT_EP_CH_DIFF_ERR_INT_EN | \ |
5011 | B_BE_CT_CH_ID_ERR_INT_EN | \ |
5012 | B_BE_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ |
5013 | B_BE_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ |
5014 | B_BE_CT_PAYLOAD_OVER_ERR_INT_EN | \ |
5015 | B_BE_CT_PAYLOAD_UNDER_ERR_INT_EN | \ |
5016 | B_BE_CT_PRE_SUB_ERR_INT_EN | \ |
5017 | B_BE_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ |
5018 | B_BE_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ |
5019 | B_BE_CT_WD_LEN_OVER_ERR_INT_EN | \ |
5020 | B_BE_REUSE_FIFO_A_OVER_ERR_INT_EN | \ |
5021 | B_BE_REUSE_FIFO_A_UNDER_ERR_INT_EN | \ |
5022 | B_BE_REUSE_FIFO_B_OVER_ERR_INT_EN | \ |
5023 | B_BE_REUSE_FIFO_B_UNDER_ERR_INT_EN | \ |
5024 | B_BE_CR_DMA_PROCESS_ERR_INT_EN | \ |
5025 | B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \ |
5026 | B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN) |
5027 | |
5028 | #define R_BE_RX_STOP 0x8914 |
5029 | #define B_BE_CPU_RX_STOP BIT(17) |
5030 | #define B_BE_HOST_RX_STOP BIT(16) |
5031 | #define B_BE_CPU_RX_CH_STOP_MSK GENMASK(15, 8) |
5032 | #define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0) |
5033 | |
5034 | #define R_BE_DISP_FWD_WLAN_0 0x8938 |
5035 | #define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30) |
5036 | #define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28) |
5037 | #define B_BE_FWD_WLAN_CPU_TYPE_11_MASK GENMASK(27, 26) |
5038 | #define B_BE_FWD_WLAN_CPU_TYPE_10_MASK GENMASK(25, 24) |
5039 | #define B_BE_FWD_WLAN_CPU_TYPE_9_MASK GENMASK(23, 22) |
5040 | #define B_BE_FWD_WLAN_CPU_TYPE_8_MASK GENMASK(21, 20) |
5041 | #define B_BE_FWD_WLAN_CPU_TYPE_7_MASK GENMASK(19, 18) |
5042 | #define B_BE_FWD_WLAN_CPU_TYPE_6_MASK GENMASK(17, 16) |
5043 | #define B_BE_FWD_WLAN_CPU_TYPE_5_MASK GENMASK(15, 14) |
5044 | #define B_BE_FWD_WLAN_CPU_TYPE_4_MASK GENMASK(13, 12) |
5045 | #define B_BE_FWD_WLAN_CPU_TYPE_3_MASK GENMASK(11, 10) |
5046 | #define B_BE_FWD_WLAN_CPU_TYPE_2_MASK GENMASK(9, 8) |
5047 | #define B_BE_FWD_WLAN_CPU_TYPE_1_MASK GENMASK(7, 6) |
5048 | #define B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK GENMASK(5, 4) |
5049 | #define B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK GENMASK(3, 2) |
5050 | #define B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK GENMASK(1, 0) |
5051 | |
5052 | #define R_BE_WDE_PKTBUF_CFG 0x8C08 |
5053 | #define B_BE_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) |
5054 | #define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8) |
5055 | #define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0) |
5056 | |
5057 | #define R_BE_WDE_BUFMGN_CTL 0x8C10 |
5058 | #define B_BE_WDE_AVAL_UPD_REQ BIT(29) |
5059 | #define B_BE_WDE_AVAL_UPD_QTAID_MASK GENMASK(27, 24) |
5060 | #define B_BE_WDE_BUFMGN_FRZTMR_MODE BIT(0) |
5061 | |
5062 | #define R_BE_WDE_ERR_IMR 0x8C38 |
5063 | #define B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) |
5064 | #define B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28) |
5065 | #define B_BE_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) |
5066 | #define B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) |
5067 | #define B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) |
5068 | #define B_BE_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) |
5069 | #define B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(23) |
5070 | #define B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(22) |
5071 | #define B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(21) |
5072 | #define B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20) |
5073 | #define B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19) |
5074 | #define B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(18) |
5075 | #define B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(17) |
5076 | #define B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(16) |
5077 | #define B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13) |
5078 | #define B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12) |
5079 | #define B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11) |
5080 | #define B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10) |
5081 | #define B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(9) |
5082 | #define B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(8) |
5083 | #define B_BE_WDE_GETNPG_STRPG_ERR_INT_EN BIT(7) |
5084 | #define B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6) |
5085 | #define B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(5) |
5086 | #define B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4) |
5087 | #define B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3) |
5088 | #define B_BE_WDE_BUFREQ_SIZELMT_INT_EN BIT(2) |
5089 | #define B_BE_WDE_BUFREQ_SIZE0_INT_EN BIT(1) |
5090 | #define B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0) |
5091 | #define B_BE_WDE_ERR_IMR_CLR (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \ |
5092 | B_BE_WDE_BUFREQ_SIZE0_INT_EN | \ |
5093 | B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \ |
5094 | B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
5095 | B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
5096 | B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \ |
5097 | B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
5098 | B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \ |
5099 | B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \ |
5100 | B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ |
5101 | B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \ |
5102 | B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \ |
5103 | B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \ |
5104 | B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \ |
5105 | B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \ |
5106 | B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \ |
5107 | B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \ |
5108 | B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
5109 | B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
5110 | B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \ |
5111 | B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \ |
5112 | B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ |
5113 | B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \ |
5114 | B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \ |
5115 | B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \ |
5116 | B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \ |
5117 | B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \ |
5118 | B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN) |
5119 | #define B_BE_WDE_ERR_IMR_SET (B_BE_WDE_BUFREQ_QTAID_ERR_INT_EN | \ |
5120 | B_BE_WDE_BUFREQ_SIZE0_INT_EN | \ |
5121 | B_BE_WDE_BUFREQ_SIZELMT_INT_EN | \ |
5122 | B_BE_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
5123 | B_BE_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
5124 | B_BE_WDE_BUFRTN_SIZE_ERR_INT_EN | \ |
5125 | B_BE_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
5126 | B_BE_WDE_GETNPG_STRPG_ERR_INT_EN | \ |
5127 | B_BE_WDE_GETNPG_PGOFST_ERR_INT_EN | \ |
5128 | B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ |
5129 | B_BE_WDE_ERR_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \ |
5130 | B_BE_WDE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \ |
5131 | B_BE_WDE_BUFMGN_MRG_QTAID_ERR_INT_EN | \ |
5132 | B_BE_WDE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \ |
5133 | B_BE_WDE_QUE_CMDTYPE_ERR_INT_EN | \ |
5134 | B_BE_WDE_QUE_DSTQUEID_ERR_INT_EN | \ |
5135 | B_BE_WDE_QUE_SRCQUEID_ERR_INT_EN | \ |
5136 | B_BE_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
5137 | B_BE_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
5138 | B_BE_WDE_PREPKTLLT_AD_ERR_INT_EN | \ |
5139 | B_BE_WDE_NXTPKTLL_AD_ERR_INT_EN | \ |
5140 | B_BE_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ |
5141 | B_BE_WDE_DATCHN_ARBT_ERR_INT_EN | \ |
5142 | B_BE_WDE_DATCHN_NULLPG_ERR_INT_EN | \ |
5143 | B_BE_WDE_DATCHN_FRZTO_ERR_INT_EN | \ |
5144 | B_BE_WDE_DATCHN_RRDY_ERR_INT_EN | \ |
5145 | B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN | \ |
5146 | B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN) |
5147 | |
5148 | #define R_BE_WDE_QTA0_CFG 0x8C40 |
5149 | #define B_BE_WDE_Q0_MAX_SIZE_MASK GENMASK(27, 16) |
5150 | #define B_BE_WDE_Q0_MIN_SIZE_MASK GENMASK(11, 0) |
5151 | |
5152 | #define R_BE_WDE_QTA1_CFG 0x8C44 |
5153 | #define B_BE_WDE_Q1_MAX_SIZE_MASK GENMASK(27, 16) |
5154 | #define B_BE_WDE_Q1_MIN_SIZE_MASK GENMASK(11, 0) |
5155 | |
5156 | #define R_BE_WDE_QTA2_CFG 0x8C48 |
5157 | #define B_BE_WDE_Q2_MAX_SIZE_MASK GENMASK(27, 16) |
5158 | #define B_BE_WDE_Q2_MIN_SIZE_MASK GENMASK(11, 0) |
5159 | |
5160 | #define R_BE_WDE_QTA3_CFG 0x8C4C |
5161 | #define B_BE_WDE_Q3_MAX_SIZE_MASK GENMASK(27, 16) |
5162 | #define B_BE_WDE_Q3_MIN_SIZE_MASK GENMASK(11, 0) |
5163 | |
5164 | #define R_BE_WDE_QTA4_CFG 0x8C50 |
5165 | #define B_BE_WDE_Q4_MAX_SIZE_MASK GENMASK(27, 16) |
5166 | #define B_BE_WDE_Q4_MIN_SIZE_MASK GENMASK(11, 0) |
5167 | |
5168 | #define R_BE_WDE_ERR1_IMR 0x8CC0 |
5169 | #define B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN BIT(8) |
5170 | #define B_BE_WDE_ERR1_IMR_CLR B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN |
5171 | #define B_BE_WDE_ERR1_IMR_SET B_BE_WDE_QUEMGN_CMACACQ_DEQNTFY_INT_EN |
5172 | |
5173 | #define R_BE_PLE_PKTBUF_CFG 0x9008 |
5174 | #define B_BE_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16) |
5175 | #define B_BE_PLE_START_BOUND_MASK GENMASK(14, 8) |
5176 | #define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0) |
5177 | |
5178 | #define R_BE_PLE_BUFMGN_CTL 0x9010 |
5179 | #define B_BE_PLE_AVAL_UPD_REQ BIT(29) |
5180 | #define B_BE_PLE_AVAL_UPD_QTAID_MASK GENMASK(27, 24) |
5181 | #define B_BE_PLE_BUFMGN_FRZTMR_MODE BIT(0) |
5182 | |
5183 | #define R_BE_PLE_ERR_IMR 0x9038 |
5184 | #define B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) |
5185 | #define B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28) |
5186 | #define B_BE_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27) |
5187 | #define B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26) |
5188 | #define B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25) |
5189 | #define B_BE_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24) |
5190 | #define B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(23) |
5191 | #define B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(22) |
5192 | #define B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(21) |
5193 | #define B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(20) |
5194 | #define B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(19) |
5195 | #define B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(18) |
5196 | #define B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(17) |
5197 | #define B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(16) |
5198 | #define B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN BIT(13) |
5199 | #define B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN BIT(12) |
5200 | #define B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN BIT(11) |
5201 | #define B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN BIT(10) |
5202 | #define B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(9) |
5203 | #define B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(8) |
5204 | #define B_BE_PLE_GETNPG_STRPG_ERR_INT_EN BIT(7) |
5205 | #define B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(6) |
5206 | #define B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(5) |
5207 | #define B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(4) |
5208 | #define B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(3) |
5209 | #define B_BE_PLE_BUFREQ_SIZELMT_INT_EN BIT(2) |
5210 | #define B_BE_PLE_BUFREQ_SIZE0_INT_EN BIT(1) |
5211 | #define B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0) |
5212 | #define B_BE_PLE_ERR_IMR_CLR (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \ |
5213 | B_BE_PLE_BUFREQ_SIZE0_INT_EN | \ |
5214 | B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \ |
5215 | B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
5216 | B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
5217 | B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \ |
5218 | B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
5219 | B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \ |
5220 | B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \ |
5221 | B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ |
5222 | B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \ |
5223 | B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \ |
5224 | B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \ |
5225 | B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \ |
5226 | B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \ |
5227 | B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \ |
5228 | B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \ |
5229 | B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
5230 | B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
5231 | B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \ |
5232 | B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \ |
5233 | B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ |
5234 | B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \ |
5235 | B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \ |
5236 | B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \ |
5237 | B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \ |
5238 | B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \ |
5239 | B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN) |
5240 | #define B_BE_PLE_ERR_IMR_SET (B_BE_PLE_BUFREQ_QTAID_ERR_INT_EN | \ |
5241 | B_BE_PLE_BUFREQ_SIZE0_INT_EN | \ |
5242 | B_BE_PLE_BUFREQ_SIZELMT_INT_EN | \ |
5243 | B_BE_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ |
5244 | B_BE_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ |
5245 | B_BE_PLE_BUFRTN_SIZE_ERR_INT_EN | \ |
5246 | B_BE_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ |
5247 | B_BE_PLE_GETNPG_STRPG_ERR_INT_EN | \ |
5248 | B_BE_PLE_GETNPG_PGOFST_ERR_INT_EN | \ |
5249 | B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ |
5250 | B_BE_PLE_BUFMGN_MRG_STRPKTID_ERR_INT_EN | \ |
5251 | B_BE_PLE_BUFMGN_MRG_ENDPKTID_ERR_INT_EN | \ |
5252 | B_BE_PLE_BUFMGN_MRG_QTAID_ERR_INT_EN | \ |
5253 | B_BE_PLE_BUFMGN_MRG_SZLMT_ERR_INT_EN | \ |
5254 | B_BE_PLE_QUE_CMDTYPE_ERR_INT_EN | \ |
5255 | B_BE_PLE_QUE_DSTQUEID_ERR_INT_EN | \ |
5256 | B_BE_PLE_QUE_SRCQUEID_ERR_INT_EN | \ |
5257 | B_BE_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ |
5258 | B_BE_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ |
5259 | B_BE_PLE_PREPKTLLT_AD_ERR_INT_EN | \ |
5260 | B_BE_PLE_NXTPKTLL_AD_ERR_INT_EN | \ |
5261 | B_BE_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ |
5262 | B_BE_PLE_DATCHN_ARBT_ERR_INT_EN | \ |
5263 | B_BE_PLE_DATCHN_NULLPG_ERR_INT_EN | \ |
5264 | B_BE_PLE_DATCHN_FRZTO_ERR_INT_EN | \ |
5265 | B_BE_PLE_DATCHN_RRDY_ERR_INT_EN | \ |
5266 | B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN | \ |
5267 | B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN) |
5268 | |
5269 | #define R_BE_PLE_QTA0_CFG 0x9040 |
5270 | #define B_BE_PLE_Q0_MAX_SIZE_MASK GENMASK(27, 16) |
5271 | #define B_BE_PLE_Q0_MIN_SIZE_MASK GENMASK(11, 0) |
5272 | |
5273 | #define R_BE_PLE_QTA1_CFG 0x9044 |
5274 | #define B_BE_PLE_Q1_MAX_SIZE_MASK GENMASK(27, 16) |
5275 | #define B_BE_PLE_Q1_MIN_SIZE_MASK GENMASK(11, 0) |
5276 | |
5277 | #define R_BE_PLE_QTA2_CFG 0x9048 |
5278 | #define B_BE_PLE_Q2_MAX_SIZE_MASK GENMASK(27, 16) |
5279 | #define B_BE_PLE_Q2_MIN_SIZE_MASK GENMASK(11, 0) |
5280 | |
5281 | #define R_BE_PLE_QTA3_CFG 0x904C |
5282 | #define B_BE_PLE_Q3_MAX_SIZE_MASK GENMASK(27, 16) |
5283 | #define B_BE_PLE_Q3_MIN_SIZE_MASK GENMASK(11, 0) |
5284 | |
5285 | #define R_BE_PLE_QTA4_CFG 0x9050 |
5286 | #define B_BE_PLE_Q4_MAX_SIZE_MASK GENMASK(27, 16) |
5287 | #define B_BE_PLE_Q4_MIN_SIZE_MASK GENMASK(11, 0) |
5288 | |
5289 | #define R_BE_PLE_QTA5_CFG 0x9054 |
5290 | #define B_BE_PLE_Q5_MAX_SIZE_MASK GENMASK(27, 16) |
5291 | #define B_BE_PLE_Q5_MIN_SIZE_MASK GENMASK(11, 0) |
5292 | |
5293 | #define R_BE_PLE_QTA6_CFG 0x9058 |
5294 | #define B_BE_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16) |
5295 | #define B_BE_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0) |
5296 | |
5297 | #define R_BE_PLE_QTA7_CFG 0x905C |
5298 | #define B_BE_PLE_Q7_MAX_SIZE_MASK GENMASK(27, 16) |
5299 | #define B_BE_PLE_Q7_MIN_SIZE_MASK GENMASK(11, 0) |
5300 | |
5301 | #define R_BE_PLE_QTA8_CFG 0x9060 |
5302 | #define B_BE_PLE_Q8_MAX_SIZE_MASK GENMASK(27, 16) |
5303 | #define B_BE_PLE_Q8_MIN_SIZE_MASK GENMASK(11, 0) |
5304 | |
5305 | #define R_BE_PLE_QTA9_CFG 0x9064 |
5306 | #define B_BE_PLE_Q9_MAX_SIZE_MASK GENMASK(27, 16) |
5307 | #define B_BE_PLE_Q9_MIN_SIZE_MASK GENMASK(11, 0) |
5308 | |
5309 | #define R_BE_PLE_QTA10_CFG 0x9068 |
5310 | #define B_BE_PLE_Q10_MAX_SIZE_MASK GENMASK(27, 16) |
5311 | #define B_BE_PLE_Q10_MIN_SIZE_MASK GENMASK(11, 0) |
5312 | |
5313 | #define R_BE_PLE_QTA11_CFG 0x906C |
5314 | #define B_BE_PLE_Q11_MAX_SIZE_MASK GENMASK(27, 16) |
5315 | #define B_BE_PLE_Q11_MIN_SIZE_MASK GENMASK(11, 0) |
5316 | |
5317 | #define R_BE_PLE_QTA12_CFG 0x9070 |
5318 | #define B_BE_PLE_Q12_MAX_SIZE_MASK GENMASK(27, 16) |
5319 | #define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0) |
5320 | |
5321 | #define R_BE_PLE_ERRFLAG1_IMR 0x90C0 |
5322 | #define B_BE_PLE_SRCHPG_PGOFST_IMR BIT(26) |
5323 | #define B_BE_PLE_SRCHPG_STRPG_IMR BIT(25) |
5324 | #define B_BE_PLE_SRCHPG_FRZTO_IMR BIT(24) |
5325 | #define B_BE_PLE_ERRFLAG1_IMR_CLR (B_BE_PLE_SRCHPG_FRZTO_IMR | \ |
5326 | B_BE_PLE_SRCHPG_STRPG_IMR | \ |
5327 | B_BE_PLE_SRCHPG_PGOFST_IMR) |
5328 | #define B_BE_PLE_ERRFLAG1_IMR_SET (B_BE_PLE_SRCHPG_FRZTO_IMR | \ |
5329 | B_BE_PLE_SRCHPG_STRPG_IMR | \ |
5330 | B_BE_PLE_SRCHPG_PGOFST_IMR) |
5331 | |
5332 | #define R_BE_PLE_DBG_FUN_INTF_CTL 0x9110 |
5333 | #define B_BE_PLE_DFI_ACTIVE BIT(31) |
5334 | #define B_BE_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) |
5335 | #define B_BE_PLE_DFI_ADDR_MASK GENMASK(15, 0) |
5336 | |
5337 | #define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114 |
5338 | #define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0) |
5339 | |
5340 | #define R_BE_WDRLS_CFG 0x9408 |
5341 | #define B_BE_WDRLS_DIS_AGAC BIT(31) |
5342 | #define B_BE_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8) |
5343 | #define B_BE_RLSRPT_BUFREQ_TO_SEL_MASK GENMASK(7, 6) |
5344 | #define B_BE_WDRLS_MODE_MASK GENMASK(1, 0) |
5345 | |
5346 | #define R_BE_WDRLS_ERR_IMR 0x9430 |
5347 | #define B_BE_WDRLS_RPT3_FRZTO_ERR_INT_EN BIT(21) |
5348 | #define B_BE_WDRLS_RPT3_AGGNUM0_ERR_INT_EN BIT(20) |
5349 | #define B_BE_WDRLS_RPT2_FRZTO_ERR_INT_EN BIT(17) |
5350 | #define B_BE_WDRLS_RPT2_AGGNUM0_ERR_INT_EN BIT(16) |
5351 | #define B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) |
5352 | #define B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) |
5353 | #define B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) |
5354 | #define B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) |
5355 | #define B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) |
5356 | #define B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) |
5357 | #define B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) |
5358 | #define B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) |
5359 | #define B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) |
5360 | #define B_BE_WDRLS_ERR_IMR_CLR (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ |
5361 | B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ |
5362 | B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \ |
5363 | B_BE_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ |
5364 | B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ |
5365 | B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ |
5366 | B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ |
5367 | B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ |
5368 | B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN) |
5369 | #define B_BE_WDRLS_ERR_IMR_SET (B_BE_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ |
5370 | B_BE_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ |
5371 | B_BE_WDRLS_CTL_FRZTO_ERR_INT_EN | \ |
5372 | B_BE_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ |
5373 | B_BE_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ |
5374 | B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ |
5375 | B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ |
5376 | B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN) |
5377 | |
5378 | #define R_BE_RLSRPT0_CFG1 0x9444 |
5379 | #define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24) |
5380 | #define S_BE_WDRLS_FLTR_TXOK 1 |
5381 | #define S_BE_WDRLS_FLTR_RTYLMT 2 |
5382 | #define S_BE_WDRLS_FLTR_LIFTIM 4 |
5383 | #define S_BE_WDRLS_FLTR_MACID 8 |
5384 | #define B_BE_RLSRPT0_TO_MASK GENMASK(23, 16) |
5385 | #define B_BE_RLSRPT0_AGGNUM_MASK GENMASK(7, 0) |
5386 | |
5387 | #define R_BE_BBRPT_COM_ERR_IMR 0x9608 |
5388 | #define B_BE_BBRPT_COM_EVT01_ISR_EN BIT(1) |
5389 | #define B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN BIT(0) |
5390 | #define B_BE_BBRPT_COM_ERR_IMR_CLR (B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN | \ |
5391 | B_BE_BBRPT_COM_EVT01_ISR_EN) |
5392 | #define B_BE_BBRPT_COM_ERR_IMR_SET B_BE_BBRPT_COM_NULL_PLPKTID_ISR_EN |
5393 | |
5394 | #define R_BE_BBRPT_CHINFO_ERR_IMR 0x9628 |
5395 | #define B_BE_ERR_BB_ONETEN_INT_EN BIT(1) |
5396 | #define B_BE_ERR_GEN_FRZTO_INT_EN BIT(0) |
5397 | #define B_BE_BBRPT_CHINFO_ERR_IMR_CLR (B_BE_ERR_GEN_FRZTO_INT_EN | \ |
5398 | B_BE_ERR_BB_ONETEN_INT_EN) |
5399 | #define B_BE_BBRPT_CHINFO_ERR_IMR_SET (B_BE_ERR_GEN_FRZTO_INT_EN | \ |
5400 | B_BE_ERR_BB_ONETEN_INT_EN) |
5401 | |
5402 | #define R_BE_BBRPT_DFS_ERR_IMR 0x9638 |
5403 | #define B_BE_BBRPT_DFS_TO_ERR_INT_EN BIT(0) |
5404 | #define B_BE_BBRPT_DFS_ERR_IMR_CLR B_BE_BBRPT_DFS_TO_ERR_INT_EN |
5405 | #define B_BE_BBRPT_DFS_ERR_IMR_SET B_BE_BBRPT_DFS_TO_ERR_INT_EN |
5406 | |
5407 | #define R_BE_LA_ERRFLAG_IMR 0x9668 |
5408 | #define B_BE_LA_IMR_DATA_LOSS BIT(0) |
5409 | #define B_BE_LA_ERRFLAG_IMR_CLR B_BE_LA_IMR_DATA_LOSS |
5410 | #define B_BE_LA_ERRFLAG_IMR_SET B_BE_LA_IMR_DATA_LOSS |
5411 | |
5412 | #define R_BE_LA_ERRFLAG_ISR 0x966C |
5413 | #define B_BE_LA_ISR_DATA_LOSS BIT(0) |
5414 | |
5415 | #define R_BE_CH_INFO_DBGFLAG_IMR 0x9688 |
5416 | #define B_BE_BCHN_EVT01_ISR_EN BIT(29) |
5417 | #define B_BE_BCHN_REQTO_ISR_EN BIT(28) |
5418 | #define B_BE_CHIF_RXDATA_AFACT_ISR_EN BIT(11) |
5419 | #define B_BE_CHIF_RXDATA_BFACT_ISR_EN BIT(10) |
5420 | #define B_BE_CHIF_HDR_SEGLEN_ISR_EN BIT(9) |
5421 | #define B_BE_CHIF_HDR_INVLD_ISR_EN BIT(8) |
5422 | #define B_BE_CHIF_BBONL_BFACT_ISR_EN BIT(4) |
5423 | #define B_BE_CHIF_RPT_OVF_ISR_EN BIT(3) |
5424 | #define B_BE_DBG_CHIF_DATA_LOSS_ISR_EN BIT(2) |
5425 | #define B_BE_CHIF_DATA_WTOUT_ISR_EN BIT(1) |
5426 | #define B_BE_CHIF_RPT_WTOUT_ISR_EN BIT(0) |
5427 | #define B_BE_CH_INFO_DBGFLAG_IMR_CLR (B_BE_CHIF_RPT_WTOUT_ISR_EN | \ |
5428 | B_BE_CHIF_DATA_WTOUT_ISR_EN | \ |
5429 | B_BE_DBG_CHIF_DATA_LOSS_ISR_EN | \ |
5430 | B_BE_CHIF_RPT_OVF_ISR_EN | \ |
5431 | B_BE_CHIF_HDR_INVLD_ISR_EN | \ |
5432 | B_BE_CHIF_HDR_SEGLEN_ISR_EN | \ |
5433 | B_BE_CHIF_RXDATA_BFACT_ISR_EN | \ |
5434 | B_BE_CHIF_RXDATA_AFACT_ISR_EN) |
5435 | #define B_BE_CH_INFO_DBGFLAG_IMR_SET 0 |
5436 | |
5437 | #define R_BE_WD_BUF_REQ 0x9800 |
5438 | #define B_BE_WD_BUF_REQ_EXEC BIT(31) |
5439 | #define B_BE_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16) |
5440 | #define B_BE_WD_BUF_REQ_LEN_MASK GENMASK(15, 0) |
5441 | |
5442 | #define R_BE_WD_BUF_STATUS 0x9804 |
5443 | #define B_BE_WD_BUF_STAT_DONE BIT(31) |
5444 | #define B_BE_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0) |
5445 | |
5446 | #define R_BE_WD_CPUQ_OP_0 0x9810 |
5447 | #define B_BE_WD_CPUQ_OP_EXEC BIT(31) |
5448 | #define B_BE_WD_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) |
5449 | #define B_BE_WD_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) |
5450 | |
5451 | #define R_BE_WD_CPUQ_OP_1 0x9814 |
5452 | #define B_BE_WD_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12) |
5453 | #define B_BE_WD_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4) |
5454 | #define B_BE_WD_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0) |
5455 | |
5456 | #define R_BE_WD_CPUQ_OP_2 0x9818 |
5457 | #define B_BE_WD_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12) |
5458 | #define B_BE_WD_CPUQ_OP_DST_QID_MASK GENMASK(9, 4) |
5459 | #define B_BE_WD_CPUQ_OP_DST_PID_MASK GENMASK(2, 0) |
5460 | |
5461 | #define R_BE_WD_CPUQ_OP_3 0x981C |
5462 | #define B_BE_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) |
5463 | #define B_BE_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) |
5464 | |
5465 | #define R_BE_WD_CPUQ_OP_STATUS 0x9820 |
5466 | #define B_BE_WD_CPUQ_OP_STAT_DONE BIT(31) |
5467 | #define B_BE_WD_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16) |
5468 | #define B_BE_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0) |
5469 | |
5470 | #define R_BE_PL_BUF_REQ 0x9840 |
5471 | #define B_BE_PL_BUF_REQ_EXEC BIT(31) |
5472 | #define B_BE_PL_BUF_REQ_QUOTA_ID_MASK GENMASK(19, 16) |
5473 | #define B_BE_PL_BUF_REQ_LEN_MASK GENMASK(15, 0) |
5474 | |
5475 | #define R_BE_PL_BUF_STATUS 0x9844 |
5476 | #define B_BE_PL_BUF_STAT_DONE BIT(31) |
5477 | #define B_BE_PL_BUF_STAT_PKTID_MASK GENMASK(11, 0) |
5478 | |
5479 | #define R_BE_PL_CPUQ_OP_0 0x9850 |
5480 | #define B_BE_PL_CPUQ_OP_EXEC BIT(31) |
5481 | #define B_BE_PL_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) |
5482 | #define B_BE_PL_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) |
5483 | |
5484 | #define R_BE_PL_CPUQ_OP_1 0x9854 |
5485 | #define B_BE_PL_CPUQ_OP_SRC_MACID_MASK GENMASK(19, 12) |
5486 | #define B_BE_PL_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4) |
5487 | #define B_BE_PL_CPUQ_OP_SRC_PID_MASK GENMASK(2, 0) |
5488 | |
5489 | #define R_BE_PL_CPUQ_OP_2 0x9858 |
5490 | #define B_BE_PL_CPUQ_OP_DST_MACID_MASK GENMASK(19, 12) |
5491 | #define B_BE_PL_CPUQ_OP_DST_QID_MASK GENMASK(9, 4) |
5492 | #define B_BE_PL_CPUQ_OP_DST_PID_MASK GENMASK(2, 0) |
5493 | |
5494 | #define R_BE_PL_CPUQ_OP_3 0x985C |
5495 | #define B_BE_PL_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) |
5496 | #define B_BE_PL_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) |
5497 | |
5498 | #define R_BE_PL_CPUQ_OP_STATUS 0x9860 |
5499 | #define B_BE_PL_CPUQ_OP_STAT_DONE BIT(31) |
5500 | #define B_BE_PL_CPUQ_OP_PKTCNT_MASK GENMASK(27, 16) |
5501 | #define B_BE_PL_CPUQ_OP_PKTID_MASK GENMASK(11, 0) |
5502 | |
5503 | #define R_BE_CPUIO_ERR_IMR 0x9888 |
5504 | #define B_BE_PLEQUE_OP_ERR_INT_EN BIT(12) |
5505 | #define B_BE_PLEBUF_OP_ERR_INT_EN BIT(8) |
5506 | #define B_BE_WDEQUE_OP_ERR_INT_EN BIT(4) |
5507 | #define B_BE_WDEBUF_OP_ERR_INT_EN BIT(0) |
5508 | #define B_BE_CPUIO_ERR_IMR_CLR (B_BE_WDEBUF_OP_ERR_INT_EN | \ |
5509 | B_BE_WDEQUE_OP_ERR_INT_EN | \ |
5510 | B_BE_PLEBUF_OP_ERR_INT_EN | \ |
5511 | B_BE_PLEQUE_OP_ERR_INT_EN) |
5512 | #define B_BE_CPUIO_ERR_IMR_SET (B_BE_WDEBUF_OP_ERR_INT_EN | \ |
5513 | B_BE_WDEQUE_OP_ERR_INT_EN | \ |
5514 | B_BE_PLEBUF_OP_ERR_INT_EN | \ |
5515 | B_BE_PLEQUE_OP_ERR_INT_EN) |
5516 | |
5517 | #define R_BE_PKTIN_ERR_IMR 0x9A20 |
5518 | #define B_BE_SW_MERGE_ERR_INT_EN BIT(1) |
5519 | #define B_BE_GET_NULL_PKTID_ERR_INT_EN BIT(0) |
5520 | #define B_BE_PKTIN_ERR_IMR_CLR (B_BE_SW_MERGE_ERR_INT_EN | \ |
5521 | B_BE_GET_NULL_PKTID_ERR_INT_EN) |
5522 | #define B_BE_PKTIN_ERR_IMR_SET (B_BE_SW_MERGE_ERR_INT_EN | \ |
5523 | B_BE_GET_NULL_PKTID_ERR_INT_EN) |
5524 | |
5525 | #define R_BE_HDR_SHCUT_SETTING 0x9B00 |
5526 | #define B_BE_TX_ADDR_MLD_TO_LIK BIT(4) |
5527 | #define B_BE_TX_HW_SEC_HDR_EN BIT(3) |
5528 | #define B_BE_TX_MAC_MPDU_PROC_EN BIT(2) |
5529 | #define B_BE_TX_HW_ACK_POLICY_EN BIT(1) |
5530 | #define B_BE_TX_HW_SEQ_EN BIT(0) |
5531 | |
5532 | #define R_BE_MPDU_TX_ERR_IMR 0x9BF4 |
5533 | #define B_BE_TX_TIMEOUT_ERR_EN BIT(0) |
5534 | #define B_BE_MPDU_TX_ERR_IMR_CLR B_BE_TX_TIMEOUT_ERR_EN |
5535 | #define B_BE_MPDU_TX_ERR_IMR_SET 0 |
5536 | |
5537 | #define R_BE_MPDU_PROC 0x9C00 |
5538 | #define B_BE_PORT_SEL BIT(29) |
5539 | #define B_BE_WPKT_WLANCPU_QSEL_MASK GENMASK(28, 27) |
5540 | #define B_BE_WPKT_DATACPU_QSEL_MASK GENMASK(26, 25) |
5541 | #define B_BE_WPKT_FW_RLS BIT(24) |
5542 | #define B_BE_FWD_RPKT_MASK GENMASK(23, 16) |
5543 | #define B_BE_FWD_WPKT_MASK GENMASK(15, 8) |
5544 | #define B_BE_RXFWD_PRIO_MASK GENMASK(5, 4) |
5545 | #define B_BE_RXFWD_EN BIT(3) |
5546 | #define B_BE_DROP_NONDMA_PPDU BIT(2) |
5547 | #define B_BE_APPEND_FCS BIT(0) |
5548 | |
5549 | #define R_BE_FWD_ERR 0x9C10 |
5550 | #define R_BE_FWD_ACTN0 0x9C14 |
5551 | #define R_BE_FWD_ACTN1 0x9C18 |
5552 | #define R_BE_FWD_ACTN2 0x9C1C |
5553 | #define R_BE_FWD_TF0 0x9C20 |
5554 | #define R_BE_FWD_TF1 0x9C24 |
5555 | |
5556 | #define R_BE_HW_PPDU_STATUS 0x9C30 |
5557 | #define B_BE_FWD_RPKTTYPE_MASK GENMASK(31, 26) |
5558 | #define B_BE_FWD_PPDU_PRTID_MASK GENMASK(25, 23) |
5559 | #define B_BE_FWD_PPDU_FW_RLS BIT(22) |
5560 | #define B_BE_FWD_PPDU_QUEID_MASK GENMASK(21, 16) |
5561 | #define B_BE_FWD_OTHER_RPKT_MASK GENMASK(15, 8) |
5562 | #define B_BE_FWD_PPDU_STAT_MASK GENMASK(7, 0) |
5563 | |
5564 | #define R_BE_CUT_AMSDU_CTRL 0x9C94 |
5565 | #define B_BE_EN_CUT_AMSDU BIT(31) |
5566 | #define B_BE_CUT_AMSDU_CHKLEN_EN BIT(30) |
5567 | #define B_BE_CA_CHK_ADDRCAM_EN BIT(29) |
5568 | #define B_BE_MPDU_CUT_CTRL_EN BIT(24) |
5569 | #define B_BE_CUT_AMSDU_CHKLEN_L_TH_MASK GENMASK(23, 16) |
5570 | #define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0) |
5571 | |
5572 | #define R_BE_WOW_CTRL 0x9CB8 |
5573 | #define B_BE_WOW_HCI BIT(5) |
5574 | #define B_BE_WOW_DROP BIT(2) |
5575 | #define B_BE_WOW_WOWEN BIT(1) |
5576 | #define B_BE_WOW_FORCE_WAKEUP BIT(0) |
5577 | |
5578 | #define R_BE_RX_HDRTRNS 0x9CC0 |
5579 | #define B_BE_RX_MGN_MLD_ADDR_EN BIT(6) |
5580 | #define B_BE_HDR_INFO_MASK GENMASK(5, 4) |
5581 | #define B_BE_HC_ADDR_HIT_EN BIT(3) |
5582 | #define B_BE_RX_ADDR_LINK_TO_MLO BIT(2) |
5583 | #define B_BE_HDR_CNV BIT(1) |
5584 | #define B_BE_RX_HDR_CNV_EN BIT(0) |
5585 | #define TRXCFG_MPDU_PROC_RX_HDR_CONV 0x00000000 |
5586 | |
5587 | #define R_BE_MPDU_RX_ERR_IMR 0x9CF4 |
5588 | #define B_BE_LEN_ERR_IMR BIT(3) |
5589 | #define B_BE_TIMEOUT_ERR_IMR BIT(1) |
5590 | #define B_BE_MPDU_RX_ERR_IMR_CLR B_BE_TIMEOUT_ERR_IMR |
5591 | #define B_BE_MPDU_RX_ERR_IMR_SET 0 |
5592 | |
5593 | #define R_BE_SEC_ENG_CTRL 0x9D00 |
5594 | #define B_BE_SEC_ENG_EN BIT(31) |
5595 | #define B_BE_CCMP_SPP_MIC BIT(30) |
5596 | #define B_BE_CCMP_SPP_CTR BIT(29) |
5597 | #define B_BE_SEC_CAM_ACC BIT(28) |
5598 | #define B_BE_WMAC_SEC_PN_SEL_MASK GENMASK(27, 26) |
5599 | #define B_BE_WMAC_SEC_MASKIV BIT(25) |
5600 | #define B_BE_WAPI_SPEC BIT(24) |
5601 | #define B_BE_REVERT_TA_RA_MLD_EN BIT(23) |
5602 | #define B_BE_SEC_DBG_SEL_MASK GENMASK(19, 16) |
5603 | #define B_BE_CAM_FORCE_CLK BIT(15) |
5604 | #define B_BE_SEC_FORCE_CLK BIT(14) |
5605 | #define B_BE_SEC_RX_SHORT_ADD_ICVERR BIT(13) |
5606 | #define B_BE_SRAM_IO_PROT BIT(12) |
5607 | #define B_BE_SEC_PRE_ENQUE_TX BIT(11) |
5608 | #define B_BE_CLK_EN_CGCMP BIT(10) |
5609 | #define B_BE_CLK_EN_WAPI BIT(9) |
5610 | #define B_BE_CLK_EN_WEP_TKIP BIT(8) |
5611 | #define B_BE_BMC_MGNT_DEC BIT(5) |
5612 | #define B_BE_UC_MGNT_DEC BIT(4) |
5613 | #define B_BE_MC_DEC BIT(3) |
5614 | #define B_BE_BC_DEC BIT(2) |
5615 | #define B_BE_SEC_RX_DEC BIT(1) |
5616 | #define B_BE_SEC_TX_ENC BIT(0) |
5617 | |
5618 | #define R_BE_SEC_MPDU_PROC 0x9D04 |
5619 | #define B_BE_DBG_ENGINE_SEL BIT(8) |
5620 | #define B_BE_STOP_RX_PKT_HANDLE BIT(7) |
5621 | #define B_BE_STOP_TX_PKT_HANDLE BIT(6) |
5622 | #define B_BE_QUEUE_FOWARD_SEL BIT(5) |
5623 | #define B_BE_RESP1_PROTECT BIT(4) |
5624 | #define B_BE_RESP0_PROTECT BIT(3) |
5625 | #define B_BE_TX_ACTIVE_PROTECT BIT(2) |
5626 | #define B_BE_APPEND_ICV BIT(1) |
5627 | #define B_BE_APPEND_MIC BIT(0) |
5628 | |
5629 | #define R_BE_SEC_CAM_ACCESS 0x9D10 |
5630 | #define B_BE_SEC_TIME_OUT_MASK GENMASK(31, 16) |
5631 | #define B_BE_SEC_CAM_POLL BIT(15) |
5632 | #define B_BE_SEC_CAM_RW BIT(14) |
5633 | #define B_BE_SEC_CAM_ACC_FAIL BIT(13) |
5634 | #define B_BE_SEC_CAM_OFFSET_MASK GENMASK(10, 0) |
5635 | |
5636 | #define R_BE_SEC_CAM_RDATA 0x9D14 |
5637 | #define B_BE_SEC_CAM_RDATA_MASK GENMASK(31, 0) |
5638 | |
5639 | #define R_BE_SEC_DEBUG2 0x9D28 |
5640 | #define B_BE_DBG_READ_MASK GENMASK(31, 0) |
5641 | |
5642 | #define R_BE_SEC_ERROR_IMR 0x9D2C |
5643 | #define B_BE_QUEUE_OPERATION_HANG_IMR BIT(4) |
5644 | #define B_BE_SEC1_RX_HANG_IMR BIT(3) |
5645 | #define B_BE_SEC1_TX_HANG_IMR BIT(2) |
5646 | #define B_BE_RX_HANG_IMR BIT(1) |
5647 | #define B_BE_TX_HANG_IMR BIT(0) |
5648 | #define B_BE_SEC_ERROR_IMR_CLR (B_BE_TX_HANG_IMR | \ |
5649 | B_BE_RX_HANG_IMR | \ |
5650 | B_BE_SEC1_TX_HANG_IMR | \ |
5651 | B_BE_SEC1_RX_HANG_IMR | \ |
5652 | B_BE_QUEUE_OPERATION_HANG_IMR) |
5653 | #define B_BE_SEC_ERROR_IMR_SET (B_BE_TX_HANG_IMR | \ |
5654 | B_BE_RX_HANG_IMR | \ |
5655 | B_BE_SEC1_TX_HANG_IMR | \ |
5656 | B_BE_SEC1_RX_HANG_IMR | \ |
5657 | B_BE_QUEUE_OPERATION_HANG_IMR) |
5658 | |
5659 | #define R_BE_SEC_ERROR_FLAG 0x9D30 |
5660 | #define B_BE_TXD_DIFF_KEYCAM_TYPE_ERROR BIT(5) |
5661 | #define B_BE_QUEUE_OPERATION_HANG_ERROR BIT(4) |
5662 | #define B_BE_SEC1_RX_HANG_ERROR BIT(3) |
5663 | #define B_BE_SEC1_TX_HANG_ERROR BIT(2) |
5664 | #define B_BE_RX_HANG_ERROR BIT(1) |
5665 | #define B_BE_TX_HANG_ERROR BIT(0) |
5666 | |
5667 | #define R_BE_TXPKTCTL_MPDUINFO_CFG 0x9F10 |
5668 | #define B_BE_MPDUINFO_FEN BIT(31) |
5669 | #define B_BE_MPDUINFO_PKTID_MASK GENMASK(27, 16) |
5670 | #define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0) |
5671 | #define MPDU_INFO_B1_OFST 18 |
5672 | |
5673 | #define R_BE_TXPKTCTL_B0_PRELD_CFG0 0x9F48 |
5674 | #define B_BE_B0_PRELD_FEN BIT(31) |
5675 | #define B_BE_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16) |
5676 | #define B_BE_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) |
5677 | #define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) |
5678 | |
5679 | #define R_BE_TXPKTCTL_B0_PRELD_CFG1 0x9F4C |
5680 | #define B_BE_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) |
5681 | #define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) |
5682 | |
5683 | #define R_BE_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78 |
5684 | #define B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN BIT(25) |
5685 | #define B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD BIT(24) |
5686 | #define B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(17) |
5687 | #define B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(16) |
5688 | #define B_BE_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11) |
5689 | #define B_BE_B0_IMR_ERR_CMDPSR_FRZTO BIT(10) |
5690 | #define B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9) |
5691 | #define B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8) |
5692 | #define B_BE_B0_IMR_ERR_USRCTL_NOINIT BIT(1) |
5693 | #define B_BE_B0_IMR_ERR_USRCTL_REINIT BIT(0) |
5694 | #define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR (B_BE_B0_IMR_ERR_USRCTL_REINIT | \ |
5695 | B_BE_B0_IMR_ERR_USRCTL_NOINIT | \ |
5696 | B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD | \ |
5697 | B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN | \ |
5698 | B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \ |
5699 | B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \ |
5700 | B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \ |
5701 | B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \ |
5702 | B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ |
5703 | B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG) |
5704 | #define B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET (B_BE_B0_IMR_ERR_USRCTL_REINIT | \ |
5705 | B_BE_B0_IMR_ERR_USRCTL_NOINIT | \ |
5706 | B_BE_B0_IMR_ERR_CMDPSR_1STCMDERR | \ |
5707 | B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE | \ |
5708 | B_BE_B0_IMR_ERR_CMDPSR_FRZTO | \ |
5709 | B_BE_B0_IMR_ERR_CMDPSR_TBLSZ | \ |
5710 | B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ |
5711 | B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG) |
5712 | |
5713 | #define R_BE_TXPKTCTL_B1_PRELD_CFG0 0x9F88 |
5714 | #define B_BE_B1_PRELD_FEN BIT(31) |
5715 | #define B_BE_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16) |
5716 | #define B_BE_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) |
5717 | #define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) |
5718 | |
5719 | #define R_BE_TXPKTCTL_B1_PRELD_CFG1 0x9F8C |
5720 | #define B_BE_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) |
5721 | #define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) |
5722 | |
5723 | #define R_BE_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8 |
5724 | #define B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN BIT(25) |
5725 | #define B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD BIT(24) |
5726 | #define B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(17) |
5727 | #define B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(16) |
5728 | #define B_BE_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11) |
5729 | #define B_BE_B1_IMR_ERR_CMDPSR_FRZTO BIT(10) |
5730 | #define B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9) |
5731 | #define B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8) |
5732 | #define B_BE_B1_IMR_ERR_USRCTL_NOINIT BIT(1) |
5733 | #define B_BE_B1_IMR_ERR_USRCTL_REINIT BIT(0) |
5734 | #define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR (B_BE_B1_IMR_ERR_USRCTL_REINIT | \ |
5735 | B_BE_B1_IMR_ERR_USRCTL_NOINIT | \ |
5736 | B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD | \ |
5737 | B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN | \ |
5738 | B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \ |
5739 | B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \ |
5740 | B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \ |
5741 | B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \ |
5742 | B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ |
5743 | B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG) |
5744 | #define B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET (B_BE_B1_IMR_ERR_USRCTL_REINIT | \ |
5745 | B_BE_B1_IMR_ERR_USRCTL_NOINIT | \ |
5746 | B_BE_B1_IMR_ERR_CMDPSR_1STCMDERR | \ |
5747 | B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE | \ |
5748 | B_BE_B1_IMR_ERR_CMDPSR_FRZTO | \ |
5749 | B_BE_B1_IMR_ERR_CMDPSR_TBLSZ | \ |
5750 | B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ |
5751 | B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG) |
5752 | |
5753 | #define R_BE_MLO_INIT_CTL 0xA114 |
5754 | #define B_BE_MLO_TABLE_INIT_DONE BIT(31) |
5755 | #define B_BE_MLO_TABLE_CLR_DONE BIT(30) |
5756 | #define B_BE_MLO_TABLE_REINIT BIT(23) |
5757 | #define B_BE_MLO_TABLE_HW_FLAG_CLR BIT(22) |
5758 | |
5759 | #define R_BE_MLO_ERR_IDCT_IMR 0xA128 |
5760 | #define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31) |
5761 | #define B_BE_MLO_ERR_IDCT_IMR_1 BIT(30) |
5762 | #define B_BE_MLO_ERR_IDCT_IMR_2 BIT(29) |
5763 | #define B_BE_MLO_ERR_IDCT_IMR_3 BIT(28) |
5764 | #define B_BE_MLO_ERR_IDCT_IMR_CLR (B_BE_MLO_ERR_IDCT_IMR_2 | \ |
5765 | B_BE_MLO_ERR_IDCT_IMR_1 | \ |
5766 | B_BE_MLO_ERR_IDCT_IMR_0) |
5767 | #define B_BE_MLO_ERR_IDCT_IMR_SET (B_BE_MLO_ERR_IDCT_IMR_2 | \ |
5768 | B_BE_MLO_ERR_IDCT_IMR_1 | \ |
5769 | B_BE_MLO_ERR_IDCT_IMR_0) |
5770 | |
5771 | #define R_BE_MLO_ERR_IDCT_ISR 0xA12C |
5772 | #define B_BE_MLO_ISR_IDCT_0 BIT(31) |
5773 | #define B_BE_MLO_ISR_IDCT_1 BIT(30) |
5774 | #define B_BE_MLO_ISR_IDCT_2 BIT(29) |
5775 | #define B_BE_MLO_ISR_IDCT_3 BIT(28) |
5776 | |
5777 | #define R_BE_PLRLS_ERR_IMR 0xA218 |
5778 | #define B_BE_PLRLS_CTL_FRZTO_IMR BIT(0) |
5779 | #define B_BE_PLRLS_ERR_IMR_CLR B_BE_PLRLS_CTL_FRZTO_IMR |
5780 | #define B_BE_PLRLS_ERR_IMR_SET B_BE_PLRLS_CTL_FRZTO_IMR |
5781 | |
5782 | #define R_BE_PLRLS_ERR_ISR 0xA21C |
5783 | #define B_BE_PLRLS_CTL_EVT03_ISR BIT(3) |
5784 | #define B_BE_PLRLS_CTL_EVT02_ISR BIT(2) |
5785 | #define B_BE_PLRLS_CTL_EVT01_ISR BIT(1) |
5786 | #define B_BE_PLRLS_CTL_FRZTO_ISR BIT(0) |
5787 | |
5788 | #define R_BE_SS_CTRL 0xA310 |
5789 | #define B_BE_SS_INIT_DONE BIT(31) |
5790 | #define B_BE_WDE_STA_DIS BIT(30) |
5791 | #define B_BE_WARM_INIT BIT(29) |
5792 | #define B_BE_BAND_TRIG_EN BIT(28) |
5793 | #define B_BE_RMAC_REQ_DIS BIT(27) |
5794 | #define B_BE_DLYTX_SEL_MASK GENMASK(25, 24) |
5795 | #define B_BE_WMM3_SWITCH_MASK GENMASK(23, 22) |
5796 | #define B_BE_WMM2_SWITCH_MASK GENMASK(21, 20) |
5797 | #define B_BE_WMM1_SWITCH_MASK GENMASK(19, 18) |
5798 | #define B_BE_WMM0_SWITCH_MASK GENMASK(17, 16) |
5799 | #define B_BE_STA_OPTION_CR BIT(15) |
5800 | #define B_BE_EMLSR_STA_EMPTY_EN BIT(11) |
5801 | #define B_BE_MLO_HW_CHGLINK_EN BIT(10) |
5802 | #define B_BE_BAND1_TRIG_EN BIT(9) |
5803 | #define B_BE_RMAC1_REQ_DIS BIT(8) |
5804 | #define B_BE_MRT_SRAM_EN BIT(7) |
5805 | #define B_BE_MRT_INIT_EN BIT(6) |
5806 | #define B_BE_AVG_LENG_EN BIT(5) |
5807 | #define B_BE_AVG_INIT_EN BIT(4) |
5808 | #define B_BE_LENG_INIT_EN BIT(2) |
5809 | #define B_BE_PMPA_INIT_EN BIT(1) |
5810 | #define B_BE_SS_EN BIT(0) |
5811 | |
5812 | #define R_BE_INTERRUPT_MASK_REG 0xA3F0 |
5813 | #define B_BE_PLE_B_PKTID_ERR_IMR BIT(2) |
5814 | #define B_BE_RPT_TIMEOUT_IMR BIT(1) |
5815 | #define B_BE_SEARCH_TIMEOUT_IMR BIT(0) |
5816 | #define B_BE_INTERRUPT_MASK_REG_CLR (B_BE_SEARCH_TIMEOUT_IMR | \ |
5817 | B_BE_RPT_TIMEOUT_IMR | \ |
5818 | B_BE_PLE_B_PKTID_ERR_IMR) |
5819 | #define B_BE_INTERRUPT_MASK_REG_SET (B_BE_SEARCH_TIMEOUT_IMR | \ |
5820 | B_BE_RPT_TIMEOUT_IMR | \ |
5821 | B_BE_PLE_B_PKTID_ERR_IMR) |
5822 | |
5823 | #define R_BE_INTERRUPT_STS_REG 0xA3F4 |
5824 | #define B_BE_PLE_B_PKTID_ERR_ISR BIT(2) |
5825 | #define B_BE_RPT_TIMEOUT_ISR BIT(1) |
5826 | #define B_BE_SEARCH_TIMEOUT_ISR BIT(0) |
5827 | |
5828 | #define R_BE_HAXI_INIT_CFG1 0xB000 |
5829 | #define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28) |
5830 | #define B_BE_CFG_WD_PERIOD_ACTIVE_MASK GENMASK(27, 24) |
5831 | #define B_BE_EN_RO_IDX_UPD_BY_IO BIT(19) |
5832 | #define B_BE_RST_KEEP_REG BIT(18) |
5833 | #define B_BE_FLUSH_HAXI_MST BIT(17) |
5834 | #define B_BE_SET_BDRAM_BOUND BIT(16) |
5835 | #define B_BE_ADDRINFO_ALIGN4B_EN BIT(15) |
5836 | #define B_BE_RXBD_DONE_MODE_MASK GENMASK(14, 13) |
5837 | #define B_BE_RXQ_RXBD_MODE_MASK GENMASK(12, 11) |
5838 | #define B_BE_DMA_MODE_MASK GENMASK(10, 8) |
5839 | #define S_BE_DMA_MOD_PCIE_NO_DATA_CPU 0x0 |
5840 | #define S_BE_DMA_MOD_PCIE_DATA_CPU 0x1 |
5841 | #define S_BE_DMA_MOD_USB 0x4 |
5842 | #define S_BE_DMA_MOD_SDIO 0x6 |
5843 | #define B_BE_STOP_AXI_MST BIT(7) |
5844 | #define B_BE_RXDMA_ALIGN64B_EN BIT(6) |
5845 | #define B_BE_RXDMA_EN BIT(5) |
5846 | #define B_BE_TXDMA_EN BIT(4) |
5847 | #define B_BE_MAX_RXDMA_MASK GENMASK(3, 2) |
5848 | #define B_BE_MAX_TXDMA_MASK GENMASK(1, 0) |
5849 | |
5850 | #define R_BE_HAXI_DMA_STOP1 0xB010 |
5851 | #define B_BE_STOP_WPDMA BIT(31) |
5852 | #define B_BE_STOP_CH14 BIT(14) |
5853 | #define B_BE_STOP_CH13 BIT(13) |
5854 | #define B_BE_STOP_CH12 BIT(12) |
5855 | #define B_BE_STOP_CH11 BIT(11) |
5856 | #define B_BE_STOP_CH10 BIT(10) |
5857 | #define B_BE_STOP_CH9 BIT(9) |
5858 | #define B_BE_STOP_CH8 BIT(8) |
5859 | #define B_BE_STOP_CH7 BIT(7) |
5860 | #define B_BE_STOP_CH6 BIT(6) |
5861 | #define B_BE_STOP_CH5 BIT(5) |
5862 | #define B_BE_STOP_CH4 BIT(4) |
5863 | #define B_BE_STOP_CH3 BIT(3) |
5864 | #define B_BE_STOP_CH2 BIT(2) |
5865 | #define B_BE_STOP_CH1 BIT(1) |
5866 | #define B_BE_STOP_CH0 BIT(0) |
5867 | |
5868 | #define R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1 0xB02C |
5869 | #define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0) |
5870 | |
5871 | #define R_BE_HAXI_IDCT_MSK 0xB0B8 |
5872 | #define B_BE_HAXI_RRESP_ERR_IDCT_MSK BIT(7) |
5873 | #define B_BE_HAXI_BRESP_ERR_IDCT_MSK BIT(6) |
5874 | #define B_BE_RXDMA_ERR_FLAG_IDCT_MSK BIT(5) |
5875 | #define B_BE_SET_FC_ERROR_FLAG_IDCT_MSK BIT(4) |
5876 | #define B_BE_TXBD_LEN0_ERR_IDCT_MSK BIT(3) |
5877 | #define B_BE_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2) |
5878 | #define B_BE_RXMDA_STUCK_IDCT_MSK BIT(1) |
5879 | #define B_BE_TXMDA_STUCK_IDCT_MSK BIT(0) |
5880 | #define B_BE_HAXI_IDCT_MSK_CLR (B_BE_TXMDA_STUCK_IDCT_MSK | \ |
5881 | B_BE_RXMDA_STUCK_IDCT_MSK | \ |
5882 | B_BE_TXBD_LEN0_ERR_IDCT_MSK | \ |
5883 | B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \ |
5884 | B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \ |
5885 | B_BE_HAXI_BRESP_ERR_IDCT_MSK | \ |
5886 | B_BE_HAXI_RRESP_ERR_IDCT_MSK) |
5887 | #define B_BE_HAXI_IDCT_MSK_SET (B_BE_TXMDA_STUCK_IDCT_MSK | \ |
5888 | B_BE_RXMDA_STUCK_IDCT_MSK | \ |
5889 | B_BE_TXBD_LEN0_ERR_IDCT_MSK | \ |
5890 | B_BE_SET_FC_ERROR_FLAG_IDCT_MSK | \ |
5891 | B_BE_RXDMA_ERR_FLAG_IDCT_MSK | \ |
5892 | B_BE_HAXI_BRESP_ERR_IDCT_MSK | \ |
5893 | B_BE_HAXI_RRESP_ERR_IDCT_MSK) |
5894 | |
5895 | #define R_BE_HAXI_IDCT 0xB0BC |
5896 | #define B_BE_HAXI_RRESP_ERR_IDCT BIT(7) |
5897 | #define B_BE_HAXI_BRESP_ERR_IDCT BIT(6) |
5898 | #define B_BE_RXDMA_ERR_FLAG_IDCT BIT(5) |
5899 | #define B_BE_SET_FC_ERROR_FLAG_IDCT BIT(4) |
5900 | #define B_BE__TXBD_LEN0_ERR_IDCT BIT(3) |
5901 | #define B_BE__TXBD_4KBOUND_ERR_IDCT BIT(2) |
5902 | #define B_BE_RXMDA_STUCK_IDCT BIT(1) |
5903 | #define B_BE_TXMDA_STUCK_IDCT BIT(0) |
5904 | |
5905 | #define R_BE_HCI_FC_CTRL 0xB700 |
5906 | #define B_BE_WD_PAGE_MODE_MASK GENMASK(17, 16) |
5907 | #define B_BE_HCI_FC_CH14_FULL_COND_MASK GENMASK(15, 14) |
5908 | #define B_BE_HCI_FC_TWD_FULL_COND_MASK GENMASK(13, 12) |
5909 | #define B_BE_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10) |
5910 | #define B_BE_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8) |
5911 | #define B_BE_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6) |
5912 | #define B_BE_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4) |
5913 | #define B_BE_HCI_FC_CH12_EN BIT(3) |
5914 | #define B_BE_HCI_FC_MODE_MASK GENMASK(2, 1) |
5915 | #define B_BE_HCI_FC_EN BIT(0) |
5916 | |
5917 | #define R_BE_CH_PAGE_CTRL 0xB704 |
5918 | #define B_BE_PREC_PAGE_CH12_V1_MASK GENMASK(21, 16) |
5919 | #define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0) |
5920 | |
5921 | #define R_BE_CH0_PAGE_CTRL 0xB718 |
5922 | #define B_BE_CH0_GRP BIT(31) |
5923 | #define B_BE_CH0_MAX_PG_MASK GENMASK(28, 16) |
5924 | #define B_BE_CH0_MIN_PG_MASK GENMASK(12, 0) |
5925 | |
5926 | #define R_BE_CH0_PAGE_INFO 0xB750 |
5927 | #define B_BE_CH0_AVAL_PG_MASK GENMASK(28, 16) |
5928 | #define B_BE_CH0_USE_PG_MASK GENMASK(12, 0) |
5929 | |
5930 | #define R_BE_PUB_PAGE_INFO3 0xB78C |
5931 | #define B_BE_G1_AVAL_PG_MASK GENMASK(28, 16) |
5932 | #define B_BE_G0_AVAL_PG_MASK GENMASK(12, 0) |
5933 | |
5934 | #define R_BE_PUB_PAGE_CTRL1 0xB790 |
5935 | #define B_BE_PUBPG_G1_MASK GENMASK(28, 16) |
5936 | #define B_BE_PUBPG_G0_MASK GENMASK(12, 0) |
5937 | |
5938 | #define R_BE_PUB_PAGE_CTRL2 0xB794 |
5939 | #define B_BE_PUBPG_ALL_MASK GENMASK(12, 0) |
5940 | |
5941 | #define R_BE_PUB_PAGE_INFO1 0xB79C |
5942 | #define B_BE_G1_USE_PG_MASK GENMASK(28, 16) |
5943 | #define B_BE_G0_USE_PG_MASK GENMASK(12, 0) |
5944 | |
5945 | #define R_BE_PUB_PAGE_INFO2 0xB7A0 |
5946 | #define B_BE_PUB_AVAL_PG_MASK GENMASK(12, 0) |
5947 | |
5948 | #define R_BE_WP_PAGE_CTRL1 0xB7A4 |
5949 | #define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16) |
5950 | #define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0) |
5951 | |
5952 | #define R_BE_WP_PAGE_CTRL2 0xB7A8 |
5953 | #define B_BE_WP_THRD_MASK GENMASK(12, 0) |
5954 | |
5955 | #define R_BE_WP_PAGE_INFO1 0xB7AC |
5956 | #define B_BE_WP_AVAL_PG_MASK GENMASK(28, 16) |
5957 | |
5958 | #define R_BE_CMAC_SHARE_FUNC_EN 0x0E000 |
5959 | #define B_BE_CMAC_SHARE_CRPRT BIT(31) |
5960 | #define B_BE_CMAC_SHARE_EN BIT(30) |
5961 | #define B_BE_FORCE_BTCOEX_REG_GCKEN BIT(24) |
5962 | #define B_BE_FORCE_CMAC_SHARE_COMMON_REG_GCKEN BIT(16) |
5963 | #define B_BE_FORCE_CMAC_SHARE_REG_GCKEN BIT(15) |
5964 | #define B_BE_RESPBA_EN BIT(2) |
5965 | #define B_BE_ADDRSRCH_EN BIT(1) |
5966 | #define B_BE_BTCOEX_EN BIT(0) |
5967 | |
5968 | #define R_BE_CMAC_SHARE_ACQCHK_CFG_0 0x0E010 |
5969 | #define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24) |
5970 | #define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4) |
5971 | #define B_BE_MACID_ACQ_GRP1_CLR_P BIT(3) |
5972 | #define B_BE_MACID_ACQ_GRP0_CLR_P BIT(2) |
5973 | #define B_BE_R_MACID_ACQ_CHK_EN BIT(0) |
5974 | |
5975 | #define R_BE_BT_BREAK_TABLE 0x0E344 |
5976 | |
5977 | #define R_BE_GNT_SW_CTRL 0x0E348 |
5978 | #define B_BE_WL_ACT2_VAL BIT(25) |
5979 | #define B_BE_WL_ACT2_SWCTRL BIT(24) |
5980 | #define B_BE_WL_ACT_VAL BIT(23) |
5981 | #define B_BE_WL_ACT_SWCTRL BIT(22) |
5982 | #define B_BE_GNT_BT_RX_BB1_VAL BIT(21) |
5983 | #define B_BE_GNT_BT_RX_BB1_SWCTRL BIT(20) |
5984 | #define B_BE_GNT_BT_TX_BB1_VAL BIT(19) |
5985 | #define B_BE_GNT_BT_TX_BB1_SWCTRL BIT(18) |
5986 | #define B_BE_GNT_BT_RX_BB0_VAL BIT(17) |
5987 | #define B_BE_GNT_BT_RX_BB0_SWCTRL BIT(16) |
5988 | #define B_BE_GNT_BT_TX_BB0_VAL BIT(15) |
5989 | #define B_BE_GNT_BT_TX_BB0_SWCTRL BIT(14) |
5990 | #define B_BE_GNT_WL_RX_VAL BIT(13) |
5991 | #define B_BE_GNT_WL_RX_SWCTRL BIT(12) |
5992 | #define B_BE_GNT_WL_TX_VAL BIT(11) |
5993 | #define B_BE_GNT_WL_TX_SWCTRL BIT(10) |
5994 | #define B_BE_GNT_BT_BB1_VAL BIT(9) |
5995 | #define B_BE_GNT_BT_BB1_SWCTRL BIT(8) |
5996 | #define B_BE_GNT_WL_BB1_VAL BIT(7) |
5997 | #define B_BE_GNT_WL_BB1_SWCTRL BIT(6) |
5998 | #define B_BE_GNT_BT_BB0_VAL BIT(5) |
5999 | #define B_BE_GNT_BT_BB0_SWCTRL BIT(4) |
6000 | #define B_BE_GNT_WL_BB0_VAL BIT(3) |
6001 | #define B_BE_GNT_WL_BB0_SWCTRL BIT(2) |
6002 | #define B_BE_GNT_WL_BB_PWR_VAL BIT(1) |
6003 | #define B_BE_GNT_WL_BB_PWR_SWCTRL BIT(0) |
6004 | |
6005 | #define R_BE_PWR_MACID_PATH_BASE 0x0E500 |
6006 | #define R_BE_PWR_MACID_LMT_BASE 0x0ED00 |
6007 | |
6008 | #define R_BE_CMAC_FUNC_EN 0x10000 |
6009 | #define R_BE_CMAC_FUNC_EN_C1 0x14000 |
6010 | #define B_BE_CMAC_CRPRT BIT(31) |
6011 | #define B_BE_CMAC_EN BIT(30) |
6012 | #define B_BE_CMAC_TXEN BIT(29) |
6013 | #define B_BE_CMAC_RXEN BIT(28) |
6014 | #define B_BE_FORCE_RESP_PKTCTL_GCKEN BIT(26) |
6015 | #define B_BE_FORCE_SIGB_REG_GCKEN BIT(25) |
6016 | #define B_BE_FORCE_POWER_REG_GCKEN BIT(23) |
6017 | #define B_BE_FORCE_RMAC_REG_GCKEN BIT(22) |
6018 | #define B_BE_FORCE_TRXPTCL_REG_GCKEN BIT(21) |
6019 | #define B_BE_FORCE_TMAC_REG_GCKEN BIT(20) |
6020 | #define B_BE_FORCE_CMAC_DMA_REG_GCKEN BIT(19) |
6021 | #define B_BE_FORCE_PTCL_REG_GCKEN BIT(18) |
6022 | #define B_BE_FORCE_SCHEDULER_RREG_GCKEN BIT(17) |
6023 | #define B_BE_FORCE_CMAC_COMMON_REG_GCKEN BIT(16) |
6024 | #define B_BE_FORCE_CMACREG_GCKEN BIT(15) |
6025 | #define B_BE_TXTIME_EN BIT(8) |
6026 | #define B_BE_RESP_PKTCTL_EN BIT(7) |
6027 | #define B_BE_SIGB_EN BIT(6) |
6028 | #define B_BE_PHYINTF_EN BIT(5) |
6029 | #define B_BE_CMAC_DMA_EN BIT(4) |
6030 | #define B_BE_PTCLTOP_EN BIT(3) |
6031 | #define B_BE_SCHEDULER_EN BIT(2) |
6032 | #define B_BE_TMAC_EN BIT(1) |
6033 | #define B_BE_RMAC_EN BIT(0) |
6034 | #define B_BE_CMAC_FUNC_EN_SET (B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN | \ |
6035 | B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN | B_BE_PTCLTOP_EN | \ |
6036 | B_BE_SCHEDULER_EN | B_BE_TMAC_EN | B_BE_RMAC_EN | \ |
6037 | B_BE_CMAC_CRPRT | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN | \ |
6038 | B_BE_SIGB_EN) |
6039 | |
6040 | #define R_BE_CK_EN 0x10004 |
6041 | #define R_BE_CK_EN_C1 0x14004 |
6042 | #define B_BE_CMAC_CKEN BIT(30) |
6043 | #define B_BE_BCN_P1_P4_CKEN BIT(15) |
6044 | #define B_BE_BCN_P0MB1_15_CKEN BIT(14) |
6045 | #define B_BE_TXTIME_CKEN BIT(8) |
6046 | #define B_BE_RESP_PKTCTL_CKEN BIT(7) |
6047 | #define B_BE_SIGB_CKEN BIT(6) |
6048 | #define B_BE_PHYINTF_CKEN BIT(5) |
6049 | #define B_BE_CMAC_DMA_CKEN BIT(4) |
6050 | #define B_BE_PTCLTOP_CKEN BIT(3) |
6051 | #define B_BE_SCHEDULER_CKEN BIT(2) |
6052 | #define B_BE_TMAC_CKEN BIT(1) |
6053 | #define B_BE_RMAC_CKEN BIT(0) |
6054 | #define B_BE_CK_EN_SET (B_BE_CMAC_CKEN | B_BE_PHYINTF_CKEN | B_BE_CMAC_DMA_CKEN | \ |
6055 | B_BE_PTCLTOP_CKEN | B_BE_SCHEDULER_CKEN | B_BE_TMAC_CKEN | \ |
6056 | B_BE_RMAC_CKEN | B_BE_TXTIME_CKEN | B_BE_RESP_PKTCTL_CKEN | \ |
6057 | B_BE_SIGB_CKEN) |
6058 | |
6059 | #define R_BE_WMAC_RFMOD 0x10010 |
6060 | #define R_BE_WMAC_RFMOD_C1 0x14010 |
6061 | #define B_BE_CMAC_ASSERTION BIT(31) |
6062 | #define B_BE_WMAC_RFMOD_MASK GENMASK(2, 0) |
6063 | #define BE_WMAC_RFMOD_20M 0 |
6064 | #define BE_WMAC_RFMOD_40M 1 |
6065 | #define BE_WMAC_RFMOD_80M 2 |
6066 | #define BE_WMAC_RFMOD_160M 3 |
6067 | #define BE_WMAC_RFMOD_320M 4 |
6068 | |
6069 | #define R_BE_TX_SUB_BAND_VALUE 0x10088 |
6070 | #define R_BE_TX_SUB_BAND_VALUE_C1 0x14088 |
6071 | #define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16) |
6072 | #define BE_PRI20_BITMAP_MAX 15 |
6073 | #define B_BE_TXSB_160M_MASK GENMASK(15, 12) |
6074 | #define S_BE_TXSB_160M_0 0 |
6075 | #define S_BE_TXSB_160M_1 1 |
6076 | #define B_BE_TXSB_80M_MASK GENMASK(11, 8) |
6077 | #define S_BE_TXSB_80M_0 0 |
6078 | #define S_BE_TXSB_80M_2 2 |
6079 | #define S_BE_TXSB_80M_4 4 |
6080 | #define B_BE_TXSB_40M_MASK GENMASK(7, 4) |
6081 | #define S_BE_TXSB_40M_0 0 |
6082 | #define S_BE_TXSB_40M_1 1 |
6083 | #define S_BE_TXSB_40M_4 4 |
6084 | #define B_BE_TXSB_20M_MASK GENMASK(3, 0) |
6085 | #define S_BE_TXSB_20M_8 8 |
6086 | #define S_BE_TXSB_20M_4 4 |
6087 | #define S_BE_TXSB_20M_2 2 |
6088 | |
6089 | #define R_BE_PTCL_RRSR0 0x1008C |
6090 | #define R_BE_PTCL_RRSR0_C1 0x1408C |
6091 | #define B_BE_RRSR_HE_MASK GENMASK(31, 24) |
6092 | #define B_BE_RRSR_VHT_MASK GENMASK(23, 16) |
6093 | #define B_BE_RRSR_HT_MASK GENMASK(15, 8) |
6094 | #define B_BE_RRSR_OFDM_MASK GENMASK(7, 0) |
6095 | |
6096 | #define R_BE_PTCL_RRSR1 0x10090 |
6097 | #define R_BE_PTCL_RRSR1_C1 0x14090 |
6098 | #define B_BE_RRSR_EHT_MASK GENMASK(23, 16) |
6099 | #define B_BE_RRSR_RATE_EN_MASK GENMASK(12, 8) |
6100 | #define B_BE_RSC_MASK GENMASK(7, 6) |
6101 | #define B_BE_RRSR_CCK_MASK GENMASK(3, 0) |
6102 | |
6103 | #define R_BE_CMAC_ERR_IMR 0x10160 |
6104 | #define R_BE_CMAC_ERR_IMR_C1 0x14160 |
6105 | #define B_BE_CMAC_FW_ERR_IDCT_EN BIT(16) |
6106 | #define B_BE_PTCL_TX_IDLETO_IDCT_EN BIT(9) |
6107 | #define B_BE_WMAC_RX_IDLETO_IDCT_EN BIT(8) |
6108 | #define B_BE_WMAC_TX_ERR_IND_EN BIT(7) |
6109 | #define B_BE_WMAC_RX_ERR_IND_EN BIT(6) |
6110 | #define B_BE_TXPWR_CTRL_ERR_IND_EN BIT(5) |
6111 | #define B_BE_PHYINTF_ERR_IND_EN BIT(4) |
6112 | #define B_BE_DMA_TOP_ERR_IND_EN BIT(3) |
6113 | #define B_BE_RESP_PKTCTL_ERR_IND_EN BIT(2) |
6114 | #define B_BE_PTCL_TOP_ERR_IND_EN BIT(1) |
6115 | #define B_BE_SCHEDULE_TOP_ERR_IND_EN BIT(0) |
6116 | |
6117 | #define R_BE_CMAC_ERR_ISR 0x10164 |
6118 | #define R_BE_CMAC_ERR_ISR_C1 0x14164 |
6119 | #define B_BE_CMAC_FW_ERR_IDCT BIT(16) |
6120 | #define B_BE_PTCL_TX_IDLETO_IDCT BIT(9) |
6121 | #define B_BE_WMAC_RX_IDLETO_IDCT BIT(8) |
6122 | #define B_BE_WMAC_TX_ERR_IND BIT(7) |
6123 | #define B_BE_WMAC_RX_ERR_IND BIT(6) |
6124 | #define B_BE_TXPWR_CTRL_ERR_IND BIT(5) |
6125 | #define B_BE_PHYINTF_ERR_IND BIT(4) |
6126 | #define B_BE_DMA_TOP_ERR_IND BIT(3) |
6127 | #define B_BE_RESP_PKTCTL_ERR_IDCT BIT(2) |
6128 | #define B_BE_PTCL_TOP_ERR_IND BIT(1) |
6129 | #define B_BE_SCHEDULE_TOP_ERR_IND BIT(0) |
6130 | |
6131 | #define R_BE_SER_L0_DBG_CNT 0x10170 |
6132 | #define R_BE_SER_L0_DBG_CNT_C1 0x14170 |
6133 | #define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24) |
6134 | #define B_BE_SER_L0_DMA_CNT_MASK GENMASK(23, 16) |
6135 | #define B_BE_SER_L0_PTCL_CNT_MASK GENMASK(15, 8) |
6136 | #define B_BE_SER_L0_SCH_CNT_MASK GENMASK(7, 0) |
6137 | |
6138 | #define R_BE_SER_L0_DBG_CNT1 0x10174 |
6139 | #define R_BE_SER_L0_DBG_CNT1_C1 0x14174 |
6140 | #define B_BE_SER_L0_TMAC_COUNTER_MASK GENMASK(23, 16) |
6141 | #define B_BE_SER_L0_RMAC_COUNTER_MASK GENMASK(15, 8) |
6142 | #define B_BE_SER_L0_TXPWR_COUNTER_MASK GENMASK(7, 0) |
6143 | |
6144 | #define R_BE_SER_L0_DBG_CNT2 0x10178 |
6145 | #define R_BE_SER_L0_DBG_CNT2_C1 0x14178 |
6146 | |
6147 | #define R_BE_SER_L0_DBG_CNT3 0x1017C |
6148 | #define R_BE_SER_L0_DBG_CNT3_C1 0x1417C |
6149 | #define B_BE_SER_L0_SUBMODULE_BIT31_CNT BIT(31) |
6150 | #define B_BE_SER_L0_SUBMODULE_BIT30_CNT BIT(30) |
6151 | #define B_BE_SER_L0_SUBMODULE_BIT29_CNT BIT(29) |
6152 | #define B_BE_SER_L0_SUBMODULE_BIT28_CNT BIT(28) |
6153 | #define B_BE_SER_L0_SUBMODULE_BIT27_CNT BIT(27) |
6154 | #define B_BE_SER_L0_SUBMODULE_BIT26_CNT BIT(26) |
6155 | #define B_BE_SER_L0_SUBMODULE_BIT25_CNT BIT(25) |
6156 | #define B_BE_SER_L0_SUBMODULE_BIT24_CNT BIT(24) |
6157 | #define B_BE_SER_L0_SUBMODULE_BIT23_CNT BIT(23) |
6158 | #define B_BE_SER_L0_SUBMODULE_BIT22_CNT BIT(22) |
6159 | #define B_BE_SER_L0_SUBMODULE_BIT21_CNT BIT(21) |
6160 | #define B_BE_SER_L0_SUBMODULE_BIT20_CNT BIT(20) |
6161 | #define B_BE_SER_L0_SUBMODULE_BIT19_CNT BIT(19) |
6162 | #define B_BE_SER_L0_SUBMODULE_BIT18_CNT BIT(18) |
6163 | #define B_BE_SER_L0_SUBMODULE_BIT17_CNT BIT(17) |
6164 | #define B_BE_SER_L0_SUBMODULE_BIT16_CNT BIT(16) |
6165 | #define B_BE_SER_L0_SUBMODULE_BIT15_CNT BIT(15) |
6166 | #define B_BE_SER_L0_SUBMODULE_BIT14_CNT BIT(14) |
6167 | #define B_BE_SER_L0_SUBMODULE_BIT13_CNT BIT(13) |
6168 | #define B_BE_SER_L0_SUBMODULE_BIT12_CNT BIT(12) |
6169 | #define B_BE_SER_L0_SUBMODULE_BIT11_CNT BIT(11) |
6170 | #define B_BE_SER_L0_SUBMODULE_BIT10_CNT BIT(10) |
6171 | #define B_BE_SER_L0_SUBMODULE_BIT9_CNT BIT(9) |
6172 | #define B_BE_SER_L0_SUBMODULE_BIT8_CNT BIT(8) |
6173 | #define B_BE_SER_L0_SUBMODULE_BIT7_CNT BIT(7) |
6174 | #define B_BE_SER_L0_SUBMODULE_BIT6_CNT BIT(6) |
6175 | #define B_BE_SER_L0_SUBMODULE_BIT5_CNT BIT(5) |
6176 | #define B_BE_SER_L0_SUBMODULE_BIT4_CNT BIT(4) |
6177 | #define B_BE_SER_L0_SUBMODULE_BIT3_CNT BIT(3) |
6178 | #define B_BE_SER_L0_SUBMODULE_BIT2_CNT BIT(2) |
6179 | #define B_BE_SER_L0_SUBMODULE_BIT1_CNT BIT(1) |
6180 | #define B_BE_SER_L0_SUBMODULE_BIT0_CNT BIT(0) |
6181 | |
6182 | #define R_BE_PORT_0_TSF_SYNC 0x102A0 |
6183 | #define R_BE_PORT_0_TSF_SYNC_C1 0x142A0 |
6184 | #define B_BE_P0_SYNC_NOW_P BIT(30) |
6185 | #define B_BE_P0_SYNC_ONCE_P BIT(29) |
6186 | #define B_BE_P0_AUTO_SYNC BIT(28) |
6187 | #define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24) |
6188 | #define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0) |
6189 | |
6190 | #define R_BE_EDCA_BCNQ_PARAM 0x10324 |
6191 | #define R_BE_EDCA_BCNQ_PARAM_C1 0x14324 |
6192 | #define B_BE_BCNQ_CW_MASK GENMASK(31, 24) |
6193 | #define B_BE_BCNQ_AIFS_MASK GENMASK(23, 16) |
6194 | #define BCN_IFS_25US 0x19 |
6195 | #define B_BE_PIFS_MASK GENMASK(15, 8) |
6196 | #define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0) |
6197 | |
6198 | #define R_BE_PREBKF_CFG_0 0x10338 |
6199 | #define R_BE_PREBKF_CFG_0_C1 0x14338 |
6200 | #define B_BE_100NS_TIME_MASK GENMASK(28, 24) |
6201 | #define B_BE_RX_AIR_END_TIME_MASK GENMASK(22, 16) |
6202 | #define B_BE_MACTX_LATENCY_MASK GENMASK(10, 8) |
6203 | #define B_BE_PREBKF_TIME_MASK GENMASK(4, 0) |
6204 | |
6205 | #define R_BE_PREBKF_CFG_1 0x1033C |
6206 | #define R_BE_PREBKF_CFG_1_C1 0x1433C |
6207 | #define B_BE_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(31, 24) |
6208 | #define B_BE_SIFS_PREBKF_MASK GENMASK(23, 16) |
6209 | #define B_BE_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8) |
6210 | #define B_BE_SIFS_MACTXEN_T1_MASK GENMASK(6, 0) |
6211 | |
6212 | #define R_BE_CCA_CFG_0 0x10340 |
6213 | #define R_BE_CCA_CFG_0_C1 0x14340 |
6214 | #define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24) |
6215 | #define B_BE_EDCCA_SEC160_EN BIT(23) |
6216 | #define B_BE_EDCCA_SEC80_EN BIT(22) |
6217 | #define B_BE_EDCCA_SEC40_EN BIT(21) |
6218 | #define B_BE_EDCCA_SEC20_EN BIT(20) |
6219 | #define B_BE_SEC160_EN BIT(19) |
6220 | #define B_BE_CCA_BITMAP_EN BIT(18) |
6221 | #define B_BE_TXPKTCTL_RST_EDCA_EN BIT(17) |
6222 | #define B_BE_WMAC_RST_EDCA_EN BIT(16) |
6223 | #define B_BE_TXFAIL_BRK_TXOP_EN BIT(11) |
6224 | #define B_BE_EDCCA_PER20_BITMAP_SIFS_EN BIT(10) |
6225 | #define B_BE_NO_GNT_WL_BRK_TXOP_EN BIT(9) |
6226 | #define B_BE_NAV_BRK_TXOP_EN BIT(8) |
6227 | #define B_BE_TX_NAV_EN BIT(7) |
6228 | #define B_BE_BCN_IGNORE_EDCCA BIT(6) |
6229 | #define B_BE_NO_GNT_WL_EN BIT(5) |
6230 | #define B_BE_EDCCA_EN BIT(4) |
6231 | #define B_BE_SEC80_EN BIT(3) |
6232 | #define B_BE_SEC40_EN BIT(2) |
6233 | #define B_BE_SEC20_EN BIT(1) |
6234 | #define B_BE_CCA_EN BIT(0) |
6235 | |
6236 | #define R_BE_CTN_CFG_0 0x1034C |
6237 | #define R_BE_CTN_CFG_0_C1 0x1434C |
6238 | #define B_BE_OTHER_LINK_BKF_BLK_TX_THD_MASK GENMASK(30, 24) |
6239 | #define B_BE_CCK_SIFS_COMP_MASK GENMASK(22, 16) |
6240 | #define B_BE_PIFS_TIMEUNIT_MASK GENMASK(15, 14) |
6241 | #define B_BE_PREBKF_TIME_NONAC_MASK GENMASK(12, 8) |
6242 | #define B_BE_SR_TX_EN BIT(2) |
6243 | #define B_BE_NAV_BLK_MGQ BIT(1) |
6244 | #define B_BE_NAV_BLK_HGQ BIT(0) |
6245 | |
6246 | #define R_BE_MUEDCA_BE_PARAM_0 0x10350 |
6247 | #define R_BE_MUEDCA_BK_PARAM_0 0x10354 |
6248 | #define R_BE_MUEDCA_VI_PARAM_0 0x10358 |
6249 | #define R_BE_MUEDCA_VO_PARAM_0 0x1035C |
6250 | |
6251 | #define R_BE_MUEDCA_EN 0x10370 |
6252 | #define R_BE_MUEDCA_EN_C1 0x14370 |
6253 | #define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24) |
6254 | #define B_BE_SIFS_MACTXEN_TB_T1_MASK GENMASK(22, 16) |
6255 | #define B_BE_MUEDCA_WMM_SEL BIT(8) |
6256 | #define B_BE_SET_MUEDCATIMER_TF_MASK GENMASK(5, 4) |
6257 | #define B_BE_SET_MUEDCATIMER_TF_0 BIT(4) |
6258 | #define B_BE_MUEDCA_EN_MASK GENMASK(1, 0) |
6259 | #define B_BE_MUEDCA_EN_0 BIT(0) |
6260 | |
6261 | #define R_BE_CTN_DRV_TXEN 0x10398 |
6262 | #define R_BE_CTN_DRV_TXEN_C1 0x14398 |
6263 | #define B_BE_CTN_TXEN_TWT_3 BIT(17) |
6264 | #define B_BE_CTN_TXEN_TWT_2 BIT(16) |
6265 | #define B_BE_CTN_TXEN_TWT_1 BIT(15) |
6266 | #define B_BE_CTN_TXEN_TWT_0 BIT(14) |
6267 | #define B_BE_CTN_TXEN_ULQ BIT(13) |
6268 | #define B_BE_CTN_TXEN_BCNQ BIT(12) |
6269 | #define B_BE_CTN_TXEN_HGQ BIT(11) |
6270 | #define B_BE_CTN_TXEN_CPUMGQ BIT(10) |
6271 | #define B_BE_CTN_TXEN_MGQ1 BIT(9) |
6272 | #define B_BE_CTN_TXEN_MGQ BIT(8) |
6273 | #define B_BE_CTN_TXEN_VO_1 BIT(7) |
6274 | #define B_BE_CTN_TXEN_VI_1 BIT(6) |
6275 | #define B_BE_CTN_TXEN_BK_1 BIT(5) |
6276 | #define B_BE_CTN_TXEN_BE_1 BIT(4) |
6277 | #define B_BE_CTN_TXEN_VO_0 BIT(3) |
6278 | #define B_BE_CTN_TXEN_VI_0 BIT(2) |
6279 | #define B_BE_CTN_TXEN_BK_0 BIT(1) |
6280 | #define B_BE_CTN_TXEN_BE_0 BIT(0) |
6281 | #define B_BE_CTN_TXEN_ALL_MASK GENMASK(17, 0) |
6282 | |
6283 | #define R_BE_TB_CHK_CCA_NAV 0x103AC |
6284 | #define R_BE_TB_CHK_CCA_NAV_C1 0x143AC |
6285 | #define B_BE_TB_CHK_TX_NAV BIT(15) |
6286 | #define B_BE_TB_CHK_INTRA_NAV BIT(14) |
6287 | #define B_BE_TB_CHK_BASIC_NAV BIT(13) |
6288 | #define B_BE_TB_CHK_NO_GNT_WL BIT(12) |
6289 | #define B_BE_TB_CHK_EDCCA_S160 BIT(11) |
6290 | #define B_BE_TB_CHK_EDCCA_S80 BIT(10) |
6291 | #define B_BE_TB_CHK_EDCCA_S40 BIT(9) |
6292 | #define B_BE_TB_CHK_EDCCA_S20 BIT(8) |
6293 | #define B_BE_TB_CHK_CCA_S160 BIT(7) |
6294 | #define B_BE_TB_CHK_CCA_S80 BIT(6) |
6295 | #define B_BE_TB_CHK_CCA_S40 BIT(5) |
6296 | #define B_BE_TB_CHK_CCA_S20 BIT(4) |
6297 | #define B_BE_TB_CHK_EDCCA_BITMAP BIT(3) |
6298 | #define B_BE_TB_CHK_CCA_BITMAP BIT(2) |
6299 | #define B_BE_TB_CHK_EDCCA_P20 BIT(1) |
6300 | #define B_BE_TB_CHK_CCA_P20 BIT(0) |
6301 | |
6302 | #define R_BE_HE_SIFS_CHK_CCA_NAV 0x103B4 |
6303 | #define R_BE_HE_SIFS_CHK_CCA_NAV_C1 0x143B4 |
6304 | #define B_BE_HE_SIFS_CHK_TX_NAV BIT(15) |
6305 | #define B_BE_HE_SIFS_CHK_INTRA_NAV BIT(14) |
6306 | #define B_BE_HE_SIFS_CHK_BASIC_NAV BIT(13) |
6307 | #define B_BE_HE_SIFS_CHK_NO_GNT_WL BIT(12) |
6308 | #define B_BE_HE_SIFS_CHK_EDCCA_S160 BIT(11) |
6309 | #define B_BE_HE_SIFS_CHK_EDCCA_S80 BIT(10) |
6310 | #define B_BE_HE_SIFS_CHK_EDCCA_S40 BIT(9) |
6311 | #define B_BE_HE_SIFS_CHK_EDCCA_S20 BIT(8) |
6312 | #define B_BE_HE_SIFS_CHK_CCA_S160 BIT(7) |
6313 | #define B_BE_HE_SIFS_CHK_CCA_S80 BIT(6) |
6314 | #define B_BE_HE_SIFS_CHK_CCA_S40 BIT(5) |
6315 | #define B_BE_HE_SIFS_CHK_CCA_S20 BIT(4) |
6316 | #define B_BE_HE_SIFS_CHK_EDCCA_BITMAP BIT(3) |
6317 | #define B_BE_HE_SIFS_CHK_CCA_BITMAP BIT(2) |
6318 | #define B_BE_HE_SIFS_CHK_EDCCA_P20 BIT(1) |
6319 | #define B_BE_HE_SIFS_CHK_CCA_P20 BIT(0) |
6320 | |
6321 | #define R_BE_HE_CTN_CHK_CCA_NAV 0x103C4 |
6322 | #define R_BE_HE_CTN_CHK_CCA_NAV_C1 0x143C4 |
6323 | #define B_BE_HE_CTN_CHK_TX_NAV BIT(15) |
6324 | #define B_BE_HE_CTN_CHK_INTRA_NAV BIT(14) |
6325 | #define B_BE_HE_CTN_CHK_BASIC_NAV BIT(13) |
6326 | #define B_BE_HE_CTN_CHK_NO_GNT_WL BIT(12) |
6327 | #define B_BE_HE_CTN_CHK_EDCCA_S160 BIT(11) |
6328 | #define B_BE_HE_CTN_CHK_EDCCA_S80 BIT(10) |
6329 | #define B_BE_HE_CTN_CHK_EDCCA_S40 BIT(9) |
6330 | #define B_BE_HE_CTN_CHK_EDCCA_S20 BIT(8) |
6331 | #define B_BE_HE_CTN_CHK_CCA_S160 BIT(7) |
6332 | #define B_BE_HE_CTN_CHK_CCA_S80 BIT(6) |
6333 | #define B_BE_HE_CTN_CHK_CCA_S40 BIT(5) |
6334 | #define B_BE_HE_CTN_CHK_CCA_S20 BIT(4) |
6335 | #define B_BE_HE_CTN_CHK_EDCCA_BITMAP BIT(3) |
6336 | #define B_BE_HE_CTN_CHK_CCA_BITMAP BIT(2) |
6337 | #define B_BE_HE_CTN_CHK_EDCCA_P20 BIT(1) |
6338 | #define B_BE_HE_CTN_CHK_CCA_P20 BIT(0) |
6339 | |
6340 | #define R_BE_SCHEDULE_ERR_IMR 0x103E8 |
6341 | #define R_BE_SCHEDULE_ERR_IMR_C1 0x143E8 |
6342 | #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0) |
6343 | #define B_BE_SCHEDULE_ERR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN |
6344 | #define B_BE_SCHEDULE_ERR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN |
6345 | |
6346 | #define R_BE_SCHEDULE_ERR_ISR 0x103EC |
6347 | #define R_BE_SCHEDULE_ERR_ISR_C1 0x143EC |
6348 | #define B_BE_SORT_NON_IDLE_ERR_INT BIT(1) |
6349 | #define B_BE_FSM_TIMEOUT_ERR_INT BIT(0) |
6350 | |
6351 | #define R_BE_PORT_CFG_P0 0x10400 |
6352 | #define R_BE_PORT_CFG_P0_C1 0x14400 |
6353 | #define B_BE_BCN_ERLY_SORT_EN_P0 BIT(18) |
6354 | #define B_BE_PROHIB_END_CAL_EN_P0 BIT(17) |
6355 | #define B_BE_BRK_SETUP_P0 BIT(16) |
6356 | #define B_BE_TBTT_UPD_SHIFT_SEL_P0 BIT(15) |
6357 | #define B_BE_BCN_DROP_ALLOW_P0 BIT(14) |
6358 | #define B_BE_TBTT_PROHIB_EN_P0 BIT(13) |
6359 | #define B_BE_BCNTX_EN_P0 BIT(12) |
6360 | #define B_BE_NET_TYPE_P0_MASK GENMASK(11, 10) |
6361 | #define B_BE_BCN_FORCETX_EN_P0 BIT(9) |
6362 | #define B_BE_TXBCN_BTCCA_EN_P0 BIT(8) |
6363 | #define B_BE_BCNERR_CNT_EN_P0 BIT(7) |
6364 | #define B_BE_BCN_AGRES_P0 BIT(6) |
6365 | #define B_BE_TSFTR_RST_P0 BIT(5) |
6366 | #define B_BE_RX_BSSID_FIT_EN_P0 BIT(4) |
6367 | #define B_BE_TSF_UDT_EN_P0 BIT(3) |
6368 | #define B_BE_PORT_FUNC_EN_P0 BIT(2) |
6369 | #define B_BE_TXBCN_RPT_EN_P0 BIT(1) |
6370 | #define B_BE_RXBCN_RPT_EN_P0 BIT(0) |
6371 | |
6372 | #define R_BE_TBTT_PROHIB_P0 0x10404 |
6373 | #define R_BE_TBTT_PROHIB_P0_C1 0x14404 |
6374 | #define B_BE_TBTT_HOLD_P0_MASK GENMASK(27, 16) |
6375 | #define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0) |
6376 | |
6377 | #define R_BE_BCN_AREA_P0 0x10408 |
6378 | #define R_BE_BCN_AREA_P0_C1 0x14408 |
6379 | #define B_BE_BCN_MSK_AREA_P0_MSK 0xfff |
6380 | #define B_BE_BCN_CTN_AREA_P0_MASK GENMASK(11, 0) |
6381 | |
6382 | #define R_BE_BCNERLYINT_CFG_P0 0x1040C |
6383 | #define R_BE_BCNERLYINT_CFG_P0_C1 0x1440C |
6384 | #define B_BE_BCNERLY_P0_MASK GENMASK(11, 0) |
6385 | |
6386 | #define R_BE_TBTTERLYINT_CFG_P0 0x1040E |
6387 | #define R_BE_TBTTERLYINT_CFG_P0_C1 0x1440E |
6388 | #define B_BE_TBTTERLY_P0_MASK GENMASK(11, 0) |
6389 | |
6390 | #define R_BE_TBTT_AGG_P0 0x10412 |
6391 | #define R_BE_TBTT_AGG_P0_C1 0x14412 |
6392 | #define B_BE_TBTT_AGG_NUM_P0_MASK GENMASK(15, 8) |
6393 | |
6394 | #define R_BE_BCN_SPACE_CFG_P0 0x10414 |
6395 | #define R_BE_BCN_SPACE_CFG_P0_C1 0x14414 |
6396 | #define B_BE_SUB_BCN_SPACE_P0_MASK GENMASK(23, 16) |
6397 | #define B_BE_BCN_SPACE_P0_MASK GENMASK(15, 0) |
6398 | |
6399 | #define R_BE_BCN_FORCETX_P0 0x10418 |
6400 | #define R_BE_BCN_FORCETX_P0_C1 0x14418 |
6401 | #define B_BE_FORCE_BCN_NUM_P0_MASK GENMASK(15, 8) |
6402 | #define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0) |
6403 | |
6404 | #define R_BE_BCN_ERR_CNT_P0 0x10420 |
6405 | #define R_BE_BCN_ERR_CNT_P0_C1 0x14420 |
6406 | #define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24) |
6407 | #define B_BE_BCN_ERR_CNT_NAV_P0_MASK GENMASK(23, 16) |
6408 | #define B_BE_BCN_ERR_CNT_EDCCA_P0_MASK GENMASK(15, 8) |
6409 | #define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0) |
6410 | |
6411 | #define R_BE_BCN_ERR_FLAG_P0 0x10424 |
6412 | #define R_BE_BCN_ERR_FLAG_P0_C1 0x14424 |
6413 | #define B_BE_BCN_ERR_FLAG_SRCHEND_P0 BIT(3) |
6414 | #define B_BE_BCN_ERR_FLAG_INVALID_P0 BIT(2) |
6415 | #define B_BE_BCN_ERR_FLAG_CMP_P0 BIT(1) |
6416 | #define B_BE_BCN_ERR_FLAG_LOCK_P0 BIT(0) |
6417 | |
6418 | #define R_BE_DTIM_CTRL_P0 0x10426 |
6419 | #define R_BE_DTIM_CTRL_P0_C1 0x14426 |
6420 | #define B_BE_DTIM_NUM_P0_MASK GENMASK(15, 8) |
6421 | #define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0) |
6422 | |
6423 | #define R_BE_TBTT_SHIFT_P0 0x10428 |
6424 | #define R_BE_TBTT_SHIFT_P0_C1 0x14428 |
6425 | #define B_BE_TBTT_SHIFT_OFST_P0_SH 0 |
6426 | #define B_BE_TBTT_SHIFT_OFST_P0_MSK 0xfff |
6427 | |
6428 | #define R_BE_BCN_CNT_TMR_P0 0x10434 |
6429 | #define R_BE_BCN_CNT_TMR_P0_C1 0x14434 |
6430 | #define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0) |
6431 | |
6432 | #define R_BE_TSFTR_LOW_P0 0x10438 |
6433 | #define R_BE_TSFTR_LOW_P0_C1 0x14438 |
6434 | #define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0) |
6435 | |
6436 | #define R_BE_TSFTR_HIGH_P0 0x1043C |
6437 | #define R_BE_TSFTR_HIGH_P0_C1 0x1443C |
6438 | #define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0) |
6439 | |
6440 | #define R_BE_BCN_DROP_ALL0 0x10560 |
6441 | |
6442 | #define R_BE_MBSSID_CTRL 0x10568 |
6443 | #define R_BE_MBSSID_CTRL_C1 0x14568 |
6444 | #define B_BE_MBSSID_MODE_SEL BIT(20) |
6445 | #define B_BE_P0MB_NUM_MASK GENMASK(19, 16) |
6446 | #define B_BE_P0MB15_EN BIT(15) |
6447 | #define B_BE_P0MB14_EN BIT(14) |
6448 | #define B_BE_P0MB13_EN BIT(13) |
6449 | #define B_BE_P0MB12_EN BIT(12) |
6450 | #define B_BE_P0MB11_EN BIT(11) |
6451 | #define B_BE_P0MB10_EN BIT(10) |
6452 | #define B_BE_P0MB9_EN BIT(9) |
6453 | #define B_BE_P0MB8_EN BIT(8) |
6454 | #define B_BE_P0MB7_EN BIT(7) |
6455 | #define B_BE_P0MB6_EN BIT(6) |
6456 | #define B_BE_P0MB5_EN BIT(5) |
6457 | #define B_BE_P0MB4_EN BIT(4) |
6458 | #define B_BE_P0MB3_EN BIT(3) |
6459 | #define B_BE_P0MB2_EN BIT(2) |
6460 | #define B_BE_P0MB1_EN BIT(1) |
6461 | |
6462 | #define R_BE_P0MB_HGQ_WINDOW_CFG_0 0x10590 |
6463 | #define R_BE_P0MB_HGQ_WINDOW_CFG_0_C1 0x14590 |
6464 | #define R_BE_PORT_HGQ_WINDOW_CFG 0x105A0 |
6465 | #define R_BE_PORT_HGQ_WINDOW_CFG_C1 0x145A0 |
6466 | |
6467 | #define R_BE_PTCL_COMMON_SETTING_0 0x10800 |
6468 | #define R_BE_PTCL_COMMON_SETTING_0_C1 0x14800 |
6469 | #define B_BE_PCIE_MODE_MASK GENMASK(15, 14) |
6470 | #define B_BE_CPUMGQ_LIFETIME_EN BIT(8) |
6471 | #define B_BE_MGQ_LIFETIME_EN BIT(7) |
6472 | #define B_BE_LIFETIME_EN BIT(6) |
6473 | #define B_BE_DIS_PTCL_CLK_GATING BIT(5) |
6474 | #define B_BE_PTCL_TRIGGER_SS_EN_UL BIT(4) |
6475 | #define B_BE_PTCL_TRIGGER_SS_EN_1 BIT(3) |
6476 | #define B_BE_PTCL_TRIGGER_SS_EN_0 BIT(2) |
6477 | #define B_BE_CMAC_TX_MODE_1 BIT(1) |
6478 | #define B_BE_CMAC_TX_MODE_0 BIT(0) |
6479 | |
6480 | #define R_BE_TB_PPDU_CTRL 0x1080C |
6481 | #define R_BE_TB_PPDU_CTRL_C1 0x1480C |
6482 | #define B_BE_TB_PPDU_BK_DIS BIT(15) |
6483 | #define B_BE_TB_PPDU_BE_DIS BIT(14) |
6484 | #define B_BE_TB_PPDU_VI_DIS BIT(13) |
6485 | #define B_BE_TB_PPDU_VO_DIS BIT(12) |
6486 | #define B_BE_QOSNULL_UPD_MUEDCA_EN BIT(3) |
6487 | #define B_BE_TB_BYPASS_TXPWR BIT(2) |
6488 | #define B_BE_SW_PREFER_AC_MASK GENMASK(1, 0) |
6489 | |
6490 | #define R_BE_AMPDU_AGG_LIMIT 0x10810 |
6491 | #define R_BE_AMPDU_AGG_LIMIT_C1 0x14810 |
6492 | #define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24) |
6493 | #define AMPDU_MAX_TIME 0x9E |
6494 | #define B_BE_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) |
6495 | #define B_BE_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) |
6496 | #define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0) |
6497 | |
6498 | #define R_BE_AGG_LEN_HT_0 0x10814 |
6499 | #define R_BE_AGG_LEN_HT_0_C1 0x14814 |
6500 | #define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) |
6501 | #define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8) |
6502 | #define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0) |
6503 | |
6504 | #define R_BE_SIFS_SETTING 0x10824 |
6505 | #define R_BE_SIFS_SETTING_C1 0x14824 |
6506 | #define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) |
6507 | #define B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) |
6508 | #define B_BE_HW_CTS2SELF_EN BIT(16) |
6509 | #define B_BE_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) |
6510 | #define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) |
6511 | |
6512 | #define R_BE_TXRATE_CHK 0x10828 |
6513 | #define R_BE_TXRATE_CHK_C1 0x14828 |
6514 | #define B_BE_LATENCY_PADDING_PKT_TH_MASK GENMASK(31, 24) |
6515 | #define B_BE_PLCP_FETCH_BUFF_MASK GENMASK(23, 16) |
6516 | #define B_BE_OFDM_CCK_ERR_PROC BIT(6) |
6517 | #define B_BE_PKT_LAST_TX BIT(5) |
6518 | #define B_BE_BAND_MODE BIT(4) |
6519 | #define B_BE_MAX_TXNSS_MASK GENMASK(3, 2) |
6520 | #define B_BE_RTS_LIMIT_IN_OFDM6 BIT(1) |
6521 | #define B_BE_CHECK_CCK_EN BIT(0) |
6522 | |
6523 | #define R_BE_MBSSID_DROP_0 0x1083C |
6524 | #define R_BE_MBSSID_DROP_0_C1 0x1483C |
6525 | #define B_BE_GI_LTF_FB_SEL BIT(30) |
6526 | #define B_BE_RATE_SEL_MASK GENMASK(29, 24) |
6527 | #define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16) |
6528 | #define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0) |
6529 | |
6530 | #define R_BE_BT_PLT 0x1087C |
6531 | #define R_BE_BT_PLT_C1 0x1487C |
6532 | #define B_BE_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) |
6533 | #define B_BE_BT_PLT_RST BIT(9) |
6534 | #define B_BE_PLT_EN BIT(8) |
6535 | #define B_BE_RX_PLT_GNT_LTE_RX BIT(7) |
6536 | #define B_BE_RX_PLT_GNT_BT_RX BIT(6) |
6537 | #define B_BE_RX_PLT_GNT_BT_TX BIT(5) |
6538 | #define B_BE_RX_PLT_GNT_WL BIT(4) |
6539 | #define B_BE_TX_PLT_GNT_LTE_RX BIT(3) |
6540 | #define B_BE_TX_PLT_GNT_BT_RX BIT(2) |
6541 | #define B_BE_TX_PLT_GNT_BT_TX BIT(1) |
6542 | #define B_BE_TX_PLT_GNT_WL BIT(0) |
6543 | |
6544 | #define R_BE_PTCL_BSS_COLOR_0 0x108A0 |
6545 | #define R_BE_PTCL_BSS_COLOR_0_C1 0x148A0 |
6546 | #define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24) |
6547 | #define B_BE_BSS_COLOB_BE_PORT_2_MASK GENMASK(21, 16) |
6548 | #define B_BE_BSS_COLOB_BE_PORT_1_MASK GENMASK(13, 8) |
6549 | #define B_BE_BSS_COLOB_BE_PORT_0_MASK GENMASK(5, 0) |
6550 | |
6551 | #define R_BE_PTCL_BSS_COLOR_1 0x108A4 |
6552 | #define R_BE_PTCL_BSS_COLOR_1_C1 0x148A4 |
6553 | #define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0) |
6554 | |
6555 | #define R_BE_PTCL_IMR_2 0x108B8 |
6556 | #define R_BE_PTCL_IMR_2_C1 0x148B8 |
6557 | #define B_BE_NO_TRX_TIMEOUT_IMR BIT(1) |
6558 | #define B_BE_TX_IDLE_TIMEOUT_IMR BIT(0) |
6559 | #define B_BE_PTCL_IMR_2_CLR B_BE_TX_IDLE_TIMEOUT_IMR |
6560 | #define B_BE_PTCL_IMR_2_SET 0 |
6561 | |
6562 | #define R_BE_PTCL_IMR0 0x108C0 |
6563 | #define R_BE_PTCL_IMR0_C1 0x148C0 |
6564 | #define B_BE_PTCL_ERROR_FLAG_IMR BIT(31) |
6565 | #define B_BE_FSM1_TIMEOUT_ERR_INT_EN BIT(1) |
6566 | #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0) |
6567 | #define B_BE_PTCL_IMR0_CLR (B_BE_FSM_TIMEOUT_ERR_INT_EN | \ |
6568 | B_BE_FSM1_TIMEOUT_ERR_INT_EN | \ |
6569 | B_BE_PTCL_ERROR_FLAG_IMR) |
6570 | #define B_BE_PTCL_IMR0_SET (B_BE_FSM_TIMEOUT_ERR_INT_EN | \ |
6571 | B_BE_FSM1_TIMEOUT_ERR_INT_EN | \ |
6572 | B_BE_PTCL_ERROR_FLAG_IMR) |
6573 | |
6574 | #define R_BE_PTCL_ISR0 0x108C4 |
6575 | #define R_BE_PTCL_ISR0_C1 0x148C4 |
6576 | #define B_BE_PTCL_ERROR_FLAG_ISR BIT(31) |
6577 | #define B_BE_FSM1_TIMEOUT_ERR BIT(1) |
6578 | #define B_BE_FSM_TIMEOUT_ERR BIT(0) |
6579 | |
6580 | #define R_BE_PTCL_IMR1 0x108C8 |
6581 | #define R_BE_PTCL_IMR1_C1 0x148C8 |
6582 | #define B_BE_F2PCMD_PKTID_IMR BIT(30) |
6583 | #define B_BE_F2PCMD_RD_PKTID_IMR BIT(29) |
6584 | #define B_BE_F2PCMD_ASSIGN_PKTID_IMR BIT(28) |
6585 | #define B_BE_F2PCMD_USER_ALLC_IMR BIT(27) |
6586 | #define B_BE_RX_SPF_U0_PKTID_IMR BIT(26) |
6587 | #define B_BE_TX_SPF_U1_PKTID_IMR BIT(25) |
6588 | #define B_BE_TX_SPF_U2_PKTID_IMR BIT(24) |
6589 | #define B_BE_TX_SPF_U3_PKTID_IMR BIT(23) |
6590 | #define B_BE_TX_RECORD_PKTID_IMR BIT(22) |
6591 | #define B_BE_TWTSP_QSEL_IMR BIT(14) |
6592 | #define B_BE_F2P_RLS_CTN_SEL_IMR BIT(13) |
6593 | #define B_BE_BCNQ_ORDER_IMR BIT(12) |
6594 | #define B_BE_Q_PKTID_IMR BIT(11) |
6595 | #define B_BE_D_PKTID_IMR BIT(10) |
6596 | #define B_BE_TXPRT_FULL_DROP_IMR BIT(9) |
6597 | #define B_BE_F2PCMDRPT_FULL_DROP_IMR BIT(8) |
6598 | #define B_BE_PTCL_IMR1_CLR (B_BE_F2PCMDRPT_FULL_DROP_IMR | \ |
6599 | B_BE_TXPRT_FULL_DROP_IMR | \ |
6600 | B_BE_D_PKTID_IMR | \ |
6601 | B_BE_Q_PKTID_IMR | \ |
6602 | B_BE_BCNQ_ORDER_IMR | \ |
6603 | B_BE_F2P_RLS_CTN_SEL_IMR | \ |
6604 | B_BE_TWTSP_QSEL_IMR | \ |
6605 | B_BE_TX_RECORD_PKTID_IMR | \ |
6606 | B_BE_TX_SPF_U3_PKTID_IMR | \ |
6607 | B_BE_TX_SPF_U2_PKTID_IMR | \ |
6608 | B_BE_TX_SPF_U1_PKTID_IMR | \ |
6609 | B_BE_RX_SPF_U0_PKTID_IMR | \ |
6610 | B_BE_F2PCMD_USER_ALLC_IMR | \ |
6611 | B_BE_F2PCMD_ASSIGN_PKTID_IMR | \ |
6612 | B_BE_F2PCMD_RD_PKTID_IMR | \ |
6613 | B_BE_F2PCMD_PKTID_IMR) |
6614 | #define B_BE_PTCL_IMR1_SET B_BE_F2PCMD_USER_ALLC_IMR |
6615 | |
6616 | #define R_BE_PTCL_ISR1 0x108CC |
6617 | #define R_BE_PTCL_ISR1_C1 0x148CC |
6618 | #define B_BE_F2PCMD_PKTID_ERR BIT(30) |
6619 | #define B_BE_F2PCMD_RD_PKTID_ERR BIT(29) |
6620 | #define B_BE_F2PCMD_ASSIGN_PKTID_ERR BIT(28) |
6621 | #define B_BE_F2PCMD_USER_ALLC_ERR BIT(27) |
6622 | #define B_BE_RX_SPF_U0_PKTID_ERR BIT(26) |
6623 | #define B_BE_TX_SPF_U1_PKTID_ERR BIT(25) |
6624 | #define B_BE_TX_SPF_U2_PKTID_ERR BIT(24) |
6625 | #define B_BE_TX_SPF_U3_PKTID_ERR BIT(23) |
6626 | #define B_BE_TX_RECORD_PKTID_ERR BIT(22) |
6627 | #define B_BE_TWTSP_QSEL_ERR BIT(14) |
6628 | #define B_BE_F2P_RLS_CTN_SEL_ERR BIT(13) |
6629 | #define B_BE_BCNQ_ORDER_ERR BIT(12) |
6630 | #define B_BE_Q_PKTID_ERR BIT(11) |
6631 | #define B_BE_D_PKTID_ERR BIT(10) |
6632 | #define B_BE_TXPRT_FULL_DROP_ERR BIT(9) |
6633 | #define B_BE_F2PCMDRPT_FULL_DROP_ERR BIT(8) |
6634 | |
6635 | #define R_BE_PTCL_FSM_MON 0x108E8 |
6636 | #define R_BE_PTCL_FSM_MON_C1 0x148E8 |
6637 | #define B_BE_PTCL_FSM2_TO_MODE BIT(30) |
6638 | #define B_BE_PTCL_FSM2_TO_THR_MASK GENMASK(29, 24) |
6639 | #define B_BE_PTCL_FSM1_TO_MODE BIT(22) |
6640 | #define B_BE_PTCL_FSM1_TO_THR_MASK GENMASK(21, 16) |
6641 | #define B_BE_PTCL_FSM0_TO_MODE BIT(14) |
6642 | #define B_BE_PTCL_FSM0_TO_THR_MASK GENMASK(13, 8) |
6643 | #define B_BE_PTCL_TX_ARB_TO_MODE BIT(6) |
6644 | #define B_BE_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) |
6645 | |
6646 | #define R_BE_PTCL_TX_CTN_SEL 0x108EC |
6647 | #define R_BE_PTCL_TX_CTN_SEL_C1 0x148EC |
6648 | #define B_BE_PTCL_TXOP_STAT BIT(8) |
6649 | #define B_BE_PTCL_BUSY BIT(7) |
6650 | #define B_BE_PTCL_DROP BIT(5) |
6651 | #define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0) |
6652 | |
6653 | #define R_BE_PTCL_DBG_INFO 0x108F0 |
6654 | |
6655 | #define R_BE_PTCL_DBG 0x108F4 |
6656 | |
6657 | #define R_BE_RX_ERROR_FLAG 0x10C00 |
6658 | #define R_BE_RX_ERROR_FLAG_C1 0x14C00 |
6659 | #define B_BE_RX_CSI_NOT_RELEASE_ERROR BIT(31) |
6660 | #define B_BE_RX_GET_NULL_PKT_ERROR BIT(30) |
6661 | #define B_BE_RX_RU0_FSM_HANG_ERROR BIT(29) |
6662 | #define B_BE_RX_RU1_FSM_HANG_ERROR BIT(28) |
6663 | #define B_BE_RX_RU2_FSM_HANG_ERROR BIT(27) |
6664 | #define B_BE_RX_RU3_FSM_HANG_ERROR BIT(26) |
6665 | #define B_BE_RX_RU4_FSM_HANG_ERROR BIT(25) |
6666 | #define B_BE_RX_RU5_FSM_HANG_ERROR BIT(24) |
6667 | #define B_BE_RX_RU6_FSM_HANG_ERROR BIT(23) |
6668 | #define B_BE_RX_RU7_FSM_HANG_ERROR BIT(22) |
6669 | #define B_BE_RX_RXSTS_FSM_HANG_ERROR BIT(21) |
6670 | #define B_BE_RX_CSI_FSM_HANG_ERROR BIT(20) |
6671 | #define B_BE_RX_TXRPT_FSM_HANG_ERROR BIT(19) |
6672 | #define B_BE_RX_F2PCMD_FSM_HANG_ERROR BIT(18) |
6673 | #define B_BE_RX_RU0_ZERO_LENGTH_ERROR BIT(17) |
6674 | #define B_BE_RX_RU1_ZERO_LENGTH_ERROR BIT(16) |
6675 | #define B_BE_RX_RU2_ZERO_LENGTH_ERROR BIT(15) |
6676 | #define B_BE_RX_RU3_ZERO_LENGTH_ERROR BIT(14) |
6677 | #define B_BE_RX_RU4_ZERO_LENGTH_ERROR BIT(13) |
6678 | #define B_BE_RX_RU5_ZERO_LENGTH_ERROR BIT(12) |
6679 | #define B_BE_RX_RU6_ZERO_LENGTH_ERROR BIT(11) |
6680 | #define B_BE_RX_RU7_ZERO_LENGTH_ERROR BIT(10) |
6681 | #define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR BIT(9) |
6682 | #define B_BE_RX_CSI_ZERO_LENGTH_ERROR BIT(8) |
6683 | #define B_BE_PLE_DATA_OPT_FSM_HANG BIT(7) |
6684 | #define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG BIT(6) |
6685 | #define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG BIT(5) |
6686 | #define B_BE_PLE_WD_OPT_FSM_HANG BIT(4) |
6687 | #define B_BE_PLE_ENQ_FSM_HANG BIT(3) |
6688 | #define B_BE_RXDATA_ENQUE_ORDER_ERROR BIT(2) |
6689 | #define B_BE_RXSTS_ENQUE_ORDER_ERROR BIT(1) |
6690 | #define B_BE_RX_CSI_PKT_NUM_ERROR BIT(0) |
6691 | |
6692 | #define R_BE_RX_ERROR_FLAG_IMR 0x10C04 |
6693 | #define R_BE_RX_ERROR_FLAG_IMR_C1 0x14C04 |
6694 | #define B_BE_RX_CSI_NOT_RELEASE_ERROR_IMR BIT(31) |
6695 | #define B_BE_RX_GET_NULL_PKT_ERROR_IMR BIT(30) |
6696 | #define B_BE_RX_RU0_FSM_HANG_ERROR_IMR BIT(29) |
6697 | #define B_BE_RX_RU1_FSM_HANG_ERROR_IMR BIT(28) |
6698 | #define B_BE_RX_RU2_FSM_HANG_ERROR_IMR BIT(27) |
6699 | #define B_BE_RX_RU3_FSM_HANG_ERROR_IMR BIT(26) |
6700 | #define B_BE_RX_RU4_FSM_HANG_ERROR_IMR BIT(25) |
6701 | #define B_BE_RX_RU5_FSM_HANG_ERROR_IMR BIT(24) |
6702 | #define B_BE_RX_RU6_FSM_HANG_ERROR_IMR BIT(23) |
6703 | #define B_BE_RX_RU7_FSM_HANG_ERROR_IMR BIT(22) |
6704 | #define B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR BIT(21) |
6705 | #define B_BE_RX_CSI_FSM_HANG_ERROR_IMR BIT(20) |
6706 | #define B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR BIT(19) |
6707 | #define B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR BIT(18) |
6708 | #define B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR BIT(17) |
6709 | #define B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR BIT(16) |
6710 | #define B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR BIT(15) |
6711 | #define B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR BIT(14) |
6712 | #define B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR BIT(13) |
6713 | #define B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR BIT(12) |
6714 | #define B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR BIT(11) |
6715 | #define B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR BIT(10) |
6716 | #define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR BIT(9) |
6717 | #define B_BE_RX_CSI_ZERO_LENGTH_ERROR_IMR BIT(8) |
6718 | #define B_BE_PLE_DATA_OPT_FSM_HANG_IMR BIT(7) |
6719 | #define B_BE_PLE_RXDATA_REQUEST_BUFFER_FSM_HANG_IMR BIT(6) |
6720 | #define B_BE_PLE_TXRPT_REQUEST_BUFFER_FSM_HANG_IMR BIT(5) |
6721 | #define B_BE_PLE_WD_OPT_FSM_HANG_IMR BIT(4) |
6722 | #define B_BE_PLE_ENQ_FSM_HANG_IMR BIT(3) |
6723 | #define B_BE_RXDATA_ENQUE_ORDER_ERROR_IMR BIT(2) |
6724 | #define B_BE_RXSTS_ENQUE_ORDER_ERROR_IMR BIT(1) |
6725 | #define B_BE_RX_CSI_PKT_NUM_ERROR_IMR BIT(0) |
6726 | #define B_BE_RX_ERROR_FLAG_IMR_CLR (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \ |
6727 | B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \ |
6728 | B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \ |
6729 | B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \ |
6730 | B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \ |
6731 | B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \ |
6732 | B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \ |
6733 | B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \ |
6734 | B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \ |
6735 | B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \ |
6736 | B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \ |
6737 | B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \ |
6738 | B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \ |
6739 | B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \ |
6740 | B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \ |
6741 | B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \ |
6742 | B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \ |
6743 | B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \ |
6744 | B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \ |
6745 | B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \ |
6746 | B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \ |
6747 | B_BE_RX_GET_NULL_PKT_ERROR_IMR) |
6748 | #define B_BE_RX_ERROR_FLAG_IMR_SET (B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR | \ |
6749 | B_BE_RX_RU7_ZERO_LENGTH_ERROR_IMR | \ |
6750 | B_BE_RX_RU6_ZERO_LENGTH_ERROR_IMR | \ |
6751 | B_BE_RX_RU5_ZERO_LENGTH_ERROR_IMR | \ |
6752 | B_BE_RX_RU4_ZERO_LENGTH_ERROR_IMR | \ |
6753 | B_BE_RX_RU3_ZERO_LENGTH_ERROR_IMR | \ |
6754 | B_BE_RX_RU2_ZERO_LENGTH_ERROR_IMR | \ |
6755 | B_BE_RX_RU1_ZERO_LENGTH_ERROR_IMR | \ |
6756 | B_BE_RX_RU0_ZERO_LENGTH_ERROR_IMR | \ |
6757 | B_BE_RX_F2PCMD_FSM_HANG_ERROR_IMR | \ |
6758 | B_BE_RX_TXRPT_FSM_HANG_ERROR_IMR | \ |
6759 | B_BE_RX_CSI_FSM_HANG_ERROR_IMR | \ |
6760 | B_BE_RX_RXSTS_FSM_HANG_ERROR_IMR | \ |
6761 | B_BE_RX_RU7_FSM_HANG_ERROR_IMR | \ |
6762 | B_BE_RX_RU6_FSM_HANG_ERROR_IMR | \ |
6763 | B_BE_RX_RU5_FSM_HANG_ERROR_IMR | \ |
6764 | B_BE_RX_RU4_FSM_HANG_ERROR_IMR | \ |
6765 | B_BE_RX_RU3_FSM_HANG_ERROR_IMR | \ |
6766 | B_BE_RX_RU2_FSM_HANG_ERROR_IMR | \ |
6767 | B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \ |
6768 | B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \ |
6769 | B_BE_RX_GET_NULL_PKT_ERROR_IMR) |
6770 | |
6771 | #define R_BE_RX_CTRL_1 0x10C0C |
6772 | #define R_BE_RX_CTRL_1_C1 0x14C0C |
6773 | #define B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK GENMASK(30, 25) |
6774 | #define B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK GENMASK(23, 18) |
6775 | #define B_BE_RXDMA_TXRPT_PORT_ID_SW_MASK GENMASK(17, 14) |
6776 | #define B_BE_RXDMA_F2PCMDRPT_PORT_ID_SW_MASK GENMASK(13, 10) |
6777 | #define B_BE_DBG_SEL_MASK GENMASK(1, 0) |
6778 | #define WLCPU_RXCH2_QID 0xA |
6779 | |
6780 | #define R_BE_TX_ERROR_FLAG 0x10C6C |
6781 | #define R_BE_TX_ERROR_FLAG_C1 0x14C6C |
6782 | #define B_BE_TX_RU0_FSM_HANG_ERROR BIT(31) |
6783 | #define B_BE_TX_RU1_FSM_HANG_ERROR BIT(30) |
6784 | #define B_BE_TX_RU2_FSM_HANG_ERROR BIT(29) |
6785 | #define B_BE_TX_RU3_FSM_HANG_ERROR BIT(28) |
6786 | #define B_BE_TX_RU4_FSM_HANG_ERROR BIT(27) |
6787 | #define B_BE_TX_RU5_FSM_HANG_ERROR BIT(26) |
6788 | #define B_BE_TX_RU6_FSM_HANG_ERROR BIT(25) |
6789 | #define B_BE_TX_RU7_FSM_HANG_ERROR BIT(24) |
6790 | #define B_BE_TX_RU8_FSM_HANG_ERROR BIT(23) |
6791 | #define B_BE_TX_RU9_FSM_HANG_ERROR BIT(22) |
6792 | #define B_BE_TX_RU10_FSM_HANG_ERROR BIT(21) |
6793 | #define B_BE_TX_RU11_FSM_HANG_ERROR BIT(20) |
6794 | #define B_BE_TX_RU12_FSM_HANG_ERROR BIT(19) |
6795 | #define B_BE_TX_RU13_FSM_HANG_ERROR BIT(18) |
6796 | #define B_BE_TX_RU14_FSM_HANG_ERROR BIT(17) |
6797 | #define B_BE_TX_RU15_FSM_HANG_ERROR BIT(16) |
6798 | #define B_BE_TX_CSI_FSM_HANG_ERROR BIT(15) |
6799 | #define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR BIT(14) |
6800 | |
6801 | #define R_BE_TX_ERROR_FLAG_IMR 0x10C70 |
6802 | #define R_BE_TX_ERROR_FLAG_IMR_C1 0x14C70 |
6803 | #define B_BE_TX_RU0_FSM_HANG_ERROR_IMR BIT(31) |
6804 | #define B_BE_TX_RU1_FSM_HANG_ERROR_IMR BIT(30) |
6805 | #define B_BE_TX_RU2_FSM_HANG_ERROR_IMR BIT(29) |
6806 | #define B_BE_TX_RU3_FSM_HANG_ERROR_IMR BIT(28) |
6807 | #define B_BE_TX_RU4_FSM_HANG_ERROR_IMR BIT(27) |
6808 | #define B_BE_TX_RU5_FSM_HANG_ERROR_IMR BIT(26) |
6809 | #define B_BE_TX_RU6_FSM_HANG_ERROR_IMR BIT(25) |
6810 | #define B_BE_TX_RU7_FSM_HANG_ERROR_IMR BIT(24) |
6811 | #define B_BE_TX_RU8_FSM_HANG_ERROR_IMR BIT(23) |
6812 | #define B_BE_TX_RU9_FSM_HANG_ERROR_IMR BIT(22) |
6813 | #define B_BE_TX_RU10_FSM_HANG_ERROR_IMR BIT(21) |
6814 | #define B_BE_TX_RU11_FSM_HANG_ERROR_IMR BIT(20) |
6815 | #define B_BE_TX_RU12_FSM_HANG_ERROR_IMR BIT(19) |
6816 | #define B_BE_TX_RU13_FSM_HANG_ERROR_IMR BIT(18) |
6817 | #define B_BE_TX_RU14_FSM_HANG_ERROR_IMR BIT(17) |
6818 | #define B_BE_TX_RU15_FSM_HANG_ERROR_IMR BIT(16) |
6819 | #define B_BE_TX_CSI_FSM_HANG_ERROR_IMR BIT(15) |
6820 | #define B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR BIT(14) |
6821 | #define B_BE_TX_ERROR_FLAG_IMR_CLR (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \ |
6822 | B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \ |
6823 | B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \ |
6824 | B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \ |
6825 | B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \ |
6826 | B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \ |
6827 | B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \ |
6828 | B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \ |
6829 | B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \ |
6830 | B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \ |
6831 | B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \ |
6832 | B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \ |
6833 | B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \ |
6834 | B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \ |
6835 | B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \ |
6836 | B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \ |
6837 | B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \ |
6838 | B_BE_TX_RU0_FSM_HANG_ERROR_IMR) |
6839 | #define B_BE_TX_ERROR_FLAG_IMR_SET (B_BE_TX_WD_PLD_ID_FSM_HANG_ERROR_IMR | \ |
6840 | B_BE_TX_CSI_FSM_HANG_ERROR_IMR | \ |
6841 | B_BE_TX_RU15_FSM_HANG_ERROR_IMR | \ |
6842 | B_BE_TX_RU14_FSM_HANG_ERROR_IMR | \ |
6843 | B_BE_TX_RU13_FSM_HANG_ERROR_IMR | \ |
6844 | B_BE_TX_RU12_FSM_HANG_ERROR_IMR | \ |
6845 | B_BE_TX_RU11_FSM_HANG_ERROR_IMR | \ |
6846 | B_BE_TX_RU10_FSM_HANG_ERROR_IMR | \ |
6847 | B_BE_TX_RU9_FSM_HANG_ERROR_IMR | \ |
6848 | B_BE_TX_RU8_FSM_HANG_ERROR_IMR | \ |
6849 | B_BE_TX_RU7_FSM_HANG_ERROR_IMR | \ |
6850 | B_BE_TX_RU6_FSM_HANG_ERROR_IMR | \ |
6851 | B_BE_TX_RU5_FSM_HANG_ERROR_IMR | \ |
6852 | B_BE_TX_RU4_FSM_HANG_ERROR_IMR | \ |
6853 | B_BE_TX_RU3_FSM_HANG_ERROR_IMR | \ |
6854 | B_BE_TX_RU2_FSM_HANG_ERROR_IMR | \ |
6855 | B_BE_TX_RU1_FSM_HANG_ERROR_IMR | \ |
6856 | B_BE_TX_RU0_FSM_HANG_ERROR_IMR) |
6857 | |
6858 | #define R_BE_RX_ERROR_FLAG_1 0x10C84 |
6859 | #define R_BE_RX_ERROR_FLAG_1_C1 0x14C84 |
6860 | #define B_BE_RX_RU8_FSM_HANG_ERROR BIT(29) |
6861 | #define B_BE_RX_RU9_FSM_HANG_ERROR BIT(28) |
6862 | #define B_BE_RX_RU10_FSM_HANG_ERROR BIT(27) |
6863 | #define B_BE_RX_RU11_FSM_HANG_ERROR BIT(26) |
6864 | #define B_BE_RX_RU12_FSM_HANG_ERROR BIT(25) |
6865 | #define B_BE_RX_RU13_FSM_HANG_ERROR BIT(24) |
6866 | #define B_BE_RX_RU14_FSM_HANG_ERROR BIT(23) |
6867 | #define B_BE_RX_RU15_FSM_HANG_ERROR BIT(22) |
6868 | #define B_BE_RX_RU8_ZERO_LENGTH_ERROR BIT(17) |
6869 | #define B_BE_RX_RU9_ZERO_LENGTH_ERROR BIT(16) |
6870 | #define B_BE_RX_RU10_ZERO_LENGTH_ERROR BIT(15) |
6871 | #define B_BE_RX_RU11_ZERO_LENGTH_ERROR BIT(14) |
6872 | #define B_BE_RX_RU12_ZERO_LENGTH_ERROR BIT(13) |
6873 | #define B_BE_RX_RU13_ZERO_LENGTH_ERROR BIT(12) |
6874 | #define B_BE_RX_RU14_ZERO_LENGTH_ERROR BIT(11) |
6875 | #define B_BE_RX_RU15_ZERO_LENGTH_ERROR BIT(10) |
6876 | |
6877 | #define R_BE_RX_ERROR_FLAG_IMR_1 0x10C88 |
6878 | #define R_BE_RX_ERROR_FLAG_IMR_1_C1 0x14C88 |
6879 | #define B_BE_RX_RU8_FSM_HANG_ERROR_IMR BIT(29) |
6880 | #define B_BE_RX_RU9_FSM_HANG_ERROR_IMR BIT(28) |
6881 | #define B_BE_RX_RU10_FSM_HANG_ERROR_IMR BIT(27) |
6882 | #define B_BE_RX_RU11_FSM_HANG_ERROR_IMR BIT(26) |
6883 | #define B_BE_RX_RU12_FSM_HANG_ERROR_IMR BIT(25) |
6884 | #define B_BE_RX_RU13_FSM_HANG_ERROR_IMR BIT(24) |
6885 | #define B_BE_RX_RU14_FSM_HANG_ERROR_IMR BIT(23) |
6886 | #define B_BE_RX_RU15_FSM_HANG_ERROR_IMR BIT(22) |
6887 | #define B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR BIT(17) |
6888 | #define B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR BIT(16) |
6889 | #define B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR BIT(15) |
6890 | #define B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR BIT(14) |
6891 | #define B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR BIT(13) |
6892 | #define B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR BIT(12) |
6893 | #define B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR BIT(11) |
6894 | #define B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR BIT(10) |
6895 | #define B_BE_TX_ERROR_FLAG_IMR_1_CLR (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \ |
6896 | B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \ |
6897 | B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \ |
6898 | B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \ |
6899 | B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \ |
6900 | B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \ |
6901 | B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \ |
6902 | B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \ |
6903 | B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \ |
6904 | B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \ |
6905 | B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \ |
6906 | B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \ |
6907 | B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \ |
6908 | B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \ |
6909 | B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \ |
6910 | B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR) |
6911 | #define B_BE_TX_ERROR_FLAG_IMR_1_SET (B_BE_RX_RU8_FSM_HANG_ERROR_IMR | \ |
6912 | B_BE_RX_RU9_FSM_HANG_ERROR_IMR | \ |
6913 | B_BE_RX_RU10_FSM_HANG_ERROR_IMR | \ |
6914 | B_BE_RX_RU11_FSM_HANG_ERROR_IMR | \ |
6915 | B_BE_RX_RU12_FSM_HANG_ERROR_IMR | \ |
6916 | B_BE_RX_RU13_FSM_HANG_ERROR_IMR | \ |
6917 | B_BE_RX_RU14_FSM_HANG_ERROR_IMR | \ |
6918 | B_BE_RX_RU15_FSM_HANG_ERROR_IMR | \ |
6919 | B_BE_RX_RU8_ZERO_LENGTH_ERROR_IMR | \ |
6920 | B_BE_RX_RU9_ZERO_LENGTH_ERROR_IMR | \ |
6921 | B_BE_RX_RU10_ZERO_LENGTH_ERROR_IMR | \ |
6922 | B_BE_RX_RU11_ZERO_LENGTH_ERROR_IMR | \ |
6923 | B_BE_RX_RU12_ZERO_LENGTH_ERROR_IMR | \ |
6924 | B_BE_RX_RU13_ZERO_LENGTH_ERROR_IMR | \ |
6925 | B_BE_RX_RU14_ZERO_LENGTH_ERROR_IMR | \ |
6926 | B_BE_RX_RU15_ZERO_LENGTH_ERROR_IMR) |
6927 | |
6928 | #define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL 0x10E08 |
6929 | #define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL_C1 0x14E08 |
6930 | #define B_BE_TSFT_OFS_MASK GENMASK(31, 16) |
6931 | #define B_BE_STMP_THSD_MASK GENMASK(15, 8) |
6932 | #define B_BE_UPD_HGQMD BIT(1) |
6933 | #define B_BE_UPD_TIMIE BIT(0) |
6934 | |
6935 | #define R_BE_WMTX_POWER_BE_BIT_CTL 0x10E0C |
6936 | #define R_BE_WMTX_POWER_BE_BIT_CTL_C1 0x14E0C |
6937 | |
6938 | #define R_BE_WMTX_TCR_BE_4 0x10E2C |
6939 | #define R_BE_WMTX_TCR_BE_4_C1 0x14E2C |
6940 | #define B_BE_UL_EHT_MUMIMO_LTF_MODE BIT(30) |
6941 | #define B_BE_UL_HE_MUMIMO_LTF_MODE BIT(29) |
6942 | #define B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK GENMASK(28, 24) |
6943 | #define B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK GENMASK(20, 16) |
6944 | #define B_BE_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(12, 8) |
6945 | #define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0) |
6946 | |
6947 | #define R_BE_RSP_CHK_SIG 0x11000 |
6948 | #define R_BE_RSP_CHK_SIG_C1 0x15000 |
6949 | #define B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) |
6950 | #define B_BE_RSP_TBPPDU_CHK_PWR BIT(29) |
6951 | #define B_BE_RESP_PAIR_MACID_LEN_EN BIT(25) |
6952 | #define B_BE_RESP_TX_ABORT_TEST_EN BIT(24) |
6953 | #define B_BE_RESP_ER_SU_RU106_EN BIT(23) |
6954 | #define B_BE_RESP_ER_SU_EN BIT(22) |
6955 | #define B_BE_TXDATA_END_PS_OPT BIT(18) |
6956 | #define B_BE_CHECK_SOUNDING_SEQ BIT(17) |
6957 | #define B_BE_RXBA_IGNOREA2 BIT(16) |
6958 | #define B_BE_ACKTO_CCK_MASK GENMASK(15, 8) |
6959 | #define B_BE_ACKTO_MASK GENMASK(8, 0) |
6960 | |
6961 | #define R_BE_TRXPTCL_RESP_0 0x11004 |
6962 | #define R_BE_TRXPTCL_RESP_0_C1 0x15004 |
6963 | #define B_BE_WMAC_RESP_STBC_EN BIT(31) |
6964 | #define B_BE_WMAC_RXFTM_TXACK_SB BIT(30) |
6965 | #define B_BE_WMAC_RXFTM_TXACKBWEQ BIT(29) |
6966 | #define B_BE_RESP_TB_CHK_TXTIME BIT(24) |
6967 | #define B_BE_RSP_CHK_CCA BIT(23) |
6968 | #define B_BE_WMAC_LDPC_EN BIT(22) |
6969 | #define B_BE_WMAC_SGIEN BIT(21) |
6970 | #define B_BE_WMAC_SPLCPEN BIT(20) |
6971 | #define B_BE_RESP_EHT_MCS15_REF BIT(19) |
6972 | #define B_BE_RESP_EHT_MCS14_REF BIT(18) |
6973 | #define B_BE_WMAC_BESP_EARLY_TXBA BIT(17) |
6974 | #define B_BE_WMAC_MBA_DUR_FORCE BIT(16) |
6975 | #define B_BE_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8) |
6976 | #define WMAC_SPEC_SIFS_OFDM_1115E 0x11 |
6977 | #define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) |
6978 | |
6979 | #define R_BE_TRXPTCL_RESP_1 0x11008 |
6980 | #define R_BE_TRXPTCL_RESP_1_C1 0x15008 |
6981 | #define B_BE_WMAC_RESP_SR_MODE_EN BIT(31) |
6982 | #define B_BE_FTM_RRSR_RATE_EN_MASK GENMASK(28, 24) |
6983 | #define B_BE_NESS_MASK GENMASK(23, 22) |
6984 | #define B_BE_WMAC_RESP_DOPPLEB_BE_EN BIT(21) |
6985 | #define B_BE_WMAC_RESP_DCM_EN BIT(20) |
6986 | #define B_BE_WMAC_CLR_ABORT_RESP_TX_CNT BIT(15) |
6987 | #define B_BE_WMAC_RESP_REF_RATE_SEL BIT(12) |
6988 | #define B_BE_WMAC_RESP_REF_RATE_MASK GENMASK(11, 0) |
6989 | |
6990 | #define R_BE_MAC_LOOPBACK 0x11020 |
6991 | #define R_BE_MAC_LOOPBACK_C1 0x15020 |
6992 | #define B_BE_MACLBK_DIS_GCLK BIT(30) |
6993 | #define B_BE_MACLBK_STS_EN BIT(29) |
6994 | #define B_BE_MACLBK_RDY_PERIOD_MASK GENMASK(28, 17) |
6995 | #define B_BE_MACLBK_PLCP_DLY_MASK GENMASK(16, 8) |
6996 | #define S_BE_MACLBK_PLCP_DLY_DEF 0x28 |
6997 | #define B_BE_MACLBK_RDY_NUM_MASK GENMASK(7, 3) |
6998 | #define B_BE_MACLBK_EN BIT(0) |
6999 | |
7000 | #define R_BE_WMAC_NAV_CTL 0x11080 |
7001 | #define R_BE_WMAC_NAV_CTL_C1 0x15080 |
7002 | #define B_BE_WMAC_NAV_UPPER_EN BIT(26) |
7003 | #define B_BE_WMAC_0P125US_TIMER_MASK GENMASK(25, 18) |
7004 | #define B_BE_WMAC_PLCP_UP_NAV_EN BIT(17) |
7005 | #define B_BE_WMAC_TF_UP_NAV_EN BIT(16) |
7006 | #define B_BE_WMAC_NAV_UPPER_MASK GENMASK(15, 8) |
7007 | #define NAV_25MS 0xC4 |
7008 | #define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0) |
7009 | |
7010 | #define R_BE_RXTRIG_TEST_USER_2 0x110B0 |
7011 | #define R_BE_RXTRIG_TEST_USER_2_C1 0x150B0 |
7012 | #define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24) |
7013 | #define B_BE_RXTRIG_RU26_DIS BIT(21) |
7014 | #define B_BE_RXTRIG_FCSCHK_EN BIT(20) |
7015 | #define B_BE_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) |
7016 | #define B_BE_RXTRIG_EN BIT(16) |
7017 | #define B_BE_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) |
7018 | |
7019 | #define R_BE_TRXPTCL_ERROR_INDICA_MASK 0x110BC |
7020 | #define R_BE_TRXPTCL_ERROR_INDICA_MASK_C1 0x150BC |
7021 | #define B_BE_WMAC_FTM_TIMEOUT_MODE BIT(30) |
7022 | #define B_BE_WMAC_FTM_TIMEOUT_THR_MASK GENMASK(29, 24) |
7023 | #define B_BE_WMAC_MODE BIT(22) |
7024 | #define B_BE_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16) |
7025 | #define B_BE_RMAC_BFMER BIT(9) |
7026 | #define B_BE_RMAC_FTM BIT(8) |
7027 | #define B_BE_RMAC_CSI BIT(7) |
7028 | #define B_BE_TMAC_MIMO_CTRL BIT(6) |
7029 | #define B_BE_TMAC_RXTB BIT(5) |
7030 | #define B_BE_TMAC_HWSIGB_GEN BIT(4) |
7031 | #define B_BE_TMAC_TXPLCP BIT(3) |
7032 | #define B_BE_TMAC_RESP BIT(2) |
7033 | #define B_BE_TMAC_TXCTL BIT(1) |
7034 | #define B_BE_TMAC_MACTX BIT(0) |
7035 | #define B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR (B_BE_TMAC_MACTX | \ |
7036 | B_BE_TMAC_TXCTL | \ |
7037 | B_BE_TMAC_RESP | \ |
7038 | B_BE_TMAC_TXPLCP | \ |
7039 | B_BE_TMAC_HWSIGB_GEN | \ |
7040 | B_BE_TMAC_RXTB | \ |
7041 | B_BE_TMAC_MIMO_CTRL | \ |
7042 | B_BE_RMAC_CSI | \ |
7043 | B_BE_RMAC_FTM | \ |
7044 | B_BE_RMAC_BFMER) |
7045 | #define B_BE_TRXPTCL_ERROR_INDICA_MASK_SET (B_BE_TMAC_MACTX | \ |
7046 | B_BE_TMAC_TXCTL | \ |
7047 | B_BE_TMAC_RESP | \ |
7048 | B_BE_TMAC_TXPLCP | \ |
7049 | B_BE_TMAC_HWSIGB_GEN | \ |
7050 | B_BE_TMAC_RXTB | \ |
7051 | B_BE_TMAC_MIMO_CTRL | \ |
7052 | B_BE_RMAC_CSI | \ |
7053 | B_BE_RMAC_FTM | \ |
7054 | B_BE_RMAC_BFMER) |
7055 | |
7056 | #define R_BE_TRXPTCL_ERROR_INDICA 0x110C0 |
7057 | #define R_BE_TRXPTCL_ERROR_INDICA_C1 0x150C0 |
7058 | #define B_BE_BFMER_ERR_FLAG BIT(9) |
7059 | #define B_BE_FTM_ERROR_FLAG_CLR BIT(8) |
7060 | #define B_BE_CSI_ERROR_FLAG_CLR BIT(7) |
7061 | #define B_BE_MIMOCTRL_ERROR_FLAG_CLR BIT(6) |
7062 | #define B_BE_RXTB_ERROR_FLAG_CLR BIT(5) |
7063 | #define B_BE_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4) |
7064 | #define B_BE_TXPLCP_ERROR_FLAG_CLR BIT(3) |
7065 | #define B_BE_RESP_ERROR_FLAG_CLR BIT(2) |
7066 | #define B_BE_TXCTL_ERROR_FLAG_CLR BIT(1) |
7067 | #define B_BE_MACTX_ERROR_FLAG_CLR BIT(0) |
7068 | |
7069 | #define R_BE_DBGSEL_TRXPTCL 0x110F4 |
7070 | #define R_BE_DBGSEL_TRXPTCL_C1 0x150F4 |
7071 | #define B_BE_WMAC_CHNSTS_STATE_MASK GENMASK(19, 16) |
7072 | #define B_BE_DBGSEL_TRIGCMD_SEL_MASK GENMASK(11, 8) |
7073 | #define B_BE_DBGSEL_TRXPTCL_MASK GENMASK(7, 0) |
7074 | |
7075 | #define R_BE_PHYINFO_ERR_IMR_V1 0x110F8 |
7076 | #define R_BE_PHYINFO_ERR_IMR_V1_C1 0x150F8 |
7077 | #define B_BE_PHYINTF_RXTB_WIDTH_MASK GENMASK(31, 30) |
7078 | #define B_BE_PHYINTF_RXTB_EN_PHASE_MASK GENMASK(29, 28) |
7079 | #define B_BE_PHYINTF_MIMO_WIDTH_MASK GENMASK(27, 26) |
7080 | #define B_BE_PHYINTF_MIMO_EN_PHASE_MASK GENMASK(25, 24) |
7081 | #define B_BE_PHYINTF_TIMEOUT_THR_V1_MASK GENMASK(21, 16) |
7082 | #define B_BE_CSI_ON_TIMEOUT_EN BIT(5) |
7083 | #define B_BE_STS_ON_TIMEOUT_EN BIT(4) |
7084 | #define B_BE_DATA_ON_TIMEOUT_EN BIT(3) |
7085 | #define B_BE_OFDM_CCA_TIMEOUT_EN BIT(2) |
7086 | #define B_BE_CCK_CCA_TIMEOUT_EN BIT(1) |
7087 | #define B_BE_PHY_TXON_TIMEOUT_EN BIT(0) |
7088 | #define B_BE_PHYINFO_ERR_IMR_V1_CLR (B_BE_PHY_TXON_TIMEOUT_EN | \ |
7089 | B_BE_CCK_CCA_TIMEOUT_EN | \ |
7090 | B_BE_OFDM_CCA_TIMEOUT_EN | \ |
7091 | B_BE_DATA_ON_TIMEOUT_EN | \ |
7092 | B_BE_STS_ON_TIMEOUT_EN | \ |
7093 | B_BE_CSI_ON_TIMEOUT_EN) |
7094 | #define B_BE_PHYINFO_ERR_IMR_V1_SET 0 |
7095 | |
7096 | #define R_BE_PHYINFO_ERR_ISR 0x110FC |
7097 | #define R_BE_PHYINFO_ERR_ISR_C1 0x150FC |
7098 | #define B_BE_CSI_ON_TIMEOUT_ERR BIT(5) |
7099 | #define B_BE_STS_ON_TIMEOUT_ERR BIT(4) |
7100 | #define B_BE_DATA_ON_TIMEOUT_ERR BIT(3) |
7101 | #define B_BE_OFDM_CCA_TIMEOUT_ERR BIT(2) |
7102 | #define B_BE_CCK_CCA_TIMEOUT_ERR BIT(1) |
7103 | #define B_BE_PHY_TXON_TIMEOUT_ERR BIT(0) |
7104 | |
7105 | #define R_BE_BFMEE_RESP_OPTION 0x11180 |
7106 | #define R_BE_BFMEE_RESP_OPTION_C1 0x15180 |
7107 | #define B_BE_BFMEE_CSI_SEC_TYPE_SH 20 |
7108 | #define B_BE_BFMEE_CSI_SEC_TYPE_MSK 0xf |
7109 | #define B_BE_BFMEE_BFRPT_SEG_SIZE_SH 16 |
7110 | #define B_BE_BFMEE_BFRPT_SEG_SIZE_MSK 0x3 |
7111 | #define B_BE_BFMEE_MIMO_EN_SEL BIT(8) |
7112 | #define B_BE_BFMEE_MU_BFEE_DIS BIT(7) |
7113 | #define B_BE_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6) |
7114 | #define B_BE_BFMEE_NOCHK_BFPOLL_BMP BIT(5) |
7115 | #define B_BE_BFMEE_VHTBFRPT_CHK BIT(4) |
7116 | #define B_BE_BFMEE_EHT_NDPA_EN BIT(3) |
7117 | #define B_BE_BFMEE_HE_NDPA_EN BIT(2) |
7118 | #define B_BE_BFMEE_VHT_NDPA_EN BIT(1) |
7119 | #define B_BE_BFMEE_HT_NDPA_EN BIT(0) |
7120 | |
7121 | #define R_BE_TRXPTCL_RESP_CSI_CTRL_0 0x11188 |
7122 | #define R_BE_TRXPTCL_RESP_CSI_CTRL_0_C1 0x15188 |
7123 | #define B_BE_BFMEE_CSISEQ_SEL BIT(29) |
7124 | #define B_BE_BFMEE_BFPARAM_SEL BIT(28) |
7125 | #define B_BE_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) |
7126 | #define B_BE_BFMEE_BF_PORT_SEL BIT(23) |
7127 | #define B_BE_BFMEE_USE_NSTS BIT(22) |
7128 | #define B_BE_BFMEE_CSI_RATE_FB_EN BIT(21) |
7129 | #define B_BE_BFMEE_CSI_GID_SEL BIT(20) |
7130 | #define B_BE_BFMEE_CSI_RSC_MASK GENMASK(19, 18) |
7131 | #define B_BE_BFMEE_CSI_FORCE_RETE_EN BIT(17) |
7132 | #define B_BE_BFMEE_CSI_USE_NDPARATE BIT(16) |
7133 | #define B_BE_BFMEE_CSI_WITHHTC_EN BIT(15) |
7134 | #define B_BE_BFMEE_CSIINFO0_BF_EN BIT(14) |
7135 | #define B_BE_BFMEE_CSIINFO0_STBC_EN BIT(13) |
7136 | #define B_BE_BFMEE_CSIINFO0_LDPC_EN BIT(12) |
7137 | #define B_BE_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) |
7138 | #define B_BE_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) |
7139 | #define B_BE_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) |
7140 | #define B_BE_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) |
7141 | #define B_BE_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) |
7142 | #define CSI_RX_BW_CFG 0x1 |
7143 | #define R_BE_TRXPTCL_RESP_CSI_CTRL_1 0x11194 |
7144 | #define R_BE_TRXPTCL_RESP_CSI_CTRL_1_C1 0x15194 |
7145 | #define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24) |
7146 | #define CSI_RRSC_BITMAP_CFG 0x2A |
7147 | |
7148 | #define R_BE_TRXPTCL_RESP_CSI_RRSC 0x1118C |
7149 | #define R_BE_TRXPTCL_RESP_CSI_RRSC_C1 0x1518C |
7150 | #define CSI_RRSC_BMAP_BE 0x2A2AFF |
7151 | |
7152 | #define R_BE_TRXPTCL_RESP_CSI_RATE 0x11190 |
7153 | #define R_BE_TRXPTCL_RESP_CSI_RATE_C1 0x15190 |
7154 | #define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24) |
7155 | #define B_BE_BFMEE_HE_CSI_RATE_MASK GENMASK(23, 16) |
7156 | #define B_BE_BFMEE_VHT_CSI_RATE_MASK GENMASK(15, 8) |
7157 | #define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0) |
7158 | #define CSI_INIT_RATE_EHT 0x3 |
7159 | |
7160 | #define R_BE_WMAC_ACK_BA_RESP_LEGACY 0x11200 |
7161 | #define R_BE_WMAC_ACK_BA_RESP_LEGACY_C1 0x15200 |
7162 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_NSTR BIT(16) |
7163 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_TX_NAV BIT(15) |
7164 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_INTRA_NAV BIT(14) |
7165 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_BASIC_NAV BIT(13) |
7166 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_BTCCA BIT(12) |
7167 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11) |
7168 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10) |
7169 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9) |
7170 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8) |
7171 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7) |
7172 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6) |
7173 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA160 BIT(5) |
7174 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA80 BIT(4) |
7175 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA40 BIT(3) |
7176 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA20 BIT(2) |
7177 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA BIT(1) |
7178 | #define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0) |
7179 | |
7180 | #define R_BE_WMAC_ACK_BA_RESP_HE 0x11204 |
7181 | #define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204 |
7182 | #define B_BE_ACK_BA_RESP_HE_CHK_NSTR BIT(16) |
7183 | #define B_BE_ACK_BA_RESP_HE_CHK_TX_NAV BIT(15) |
7184 | #define B_BE_ACK_BA_RESP_HE_CHK_INTRA_NAV BIT(14) |
7185 | #define B_BE_ACK_BA_RESP_HE_CHK_BASIC_NAV BIT(13) |
7186 | #define B_BE_ACK_BA_RESP_HE_CHK_BTCCA BIT(12) |
7187 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA160 BIT(11) |
7188 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA80 BIT(10) |
7189 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA40 BIT(9) |
7190 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA20 BIT(8) |
7191 | #define B_BE_ACK_BA_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7) |
7192 | #define B_BE_ACK_BA_RESP_HE_CHK_CCA_PER20_BMP BIT(6) |
7193 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA160 BIT(5) |
7194 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA80 BIT(4) |
7195 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA40 BIT(3) |
7196 | #define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA20 BIT(2) |
7197 | #define B_BE_ACK_BA_RESP_HE_CHK_EDCCA BIT(1) |
7198 | #define B_BE_ACK_BA_RESP_HE_CHK_CCA BIT(0) |
7199 | |
7200 | #define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC 0x11208 |
7201 | #define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC_C1 0x15208 |
7202 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_NSTR BIT(16) |
7203 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_TX_NAV BIT(15) |
7204 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_INTRA_NAV BIT(14) |
7205 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BASIC_NAV BIT(13) |
7206 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BTCCA BIT(12) |
7207 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA160 BIT(11) |
7208 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA80 BIT(10) |
7209 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9) |
7210 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA20 BIT(8) |
7211 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7) |
7212 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA_PER20_BMP BIT(6) |
7213 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA160 BIT(5) |
7214 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4) |
7215 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA40 BIT(3) |
7216 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA20 BIT(2) |
7217 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA BIT(1) |
7218 | #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0) |
7219 | |
7220 | #define R_BE_RCR 0x11400 |
7221 | #define R_BE_RCR_C1 0x15400 |
7222 | #define B_BE_BUSY_CHKSN BIT(15) |
7223 | #define B_BE_DYN_CHEN BIT(14) |
7224 | #define B_BE_AUTO_RST BIT(13) |
7225 | #define B_BE_TIMER_SEL BIT(12) |
7226 | #define B_BE_STOP_RX_IN BIT(11) |
7227 | #define B_BE_PSR_RDY_CHKDIS BIT(10) |
7228 | #define B_BE_DRV_INFO_SZ_MASK GENMASK(9, 8) |
7229 | #define B_BE_HDR_CNV_SZ_MASK GENMASK(7, 6) |
7230 | #define B_BE_PHY_RPT_SZ_MASK GENMASK(5, 4) |
7231 | #define B_BE_CH_EN BIT(0) |
7232 | |
7233 | #define R_BE_DLK_PROTECT_CTL 0x11402 |
7234 | #define R_BE_DLK_PROTECT_CTL_C1 0x15402 |
7235 | #define B_BE_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) |
7236 | #define TRXCFG_RMAC_CCA_TO 32 |
7237 | #define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) |
7238 | #define TRXCFG_RMAC_DATA_TO 15 |
7239 | #define B_BE_RX_DLK_RST_FSM BIT(3) |
7240 | #define B_BE_RX_DLK_RST_SKIPDMA BIT(2) |
7241 | #define B_BE_RX_DLK_RST_EN BIT(1) |
7242 | #define B_BE_RX_DLK_INT_EN BIT(0) |
7243 | |
7244 | #define R_BE_PLCP_HDR_FLTR 0x11404 |
7245 | #define R_BE_PLCP_HDR_FLTR_C1 0x15404 |
7246 | #define B_BE_PLCP_RXFA_RESET_TYPE_MASK GENMASK(15, 12) |
7247 | #define B_BE_PLCP_RXFA_RESET_EN BIT(11) |
7248 | #define B_BE_DIS_CHK_MIN_LEN BIT(8) |
7249 | #define B_BE_HE_SIGB_CRC_CHK BIT(6) |
7250 | #define B_BE_VHT_MU_SIGB_CRC_CHK BIT(5) |
7251 | #define B_BE_VHT_SU_SIGB_CRC_CHK BIT(4) |
7252 | #define B_BE_SIGA_CRC_CHK BIT(3) |
7253 | #define B_BE_LSIG_PARITY_CHK_EN BIT(2) |
7254 | #define B_BE_CCK_SIG_CHK BIT(1) |
7255 | #define B_BE_CCK_CRC_CHK BIT(0) |
7256 | |
7257 | #define R_BE_RX_FLTR_OPT 0x11420 |
7258 | #define R_BE_RX_FLTR_OPT_C1 0x15420 |
7259 | #define B_BE_UID_FILTER_MASK GENMASK(31, 24) |
7260 | #define B_BE_UNSPT_TYPE BIT(22) |
7261 | #define B_BE_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) |
7262 | #define B_BE_A_FTM_REQ BIT(14) |
7263 | #define B_BE_A_ERR_PKT BIT(13) |
7264 | #define B_BE_A_UNSUP_PKT BIT(12) |
7265 | #define B_BE_A_CRC32_ERR BIT(11) |
7266 | #define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8) |
7267 | #define B_BE_A_BCN_CHK_EN BIT(7) |
7268 | #define B_BE_A_MC_LIST_CAM_MATCH BIT(6) |
7269 | #define B_BE_A_BC_CAM_MATCH BIT(5) |
7270 | #define B_BE_A_UC_CAM_MATCH BIT(4) |
7271 | #define B_BE_A_MC BIT(3) |
7272 | #define B_BE_A_BC BIT(2) |
7273 | #define B_BE_A_A1_MATCH BIT(1) |
7274 | #define B_BE_SNIFFER_MODE BIT(0) |
7275 | |
7276 | #define R_BE_CTRL_FLTR 0x11424 |
7277 | #define R_BE_CTRL_FLTR_C1 0x15424 |
7278 | #define B_BE_CTRL_STYPE_MASK GENMASK(15, 0) |
7279 | #define RX_FLTR_FRAME_DROP_BE 0x0000 |
7280 | #define RX_FLTR_FRAME_ACCEPT_BE 0xFFFF |
7281 | |
7282 | #define R_BE_MGNT_FLTR 0x11428 |
7283 | #define R_BE_MGNT_FLTR_C1 0x15428 |
7284 | #define B_BE_MGNT_STYPE_MASK GENMASK(15, 0) |
7285 | |
7286 | #define R_BE_DATA_FLTR 0x1142C |
7287 | #define R_BE_DATA_FLTR_C1 0x1542C |
7288 | #define B_BE_DATA_STYPE_MASK GENMASK(15, 0) |
7289 | |
7290 | #define R_BE_ADDR_CAM_CTRL 0x11434 |
7291 | #define R_BE_ADDR_CAM_CTRL_C1 0x15434 |
7292 | #define B_BE_ADDR_CAM_RANGE_MASK GENMASK(23, 16) |
7293 | #define ADDR_CAM_SERCH_RANGE 0x7f |
7294 | #define B_BE_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) |
7295 | #define B_BE_ADDR_CAM_IORST BIT(10) |
7296 | #define B_BE_DIS_ADDR_CLK_GATED BIT(9) |
7297 | #define B_BE_ADDR_CAM_CLR BIT(8) |
7298 | #define B_BE_ADDR_CAM_A2_B0_CHK BIT(2) |
7299 | #define B_BE_ADDR_CAM_SRCH_PERPKT BIT(1) |
7300 | #define B_BE_ADDR_CAM_EN BIT(0) |
7301 | |
7302 | #define R_BE_RESPBA_CAM_CTRL 0x1143C |
7303 | #define R_BE_RESPBA_CAM_CTRL_C1 0x1543C |
7304 | #define B_BE_BACAM_SKIP_ALL_QOSNULL BIT(24) |
7305 | #define B_BE_BACAM_STD_SSN_SEL BIT(20) |
7306 | #define B_BE_BACAM_TEMP_SZ_MASK GENMASK(17, 16) |
7307 | #define B_BE_BACAM_RST_IDX_MASK GENMASK(15, 8) |
7308 | #define B_BE_BACAM_SHIFT_POLL BIT(7) |
7309 | #define B_BE_BACAM_IORST BIT(6) |
7310 | #define B_BE_BACAM_GCK_DIS BIT(5) |
7311 | #define B_BE_COMPL_VAL BIT(3) |
7312 | #define B_BE_SSN_SEL BIT(2) |
7313 | #define B_BE_BACAM_RST_MASK GENMASK(1, 0) |
7314 | #define S_BE_BACAM_RST_DONE 0 |
7315 | #define S_BE_BACAM_RST_ENT 1 |
7316 | #define S_BE_BACAM_RST_ALL 2 |
7317 | |
7318 | #define R_BE_PPDU_STAT 0x11440 |
7319 | #define R_BE_PPDU_STAT_C1 0x15440 |
7320 | #define B_BE_STAT_IORST BIT(13) |
7321 | #define B_BE_STAT_GCKDIS BIT(12) |
7322 | #define B_BE_PPDU_STAT_WR_BW_MASK GENMASK(11, 10) |
7323 | #define B_BE_PPDU_STAT_RPT_TRIG BIT(8) |
7324 | #define B_BE_PPDU_STAT_RPT_DMA BIT(6) |
7325 | #define B_BE_PPDU_STAT_RPT_CRC32 BIT(5) |
7326 | #define B_BE_PPDU_STAT_RPT_ADDR BIT(4) |
7327 | #define B_BE_APP_PLCP_HDR_RPT BIT(3) |
7328 | #define B_BE_APP_RX_CNT_RPT BIT(2) |
7329 | #define B_BE_PPDU_MAC_INFO BIT(1) |
7330 | #define B_BE_PPDU_STAT_RPT_EN BIT(0) |
7331 | |
7332 | #define R_BE_RX_SR_CTRL 0x1144A |
7333 | #define R_BE_RX_SR_CTRL_C1 0x1544A |
7334 | #define B_BE_SR_OP_MODE_MASK GENMASK(5, 4) |
7335 | #define B_BE_SRG_CHK_EN BIT(2) |
7336 | #define B_BE_SR_CTRL_PLCP_EN BIT(1) |
7337 | #define B_BE_SR_EN BIT(0) |
7338 | |
7339 | #define R_BE_BSSID_SRC_CTRL 0x1144B |
7340 | #define R_BE_BSSID_SRC_CTRL_C1 0x1544B |
7341 | #define B_BE_BSSID_MATCH BIT(3) |
7342 | #define B_BE_PARTIAL_AID_MATCH BIT(2) |
7343 | #define B_BE_BSSCOLOR_MATCH BIT(1) |
7344 | #define B_BE_PLCP_SRC_EN BIT(0) |
7345 | |
7346 | #define R_BE_CSIRPT_OPTION 0x11464 |
7347 | #define R_BE_CSIRPT_OPTION_C1 0x15464 |
7348 | #define B_BE_CSIPRT_EHTSU_AID_EN BIT(26) |
7349 | #define B_BE_CSIPRT_HESU_AID_EN BIT(25) |
7350 | #define B_BE_CSIPRT_VHTSU_AID_EN BIT(24) |
7351 | |
7352 | #define R_BE_RX_ERR_ISR 0x114F4 |
7353 | #define R_BE_RX_ERR_ISR_C1 0x154F4 |
7354 | #define B_BE_RX_ERR_TRIG_ACT_TO BIT(9) |
7355 | #define B_BE_RX_ERR_STS_ACT_TO BIT(8) |
7356 | #define B_BE_RX_ERR_CSI_ACT_TO BIT(7) |
7357 | #define B_BE_RX_ERR_ACT_TO BIT(6) |
7358 | #define B_BE_CSI_DATAON_ASSERT_TO BIT(5) |
7359 | #define B_BE_DATAON_ASSERT_TO BIT(4) |
7360 | #define B_BE_CCA_ASSERT_TO BIT(3) |
7361 | #define B_BE_RX_ERR_DMA_TO BIT(2) |
7362 | #define B_BE_RX_ERR_DATA_TO BIT(1) |
7363 | #define B_BE_RX_ERR_CCA_TO BIT(0) |
7364 | |
7365 | #define R_BE_RX_ERR_IMR 0x114F8 |
7366 | #define R_BE_RX_ERR_IMR_C1 0x154F8 |
7367 | #define B_BE_RX_ERR_TRIG_ACT_TO_MSK BIT(9) |
7368 | #define B_BE_RX_ERR_STS_ACT_TO_MSK BIT(8) |
7369 | #define B_BE_RX_ERR_CSI_ACT_TO_MSK BIT(7) |
7370 | #define B_BE_RX_ERR_ACT_TO_MSK BIT(6) |
7371 | #define B_BE_CSI_DATAON_ASSERT_TO_MSK BIT(5) |
7372 | #define B_BE_DATAON_ASSERT_TO_MSK BIT(4) |
7373 | #define B_BE_CCA_ASSERT_TO_MSK BIT(3) |
7374 | #define B_BE_RX_ERR_DMA_TO_MSK BIT(2) |
7375 | #define B_BE_RX_ERR_DATA_TO_MSK BIT(1) |
7376 | #define B_BE_RX_ERR_CCA_TO_MSK BIT(0) |
7377 | #define B_BE_RX_ERR_IMR_CLR (B_BE_RX_ERR_CCA_TO_MSK | \ |
7378 | B_BE_RX_ERR_DATA_TO_MSK | \ |
7379 | B_BE_RX_ERR_DMA_TO_MSK | \ |
7380 | B_BE_CCA_ASSERT_TO_MSK | \ |
7381 | B_BE_DATAON_ASSERT_TO_MSK | \ |
7382 | B_BE_CSI_DATAON_ASSERT_TO_MSK | \ |
7383 | B_BE_RX_ERR_ACT_TO_MSK | \ |
7384 | B_BE_RX_ERR_CSI_ACT_TO_MSK | \ |
7385 | B_BE_RX_ERR_STS_ACT_TO_MSK | \ |
7386 | B_BE_RX_ERR_TRIG_ACT_TO_MSK) |
7387 | #define B_BE_RX_ERR_IMR_SET (B_BE_RX_ERR_ACT_TO_MSK | \ |
7388 | B_BE_RX_ERR_STS_ACT_TO_MSK | \ |
7389 | B_BE_RX_ERR_TRIG_ACT_TO_MSK) |
7390 | |
7391 | #define R_BE_RX_PLCP_EXT_OPTION_1 0x11514 |
7392 | #define R_BE_RX_PLCP_EXT_OPTION_1_C1 0x15514 |
7393 | #define B_BE_PLCP_CLOSE_RX_UNSPUUORT BIT(19) |
7394 | #define B_BE_PLCP_CLOSE_RX_BB_BRK BIT(18) |
7395 | #define B_BE_PLCP_CLOSE_RX_PSDU_PRES BIT(17) |
7396 | #define B_BE_PLCP_CLOSE_RX_NDP BIT(16) |
7397 | #define B_BE_PLCP_NSS_SRC BIT(11) |
7398 | #define B_BE_PLCP_DOPPLEB_BE_SRC BIT(10) |
7399 | #define B_BE_PLCP_STBC_SRC BIT(9) |
7400 | #define B_BE_PLCP_SU_PSDU_LEN_SRC BIT(8) |
7401 | #define B_BE_PLCP_RXSB_SRC BIT(7) |
7402 | #define B_BE_PLCP_BW_SRC_MASK GENMASK(6, 5) |
7403 | #define B_BE_PLCP_GILTF_SRC BIT(4) |
7404 | #define B_BE_PLCP_NSTS_SRC BIT(3) |
7405 | #define B_BE_PLCP_MCS_SRC BIT(2) |
7406 | #define B_BE_PLCP_CH20_WIDATA_SRC BIT(1) |
7407 | #define B_BE_PLCP_PPDU_TYPE_SRC BIT(0) |
7408 | |
7409 | #define R_BE_RESP_CSI_RESERVED_PAGE 0x11810 |
7410 | #define R_BE_RESP_CSI_RESERVED_PAGE_C1 0x15810 |
7411 | #define B_BE_CSI_RESERVED_PAGE_NUM_MASK GENMASK(27, 16) |
7412 | #define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0) |
7413 | |
7414 | #define R_BE_RESP_IMR 0x11884 |
7415 | #define R_BE_RESP_IMR_C1 0x15884 |
7416 | #define B_BE_RESP_TBL_FLAG_ERR_ISR_EN BIT(17) |
7417 | #define B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN BIT(16) |
7418 | #define B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN BIT(15) |
7419 | #define B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN BIT(14) |
7420 | #define B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN BIT(13) |
7421 | #define B_BE_RESP_PLDID_RDY_ERR_ISR_EN BIT(12) |
7422 | #define B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN BIT(11) |
7423 | #define B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN BIT(10) |
7424 | #define B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN BIT(9) |
7425 | #define B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN BIT(8) |
7426 | #define B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN BIT(6) |
7427 | #define B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN BIT(5) |
7428 | #define B_BE_RESP_TXCMD_TBL_ERR_ISR_EN BIT(4) |
7429 | #define B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN BIT(3) |
7430 | #define B_BE_RESP_INITCMD_RESERVD_PAGE_ABORT_ERR_ISR_EN BIT(2) |
7431 | #define B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN BIT(1) |
7432 | #define B_BE_RESP_DMAC_PROC_ERR_ISR_EN BIT(0) |
7433 | #define B_BE_RESP_IMR_CLR (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \ |
7434 | B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \ |
7435 | B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \ |
7436 | B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \ |
7437 | B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \ |
7438 | B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \ |
7439 | B_BE_RESP_RXDMA_REQ_MACID_ERR_ISR_EN | \ |
7440 | B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN | \ |
7441 | B_BE_RESP_RXDMA_WRPTR_INVLD_ERR_ISR_EN | \ |
7442 | B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \ |
7443 | B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \ |
7444 | B_BE_RESP_TXDMA_READ_DATA_ERR_ISR_EN | \ |
7445 | B_BE_RESP_TOO_MANY_PLD_ERR_ISR_EN | \ |
7446 | B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \ |
7447 | B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN) |
7448 | #define B_BE_RESP_IMR_SET (B_BE_RESP_DMAC_PROC_ERR_ISR_EN | \ |
7449 | B_BE_RESP_INITCMD_TX_ST_ABORT_ERR_ISR_EN | \ |
7450 | B_BE_RESP_INITCMD_RX_ST_ABORT_ERR_ISR_EN | \ |
7451 | B_BE_RESP_TXCMD_TBL_ERR_ISR_EN | \ |
7452 | B_BE_RESP_TXCMD_DMAC_PROC_ERR_ISR_EN | \ |
7453 | B_BE_RESP_TXCMD_TX_ST_ABORT_ERR_ISR_EN | \ |
7454 | B_BE_RESP_RX_OVERWRITE_ERR_ISR_EN | \ |
7455 | B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \ |
7456 | B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \ |
7457 | B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN) |
7458 | |
7459 | #define R_BE_PWR_MODULE 0x11900 |
7460 | #define R_BE_PWR_MODULE_C1 0x15900 |
7461 | #define R_BE_PWR_LISTEN_PATH 0x11988 |
7462 | #define B_BE_PWR_LISTEN_PATH_EN GENMASK(31, 28) |
7463 | |
7464 | #define R_BE_PWR_REF_CTRL 0x11A20 |
7465 | #define B_BE_PWR_REF_CTRL_OFDM GENMASK(9, 1) |
7466 | #define B_BE_PWR_REF_CTRL_CCK GENMASK(18, 10) |
7467 | #define B_BE_PWR_OFST_LMT_DB GENMASK(27, 19) |
7468 | #define R_BE_PWR_OFST_LMTBF 0x11A24 |
7469 | #define B_BE_PWR_OFST_LMTBF_DB GENMASK(8, 0) |
7470 | #define R_BE_PWR_FORCE_LMT 0x11A28 |
7471 | #define B_BE_PWR_FORCE_LMT_ON BIT(6) |
7472 | |
7473 | #define R_BE_PWR_RATE_CTRL 0x11A2C |
7474 | #define B_BE_PWR_OFST_BYRATE_DB GENMASK(8, 0) |
7475 | #define B_BE_FORCE_PWR_BY_RATE_EN BIT(19) |
7476 | #define B_BE_FORCE_PWR_BY_RATE_VAL GENMASK(28, 20) |
7477 | |
7478 | #define R_BE_PWR_RATE_OFST_CTRL 0x11A30 |
7479 | #define R_BE_PWR_RATE_OFST_END 0x11A38 |
7480 | #define R_BE_PWR_RULMT_START 0x12048 |
7481 | #define R_BE_PWR_RULMT_END 0x120e4 |
7482 | |
7483 | #define R_BE_PWR_BOOST 0x11A40 |
7484 | #define B_BE_PWR_CTRL_SEL BIT(16) |
7485 | #define B_BE_PWR_FORCE_RATE_ON BIT(29) |
7486 | #define R_BE_PWR_OFST_RULMT 0x11A44 |
7487 | #define B_BE_PWR_OFST_RULMT_DB GENMASK(17, 9) |
7488 | #define B_BE_PWR_FORCE_RU_ON BIT(18) |
7489 | #define B_BE_PWR_FORCE_RU_ENON BIT(28) |
7490 | #define R_BE_PWR_FORCE_MACID 0x11A48 |
7491 | #define B_BE_PWR_FORCE_MACID_ON BIT(9) |
7492 | |
7493 | #define R_BE_PWR_REG_CTRL 0x11A50 |
7494 | #define B_BE_PWR_BT_EN BIT(23) |
7495 | |
7496 | #define R_BE_PWR_COEX_CTRL 0x11A54 |
7497 | #define B_BE_PWR_BT_VAL GENMASK(8, 0) |
7498 | #define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27) |
7499 | |
7500 | #define R_BE_PWR_OFST_SW 0x11AE8 |
7501 | #define B_BE_PWR_OFST_SW_DB GENMASK(27, 24) |
7502 | |
7503 | #define R_BE_PWR_FTM 0x11B00 |
7504 | #define R_BE_PWR_FTM_SS 0x11B04 |
7505 | |
7506 | #define R_BE_PWR_BY_RATE 0x11E00 |
7507 | #define R_BE_PWR_BY_RATE_MAX 0x11FA8 |
7508 | #define R_BE_PWR_LMT 0x11FAC |
7509 | #define R_BE_PWR_LMT_MAX 0x12040 |
7510 | #define R_BE_PWR_BY_RATE_END 0x12044 |
7511 | #define R_BE_PWR_RU_LMT 0x12048 |
7512 | #define R_BE_PWR_RU_LMT_MAX 0x120E4 |
7513 | |
7514 | #define R_BE_C0_TXPWR_IMR 0x128E0 |
7515 | #define R_BE_C0_TXPWR_IMR_C1 0x168E0 |
7516 | #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0) |
7517 | #define B_BE_C0_TXPWR_IMR_CLR B_BE_FSM_TIMEOUT_ERR_INT_EN |
7518 | #define B_BE_C0_TXPWR_IMR_SET B_BE_FSM_TIMEOUT_ERR_INT_EN |
7519 | |
7520 | #define R_BE_TXPWR_ERR_FLAG 0x128E4 |
7521 | #define R_BE_TXPWR_ERR_IMR 0x128E0 |
7522 | #define R_BE_TXPWR_ERR_FLAG_C1 0x158E4 |
7523 | #define R_BE_TXPWR_ERR_IMR_C1 0x158E0 |
7524 | |
7525 | #define CMAC1_START_ADDR_BE 0x14000 |
7526 | #define CMAC1_END_ADDR_BE 0x17FFF |
7527 | |
7528 | #define RR_MOD 0x00 |
7529 | #define RR_MOD_V1 0x10000 |
7530 | #define RR_MOD_IQK GENMASK(19, 4) |
7531 | #define RR_MOD_DPK GENMASK(19, 5) |
7532 | #define RR_MOD_MASK GENMASK(19, 16) |
7533 | #define RR_MOD_DCK GENMASK(14, 10) |
7534 | #define RR_MOD_RGM GENMASK(13, 4) |
7535 | #define RR_MOD_RXB GENMASK(9, 5) |
7536 | #define RR_MOD_V_DOWN 0x0 |
7537 | #define RR_MOD_V_STANDBY 0x1 |
7538 | #define RR_TXAGC 0x10001 |
7539 | #define RR_MOD_V_TX 0x2 |
7540 | #define RR_MOD_V_RX 0x3 |
7541 | #define RR_MOD_V_TXIQK 0x4 |
7542 | #define RR_MOD_V_DPK 0x5 |
7543 | #define RR_MOD_V_RXK1 0x6 |
7544 | #define RR_MOD_V_RXK2 0x7 |
7545 | #define RR_MOD_NBW GENMASK(15, 14) |
7546 | #define RR_MOD_M_RXG GENMASK(13, 4) |
7547 | #define RR_MOD_M_RXBB GENMASK(9, 5) |
7548 | #define RR_MOD_LO_SEL BIT(1) |
7549 | #define RR_MODOPT 0x01 |
7550 | #define RR_TXG_SEL GENMASK(19, 17) |
7551 | #define RR_MODOPT_M_TXPWR GENMASK(5, 0) |
7552 | #define RR_WLSEL 0x02 |
7553 | #define RR_WLSEL_AG GENMASK(18, 16) |
7554 | #define RR_RSV1 0x05 |
7555 | #define RR_RSV1_RST BIT(0) |
7556 | #define RR_BBDC 0x10005 |
7557 | #define RR_BBDC_SEL BIT(0) |
7558 | #define RR_DTXLOK 0x08 |
7559 | #define RR_RSV2 0x09 |
7560 | #define RR_LOKVB 0x0a |
7561 | #define RR_LOKVB_COI GENMASK(19, 14) |
7562 | #define RR_LOKVB_COQ GENMASK(9, 4) |
7563 | #define RR_TXIG 0x11 |
7564 | #define RR_TXIG_TG GENMASK(16, 12) |
7565 | #define RR_TXIG_GR1 GENMASK(6, 4) |
7566 | #define RR_TXIG_GR0 GENMASK(1, 0) |
7567 | #define RR_CHTR 0x17 |
7568 | #define RR_CHTR_MOD GENMASK(11, 10) |
7569 | #define RR_CHTR_TXRX GENMASK(9, 0) |
7570 | #define RR_CFGCH 0x18 |
7571 | #define RR_CFGCH_V1 0x10018 |
7572 | #define RR_CFGCH_BAND1 GENMASK(17, 16) |
7573 | #define CFGCH_BAND1_2G 0 |
7574 | #define CFGCH_BAND1_5G 1 |
7575 | #define CFGCH_BAND1_6G 3 |
7576 | #define RR_CFGCH_POW_LCK BIT(15) |
7577 | #define RR_CFGCH_TRX_AH BIT(14) |
7578 | #define RR_CFGCH_BCN BIT(13) |
7579 | #define RR_CFGCH_BW2 BIT(12) |
7580 | #define RR_CFGCH_BAND0 GENMASK(9, 8) |
7581 | #define CFGCH_BAND0_2G 0 |
7582 | #define CFGCH_BAND0_5G 1 |
7583 | #define CFGCH_BAND0_6G 0 |
7584 | #define RR_CFGCH_BW_V2 GENMASK(12, 10) |
7585 | #define CFGCH_BW_V2_20M 0 |
7586 | #define CFGCH_BW_V2_40M 1 |
7587 | #define CFGCH_BW_V2_80M 2 |
7588 | #define CFGCH_BW_V2_160M 3 |
7589 | #define CFGCH_BW_V2_320M 4 |
7590 | #define RR_CFGCH_BW GENMASK(11, 10) |
7591 | #define RR_CFGCH_CH GENMASK(7, 0) |
7592 | #define CFGCH_BW_20M 3 |
7593 | #define CFGCH_BW_40M 2 |
7594 | #define CFGCH_BW_80M 1 |
7595 | #define CFGCH_BW_160M 0 |
7596 | #define RR_APK 0x19 |
7597 | #define RR_APK_MOD GENMASK(5, 4) |
7598 | #define RR_BTC 0x1a |
7599 | #define RR_BTC_TXBB GENMASK(14, 12) |
7600 | #define RR_BTC_RXBB GENMASK(11, 10) |
7601 | #define RR_RCKC 0x1b |
7602 | #define RR_RCKC_CA GENMASK(14, 10) |
7603 | #define RR_RCKS 0x1c |
7604 | #define RR_RCKO 0x1d |
7605 | #define RR_RCKO_OFF GENMASK(13, 9) |
7606 | #define RR_RXKPLL 0x1e |
7607 | #define RR_RXKPLL_OFF GENMASK(5, 0) |
7608 | #define RR_RXKPLL_POW BIT(19) |
7609 | #define RR_RSV4 0x1f |
7610 | #define RR_RSV4_AGH GENMASK(17, 16) |
7611 | #define RR_RSV4_PLLCH GENMASK(9, 0) |
7612 | #define RR_RXK 0x20 |
7613 | #define RR_RXK_SEL2G BIT(8) |
7614 | #define RR_RXK_SEL5G BIT(7) |
7615 | #define RR_RXK_PLLEN BIT(5) |
7616 | #define RR_LUTWA 0x33 |
7617 | #define RR_LUTWA_MASK GENMASK(9, 0) |
7618 | #define RR_LUTWA_M1 GENMASK(7, 0) |
7619 | #define RR_LUTWA_M2 GENMASK(4, 0) |
7620 | #define RR_LUTWD1 0x3e |
7621 | #define RR_LUTWD0 0x3f |
7622 | #define RR_LUTWD0_MB GENMASK(11, 6) |
7623 | #define RR_LUTWD0_LB GENMASK(5, 0) |
7624 | #define RR_TM 0x42 |
7625 | #define RR_TM_TRI BIT(19) |
7626 | #define RR_TM_VAL_V1 GENMASK(7, 0) |
7627 | #define RR_TM_VAL GENMASK(6, 1) |
7628 | #define RR_TM2 0x43 |
7629 | #define RR_TM2_OFF GENMASK(19, 16) |
7630 | #define RR_TXG1 0x51 |
7631 | #define RR_TXG1_ATT2 BIT(19) |
7632 | #define RR_TXG1_ATT1 BIT(11) |
7633 | #define RR_TXG2 0x52 |
7634 | #define RR_TXG2_ATT0 BIT(11) |
7635 | #define RR_BSPAD 0x54 |
7636 | #define RR_TXGA 0x55 |
7637 | #define RR_TXGA_TRK_EN BIT(7) |
7638 | #define RR_TXGA_LOK_EXT GENMASK(4, 0) |
7639 | #define RR_TXGA_LOK_EN BIT(0) |
7640 | #define RR_TXGA_V1 0x10055 |
7641 | #define RR_TXGA_V1_TRK_EN BIT(7) |
7642 | #define RR_GAINTX 0x56 |
7643 | #define RR_GAINTX_ALL GENMASK(15, 0) |
7644 | #define RR_GAINTX_PAD GENMASK(9, 5) |
7645 | #define RR_GAINTX_BB GENMASK(4, 0) |
7646 | #define RR_TXMO 0x58 |
7647 | #define RR_TXMO_COI GENMASK(19, 15) |
7648 | #define RR_TXMO_COQ GENMASK(14, 10) |
7649 | #define RR_TXMO_FII GENMASK(9, 6) |
7650 | #define RR_TXMO_FIQ GENMASK(5, 2) |
7651 | #define RR_TXA 0x5d |
7652 | #define RR_TXA_TRK GENMASK(19, 14) |
7653 | #define RR_TXRSV 0x5c |
7654 | #define RR_TXRSV_GAPK BIT(19) |
7655 | #define RR_BIAS 0x5e |
7656 | #define RR_BIAS_GAPK BIT(19) |
7657 | #define RR_TXAC 0x5f |
7658 | #define RR_TXAC_IQG GENMASK(3, 0) |
7659 | #define RR_BIASA 0x60 |
7660 | #define RR_BIASA_TXA GENMASK(19, 16) |
7661 | #define RR_BIASA_TXG GENMASK(15, 12) |
7662 | #define RR_BIASD_TXA_V1 GENMASK(15, 12) |
7663 | #define RR_BIASA_TXA_V1 GENMASK(11, 8) |
7664 | #define RR_BIASD_TXG_V1 GENMASK(7, 4) |
7665 | #define RR_BIASA_TXG_V1 GENMASK(3, 0) |
7666 | #define RR_BIASA_A GENMASK(2, 0) |
7667 | #define RR_BIASA2 0x63 |
7668 | #define RR_BIASA2_LB GENMASK(4, 2) |
7669 | #define RR_TXATANK 0x64 |
7670 | #define RR_TXATANK_LBSW2 GENMASK(17, 15) |
7671 | #define RR_TXATANK_LBSW GENMASK(16, 15) |
7672 | #define RR_TXA2 0x65 |
7673 | #define RR_TXA2_LDO GENMASK(19, 16) |
7674 | #define RR_TRXIQ 0x66 |
7675 | #define RR_RSV6 0x6d |
7676 | #define RR_TXVBUF 0x7c |
7677 | #define RR_TXVBUF_DACEN BIT(5) |
7678 | #define RR_TXPOW 0x7f |
7679 | #define RR_TXPOW_TXA BIT(8) |
7680 | #define RR_TXPOW_TXAS BIT(7) |
7681 | #define RR_TXPOW_TXG BIT(1) |
7682 | #define RR_RXPOW 0x80 |
7683 | #define RR_RXPOW_IQK GENMASK(17, 16) |
7684 | #define RR_RXBB 0x83 |
7685 | #define RR_RXBB_VOBUF GENMASK(15, 12) |
7686 | #define RR_RXBB_C2G GENMASK(16, 10) |
7687 | #define RR_RXBB_C2 GENMASK(11, 8) |
7688 | #define RR_RXBB_C1G GENMASK(9, 8) |
7689 | #define RR_RXBB_FATT GENMASK(7, 0) |
7690 | #define RR_RXBB_ATTR GENMASK(7, 4) |
7691 | #define RR_RXBB_ATTC GENMASK(2, 0) |
7692 | #define RR_RXG 0x84 |
7693 | #define RR_RXG_IQKMOD GENMASK(19, 16) |
7694 | #define RR_XGLNA2 0x85 |
7695 | #define RR_XGLNA2_SW GENMASK(1, 0) |
7696 | #define RR_RXAE 0x89 |
7697 | #define RR_RXAE_IQKMOD GENMASK(3, 0) |
7698 | #define RR_RXA 0x8a |
7699 | #define RR_RXA_DPK GENMASK(9, 8) |
7700 | #define RR_RXA_LNA 0x8b |
7701 | #define RR_RXA2 0x8c |
7702 | #define RR_RAA2_SATT GENMASK(15, 13) |
7703 | #define RR_RAA2_SWATT GENMASK(15, 9) |
7704 | #define RR_RXA2_C1 GENMASK(12, 10) |
7705 | #define RR_RXA2_C2 GENMASK(9, 3) |
7706 | #define RR_RXA2_CC2 GENMASK(8, 7) |
7707 | #define RR_RXA2_IATT GENMASK(7, 4) |
7708 | #define RR_RXA2_HATT GENMASK(6, 0) |
7709 | #define RR_RXA2_ATT GENMASK(3, 0) |
7710 | #define RR_RXIQGEN 0x8d |
7711 | #define RR_RXIQGEN_ATTL GENMASK(12, 8) |
7712 | #define RR_RXIQGEN_ATTH GENMASK(14, 13) |
7713 | #define RR_RXBB2 0x8f |
7714 | #define RR_RXBB2_DAC_EN BIT(13) |
7715 | #define RR_RXBB2_CKT BIT(12) |
7716 | #define RR_EN_TIA_IDA GENMASK(11, 10) |
7717 | #define RR_RXBB2_IDAC GENMASK(11, 9) |
7718 | #define RR_RXBB2_EBW GENMASK(6, 5) |
7719 | #define RR_XALNA2 0x90 |
7720 | #define RR_XALNA2_SW2 GENMASK(9, 8) |
7721 | #define RR_XALNA2_SW GENMASK(1, 0) |
7722 | #define RR_DCK 0x92 |
7723 | #define RR_DCK_S1 GENMASK(19, 16) |
7724 | #define RR_DCK_TIA GENMASK(15, 9) |
7725 | #define RR_DCK_DONE GENMASK(7, 5) |
7726 | #define RR_DCK_FINE BIT(1) |
7727 | #define RR_DCK_LV BIT(0) |
7728 | #define RR_DCK1 0x93 |
7729 | #define RR_DCK1_S1 GENMASK(19, 16) |
7730 | #define RR_DCK1_TIA GENMASK(15, 9) |
7731 | #define RR_DCK1_DONE BIT(5) |
7732 | #define RR_DCK1_CLR GENMASK(3, 0) |
7733 | #define RR_DCK1_SEL BIT(3) |
7734 | #define RR_DCK2 0x94 |
7735 | #define RR_DCK2_CYCLE GENMASK(7, 2) |
7736 | #define RR_DCKC 0x95 |
7737 | #define RR_DCKC_CHK BIT(3) |
7738 | #define RR_IQGEN 0x97 |
7739 | #define RR_IQGEN_BIAS GENMASK(11, 8) |
7740 | #define RR_TXIQK 0x98 |
7741 | #define RR_TXIQK_ATT2 GENMASK(15, 12) |
7742 | #define RR_TXIQK_ATT1 GENMASK(6, 0) |
7743 | #define RR_TIA 0x9e |
7744 | #define RR_TIA_N6 BIT(8) |
7745 | #define RR_MIXER 0x9f |
7746 | #define RR_MIXER_GN GENMASK(4, 3) |
7747 | #define RR_POW 0xa0 |
7748 | #define RR_POW_SYN GENMASK(3, 2) |
7749 | #define RR_POW_SYN_V1 GENMASK(3, 0) |
7750 | #define RR_LOGEN 0xa3 |
7751 | #define RR_LOGEN_RPT GENMASK(19, 16) |
7752 | #define RR_SX 0xaf |
7753 | #define RR_IBD 0xc9 |
7754 | #define RR_IBD_VAL GENMASK(4, 0) |
7755 | #define RR_LDO 0xb1 |
7756 | #define RR_LDO_SEL GENMASK(8, 6) |
7757 | #define RR_VCO 0xb2 |
7758 | #define RR_VCO_SEL GENMASK(9, 8) |
7759 | #define RR_VCI 0xb3 |
7760 | #define RR_VCI_ON BIT(7) |
7761 | #define RR_LPF 0xb7 |
7762 | #define RR_LPF_BUSY BIT(8) |
7763 | #define RR_XTALX2 0xb8 |
7764 | #define RR_MALSEL 0xbe |
7765 | #define RR_SYNFB 0xc5 |
7766 | #define RR_SYNFB_LK BIT(15) |
7767 | #define RR_AACK 0xca |
7768 | #define RR_LCKST 0xcf |
7769 | #define RR_LCKST_BIN BIT(0) |
7770 | #define RR_LCK_TRG 0xd3 |
7771 | #define RR_LCK_TRGSEL BIT(8) |
7772 | #define RR_LCK_ST BIT(4) |
7773 | #define RR_MMD 0xd5 |
7774 | #define RR_MMD_RST_EN BIT(8) |
7775 | #define RR_MMD_RST_SYN BIT(6) |
7776 | #define RR_SMD 0xd6 |
7777 | #define RR_VCO2 BIT(19) |
7778 | #define RR_IQKPLL 0xdc |
7779 | #define RR_IQKPLL_MOD GENMASK(9, 8) |
7780 | #define RR_SYNLUT 0xdd |
7781 | #define RR_SYNLUT_MOD BIT(4) |
7782 | #define RR_RCKD 0xde |
7783 | #define RR_RCKD_POW GENMASK(19, 13) |
7784 | #define RR_RCKD_BW BIT(2) |
7785 | #define RR_TXADBG 0xde |
7786 | #define RR_LUTDBG 0xdf |
7787 | #define RR_LUTDBG_TIA BIT(12) |
7788 | #define RR_LUTDBG_LOK BIT(2) |
7789 | #define RR_LUTPLL 0xec |
7790 | #define RR_CAL_RW BIT(19) |
7791 | #define RR_LUTWE2 0xee |
7792 | #define RR_LUTWE2_RTXBW BIT(2) |
7793 | #define RR_LUTWE2_DIS BIT(6) |
7794 | #define RR_LUTWE 0xef |
7795 | #define RR_LUTWE_LOK BIT(2) |
7796 | #define RR_RFC 0xf0 |
7797 | #define RR_WCAL BIT(16) |
7798 | #define RR_RFC_CKEN BIT(1) |
7799 | |
7800 | #define R_UPD_P0 0x0000 |
7801 | #define R_BBCLK 0x0000 |
7802 | #define B_CLK_640M BIT(2) |
7803 | #define R_RSTB_WATCH_DOG 0x000C |
7804 | #define B_P0_RSTB_WATCH_DOG BIT(0) |
7805 | #define B_P1_RSTB_WATCH_DOG BIT(1) |
7806 | #define B_UPD_P0_EN BIT(31) |
7807 | #define R_EMLSR 0x0044 |
7808 | #define B_EMLSR_PARM GENMASK(27, 12) |
7809 | #define R_SPOOF_CG 0x00B4 |
7810 | #define B_SPOOF_CG_EN BIT(17) |
7811 | #define R_CHINFO_SEG 0x00B4 |
7812 | #define B_CHINFO_SEG_LEN GENMASK(2, 0) |
7813 | #define B_CHINFO_SEG GENMASK(16, 7) |
7814 | #define R_DFS_FFT_CG 0x00B8 |
7815 | #define B_DFS_CG_EN BIT(1) |
7816 | #define B_DFS_FFT_EN BIT(0) |
7817 | #define R_CHINFO_DATA 0x00C0 |
7818 | #define B_CHINFO_DATA_BITMAP GENMASK(22, 0) |
7819 | #define R_ANAPAR_PW15 0x030C |
7820 | #define B_ANAPAR_PW15 GENMASK(31, 24) |
7821 | #define B_ANAPAR_PW15_H GENMASK(27, 24) |
7822 | #define B_ANAPAR_PW15_H2 GENMASK(27, 26) |
7823 | #define R_ANAPAR 0x032C |
7824 | #define B_ANAPAR_15 GENMASK(31, 16) |
7825 | #define B_ANAPAR_ADCCLK BIT(30) |
7826 | #define B_ANAPAR_FLTRST BIT(22) |
7827 | #define B_ANAPAR_CRXBB GENMASK(18, 16) |
7828 | #define B_ANAPAR_EN BIT(16) |
7829 | #define B_ANAPAR_14 GENMASK(15, 0) |
7830 | #define R_RFE_E_A2 0x0334 |
7831 | #define R_RFE_O_SEL_A2 0x0338 |
7832 | #define R_RFE_SEL0_A2 0x033C |
7833 | #define B_RFE_SEL0_MASK GENMASK(1, 0) |
7834 | #define R_RFE_SEL32_A2 0x0340 |
7835 | #define R_CIRST 0x035c |
7836 | #define B_CIRST_SYN GENMASK(11, 10) |
7837 | #define R_SWSI_DATA_V1 0x0370 |
7838 | #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0) |
7839 | #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20) |
7840 | #define B_SWSI_DATA_PATH_V1 GENMASK(30, 28) |
7841 | #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31) |
7842 | #define R_SWSI_BIT_MASK_V1 0x0374 |
7843 | #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0) |
7844 | #define R_SWSI_READ_ADDR_V1 0x0378 |
7845 | #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0) |
7846 | #define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8) |
7847 | #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0) |
7848 | #define R_BRK_R 0x0418 |
7849 | #define B_VHTMCS_LMT GENMASK(22, 21) |
7850 | #define B_HTMCS_LMT GENMASK(9, 8) |
7851 | #define R_BRK_EHT 0x0474 |
7852 | #define B_RXEHT_NSS_MAX GENMASK(4, 2) |
7853 | #define R_BRK_RXEHT 0x0478 |
7854 | #define B_RXEHT_N_USER_MAX GENMASK(31, 24) |
7855 | #define B_RXEHTTB_NSS_MAX GENMASK(16, 14) |
7856 | #define R_EN_SND_WO_NDP 0x047c |
7857 | #define R_EN_SND_WO_NDP_C1 0x147c |
7858 | #define B_EN_SND_WO_NDP BIT(1) |
7859 | #define R_BRK_HE 0x0480 |
7860 | #define B_TB_NSS_MAX GENMASK(25, 23) |
7861 | #define B_NSS_MAX GENMASK(16, 14) |
7862 | #define B_N_USR_MAX GENMASK(13, 6) |
7863 | #define R_RXCCA_BE1 0x0520 |
7864 | #define B_RXCCA_BE1_DIS BIT(0) |
7865 | #define R_UPD_CLK_ADC 0x0700 |
7866 | #define B_UPD_CLK_ADC_VAL GENMASK(26, 25) |
7867 | #define B_UPD_CLK_ADC_ON BIT(24) |
7868 | #define B_ENABLE_CCK BIT(5) |
7869 | #define R_RSTB_ASYNC 0x0704 |
7870 | #define B_RSTB_ASYNC_ALL BIT(1) |
7871 | #define R_P0_ANT_SW 0x0728 |
7872 | #define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12) |
7873 | #define B_P0_TRSW_TX_EXTEND GENMASK(3, 0) |
7874 | #define R_MAC_PIN_SEL 0x0734 |
7875 | #define B_CH_IDX_SEG0 GENMASK(23, 16) |
7876 | #define R_PLCP_HISTOGRAM 0x0738 |
7877 | #define B_STS_PARSING_TIME GENMASK(19, 16) |
7878 | #define B_STS_DIS_TRIG_BY_FAIL BIT(3) |
7879 | #define B_STS_DIS_TRIG_BY_BRK BIT(2) |
7880 | #define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL |
7881 | #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2) |
7882 | #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C |
7883 | #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f |
7884 | #define R_PHY_STS_BITMAP_R2T 0x0740 |
7885 | #define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744 |
7886 | #define R_PHY_STS_BITMAP_OFDM_BRK 0x0748 |
7887 | #define R_PHY_STS_BITMAP_CCK_BRK 0x074C |
7888 | #define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750 |
7889 | #define R_PHY_STS_BITMAP_HE_MU 0x0754 |
7890 | #define R_PHY_STS_BITMAP_VHT_MU 0x0758 |
7891 | #define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C |
7892 | #define R_PHY_STS_BITMAP_TRIGBASE 0x0760 |
7893 | #define R_PHY_STS_BITMAP_CCK 0x0764 |
7894 | #define R_PHY_STS_BITMAP_LEGACY 0x0768 |
7895 | #define R_PHY_STS_BITMAP_HT 0x076C |
7896 | #define R_PHY_STS_BITMAP_VHT 0x0770 |
7897 | #define R_PHY_STS_BITMAP_HE 0x0774 |
7898 | #define R_EDCCA_RPTREG_SEL_BE 0x078C |
7899 | #define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20) |
7900 | #define R_PMAC_GNT 0x0980 |
7901 | #define B_PMAC_GNT_TXEN BIT(0) |
7902 | #define B_PMAC_GNT_RXEN BIT(16) |
7903 | #define B_PMAC_GNT_P1 GENMASK(20, 17) |
7904 | #define B_PMAC_GNT_P2 GENMASK(29, 26) |
7905 | #define R_PMAC_RX_CFG1 0x0988 |
7906 | #define B_PMAC_OPT1_MSK GENMASK(11, 0) |
7907 | #define R_PMAC_RXMOD 0x0994 |
7908 | #define B_PMAC_RXMOD_MSK GENMASK(7, 4) |
7909 | #define R_MAC_SEL 0x09A4 |
7910 | #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31) |
7911 | #define B_MAC_SEL GENMASK(19, 17) |
7912 | #define B_MAC_SEL_PWR_EN BIT(16) |
7913 | #define B_MAC_SEL_DPD_EN BIT(10) |
7914 | #define B_MAC_SEL_MOD GENMASK(4, 2) |
7915 | #define R_PMAC_TX_CTRL 0x09C0 |
7916 | #define B_PMAC_TXEN_DIS BIT(0) |
7917 | #define R_PMAC_TX_PRD 0x09C4 |
7918 | #define B_PMAC_TX_PRD_MSK GENMASK(31, 8) |
7919 | #define B_PMAC_CTX_EN BIT(0) |
7920 | #define B_PMAC_PTX_EN BIT(4) |
7921 | #define R_PMAC_TX_CNT 0x09C8 |
7922 | #define B_PMAC_TX_CNT_MSK GENMASK(31, 0) |
7923 | #define R_P80_AT_HIGH_FREQ 0x09D8 |
7924 | #define B_P80_AT_HIGH_FREQ BIT(26) |
7925 | #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10 |
7926 | #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0) |
7927 | #define R_CCX 0x0C00 |
7928 | #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) |
7929 | #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4) |
7930 | #define B_MEASUREMENT_TRIG_MSK BIT(2) |
7931 | #define B_CCX_TRIG_OPT_MSK BIT(1) |
7932 | #define B_CCX_EN_MSK BIT(0) |
7933 | #define R_IFS_COUNTER 0x0C28 |
7934 | #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) |
7935 | #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) |
7936 | #define B_IFS_COUNTER_CLR_MSK BIT(13) |
7937 | #define B_IFS_COLLECT_EN BIT(12) |
7938 | #define R_IFS_T1 0x0C2C |
7939 | #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) |
7940 | #define B_IFS_T1_EN_MSK BIT(15) |
7941 | #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) |
7942 | #define R_IFS_T2 0x0C30 |
7943 | #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) |
7944 | #define B_IFS_T2_EN_MSK BIT(15) |
7945 | #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) |
7946 | #define R_IFS_T3 0x0C34 |
7947 | #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) |
7948 | #define B_IFS_T3_EN_MSK BIT(15) |
7949 | #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) |
7950 | #define R_IFS_T4 0x0C38 |
7951 | #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) |
7952 | #define B_IFS_T4_EN_MSK BIT(15) |
7953 | #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) |
7954 | #define R_PD_CTRL 0x0C3C |
7955 | #define B_PD_HIT_DIS BIT(9) |
7956 | #define R_IOQ_IQK_DPK 0x0C60 |
7957 | #define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0) |
7958 | #define B_IOQ_IQK_DPK_EN BIT(1) |
7959 | #define R_GNT_BT_WGT_EN 0x0C6C |
7960 | #define B_GNT_BT_WGT_EN BIT(21) |
7961 | #define R_IQK_DPK_RST 0x0C6C |
7962 | #define R_IQK_DPK_RST_C1 0x1C6C |
7963 | #define B_IQK_DPK_RST BIT(0) |
7964 | #define R_TX_COLLISION_T2R_ST 0x0C70 |
7965 | #define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20) |
7966 | #define R_TXGATING 0x0C74 |
7967 | #define B_TXGATING_EN BIT(4) |
7968 | #define R_TXRFC 0x0C7C |
7969 | #define R_TXRFC_C1 0x1C7C |
7970 | #define B_TXRFC_RST GENMASK(23, 21) |
7971 | #define R_PD_ARBITER_OFF 0x0C80 |
7972 | #define B_PD_ARBITER_OFF BIT(31) |
7973 | #define R_SNDCCA_A1 0x0C9C |
7974 | #define B_SNDCCA_A1_EN GENMASK(19, 12) |
7975 | #define R_SNDCCA_A2 0x0CA0 |
7976 | #define B_SNDCCA_A2_VAL GENMASK(19, 12) |
7977 | #define R_UDP_COEEF 0x0CBC |
7978 | #define B_UDP_COEEF BIT(19) |
7979 | #define R_TX_COLLISION_T2R_ST_BE 0x0CC8 |
7980 | #define B_TX_COLLISION_T2R_ST_BE_M GENMASK(13, 8) |
7981 | #define R_RXHT_MCS_LIMIT 0x0D18 |
7982 | #define B_RXHT_MCS_LIMIT GENMASK(9, 8) |
7983 | #define R_RXVHT_MCS_LIMIT 0x0D18 |
7984 | #define B_RXVHT_MCS_LIMIT GENMASK(22, 21) |
7985 | #define R_P0_EN_SOUND_WO_NDP 0x0D7C |
7986 | #define B_P0_EN_SOUND_WO_NDP BIT(1) |
7987 | #define R_RXHE 0x0D80 |
7988 | #define B_RXHETB_MAX_NSS GENMASK(25, 23) |
7989 | #define B_RXHE_MAX_NSS GENMASK(16, 14) |
7990 | #define B_RXHE_USER_MAX GENMASK(13, 6) |
7991 | #define R_SPOOF_ASYNC_RST 0x0D84 |
7992 | #define B_SPOOF_ASYNC_RST BIT(15) |
7993 | #define R_NDP_BRK0 0xDA0 |
7994 | #define R_NDP_BRK1 0xDA4 |
7995 | #define B_NDP_RU_BRK BIT(0) |
7996 | #define R_BRK_ASYNC_RST_EN_1 0x0DC0 |
7997 | #define R_BRK_ASYNC_RST_EN_2 0x0DC4 |
7998 | #define R_BRK_ASYNC_RST_EN_3 0x0DC8 |
7999 | #define R_CTLTOP 0x1008 |
8000 | #define B_CTLTOP_ON BIT(23) |
8001 | #define B_CTLTOP_VAL GENMASK(15, 12) |
8002 | #define R_CLK_GCK 0x1008 |
8003 | #define B_CLK_GCK GENMASK(24, 0) |
8004 | #define R_EDCCA_RPT_SEL_BE 0x10CC |
8005 | #define R_ADC_FIFO_V1 0x10FC |
8006 | #define B_ADC_FIFO_EN_V1 GENMASK(31, 24) |
8007 | #define R_S0_HW_SI_DIS 0x1200 |
8008 | #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) |
8009 | #define R_P0_RXCK 0x12A0 |
8010 | #define B_P0_RXCK_ADJ GENMASK(31, 23) |
8011 | #define B_P0_RXCK_BW3 BIT(30) |
8012 | #define B_P0_TXCK_ALL GENMASK(19, 12) |
8013 | #define B_P0_RXCK_ON BIT(19) |
8014 | #define B_P0_RXCK_VAL GENMASK(18, 16) |
8015 | #define B_P0_TXCK_ON BIT(15) |
8016 | #define B_P0_TXCK_VAL GENMASK(14, 12) |
8017 | #define R_P0_RFMODE 0x12AC |
8018 | #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) |
8019 | #define B_P0_RFMODE_MUX GENMASK(11, 4) |
8020 | #define R_P0_RFMODE_ORI_RX 0x12AC |
8021 | #define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12) |
8022 | #define R_P0_RFMODE_FTM_RX 0x12B0 |
8023 | #define B_P0_RFMODE_FTM_RX GENMASK(11, 0) |
8024 | #define R_P0_NRBW 0x12B8 |
8025 | #define B_P0_NRBW_DBG BIT(30) |
8026 | #define R_S0_RXDC 0x12D4 |
8027 | #define B_S0_RXDC_I GENMASK(25, 16) |
8028 | #define B_S0_RXDC_Q GENMASK(31, 26) |
8029 | #define R_S0_RXDC2 0x12D8 |
8030 | #define B_S0_RXDC2_SEL GENMASK(9, 8) |
8031 | #define B_S0_RXDC2_AVG GENMASK(7, 6) |
8032 | #define B_S0_RXDC2_MEN GENMASK(5, 4) |
8033 | #define B_S0_RXDC2_Q2 GENMASK(3, 0) |
8034 | #define R_CFO_COMP_SEG0_L 0x1384 |
8035 | #define R_CFO_COMP_SEG0_H 0x1388 |
8036 | #define R_CFO_COMP_SEG0_CTRL 0x138C |
8037 | #define R_DBG32_D 0x1730 |
8038 | #define R_EDCCA_RPT_A 0x1738 |
8039 | #define R_EDCCA_RPT_B 0x173c |
8040 | #define B_EDCCA_RPT_B_FB BIT(7) |
8041 | #define B_EDCCA_RPT_B_P20 BIT(6) |
8042 | #define B_EDCCA_RPT_B_S20 BIT(5) |
8043 | #define B_EDCCA_RPT_B_S40 BIT(4) |
8044 | #define B_EDCCA_RPT_B_S80 BIT(3) |
8045 | #define B_EDCCA_RPT_B_PATH_MASK GENMASK(2, 1) |
8046 | #define R_SWSI_V1 0x174C |
8047 | #define B_SWSI_W_BUSY_V1 BIT(24) |
8048 | #define B_SWSI_R_BUSY_V1 BIT(25) |
8049 | #define B_SWSI_R_DATA_DONE_V1 BIT(26) |
8050 | #define R_TX_COUNTER 0x1A40 |
8051 | #define R_IFS_CLM_TX_CNT 0x1ACC |
8052 | #define R_IFS_CLM_TX_CNT_V1 0x0ECC |
8053 | #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) |
8054 | #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) |
8055 | #define R_IFS_CLM_CCA 0x1AD0 |
8056 | #define R_IFS_CLM_CCA_V1 0x0ED0 |
8057 | #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) |
8058 | #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) |
8059 | #define R_IFS_CLM_FA 0x1AD4 |
8060 | #define R_IFS_CLM_FA_V1 0x0ED4 |
8061 | #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) |
8062 | #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) |
8063 | #define R_IFS_HIS 0x1AD8 |
8064 | #define R_IFS_HIS_V1 0x0ED8 |
8065 | #define B_IFS_T4_HIS_MSK GENMASK(31, 24) |
8066 | #define B_IFS_T3_HIS_MSK GENMASK(23, 16) |
8067 | #define B_IFS_T2_HIS_MSK GENMASK(15, 8) |
8068 | #define B_IFS_T1_HIS_MSK GENMASK(7, 0) |
8069 | #define R_IFS_AVG_L 0x1ADC |
8070 | #define R_IFS_AVG_L_V1 0x0EDC |
8071 | #define B_IFS_T2_AVG_MSK GENMASK(31, 16) |
8072 | #define B_IFS_T1_AVG_MSK GENMASK(15, 0) |
8073 | #define R_IFS_AVG_H 0x1AE0 |
8074 | #define R_IFS_AVG_H_V1 0x0EE0 |
8075 | #define B_IFS_T4_AVG_MSK GENMASK(31, 16) |
8076 | #define B_IFS_T3_AVG_MSK GENMASK(15, 0) |
8077 | #define R_IFS_CCA_L 0x1AE4 |
8078 | #define R_IFS_CCA_L_V1 0x0EE4 |
8079 | #define B_IFS_T2_CCA_MSK GENMASK(31, 16) |
8080 | #define B_IFS_T1_CCA_MSK GENMASK(15, 0) |
8081 | #define R_IFS_CCA_H 0x1AE8 |
8082 | #define R_IFS_CCA_H_V1 0x0EE8 |
8083 | #define B_IFS_T4_CCA_MSK GENMASK(31, 16) |
8084 | #define B_IFS_T3_CCA_MSK GENMASK(15, 0) |
8085 | #define R_IFSCNT 0x1AEC |
8086 | #define R_IFSCNT_V1 0x0EEC |
8087 | #define B_IFSCNT_DONE_MSK BIT(16) |
8088 | #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0) |
8089 | #define R_TXAGC_TP 0x1C04 |
8090 | #define B_TXAGC_TP GENMASK(2, 0) |
8091 | #define R_TSSI_THER 0x1C10 |
8092 | #define B_TSSI_THER GENMASK(29, 24) |
8093 | #define R_TSSI_CWRPT 0x1C18 |
8094 | #define B_TSSI_CWRPT_RDY BIT(16) |
8095 | #define B_TSSI_CWRPT GENMASK(8, 0) |
8096 | #define R_TXAGC_BTP 0x1CA0 |
8097 | #define B_TXAGC_BTP GENMASK(31, 24) |
8098 | #define R_TXAGC_BB 0x1C60 |
8099 | #define B_TXAGC_BB_OFT GENMASK(31, 16) |
8100 | #define B_TXAGC_BB GENMASK(31, 24) |
8101 | #define B_TXAGC_RF GENMASK(5, 0) |
8102 | #define R_PATH0_TXPWR 0x1C78 |
8103 | #define B_PATH0_TXPWR GENMASK(8, 0) |
8104 | #define R_S0_ADDCK 0x1E00 |
8105 | #define B_S0_ADDCK_I GENMASK(9, 0) |
8106 | #define B_S0_ADDCK_Q GENMASK(19, 10) |
8107 | #define R_EDCCA_RPT_SEL 0x20CC |
8108 | #define B_EDCCA_RPT_SEL_MSK GENMASK(2, 0) |
8109 | #define R_ADC_FIFO 0x20fc |
8110 | #define B_ADC_FIFO_RST GENMASK(31, 24) |
8111 | #define B_ADC_FIFO_RXK GENMASK(31, 16) |
8112 | #define B_ADC_FIFO_A3 BIT(28) |
8113 | #define B_ADC_FIFO_A2 BIT(24) |
8114 | #define B_ADC_FIFO_A1 BIT(20) |
8115 | #define B_ADC_FIFO_A0 BIT(16) |
8116 | #define R_TXFIR0 0x2300 |
8117 | #define B_TXFIR_C01 GENMASK(23, 0) |
8118 | #define R_TXFIR2 0x2304 |
8119 | #define B_TXFIR_C23 GENMASK(23, 0) |
8120 | #define R_TXFIR4 0x2308 |
8121 | #define B_TXFIR_C45 GENMASK(23, 0) |
8122 | #define R_TXFIR6 0x230c |
8123 | #define B_TXFIR_C67 GENMASK(23, 0) |
8124 | #define R_TXFIR8 0x2310 |
8125 | #define B_TXFIR_C89 GENMASK(23, 0) |
8126 | #define R_TXFIRA 0x2314 |
8127 | #define B_TXFIR_CAB GENMASK(23, 0) |
8128 | #define R_TXFIRC 0x2318 |
8129 | #define B_TXFIR_CCD GENMASK(23, 0) |
8130 | #define R_TXFIRE 0x231c |
8131 | #define B_TXFIR_CEF GENMASK(23, 0) |
8132 | #define R_11B_RX_V1 0x2320 |
8133 | #define B_11B_RXCCA_DIS_V1 BIT(0) |
8134 | #define R_RPL_OFST 0x2340 |
8135 | #define B_RPL_OFST_MASK GENMASK(14, 8) |
8136 | #define R_RXCCA 0x2344 |
8137 | #define B_RXCCA_DIS BIT(31) |
8138 | #define R_RXCCA_V1 0x2320 |
8139 | #define B_RXCCA_DIS_V1 BIT(0) |
8140 | #define R_RXSC 0x237C |
8141 | #define B_RXSC_EN BIT(0) |
8142 | #define R_RX_RPL_OFST 0x23AC |
8143 | #define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0) |
8144 | #define R_RXSCOBC 0x23B0 |
8145 | #define B_RXSCOBC_TH GENMASK(18, 0) |
8146 | #define R_RXSCOCCK 0x23B4 |
8147 | #define B_RXSCOCCK_TH GENMASK(18, 0) |
8148 | #define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410 |
8149 | #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14) |
8150 | #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13) |
8151 | #define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10 |
8152 | #define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0) |
8153 | #define R_AFEDAC0 0x2A5C |
8154 | #define B_AFEDAC0 GENMASK(31, 27) |
8155 | #define R_AFEDAC1 0x2A60 |
8156 | #define B_AFEDAC1 GENMASK(2, 0) |
8157 | #define R_IQKDPK_HC 0x2AB8 |
8158 | #define B_IQKDPK_HC BIT(28) |
8159 | #define R_HWSI_ADD0 0x2ADC |
8160 | #define R_HWSI_ADD1 0x2BDC |
8161 | #define B_HWSI_ADD_MASK GENMASK(11, 4) |
8162 | #define B_HWSI_ADD_CTL_MASK GENMASK(2, 0) |
8163 | #define B_HWSI_ADD_RD BIT(2) |
8164 | #define B_HWSI_ADD_POLL_MASK GENMASK(1, 0) |
8165 | #define B_HWSI_ADD_RUN BIT(1) |
8166 | #define B_HWSI_ADD_BUSY BIT(0) |
8167 | #define R_HWSI_DATA 0x2AE0 |
8168 | #define B_HWSI_DATA_VAL GENMASK(27, 8) |
8169 | #define B_HWSI_DATA_ADDR GENMASK(7, 0) |
8170 | #define R_HWSI_VAL0 0x2C24 |
8171 | #define R_HWSI_VAL1 0x2D24 |
8172 | #define B_HWSI_VAL_RDONE BIT(31) |
8173 | #define B_HWSI_VAL_BUSY BIT(29) |
8174 | #define R_P1_EN_SOUND_WO_NDP 0x2D7C |
8175 | #define B_P1_EN_SOUND_WO_NDP BIT(1) |
8176 | #define R_EDCCA_RPT_A_BE 0x2E38 |
8177 | #define R_EDCCA_RPT_B_BE 0x2E3C |
8178 | #define R_S1_HW_SI_DIS 0x3200 |
8179 | #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) |
8180 | #define R_P1_RXCK 0x32A0 |
8181 | #define B_P1_RXCK_BW3 BIT(30) |
8182 | #define B_P1_TXCK_ALL GENMASK(19, 12) |
8183 | #define B_P1_RXCK_ON BIT(19) |
8184 | #define B_P1_RXCK_VAL GENMASK(18, 16) |
8185 | #define R_P1_RFMODE 0x32AC |
8186 | #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) |
8187 | #define B_P1_RFMODE_MUX GENMASK(11, 4) |
8188 | #define R_P1_RFMODE_ORI_RX 0x32AC |
8189 | #define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12) |
8190 | #define R_P1_RFMODE_FTM_RX 0x32B0 |
8191 | #define B_P1_RFMODE_FTM_RX GENMASK(11, 0) |
8192 | #define R_P1_DBGMOD 0x32B8 |
8193 | #define B_P1_DBGMOD_ON BIT(30) |
8194 | #define R_S1_RXDC 0x32D4 |
8195 | #define B_S1_RXDC_I GENMASK(25, 16) |
8196 | #define B_S1_RXDC_Q GENMASK(31, 26) |
8197 | #define R_S1_RXDC2 0x32D8 |
8198 | #define B_S1_RXDC2_EN GENMASK(5, 4) |
8199 | #define B_S1_RXDC2_SEL GENMASK(9, 8) |
8200 | #define B_S1_RXDC2_Q2 GENMASK(3, 0) |
8201 | #define R_TXAGC_BB_S1 0x3C60 |
8202 | #define B_TXAGC_BB_S1_OFT GENMASK(31, 16) |
8203 | #define B_TXAGC_BB_S1 GENMASK(31, 24) |
8204 | #define R_PATH1_TXPWR 0x3C78 |
8205 | #define B_PATH1_TXPWR GENMASK(8, 0) |
8206 | #define R_S1_ADDCK 0x3E00 |
8207 | #define B_S1_ADDCK_I GENMASK(9, 0) |
8208 | #define B_S1_ADDCK_Q GENMASK(19, 10) |
8209 | #define R_OP1DB_A 0x40B0 |
8210 | #define B_OP1DB_A GENMASK(31, 24) |
8211 | #define R_OP1DB1_A 0x40BC |
8212 | #define B_TIA10_A GENMASK(15, 0) |
8213 | #define B_TIA1_A GENMASK(15, 8) |
8214 | #define B_TIA0_A GENMASK(7, 0) |
8215 | #define R_BKOFF_A 0x40E0 |
8216 | #define B_BKOFF_IBADC_A GENMASK(23, 18) |
8217 | #define R_BACKOFF_A 0x40E4 |
8218 | #define B_LNA_IBADC_A GENMASK(29, 18) |
8219 | #define B_BACKOFF_LNA_A GENMASK(29, 24) |
8220 | #define B_BACKOFF_IBADC_A GENMASK(23, 18) |
8221 | #define R_RXBY_WBADC_A 0x40F4 |
8222 | #define B_RXBY_WBADC_A GENMASK(14, 10) |
8223 | #define R_MUIC 0x40F8 |
8224 | #define B_MUIC_EN BIT(0) |
8225 | #define R_BT_RXBY_WBADC_A 0x4160 |
8226 | #define B_BT_RXBY_WBADC_A BIT(31) |
8227 | #define R_BT_SHARE_A 0x4164 |
8228 | #define B_BT_SHARE_A BIT(0) |
8229 | #define B_BT_TRK_OFF_A BIT(1) |
8230 | #define B_BTG_PATH_A BIT(4) |
8231 | #define R_FORCE_FIR_A 0x418C |
8232 | #define B_FORCE_FIR_A GENMASK(1, 0) |
8233 | #define R_DCFO 0x4264 |
8234 | #define B_DCFO GENMASK(7, 0) |
8235 | #define R_SEG0CSI 0x42AC |
8236 | #define R_SEG0CSI_V1 0x42B0 |
8237 | #define B_SEG0CSI_IDX GENMASK(10, 0) |
8238 | #define R_SEG0CSI_EN 0x42C4 |
8239 | #define R_SEG0CSI_EN_V1 0x42C8 |
8240 | #define B_SEG0CSI_EN BIT(23) |
8241 | #define R_BSS_CLR_MAP 0x43ac |
8242 | #define R_BSS_CLR_MAP_V1 0x43B0 |
8243 | #define R_BSS_CLR_MAP_V2 0x4EB0 |
8244 | #define B_BSS_CLR_MAP_VLD0 BIT(28) |
8245 | #define B_BSS_CLR_MAP_TGT GENMASK(27, 22) |
8246 | #define B_BSS_CLR_MAP_STAID GENMASK(21, 11) |
8247 | #define R_CFO_TRK0 0x4404 |
8248 | #define R_CFO_TRK1 0x440C |
8249 | #define B_CFO_TRK_MSK GENMASK(14, 10) |
8250 | #define R_T2F_GI_COMB 0x4424 |
8251 | #define B_T2F_GI_COMB_EN BIT(2) |
8252 | #define R_BT_DYN_DC_EST_EN 0x441C |
8253 | #define R_BT_DYN_DC_EST_EN_V1 0x4420 |
8254 | #define B_BT_DYN_DC_EST_EN_MSK BIT(31) |
8255 | #define R_ASSIGN_SBD_OPT_V1 0x4440 |
8256 | #define B_ASSIGN_SBD_OPT_EN_V1 BIT(31) |
8257 | #define R_ASSIGN_SBD_OPT 0x4450 |
8258 | #define B_ASSIGN_SBD_OPT_EN BIT(24) |
8259 | #define R_DCFO_COMP_S0 0x448C |
8260 | #define B_DCFO_COMP_S0_MSK GENMASK(11, 0) |
8261 | #define R_DCFO_WEIGHT 0x4490 |
8262 | #define B_DCFO_WEIGHT_MSK GENMASK(27, 24) |
8263 | #define R_DCFO_OPT 0x4494 |
8264 | #define B_DCFO_OPT_EN BIT(29) |
8265 | #define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24) |
8266 | #define R_BANDEDGE 0x4498 |
8267 | #define B_BANDEDGE_EN BIT(30) |
8268 | #define R_DPD_BF 0x44a0 |
8269 | #define B_DPD_BF_OFDM GENMASK(16, 12) |
8270 | #define B_DPD_BF_SCA GENMASK(6, 0) |
8271 | #define R_LNA_OP 0x44B0 |
8272 | #define B_LNA6 GENMASK(31, 24) |
8273 | #define R_LNA_TIA 0x44BC |
8274 | #define B_TIA10_B GENMASK(15, 0) |
8275 | #define B_TIA1_B GENMASK(15, 8) |
8276 | #define B_TIA0_B GENMASK(7, 0) |
8277 | #define R_BKOFF_B 0x44E0 |
8278 | #define B_BKOFF_IBADC_B GENMASK(23, 18) |
8279 | #define R_BACKOFF_B 0x44E4 |
8280 | #define B_LNA_IBADC_B GENMASK(29, 18) |
8281 | #define B_BACKOFF_LNA_B GENMASK(29, 24) |
8282 | #define B_BACKOFF_IBADC_B GENMASK(23, 18) |
8283 | #define R_RXBY_WBADC_B 0x44F4 |
8284 | #define B_RXBY_WBADC_B GENMASK(14, 10) |
8285 | #define R_BT_RXBY_WBADC_B 0x4560 |
8286 | #define B_BT_RXBY_WBADC_B BIT(31) |
8287 | #define R_BT_SHARE_B 0x4564 |
8288 | #define B_BT_SHARE_B BIT(0) |
8289 | #define B_BT_TRK_OFF_B BIT(1) |
8290 | #define B_BTG_PATH_B BIT(4) |
8291 | #define R_TXPATH_SEL 0x458C |
8292 | #define B_TXPATH_SEL_MSK GENMASK(31, 28) |
8293 | #define R_FORCE_FIR_B 0x458C |
8294 | #define B_FORCE_FIR_B GENMASK(1, 0) |
8295 | #define R_TXPWR 0x4594 |
8296 | #define B_TXPWR_MSK GENMASK(30, 22) |
8297 | #define R_TXNSS_MAP 0x45B4 |
8298 | #define B_TXNSS_MAP_MSK GENMASK(20, 17) |
8299 | #define R_PCOEFF0_V1 0x45BC |
8300 | #define B_PCOEFF01_MSK_V1 GENMASK(23, 0) |
8301 | #define R_PCOEFF2_V1 0x45CC |
8302 | #define B_PCOEFF23_MSK_V1 GENMASK(23, 0) |
8303 | #define R_PCOEFF4_V1 0x45D0 |
8304 | #define B_PCOEFF45_MSK_V1 GENMASK(23, 0) |
8305 | #define R_PCOEFF6_V1 0x45D4 |
8306 | #define B_PCOEFF67_MSK_V1 GENMASK(23, 0) |
8307 | #define R_PCOEFF8_V1 0x45D8 |
8308 | #define B_PCOEFF89_MSK_V1 GENMASK(23, 0) |
8309 | #define R_PCOEFFA_V1 0x45C0 |
8310 | #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0) |
8311 | #define R_PCOEFFC_V1 0x45C4 |
8312 | #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0) |
8313 | #define R_PCOEFFE_V1 0x45C8 |
8314 | #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0) |
8315 | #define R_PATH0_IB_PKPW 0x4628 |
8316 | #define B_PATH0_IB_PKPW_MSK GENMASK(11, 6) |
8317 | #define R_PATH0_LNA_ERR1 0x462C |
8318 | #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24) |
8319 | #define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12) |
8320 | #define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6) |
8321 | #define R_PATH0_LNA_ERR2 0x4630 |
8322 | #define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18) |
8323 | #define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12) |
8324 | #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0) |
8325 | #define R_PATH0_LNA_ERR3 0x4634 |
8326 | #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24) |
8327 | #define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18) |
8328 | #define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6) |
8329 | #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0) |
8330 | #define R_PATH0_LNA_ERR4 0x4638 |
8331 | #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24) |
8332 | #define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12) |
8333 | #define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6) |
8334 | #define R_PATH0_LNA_ERR5 0x463C |
8335 | #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0) |
8336 | #define R_PATH0_TIA_ERR_G0 0x4640 |
8337 | #define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18) |
8338 | #define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12) |
8339 | #define R_PATH0_TIA_ERR_G1 0x4644 |
8340 | #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30) |
8341 | #define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6) |
8342 | #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0) |
8343 | #define R_PATH0_IB_PBK 0x4650 |
8344 | #define B_PATH0_IB_PBK_MSK GENMASK(14, 10) |
8345 | #define R_PATH0_RXB_INIT 0x4658 |
8346 | #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5) |
8347 | #define R_PATH0_LNA_INIT 0x4668 |
8348 | #define R_PATH0_LNA_INIT_V1 0x472C |
8349 | #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24) |
8350 | #define R_PATH0_BTG 0x466C |
8351 | #define B_PATH0_BTG_SHEN GENMASK(18, 17) |
8352 | #define R_PATH0_TIA_INIT 0x4674 |
8353 | #define B_PATH0_TIA_INIT_IDX_MSK BIT(17) |
8354 | #define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0 |
8355 | #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24 |
8356 | #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8 |
8357 | #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3 0x41C8 |
8358 | #define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) |
8359 | #define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4 |
8360 | #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28 |
8361 | #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC |
8362 | #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3 0x41CC |
8363 | #define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) |
8364 | #define R_PATH0_RXB_INIT_V1 0x46A8 |
8365 | #define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10) |
8366 | #define R_PATH0_G_LNA6_OP1DB_V1 0x4688 |
8367 | #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24) |
8368 | #define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694 |
8369 | #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0) |
8370 | #define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694 |
8371 | #define B_PATH0_R_G_OFST_MASK GENMASK(23, 16) |
8372 | #define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8) |
8373 | #define R_CDD_EVM_CHK_EN 0x46C0 |
8374 | #define B_CDD_EVM_CHK_EN BIT(0) |
8375 | #define R_PATH0_BAND_SEL_V1 0x4738 |
8376 | #define B_PATH0_BAND_SEL_MSK_V1 BIT(17) |
8377 | #define R_PATH0_BT_SHARE_V1 0x4738 |
8378 | #define B_PATH0_BT_SHARE_V1 BIT(19) |
8379 | #define R_PATH0_BTG_PATH_V1 0x4738 |
8380 | #define B_PATH0_BTG_PATH_V1 BIT(22) |
8381 | #define R_P0_NBIIDX 0x469C |
8382 | #define B_P0_NBIIDX_VAL GENMASK(11, 0) |
8383 | #define B_P0_NBIIDX_NOTCH_EN BIT(12) |
8384 | #define R_P0_BACKOFF_IBADC_V1 0x469C |
8385 | #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26) |
8386 | #define B_P0_NBIIDX_NOTCH_EN_V1 BIT(12) |
8387 | #define R_P1_MODE 0x4718 |
8388 | #define B_P1_MODE_SEL GENMASK(31, 30) |
8389 | #define R_P0_AGC_CTL 0x4730 |
8390 | #define B_P0_AGC_EN BIT(31) |
8391 | #define R_PATH1_LNA_INIT 0x473C |
8392 | #define R_PATH1_LNA_INIT_V1 0x4A80 |
8393 | #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24) |
8394 | #define R_PATH0_TIA_INIT_V1 0x473C |
8395 | #define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9) |
8396 | #define R_PATH1_TIA_INIT 0x4748 |
8397 | #define B_PATH1_TIA_INIT_IDX_MSK BIT(17) |
8398 | #define R_PATH1_BTG 0x4740 |
8399 | #define B_PATH1_BTG_SHEN GENMASK(18, 17) |
8400 | #define R_PATH1_RXB_INIT 0x472C |
8401 | #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5) |
8402 | #define R_PATH1_G_LNA6_OP1DB_V1 0x476C |
8403 | #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24) |
8404 | #define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774 |
8405 | #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8 |
8406 | #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8 |
8407 | #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3 0x45C8 |
8408 | #define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) |
8409 | #define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778 |
8410 | #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC |
8411 | #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC |
8412 | #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3 0x45CC |
8413 | #define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) |
8414 | #define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778 |
8415 | #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0) |
8416 | #define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778 |
8417 | #define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8) |
8418 | #define R_PATH1_BAND_SEL_V1 0x4AA4 |
8419 | #define B_PATH1_BAND_SEL_MSK_V1 BIT(17) |
8420 | #define R_PATH1_BT_SHARE_V1 0x4AA4 |
8421 | #define B_PATH1_BT_SHARE_V1 BIT(19) |
8422 | #define R_PATH1_BTG_PATH_V1 0x4AA4 |
8423 | #define B_PATH1_BTG_PATH_V1 BIT(22) |
8424 | #define R_P1_NBIIDX 0x4770 |
8425 | #define B_P1_NBIIDX_VAL GENMASK(11, 0) |
8426 | #define B_P1_NBIIDX_NOTCH_EN BIT(12) |
8427 | #define R_PKT_CTRL 0x47D4 |
8428 | #define B_PKT_POP_EN BIT(8) |
8429 | #define R_SEG0R_PD 0x481C |
8430 | #define R_SEG0R_PD_V1 0x4860 |
8431 | #define R_SEG0R_PD_V2 0x6A74 |
8432 | #define R_SEG0R_EDCCA_LVL 0x4840 |
8433 | #define R_SEG0R_EDCCA_LVL_V1 0x4884 |
8434 | #define B_EDCCA_LVL_MSK3 GENMASK(31, 24) |
8435 | #define B_EDCCA_LVL_MSK1 GENMASK(15, 8) |
8436 | #define B_EDCCA_LVL_MSK0 GENMASK(7, 0) |
8437 | #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30) |
8438 | #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29) |
8439 | #define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6) |
8440 | #define R_2P4G_BAND 0x4970 |
8441 | #define B_2P4G_BAND_SEL BIT(1) |
8442 | #define R_FC0_BW 0x4974 |
8443 | #define R_FC0_BW_V1 0x49C0 |
8444 | #define B_FC0_BW_SET GENMASK(31, 30) |
8445 | #define B_ANT_RX_BT_SEG0 GENMASK(25, 22) |
8446 | #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18) |
8447 | #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14) |
8448 | #define B_FC0_BW_INV GENMASK(6, 0) |
8449 | #define R_Q_MATRIX_00 0x497C |
8450 | #define B_Q_MATRIX_00_IMAGINARY GENMASK(15, 0) |
8451 | #define B_Q_MATRIX_00_REAL GENMASK(31, 16) |
8452 | #define R_CHBW_MOD 0x4978 |
8453 | #define R_CHBW_MOD_V1 0x49C4 |
8454 | #define B_BT_SHARE BIT(14) |
8455 | #define B_CHBW_MOD_SBW GENMASK(13, 12) |
8456 | #define B_CHBW_MOD_PRICH GENMASK(11, 8) |
8457 | #define B_ANT_RX_SEG0 GENMASK(3, 0) |
8458 | #define R_Q_MATRIX_11 0x4988 |
8459 | #define B_Q_MATRIX_11_IMAGINARY GENMASK(15, 0) |
8460 | #define B_Q_MATRIX_11_REAL GENMASK(31, 16) |
8461 | #define R_CUSTOMIZE_Q_MATRIX 0x498C |
8462 | #define B_CUSTOMIZE_Q_MATRIX_EN BIT(0) |
8463 | #define R_P0_RPL1 0x49B0 |
8464 | #define B_P0_RPL1_41_MASK GENMASK(31, 24) |
8465 | #define B_P0_RPL1_40_MASK GENMASK(23, 16) |
8466 | #define B_P0_RPL1_20_MASK GENMASK(15, 8) |
8467 | #define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK) |
8468 | #define B_P0_RPL1_SHIFT 8 |
8469 | #define B_P0_RPL1_BIAS_MASK GENMASK(7, 0) |
8470 | #define R_P0_RPL2 0x49B4 |
8471 | #define B_P0_RTL2_8A_MASK GENMASK(31, 24) |
8472 | #define B_P0_RTL2_81_MASK GENMASK(23, 16) |
8473 | #define B_P0_RTL2_80_MASK GENMASK(15, 8) |
8474 | #define B_P0_RTL2_42_MASK GENMASK(7, 0) |
8475 | #define R_P0_RPL3 0x49B8 |
8476 | #define B_P0_RTL3_89_MASK GENMASK(31, 24) |
8477 | #define B_P0_RTL3_84_MASK GENMASK(23, 16) |
8478 | #define B_P0_RTL3_83_MASK GENMASK(15, 8) |
8479 | #define B_P0_RTL3_82_MASK GENMASK(7, 0) |
8480 | #define R_PD_BOOST_EN 0x49E8 |
8481 | #define B_PD_BOOST_EN BIT(7) |
8482 | #define R_P1_BACKOFF_IBADC_V1 0x49F0 |
8483 | #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26) |
8484 | #define R_P1_RPL1 0x4A00 |
8485 | #define R_P1_RPL2 0x4A04 |
8486 | #define R_P1_RPL3 0x4A08 |
8487 | #define R_BK_FC0_INV_V1 0x4A1C |
8488 | #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0) |
8489 | #define R_CCK_FC0_INV_V1 0x4A20 |
8490 | #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0) |
8491 | #define R_PATH1_RXB_INIT_V1 0x4A5C |
8492 | #define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10) |
8493 | #define R_P1_AGC_CTL 0x4A9C |
8494 | #define B_P1_AGC_EN BIT(31) |
8495 | #define R_PATH1_TIA_INIT_V1 0x4AA8 |
8496 | #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9) |
8497 | #define R_P0_AGC_RSVD 0x4ACC |
8498 | #define R_PATH0_RXBB_V1 0x4AD4 |
8499 | #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0) |
8500 | #define R_P1_AGC_RSVD 0x4AD8 |
8501 | #define R_PATH1_RXBB_V1 0x4AE0 |
8502 | #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0) |
8503 | #define R_PATH0_BT_BACKOFF_V1 0x4AE4 |
8504 | #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0) |
8505 | #define R_PATH1_BT_BACKOFF_V1 0x4AEC |
8506 | #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0) |
8507 | #define R_DCFO_COMP_S0_V2 0x4B20 |
8508 | #define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0) |
8509 | #define R_PATH0_TX_CFR 0x4B30 |
8510 | #define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10) |
8511 | #define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0) |
8512 | #define R_PATH0_TX_POLAR_CLIPPING 0x4B3C |
8513 | #define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16) |
8514 | #define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12) |
8515 | #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00 |
8516 | #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) |
8517 | #define R_PATH0_NOTCH 0x4C14 |
8518 | #define B_PATH0_NOTCH_EN BIT(12) |
8519 | #define B_PATH0_NOTCH_VAL GENMASK(11, 0) |
8520 | #define R_PATH0_NOTCH2 0x4C20 |
8521 | #define B_PATH0_NOTCH2_EN BIT(12) |
8522 | #define B_PATH0_NOTCH2_VAL GENMASK(11, 0) |
8523 | #define R_PATH0_5MDET 0x4C4C |
8524 | #define R_PATH0_5MDET_V1 0x46F8 |
8525 | #define B_PATH0_5MDET_EN BIT(12) |
8526 | #define B_PATH0_5MDET_SB2 BIT(8) |
8527 | #define B_PATH0_5MDET_SB0 BIT(6) |
8528 | #define B_PATH0_5MDET_TH GENMASK(5, 0) |
8529 | #define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4 |
8530 | #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) |
8531 | #define R_PATH1_NOTCH 0x4CD8 |
8532 | #define B_PATH1_NOTCH_EN BIT(12) |
8533 | #define B_PATH1_NOTCH_VAL GENMASK(11, 0) |
8534 | #define R_PATH1_NOTCH2 0x4CE4 |
8535 | #define B_PATH1_NOTCH2_EN BIT(12) |
8536 | #define B_PATH1_NOTCH2_VAL GENMASK(11, 0) |
8537 | #define R_PATH1_5MDET 0x4D10 |
8538 | #define R_PATH1_5MDET_V1 0x47B8 |
8539 | #define B_PATH1_5MDET_EN BIT(12) |
8540 | #define B_PATH1_5MDET_SB2 BIT(8) |
8541 | #define B_PATH1_5MDET_SB0 BIT(6) |
8542 | #define B_PATH1_5MDET_TH GENMASK(5, 0) |
8543 | #define R_S0S1_CSI_WGT 0x4D34 |
8544 | #define B_S0S1_CSI_WGT_EN BIT(0) |
8545 | #define B_S0S1_CSI_WGT_TONE_IDX GENMASK(31, 20) |
8546 | #define R_CHINFO_ELM_SRC 0x4D84 |
8547 | #define B_CHINFO_ELM_BITMAP GENMASK(22, 0) |
8548 | #define B_CHINFO_SRC GENMASK(31, 30) |
8549 | #define R_CHINFO_TYPE_SCAL 0x4D88 |
8550 | #define B_CHINFO_TYPE GENMASK(2, 1) |
8551 | #define B_CHINFO_SCAL BIT(8) |
8552 | #define R_RPL_BIAS_COMP 0x4DF0 |
8553 | #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0) |
8554 | #define R_RPL_PATHAB 0x4E0C |
8555 | #define B_RPL_PATHB_MASK GENMASK(23, 16) |
8556 | #define B_RPL_PATHA_MASK GENMASK(15, 8) |
8557 | #define 0x4E2C |
8558 | #define GENMASK(15, 8) |
8559 | #define GENMASK(7, 0) |
8560 | #define R_FC0_V1 0x4E30 |
8561 | #define B_FC0_MSK_V1 GENMASK(12, 0) |
8562 | #define R_RX_BW40_2XFFT_EN_V1 0x4E30 |
8563 | #define B_RX_BW40_2XFFT_EN_MSK_V1 BIT(26) |
8564 | #define R_DCFO_COMP_S0_V1 0x4A40 |
8565 | #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0) |
8566 | #define R_BMODE_PDTH_V1 0x4B64 |
8567 | #define R_BMODE_PDTH_V2 0x6708 |
8568 | #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24) |
8569 | #define R_BMODE_PDTH_EN_V1 0x4B74 |
8570 | #define R_BMODE_PDTH_EN_V2 0x6718 |
8571 | #define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30) |
8572 | #define R_BSS_CLR_VLD_V2 0x4EBC |
8573 | #define B_BSS_CLR_VLD0_V2 BIT(2) |
8574 | #define R_CFO_COMP_SEG1_L 0x5384 |
8575 | #define R_CFO_COMP_SEG1_H 0x5388 |
8576 | #define R_CFO_COMP_SEG1_CTRL 0x538C |
8577 | #define B_CFO_COMP_VALID_BIT BIT(29) |
8578 | #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) |
8579 | #define B_CFO_COMP_VAL_MSK GENMASK(11, 0) |
8580 | #define R_TSSI_PA_K1 0x5600 |
8581 | #define R_TSSI_PA_K2 0x5604 |
8582 | #define R_P0_TSSI_ALIM1 0x5630 |
8583 | #define B_P0_TSSI_ALIM1 GENMASK(29, 0) |
8584 | #define B_P0_TSSI_ALIM11 GENMASK(29, 20) |
8585 | #define B_P0_TSSI_ALIM12 GENMASK(19, 10) |
8586 | #define B_P0_TSSI_ALIM13 GENMASK(9, 0) |
8587 | #define R_P0_TSSI_ALIM3 0x5634 |
8588 | #define B_P0_TSSI_ALIM31 GENMASK(9, 0) |
8589 | #define R_TSSI_PA_K5 0x5638 |
8590 | #define R_P0_TSSI_ALIM2 0x563c |
8591 | #define B_P0_TSSI_ALIM2 GENMASK(29, 0) |
8592 | #define R_P0_TSSI_ALIM4 0x5640 |
8593 | #define R_TSSI_PA_K8 0x5644 |
8594 | #define R_P0_TSSI_ADC_CLK 0x566c |
8595 | #define B_P0_TSSI_ADC_CLK GENMASK(17, 16) |
8596 | #define R_UPD_CLK 0x5670 |
8597 | #define B_DAC_VAL BIT(31) |
8598 | #define B_ACK_VAL GENMASK(30, 29) |
8599 | #define B_DPD_DIS BIT(14) |
8600 | #define B_DPD_GDIS BIT(13) |
8601 | #define B_IQK_RFC_ON BIT(1) |
8602 | #define R_TXPWRB 0x56CC |
8603 | #define B_TXPWRB_ON BIT(28) |
8604 | #define B_TXPWRB_VAL GENMASK(27, 19) |
8605 | #define R_DPD_OFT_EN 0x5800 |
8606 | #define B_DPD_OFT_EN BIT(28) |
8607 | #define B_DPD_TSSI_CW GENMASK(26, 18) |
8608 | #define B_DPD_PWR_CW GENMASK(17, 9) |
8609 | #define B_DPD_REF GENMASK(8, 0) |
8610 | #define R_P0_TSSIC 0x5814 |
8611 | #define B_P0_TSSIC_BYPASS BIT(11) |
8612 | #define R_DPD_OFT_ADDR 0x5804 |
8613 | #define B_DPD_OFT_ADDR GENMASK(31, 27) |
8614 | #define R_TXPWRB_H 0x580c |
8615 | #define B_TXPWRB_RDY BIT(15) |
8616 | #define R_P0_TMETER 0x5810 |
8617 | #define B_P0_TMETER GENMASK(15, 10) |
8618 | #define B_P0_TMETER_DIS BIT(16) |
8619 | #define B_P0_TMETER_TRK BIT(24) |
8620 | #define R_P1_TSSIC 0x7814 |
8621 | #define B_P1_TSSIC_BYPASS BIT(11) |
8622 | #define R_P0_TSSI_TRK 0x5818 |
8623 | #define B_P0_TSSI_TRK_EN BIT(30) |
8624 | #define B_P0_TSSI_RFC GENMASK(28, 27) |
8625 | #define B_P0_TSSI_OFT_EN BIT(28) |
8626 | #define B_P0_TSSI_OFT GENMASK(7, 0) |
8627 | #define R_P0_TSSI_AVG 0x5820 |
8628 | #define B_P0_TSSI_EN BIT(31) |
8629 | #define B_P0_TSSI_AVG GENMASK(15, 12) |
8630 | #define R_P0_RFCTM 0x5864 |
8631 | #define B_P0_RFCTM_EN BIT(29) |
8632 | #define B_P0_RFCTM_VAL GENMASK(25, 20) |
8633 | #define R_P0_RFCTM_RDY BIT(26) |
8634 | #define R_P0_TRSW 0x5868 |
8635 | #define B_P0_BT_FORCE_ANTIDX_EN BIT(12) |
8636 | #define B_P0_TRSW_X BIT(2) |
8637 | #define B_P0_TRSW_A BIT(1) |
8638 | #define B_P0_TX_ANT_SEL BIT(1) |
8639 | #define B_P0_TRSW_B BIT(0) |
8640 | #define B_P0_ANT_TRAIN_EN BIT(0) |
8641 | #define B_P0_TRSW_SO_A2 GENMASK(7, 5) |
8642 | #define R_P0_ANTSEL 0x586C |
8643 | #define B_P0_ANTSEL_SW_5G BIT(25) |
8644 | #define B_P0_ANTSEL_SW_2G BIT(23) |
8645 | #define B_P0_ANTSEL_BTG_TRX BIT(21) |
8646 | #define B_P0_ANTSEL_CGCS_CTRL BIT(17) |
8647 | #define B_P0_ANTSEL_HW_CTRL BIT(16) |
8648 | #define B_P0_ANTSEL_TX_ORI GENMASK(15, 12) |
8649 | #define B_P0_ANTSEL_RX_ALT GENMASK(11, 8) |
8650 | #define B_P0_ANTSEL_RX_ORI GENMASK(7, 4) |
8651 | #define R_RFSW_CTRL_ANT0_BASE 0x5870 |
8652 | #define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0) |
8653 | #define R_RFE_SEL0_BASE 0x5880 |
8654 | #define B_RFE_SEL0_SRC_MASK GENMASK(3, 0) |
8655 | #define R_RFE_SEL32_BASE 0x5884 |
8656 | #define RFE_SEL0_SRC_ANTSEL_0 8 |
8657 | #define R_RFE_INV0 0x5890 |
8658 | #define R_P0_RFM 0x5894 |
8659 | #define B_P0_RFM_DIS_WL BIT(7) |
8660 | #define B_P0_RFM_TX_OPT BIT(6) |
8661 | #define B_P0_RFM_BT_EN BIT(5) |
8662 | #define B_P0_RFM_OUT GENMASK(4, 0) |
8663 | #define R_P0_PATH_RST 0x58AC |
8664 | #define R_P0_TXDPD 0x58D4 |
8665 | #define B_P0_TXDPD GENMASK(31, 28) |
8666 | #define R_P0_TXPW_RSTB 0x58DC |
8667 | #define B_P0_TXPW_RSTB_MANON BIT(30) |
8668 | #define B_P0_TXPW_RSTB_TSSI BIT(31) |
8669 | #define R_P0_TSSI_MV_AVG 0x58E4 |
8670 | #define B_P0_TSSI_MV_MIX GENMASK(19, 11) |
8671 | #define B_P0_TSSI_MV_AVG GENMASK(13, 11) |
8672 | #define B_P0_TSSI_MV_CLR BIT(14) |
8673 | #define R_TXGAIN_SCALE 0x58F0 |
8674 | #define B_TXGAIN_SCALE_EN BIT(19) |
8675 | #define B_TXGAIN_SCALE_OFT GENMASK(31, 24) |
8676 | #define R_P0_DAC_COMP_POST_DPD_EN 0x58F8 |
8677 | #define B_P0_DAC_COMP_POST_DPD_EN BIT(31) |
8678 | #define R_P0_TSSI_BASE 0x5C00 |
8679 | #define R_S0_DACKI 0x5E00 |
8680 | #define B_S0_DACKI_AR GENMASK(31, 28) |
8681 | #define B_S0_DACKI_EN BIT(3) |
8682 | #define R_S0_DACKI2 0x5E30 |
8683 | #define B_S0_DACKI2_K GENMASK(21, 12) |
8684 | #define R_S0_DACKI7 0x5E44 |
8685 | #define B_S0_DACKI7_K GENMASK(15, 8) |
8686 | #define R_S0_DACKI8 0x5E48 |
8687 | #define B_S0_DACKI8_K GENMASK(15, 8) |
8688 | #define R_S0_DACKQ 0x5E50 |
8689 | #define B_S0_DACKQ_AR GENMASK(31, 28) |
8690 | #define B_S0_DACKQ_EN BIT(3) |
8691 | #define R_S0_DACKQ2 0x5E80 |
8692 | #define B_S0_DACKQ2_K GENMASK(21, 12) |
8693 | #define R_S0_DACKQ7 0x5E94 |
8694 | #define B_S0_DACKQ7_K GENMASK(15, 8) |
8695 | #define R_S0_DACKQ8 0x5E98 |
8696 | #define B_S0_DACKQ8_K GENMASK(15, 8) |
8697 | #define R_DCFO_WEIGHT_V1 0x6244 |
8698 | #define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28) |
8699 | #define R_DAC_CLK 0x625C |
8700 | #define B_DAC_CLK GENMASK(31, 30) |
8701 | #define R_DCFO_OPT_V1 0x6260 |
8702 | #define B_DCFO_OPT_EN_V1 BIT(17) |
8703 | #define R_TXFCTR 0x627C |
8704 | #define B_TXFCTR_THD GENMASK(19, 10) |
8705 | #define R_TXSCALE 0x6284 |
8706 | #define B_TXFCTR_EN BIT(19) |
8707 | #define R_PCOEFF01 0x6684 |
8708 | #define B_PCOEFF01 GENMASK(23, 0) |
8709 | #define R_PCOEFF23 0x6688 |
8710 | #define B_PCOEFF23 GENMASK(23, 0) |
8711 | #define R_PCOEFF45 0x668c |
8712 | #define B_PCOEFF45 GENMASK(23, 0) |
8713 | #define R_PCOEFF67 0x6690 |
8714 | #define B_PCOEFF67 GENMASK(23, 0) |
8715 | #define R_PCOEFF89 0x6694 |
8716 | #define B_PCOEFF89 GENMASK(23, 0) |
8717 | #define R_PCOEFFAB 0x6698 |
8718 | #define B_PCOEFFAB GENMASK(23, 0) |
8719 | #define R_PCOEFFCD 0x669c |
8720 | #define B_PCOEFFCD GENMASK(23, 0) |
8721 | #define R_PCOEFFEF 0x66a0 |
8722 | #define B_PCOEFFEF GENMASK(23, 0) |
8723 | #define R_MGAIN_BIAS 0x672c |
8724 | #define B_MGAIN_BIAS_BW20 GENMASK(3, 0) |
8725 | #define B_MGAIN_BIAS_BW40 GENMASK(7, 4) |
8726 | #define R_CCK_RPL_OFST 0x6750 |
8727 | #define B_CCK_RPL_OFST GENMASK(7, 0) |
8728 | #define R_BK_FC0INV 0x6758 |
8729 | #define B_BK_FC0INV GENMASK(18, 0) |
8730 | #define R_CCK_FC0INV 0x675c |
8731 | #define B_CCK_FC0INV GENMASK(18, 0) |
8732 | #define R_SEG0R_EDCCA_LVL_BE 0x69EC |
8733 | #define R_SEG0R_PPDU_LVL_BE 0x69F0 |
8734 | #define R_SEGSND 0x6A14 |
8735 | #define B_SEGSND_EN BIT(31) |
8736 | #define R_DBCC 0x6B48 |
8737 | #define B_DBCC_EN BIT(0) |
8738 | #define R_FC0 0x6B4C |
8739 | #define B_BW40_2XFFT BIT(31) |
8740 | #define B_FC0 GENMASK(12, 0) |
8741 | #define R_FC0INV_SBW 0x6B50 |
8742 | #define B_SMALLBW GENMASK(31, 30) |
8743 | #define B_RX_BT_SG0 GENMASK(25, 22) |
8744 | #define B_RX_1RCCA GENMASK(17, 14) |
8745 | #define B_FC0_INV GENMASK(6, 0) |
8746 | #define R_ANT_CHBW 0x6B54 |
8747 | #define B_ANT_BT_SHARE BIT(16) |
8748 | #define B_CHBW_BW GENMASK(14, 12) |
8749 | #define B_CHBW_PRICH GENMASK(11, 8) |
8750 | #define B_ANT_RX_SG0 GENMASK(3, 0) |
8751 | #define R_SLOPE 0x6B6C |
8752 | #define B_EHT_RATE_TH GENMASK(31, 28) |
8753 | #define B_SLOPE_B GENMASK(27, 14) |
8754 | #define B_SLOPE_A GENMASK(13, 0) |
8755 | #define R_SC_CORNER 0x6B70 |
8756 | #define B_SC_CORNER GENMASK(10, 0) |
8757 | #define R_MAG_A 0x6BF4 |
8758 | #define B_MGA_AEND GENMASK(31, 24) |
8759 | #define R_MAG_AB 0x6BF8 |
8760 | #define B_BY_SLOPE GENMASK(31, 24) |
8761 | #define B_MAG_AB GENMASK(23, 0) |
8762 | #define R_BEDGE 0x6BFC |
8763 | #define B_EHT_MCS14 BIT(31) |
8764 | #define B_HE_RATE_TH GENMASK(30, 27) |
8765 | #define R_BEDGE2 0x6C00 |
8766 | #define B_EHT_MCS15 BIT(31) |
8767 | #define B_HT_VHT_TH GENMASK(11, 0) |
8768 | #define R_BEDGE3 0x6C04 |
8769 | #define B_TB_EN BIT(23) |
8770 | #define B_HEMU_EN BIT(21) |
8771 | #define B_HEERSU_EN BIT(19) |
8772 | #define B_EHTTB_EN BIT(15) |
8773 | #define B_BEDGE_CFG GENMASK(1, 0) |
8774 | #define R_SU_PUNC 0x6C08 |
8775 | #define B_SU_PUNC_EN BIT(1) |
8776 | #define R_BEDGE5 0x6C10 |
8777 | #define B_HWGEN_EN BIT(25) |
8778 | #define B_PWROFST_COMP BIT(20) |
8779 | #define R_RPL_BIAS_COMP1 0x6DF0 |
8780 | #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0) |
8781 | #define R_DBCC_FA 0x703C |
8782 | #define B_DBCC_FA BIT(12) |
8783 | #define R_P1_TSSI_ALIM1 0x7630 |
8784 | #define B_P1_TSSI_ALIM1 GENMASK(29, 0) |
8785 | #define B_P1_TSSI_ALIM11 GENMASK(29, 20) |
8786 | #define B_P1_TSSI_ALIM12 GENMASK(19, 10) |
8787 | #define B_P1_TSSI_ALIM13 GENMASK(9, 0) |
8788 | #define R_P1_TSSI_ALIM3 0x7634 |
8789 | #define B_P1_TSSI_ALIM31 GENMASK(9, 0) |
8790 | #define R_P1_TSSI_ALIM2 0x763c |
8791 | #define B_P1_TSSI_ALIM2 GENMASK(29, 0) |
8792 | #define R_P1_TSSI_ADC_CLK 0x766c |
8793 | #define B_P1_TSSI_ADC_CLK GENMASK(17, 16) |
8794 | #define R_P1_TSSIC 0x7814 |
8795 | #define B_P1_TSSIC_BYPASS BIT(11) |
8796 | #define R_P1_TMETER 0x7810 |
8797 | #define B_P1_TMETER GENMASK(15, 10) |
8798 | #define B_P1_TMETER_DIS BIT(16) |
8799 | #define B_P1_TMETER_TRK BIT(24) |
8800 | #define R_P1_TSSI_TRK 0x7818 |
8801 | #define B_P1_TSSI_TRK_EN BIT(30) |
8802 | #define B_P1_TSSI_RFC GENMASK(28, 27) |
8803 | #define B_P1_TSSI_OFT_EN BIT(28) |
8804 | #define B_P1_TSSI_OFT GENMASK(7, 0) |
8805 | #define R_P1_TSSI_AVG 0x7820 |
8806 | #define B_P1_TSSI_EN BIT(31) |
8807 | #define B_P1_TSSI_AVG GENMASK(15, 12) |
8808 | #define R_P1_RFCTM 0x7864 |
8809 | #define R_P1_RFCTM_RDY BIT(26) |
8810 | #define B_P1_RFCTM_VAL GENMASK(25, 20) |
8811 | #define B_P1_RFCTM_DEL GENMASK(19, 11) |
8812 | #define R_P1_PATH_RST 0x78AC |
8813 | #define R_P1_TXPW_RSTB 0x78DC |
8814 | #define B_P1_TXPW_RSTB_MANON BIT(30) |
8815 | #define B_P1_TXPW_RSTB_TSSI BIT(31) |
8816 | #define R_P1_TSSI_MV_AVG 0x78E4 |
8817 | #define B_P1_TSSI_MV_MIX GENMASK(19, 11) |
8818 | #define B_P1_TSSI_MV_AVG GENMASK(13, 11) |
8819 | #define B_P1_TSSI_MV_CLR BIT(14) |
8820 | #define R_P1_DAC_COMP_POST_DPD_EN 0x78F8 |
8821 | #define B_P1_DAC_COMP_POST_DPD_EN BIT(31) |
8822 | #define R_TSSI_THOF 0x7C00 |
8823 | #define R_S1_DACKI 0x7E00 |
8824 | #define B_S1_DACKI_AR GENMASK(31, 28) |
8825 | #define B_S1_DACKI_EN BIT(3) |
8826 | #define R_S1_DACKI2 0x7E30 |
8827 | #define B_S1_DACKI2_K GENMASK(21, 12) |
8828 | #define R_S1_DACKI7 0x7E44 |
8829 | #define B_S1_DACKI_K GENMASK(15, 8) |
8830 | #define R_S1_DACKI8 0x7E48 |
8831 | #define B_S1_DACKI8_K GENMASK(15, 8) |
8832 | #define R_S1_DACKQ 0x7E50 |
8833 | #define B_S1_DACKQ_AR GENMASK(31, 28) |
8834 | #define B_S1_DACKQ_EN BIT(3) |
8835 | #define R_S1_DACKQ2 0x7E80 |
8836 | #define B_S1_DACKQ2_K GENMASK(21, 12) |
8837 | #define R_S1_DACKQ7 0x7E94 |
8838 | #define B_S1_DACKQ7_K GENMASK(15, 8) |
8839 | #define R_S1_DACKQ8 0x7E98 |
8840 | #define B_S1_DACKQ8_K GENMASK(15, 8) |
8841 | #define R_NCTL_CFG 0x8000 |
8842 | #define B_NCTL_CFG_SPAGE GENMASK(2, 1) |
8843 | #define R_NCTL_RPT 0x8008 |
8844 | #define B_NCTL_RPT_FLG BIT(26) |
8845 | #define R_NCTL_N1 0x8010 |
8846 | #define B_NCTL_N1_CIP GENMASK(7, 0) |
8847 | #define R_NCTL_N2 0x8014 |
8848 | #define R_IQK_COM 0x8018 |
8849 | #define R_IQK_DIF 0x801C |
8850 | #define B_IQK_DIF_TRX GENMASK(1, 0) |
8851 | #define R_IQK_DIF1 0x8020 |
8852 | #define B_IQK_DIF1_TXPI GENMASK(19, 0) |
8853 | #define R_IQK_DIF2 0x8024 |
8854 | #define B_IQK_DIF2_RXPI GENMASK(19, 0) |
8855 | #define R_IQK_DIF4 0x802C |
8856 | #define B_IQK_DIF4_RXT GENMASK(27, 16) |
8857 | #define B_IQK_DIF4_TXT GENMASK(11, 0) |
8858 | #define IQK_DF4_TXT_8_25MHZ 0x021 |
8859 | #define R_IQK_CFG 0x8034 |
8860 | #define B_IQK_CFG_SET GENMASK(5, 4) |
8861 | #define R_IQK_RXA 0x8044 |
8862 | #define B_IQK_RXAGC GENMASK(15, 13) |
8863 | #define R_TPG_SEL 0x8068 |
8864 | #define R_TPG_MOD 0x806C |
8865 | #define B_TPG_MOD_F GENMASK(2, 1) |
8866 | #define R_MDPK_SYNC 0x8070 |
8867 | #define B_MDPK_SYNC_SEL BIT(31) |
8868 | #define B_MDPK_SYNC_MAN GENMASK(31, 28) |
8869 | #define B_MDPK_SYNC_DMAN GENMASK(30, 28) |
8870 | #define R_MDPK_RX_DCK 0x8074 |
8871 | #define B_MDPK_RX_DCK_EN BIT(31) |
8872 | #define R_KIP_MOD 0x8078 |
8873 | #define B_KIP_MOD GENMASK(19, 0) |
8874 | #define R_NCTL_RW 0x8080 |
8875 | #define R_KIP_SYSCFG 0x8088 |
8876 | #define R_KIP_CLK 0x808C |
8877 | #define R_DPK_IDL 0x809C |
8878 | #define B_DPK_IDL_SEL GENMASK(10, 9) |
8879 | #define B_DPK_IDL BIT(8) |
8880 | #define R_LDL_NORM 0x80A0 |
8881 | #define B_LDL_NORM_MA BIT(16) |
8882 | #define B_LDL_NORM_PN GENMASK(12, 8) |
8883 | #define B_LDL_NORM_OP GENMASK(1, 0) |
8884 | #define R_DPK_CTL 0x80B0 |
8885 | #define B_DPK_CTL_EN BIT(28) |
8886 | #define R_DPK_CFG 0x80B8 |
8887 | #define B_DPK_CFG_IDX GENMASK(14, 12) |
8888 | #define R_DPK_CFG2 0x80BC |
8889 | #define B_DPK_CFG2_ST BIT(14) |
8890 | #define R_DPK_CFG3 0x80C0 |
8891 | #define R_KPATH_CFG 0x80D0 |
8892 | #define B_KPATH_CFG_ED GENMASK(21, 20) |
8893 | #define R_KIP_RPT1 0x80D4 |
8894 | #define B_KIP_RPT1_SEL GENMASK(21, 16) |
8895 | #define B_KIP_RPT1_SEL_V1 GENMASK(19, 16) |
8896 | #define R_SRAM_IQRX 0x80D8 |
8897 | #define R_IDL_MPA 0x80DC |
8898 | #define B_IDL_DN BIT(31) |
8899 | #define B_IDL_MD530 BIT(1) |
8900 | #define B_IDL_MD500 BIT(0) |
8901 | #define R_GAPK 0x80E0 |
8902 | #define B_GAPK_ADR BIT(0) |
8903 | #define R_SRAM_IQRX2 0x80E8 |
8904 | #define R_DPK_MPA 0x80EC |
8905 | #define B_DPK_MPA_T0 BIT(10) |
8906 | #define B_DPK_MPA_T1 BIT(9) |
8907 | #define B_DPK_MPA_T2 BIT(8) |
8908 | #define R_DPK_WR 0x80F4 |
8909 | #define B_DPK_WR_ST BIT(29) |
8910 | #define R_DPK_TRK 0x80f0 |
8911 | #define B_DPK_TRK_DIS BIT(31) |
8912 | #define R_RPT_COM 0x80FC |
8913 | #define B_PRT_COM_SYNERR BIT(30) |
8914 | #define B_PRT_COM_DCI GENMASK(27, 16) |
8915 | #define B_PRT_COM_CORV GENMASK(15, 8) |
8916 | #define B_RPT_COM_RDY GENMASK(15, 0) |
8917 | #define B_PRT_COM_DCQ GENMASK(11, 0) |
8918 | #define B_PRT_COM_RXOV BIT(8) |
8919 | #define B_PRT_COM_GL GENMASK(7, 4) |
8920 | #define B_PRT_COM_CORI GENMASK(7, 0) |
8921 | #define B_PRT_COM_RXBB GENMASK(5, 0) |
8922 | #define B_PRT_COM_RXBB_V1 GENMASK(4, 0) |
8923 | #define B_PRT_COM_DONE BIT(0) |
8924 | #define R_COEF_SEL 0x8104 |
8925 | #define R_COEF_SEL_C1 0x8204 |
8926 | #define B_COEF_SEL_IQC BIT(0) |
8927 | #define B_COEF_SEL_IQC_V1 GENMASK(1, 0) |
8928 | #define B_COEF_SEL_MDPD BIT(8) |
8929 | #define B_COEF_SEL_MDPD_V1 GENMASK(9, 8) |
8930 | #define B_COEF_SEL_EN BIT(31) |
8931 | #define R_CFIR_SYS 0x8120 |
8932 | #define R_IQK_RES 0x8124 |
8933 | #define B_IQK_RES_K BIT(28) |
8934 | #define B_IQK_RES_TXCFIR GENMASK(11, 8) |
8935 | #define B_IQK_RES_RXCFIR GENMASK(3, 0) |
8936 | #define R_TXIQC 0x8138 |
8937 | #define R_RXIQC 0x813c |
8938 | #define B_RXIQC_BYPASS BIT(0) |
8939 | #define B_RXIQC_BYPASS2 BIT(2) |
8940 | #define B_RXIQC_NEWP GENMASK(19, 8) |
8941 | #define B_RXIQC_NEWX GENMASK(31, 20) |
8942 | #define R_KIP 0x8140 |
8943 | #define B_KIP_DBCC BIT(0) |
8944 | #define B_KIP_RFGAIN BIT(8) |
8945 | #define R_RFGAIN 0x8144 |
8946 | #define B_RFGAIN_PAD GENMASK(4, 0) |
8947 | #define B_RFGAIN_TXBB GENMASK(12, 8) |
8948 | #define R_RFGAIN_BND 0x8148 |
8949 | #define B_RFGAIN_BND GENMASK(4, 0) |
8950 | #define R_CFIR_MAP 0x8150 |
8951 | #define R_CFIR_LUT 0x8154 |
8952 | #define R_CFIR_LUT_C1 0x8254 |
8953 | #define B_CFIR_LUT_SEL BIT(8) |
8954 | #define B_CFIR_LUT_SET BIT(4) |
8955 | #define B_CFIR_LUT_G5 BIT(5) |
8956 | #define B_CFIR_LUT_G3 BIT(3) |
8957 | #define B_CFIR_LUT_G2 BIT(2) |
8958 | #define B_CFIR_LUT_GP_V1 GENMASK(2, 0) |
8959 | #define B_CFIR_LUT_GP GENMASK(1, 0) |
8960 | #define R_DPK_GN 0x819C |
8961 | #define B_DPK_GN_EN GENMASK(17, 16) |
8962 | #define B_DPK_GN_AG GENMASK(9, 0) |
8963 | #define R_DPD_V1 0x81a0 |
8964 | #define B_DPD_LBK BIT(7) |
8965 | #define R_DPD_CH0 0x81AC |
8966 | #define R_DPD_BND 0x81B4 |
8967 | #define B_DPD_BND_1 GENMASK(24, 16) |
8968 | #define B_DPD_BND_0 GENMASK(8, 0) |
8969 | #define R_DPD_CH0A 0x81BC |
8970 | #define B_DPD_MEN GENMASK(31, 28) |
8971 | #define B_DPD_ORDER GENMASK(26, 24) |
8972 | #define B_DPD_ORDER_V1 GENMASK(26, 25) |
8973 | #define B_DPD_CFG GENMASK(22, 0) |
8974 | #define B_DPD_SEL GENMASK(13, 8) |
8975 | #define R_TXAGC_RFK 0x81C4 |
8976 | #define B_TXAGC_RFK_CH0 GENMASK(5, 0) |
8977 | #define R_DPD_COM 0x81C8 |
8978 | #define B_DPD_COM_OF BIT(15) |
8979 | #define R_KIP_IQP 0x81CC |
8980 | #define B_KIP_IQP_SW GENMASK(13, 12) |
8981 | #define B_KIP_IQP_IQSW GENMASK(5, 0) |
8982 | #define R_KIP_RPT 0x81D4 |
8983 | #define B_KIP_RPT_SEL GENMASK(21, 16) |
8984 | #define R_W_COEF 0x81D8 |
8985 | #define R_LOAD_COEF 0x81DC |
8986 | #define B_LOAD_COEF_MDPD BIT(16) |
8987 | #define B_LOAD_COEF_CFIR GENMASK(1, 0) |
8988 | #define B_LOAD_COEF_DI BIT(1) |
8989 | #define B_LOAD_COEF_AUTO BIT(0) |
8990 | #define R_DPK_GL 0x81F0 |
8991 | #define B_DPK_GL_A0 GENMASK(31, 28) |
8992 | #define B_DPK_GL_A1 GENMASK(17, 0) |
8993 | #define R_RPT_PER 0x81FC |
8994 | #define B_RPT_PER_KSET GENMASK(31, 29) |
8995 | #define B_RPT_PER_TSSI GENMASK(28, 16) |
8996 | #define B_RPT_PER_OF GENMASK(15, 8) |
8997 | #define B_RPT_PER_TH GENMASK(5, 0) |
8998 | #define R_IQRSN 0x8220 |
8999 | #define B_IQRSN_K1 BIT(28) |
9000 | #define B_IQRSN_K2 BIT(16) |
9001 | #define R_RXCFIR_P0C0 0x8D40 |
9002 | #define R_RXCFIR_P0C1 0x8D84 |
9003 | #define R_RXCFIR_P0C2 0x8DC8 |
9004 | #define R_RXCFIR_P0C3 0x8E0C |
9005 | #define R_TXCFIR_P0C0 0x8F50 |
9006 | #define R_TXCFIR_P0C1 0x8F84 |
9007 | #define R_TXCFIR_P0C2 0x8FB8 |
9008 | #define R_TXCFIR_P0C3 0x8FEC |
9009 | #define R_RXCFIR_P1C0 0x9140 |
9010 | #define R_RXCFIR_P1C1 0x9184 |
9011 | #define R_RXCFIR_P1C2 0x91C8 |
9012 | #define R_RXCFIR_P1C3 0x920C |
9013 | #define R_TXCFIR_P1C0 0x9350 |
9014 | #define R_TXCFIR_P1C1 0x9384 |
9015 | #define R_TXCFIR_P1C2 0x93B8 |
9016 | #define R_TXCFIR_P1C3 0x93EC |
9017 | #define R_IQKINF 0x9FE0 |
9018 | #define B_IQKINF_VER GENMASK(31, 24) |
9019 | #define B_IQKINF_FAIL_RXGRP GENMASK(23, 16) |
9020 | #define B_IQKINF_FAIL_TXGRP GENMASK(15, 8) |
9021 | #define B_IQKINF_FAIL GENMASK(3, 0) |
9022 | #define B_IQKINF_F_RX BIT(3) |
9023 | #define B_IQKINF_FTX BIT(2) |
9024 | #define B_IQKINF_FFIN BIT(1) |
9025 | #define B_IQKINF_FCOR BIT(0) |
9026 | #define R_IQKCH 0x9FE4 |
9027 | #define B_IQKCH_CH GENMASK(15, 8) |
9028 | #define B_IQKCH_BW GENMASK(7, 4) |
9029 | #define B_IQKCH_BAND GENMASK(3, 0) |
9030 | #define R_IQKINF2 0x9FE8 |
9031 | #define B_IQKINF2_FCNT GENMASK(23, 16) |
9032 | #define B_IQKINF2_KCNT GENMASK(15, 8) |
9033 | #define B_IQKINF2_NCTLV GENMASK(7, 0) |
9034 | #define R_DCOF0 0xC000 |
9035 | #define B_DCOF0_RST BIT(17) |
9036 | #define B_DCOF0_V GENMASK(4, 1) |
9037 | #define R_DCOF1 0xC004 |
9038 | #define B_DCOF1_RST BIT(17) |
9039 | #define B_DCOF1_S BIT(0) |
9040 | #define R_DCOF8 0xC020 |
9041 | #define B_DCOF8_V GENMASK(4, 1) |
9042 | #define R_DCOF9 0xC024 |
9043 | #define B_DCOF9_RST BIT(17) |
9044 | #define R_DACK_S0P0 0xC040 |
9045 | #define B_DACK_S0P0_OK BIT(31) |
9046 | #define R_DACK_BIAS00 0xc048 |
9047 | #define B_DACK_BIAS00 GENMASK(11, 2) |
9048 | #define R_DACK_S0P2 0xC05C |
9049 | #define B_DACK_S0M0 GENMASK(31, 24) |
9050 | #define B_DACK_S0P2_OK BIT(2) |
9051 | #define R_DACK_DADCK00 0xC060 |
9052 | #define B_DACK_DADCK00 GENMASK(31, 24) |
9053 | #define R_DACK_S0P1 0xC064 |
9054 | #define B_DACK_S0P1_OK BIT(31) |
9055 | #define R_DACK_BIAS01 0xC06C |
9056 | #define B_DACK_BIAS01 GENMASK(11, 2) |
9057 | #define R_DACK_S0P3 0xC080 |
9058 | #define B_DACK_S0M1 GENMASK(31, 24) |
9059 | #define B_DACK_S0P3_OK BIT(2) |
9060 | #define R_DACK_DADCK01 0xC084 |
9061 | #define B_DACK_DADCK01 GENMASK(31, 24) |
9062 | #define R_DRCK_FH 0xC094 |
9063 | #define B_DRCK_LAT BIT(9) |
9064 | #define R_DRCK 0xC0C4 |
9065 | #define B_DRCK_MUL GENMASK(21, 17) |
9066 | #define B_DRCK_IDLE BIT(9) |
9067 | #define B_DRCK_EN BIT(6) |
9068 | #define B_DRCK_VAL GENMASK(4, 0) |
9069 | #define R_DRCK_RES 0xC0C8 |
9070 | #define B_DRCK_RES GENMASK(19, 15) |
9071 | #define B_DRCK_POL BIT(3) |
9072 | #define R_DRCK_V1 0xC0CC |
9073 | #define B_DRCK_V1_SEL BIT(9) |
9074 | #define B_DRCK_V1_KICK BIT(6) |
9075 | #define B_DRCK_V1_CV GENMASK(4, 0) |
9076 | #define R_DRCK_RS 0xC0D0 |
9077 | #define B_DRCK_RS_LPS GENMASK(19, 15) |
9078 | #define B_DRCK_RS_DONE BIT(3) |
9079 | #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4 |
9080 | #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) |
9081 | #define R_P0_CFCH_BW0 0xC0D4 |
9082 | #define B_P0_CFCH_BW0 GENMASK(27, 26) |
9083 | #define B_P0_CFCH_EN GENMASK(14, 11) |
9084 | #define B_P0_CFCH_CTL GENMASK(10, 7) |
9085 | #define R_P0_CFCH_BW1 0xC0D8 |
9086 | #define B_P0_CFCH_EX BIT(13) |
9087 | #define B_P0_CFCH_BW1 GENMASK(8, 5) |
9088 | #define R_WDADC 0xC0E4 |
9089 | #define B_WDADC_SEL GENMASK(5, 4) |
9090 | #define R_ADCMOD 0xC0E8 |
9091 | #define B_ADCMOD_LP GENMASK(31, 16) |
9092 | #define R_DCIM 0xC0EC |
9093 | #define B_DCIM_FR GENMASK(14, 13) |
9094 | #define R_ADDCK0D 0xC0F0 |
9095 | #define B_ADDCK0D_VAL2 GENMASK(31, 26) |
9096 | #define B_ADDCK0D_VAL GENMASK(25, 16) |
9097 | #define B_ADDCK_DS BIT(16) |
9098 | #define R_ADDCK0 0xC0F4 |
9099 | #define B_ADDCK0_TRG BIT(11) |
9100 | #define B_ADDCK0_IQ BIT(10) |
9101 | #define B_ADDCK0 GENMASK(9, 8) |
9102 | #define B_ADDCK0_MAN GENMASK(5, 4) |
9103 | #define B_ADDCK0_EN BIT(4) |
9104 | #define B_ADDCK0_VAL GENMASK(3, 0) |
9105 | #define B_ADDCK0_RST BIT(2) |
9106 | #define R_ADDCK0_RL 0xC0F8 |
9107 | #define B_ADDCK0_RLS GENMASK(29, 28) |
9108 | #define B_ADDCK0_RL1 GENMASK(27, 18) |
9109 | #define B_ADDCK0_RL0 GENMASK(17, 8) |
9110 | #define R_ADDCKR0 0xC0FC |
9111 | #define B_ADDCKR0_A0 GENMASK(19, 10) |
9112 | #define B_ADDCKR0_DC GENMASK(15, 4) |
9113 | #define B_ADDCKR0_A1 GENMASK(9, 0) |
9114 | #define R_DACK10 0xC100 |
9115 | #define B_DACK10 GENMASK(4, 1) |
9116 | #define R_DACK1_K 0xc104 |
9117 | #define B_DACK1_EN BIT(0) |
9118 | #define R_DACK11 0xC120 |
9119 | #define B_DACK11 GENMASK(4, 1) |
9120 | #define R_DACK_S1P0 0xC140 |
9121 | #define B_DACK_S1P0_OK BIT(31) |
9122 | #define R_DACK_BIAS10 0xC148 |
9123 | #define B_DACK_BIAS10 GENMASK(11, 2) |
9124 | #define R_DACK10S 0xC15C |
9125 | #define B_DACK10S GENMASK(31, 24) |
9126 | #define R_DACK_S1P2 0xC15C |
9127 | #define B_DACK_S1P2_OK BIT(2) |
9128 | #define R_DACK_DADCK10 0xC160 |
9129 | #define B_DACK_DADCK10 GENMASK(31, 24) |
9130 | #define R_DACK_S1P1 0xC164 |
9131 | #define B_DACK_S1P1_OK BIT(31) |
9132 | #define R_DACK_BIAS11 0xC16C |
9133 | #define B_DACK_BIAS11 GENMASK(11, 2) |
9134 | #define R_DACK11S 0xC180 |
9135 | #define B_DACK11S GENMASK(31, 24) |
9136 | #define R_DACK_S1P3 0xC180 |
9137 | #define B_DACK_S1P3_OK BIT(2) |
9138 | #define R_DACK_DADCK11 0xC184 |
9139 | #define B_DACK_DADCK11 GENMASK(31, 24) |
9140 | #define R_PATH1_SAMPL_DLY_T_V1 0xC1D4 |
9141 | #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) |
9142 | #define R_PATH0_BW_SEL_V1 0xC0D8 |
9143 | #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5) |
9144 | #define R_PATH1_BW_SEL_V1 0xC1D8 |
9145 | #define B_PATH1_BW_SEL_EX BIT(13) |
9146 | #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5) |
9147 | #define R_ADDCK1D 0xC1F0 |
9148 | #define B_ADDCK1D_VAL2 GENMASK(31, 26) |
9149 | #define B_ADDCK1D_VAL GENMASK(25, 16) |
9150 | #define R_ADDCK1 0xC1F4 |
9151 | #define B_ADDCK1_TRG BIT(11) |
9152 | #define B_ADDCK1 GENMASK(9, 8) |
9153 | #define B_ADDCK1_MAN GENMASK(5, 4) |
9154 | #define B_ADDCK1_EN BIT(4) |
9155 | #define B_ADDCK1_RST BIT(2) |
9156 | #define R_ADDCK1_RL 0xC1F8 |
9157 | #define B_ADDCK1_RLS GENMASK(29, 28) |
9158 | #define B_ADDCK1_RL1 GENMASK(27, 18) |
9159 | #define B_ADDCK1_RL0 GENMASK(17, 8) |
9160 | #define R_ADDCKR1 0xC1fC |
9161 | #define B_ADDCKR1_A0 GENMASK(19, 10) |
9162 | #define B_ADDCKR1_A1 GENMASK(9, 0) |
9163 | #define R_DACKN0_CTL 0xC210 |
9164 | #define B_DACKN0_EN BIT(0) |
9165 | #define B_DACKN0_V GENMASK(21, 14) |
9166 | #define R_DACKN1_CTL 0xC224 |
9167 | #define B_DACKN1_V GENMASK(21, 14) |
9168 | #define R_GAIN_MAP0 0xE44C |
9169 | #define B_GAIN_MAP0_EN BIT(0) |
9170 | #define R_GAIN_MAP1 0xE54C |
9171 | #define B_GAIN_MAP1_EN BIT(0) |
9172 | #define R_GOTX_IQKDPK_C0 0xE464 |
9173 | #define R_GOTX_IQKDPK_C1 0xE564 |
9174 | #define B_GOTX_IQKDPK GENMASK(28, 27) |
9175 | #define R_IQK_DPK_PRST 0xE4AC |
9176 | #define R_IQK_DPK_PRST_C1 0xE5AC |
9177 | #define B_IQK_DPK_PRST BIT(27) |
9178 | #define R_TXPWR_RSTA 0xE60C |
9179 | #define B_TXPWR_RSTA BIT(16) |
9180 | #define R_TSSI_PWR_P0 0xE610 |
9181 | #define R_TSSI_PWR_P1 0xE710 |
9182 | #define B_TSSI_CONT_EN BIT(3) |
9183 | #define R_TSSI_MAP_OFST_P0 0xE620 |
9184 | #define R_TSSI_MAP_OFST_P1 0xE720 |
9185 | #define B_TSSI_MAP_OFST_OFDM GENMASK(17, 9) |
9186 | #define B_TSSI_MAP_OFST_CCK GENMASK(26, 18) |
9187 | #define R_TXAGC_REF0_P0 0xE628 |
9188 | #define R_TXAGC_REF0_P1 0xE728 |
9189 | #define B_TXAGC_REF0_OFDM_DBM GENMASK(8, 0) |
9190 | #define B_TXAGC_REF0_CCK_DBM GENMASK(17, 9) |
9191 | #define B_TXAGC_REF0_OFDM_CW GENMASK(26, 18) |
9192 | #define R_TXAGC_REF1_P0 0xE62C |
9193 | #define R_TXAGC_REF1_P1 0xE72C |
9194 | #define B_TXAGC_REF1_CCK_CW GENMASK(8, 0) |
9195 | #define R_TXPWR_RSTB 0xE70C |
9196 | #define B_TXPWR_RSTB BIT(16) |
9197 | |
9198 | /* WiFi CPU local domain */ |
9199 | #define R_AX_WDT_CTRL 0x0040 |
9200 | #define B_AX_WDT_EN BIT(31) |
9201 | #define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29) |
9202 | #define B_AX_IO_HANG_IMR BIT(27) |
9203 | #define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26) |
9204 | #define B_AX_IO_HANG_DMAC_EN BIT(25) |
9205 | #define B_AX_WDT_CLR BIT(16) |
9206 | #define B_AX_WDT_COUNT_MASK GENMASK(15, 0) |
9207 | #define WDT_CTRL_ALL_DIS 0 |
9208 | |
9209 | #define R_AX_WDT_STATUS 0x0044 |
9210 | #define B_AX_FS_WDT_INT BIT(8) |
9211 | #define B_AX_FS_WDT_INT_MSK BIT(0) |
9212 | |
9213 | #endif |
9214 | |