| 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
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| 2 | /* Copyright(c) 2019-2022 Realtek Corporation |
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| 3 | */ |
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| 4 | |
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| 5 | #ifndef __RTW89_8852C_H__ |
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| 6 | #define __RTW89_8852C_H__ |
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| 7 | |
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| 8 | #include "core.h" |
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| 9 | |
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| 10 | #define RF_PATH_NUM_8852C 2 |
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| 11 | #define BB_PATH_NUM_8852C 2 |
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| 12 | |
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| 13 | struct rtw8852c_u_efuse { |
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| 14 | u8 rsvd[0x38]; |
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| 15 | u8 mac_addr[ETH_ALEN]; |
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| 16 | }; |
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| 17 | |
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| 18 | struct rtw8852c_e_efuse { |
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| 19 | u8 mac_addr[ETH_ALEN]; |
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| 20 | }; |
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| 21 | |
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| 22 | struct rtw8852c_tssi_offset { |
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| 23 | u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; |
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| 24 | u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; |
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| 25 | u8 rsvd[7]; |
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| 26 | u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; |
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| 27 | } __packed; |
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| 28 | |
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| 29 | struct rtw8852c_efuse { |
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| 30 | u8 rsvd[0x210]; |
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| 31 | struct rtw8852c_tssi_offset path_a_tssi; |
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| 32 | u8 rsvd1[10]; |
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| 33 | struct rtw8852c_tssi_offset path_b_tssi; |
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| 34 | u8 rsvd2[94]; |
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| 35 | u8 channel_plan; |
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| 36 | u8 xtal_k; |
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| 37 | u8 rsvd3; |
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| 38 | u8 iqk_lck; |
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| 39 | u8 rsvd4[5]; |
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| 40 | u8 reg_setting:2; |
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| 41 | u8 tx_diversity:1; |
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| 42 | u8 rx_diversity:2; |
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| 43 | u8 ac_mode:1; |
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| 44 | u8 module_type:2; |
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| 45 | u8 rsvd5; |
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| 46 | u8 shared_ant:1; |
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| 47 | u8 coex_type:3; |
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| 48 | u8 ant_iso:1; |
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| 49 | u8 radio_on_off:1; |
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| 50 | u8 rsvd6:2; |
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| 51 | u8 eeprom_version; |
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| 52 | u8 customer_id; |
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| 53 | u8 tx_bb_swing_2g; |
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| 54 | u8 tx_bb_swing_5g; |
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| 55 | u8 tx_cali_pwr_trk_mode; |
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| 56 | u8 trx_path_selection; |
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| 57 | u8 rfe_type; |
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| 58 | u8 country_code[2]; |
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| 59 | u8 rsvd7[3]; |
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| 60 | u8 path_a_therm; |
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| 61 | u8 path_b_therm; |
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| 62 | u8 rsvd8[2]; |
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| 63 | u8 rx_gain_2g_ofdm; |
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| 64 | u8 rsvd9; |
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| 65 | u8 rx_gain_2g_cck; |
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| 66 | u8 rsvd10; |
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| 67 | u8 rx_gain_5g_low; |
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| 68 | u8 rsvd11; |
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| 69 | u8 rx_gain_5g_mid; |
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| 70 | u8 rsvd12; |
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| 71 | u8 rx_gain_5g_high; |
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| 72 | u8 rsvd13[35]; |
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| 73 | u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM]; |
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| 74 | u8 rsvd14[10]; |
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| 75 | u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM]; |
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| 76 | u8 rsvd15[94]; |
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| 77 | u8 rx_gain_6g_l0; |
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| 78 | u8 rsvd16; |
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| 79 | u8 rx_gain_6g_l1; |
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| 80 | u8 rsvd17; |
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| 81 | u8 rx_gain_6g_m0; |
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| 82 | u8 rsvd18; |
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| 83 | u8 rx_gain_6g_m1; |
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| 84 | u8 rsvd19; |
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| 85 | u8 rx_gain_6g_h0; |
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| 86 | u8 rsvd20; |
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| 87 | u8 rx_gain_6g_h1; |
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| 88 | u8 rsvd21; |
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| 89 | u8 rx_gain_6g_uh0; |
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| 90 | u8 rsvd22; |
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| 91 | u8 rx_gain_6g_uh1; |
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| 92 | u8 rsvd23; |
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| 93 | u8 channel_plan_6g; |
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| 94 | u8 rsvd24[71]; |
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| 95 | union { |
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| 96 | struct rtw8852c_u_efuse u; |
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| 97 | struct rtw8852c_e_efuse e; |
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| 98 | }; |
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| 99 | } __packed; |
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| 100 | |
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| 101 | extern const struct rtw89_chip_info rtw8852c_chip_info; |
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| 102 | |
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| 103 | #endif |
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| 104 | |
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