1/*
2 * Copyright (c) 2014 Redpine Signals Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef __RSI_BOOTPARAMS_HEADER_H__
18#define __RSI_BOOTPARAMS_HEADER_H__
19
20#define CRYSTAL_GOOD_TIME BIT(0)
21#define BOOTUP_MODE_INFO BIT(1)
22#define WIFI_TAPLL_CONFIGS BIT(5)
23#define WIFI_PLL960_CONFIGS BIT(6)
24#define WIFI_AFEPLL_CONFIGS BIT(7)
25#define WIFI_SWITCH_CLK_CONFIGS BIT(8)
26
27#define TA_PLL_M_VAL_20 9
28#define TA_PLL_N_VAL_20 0
29#define TA_PLL_P_VAL_20 4
30
31#define PLL960_M_VAL_20 0x14
32#define PLL960_N_VAL_20 0
33#define PLL960_P_VAL_20 5
34
35#define UMAC_CLK_40MHZ 80
36
37#define TA_PLL_M_VAL_40 9
38#define TA_PLL_N_VAL_40 0
39#define TA_PLL_P_VAL_40 4
40
41#define PLL960_M_VAL_40 0x14
42#define PLL960_N_VAL_40 0
43#define PLL960_P_VAL_40 5
44
45#define UMAC_CLK_20BW \
46 (((TA_PLL_M_VAL_20 + 1) * 40) / \
47 ((TA_PLL_N_VAL_20 + 1) * (TA_PLL_P_VAL_20 + 1)))
48#define VALID_20 \
49 (WIFI_TAPLL_CONFIGS | WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | \
50 WIFI_SWITCH_CLK_CONFIGS | BOOTUP_MODE_INFO | CRYSTAL_GOOD_TIME)
51#define UMAC_CLK_40BW \
52 (((TA_PLL_M_VAL_40 + 1) * 40) / \
53 ((TA_PLL_N_VAL_40 + 1) * (TA_PLL_P_VAL_40 + 1)))
54#define VALID_40 \
55 (WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \
56 WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO)
57
58/* structure to store configs related to TAPLL programming */
59struct tapll_info {
60 __le16 pll_reg_1;
61 __le16 pll_reg_2;
62} __packed;
63
64/* structure to store configs related to PLL960 programming */
65struct pll960_info {
66 __le16 pll_reg_1;
67 __le16 pll_reg_2;
68 __le16 pll_reg_3;
69} __packed;
70
71/* structure to store configs related to AFEPLL programming */
72struct afepll_info {
73 __le16 pll_reg;
74} __packed;
75
76/* structure to store configs related to pll configs */
77struct pll_config {
78 struct tapll_info tapll_info_g;
79 struct pll960_info pll960_info_g;
80 struct afepll_info afepll_info_g;
81} __packed;
82
83struct pll_config_9116 {
84 __le16 pll_ctrl_set_reg;
85 __le16 pll_ctrl_clr_reg;
86 __le16 pll_modem_conig_reg;
87 __le16 soc_clk_config_reg;
88 __le16 adc_dac_strm1_config_reg;
89 __le16 adc_dac_strm2_config_reg;
90} __packed;
91
92/* structure to store configs related to UMAC clk programming */
93struct switch_clk {
94 __le16 switch_clk_info;
95 /* If switch_bbp_lmac_clk_reg is set then this value will be programmed
96 * into reg
97 */
98 __le16 bbp_lmac_clk_reg_val;
99 /* if switch_umac_clk is set then this value will be programmed */
100 __le16 umac_clock_reg_config;
101 /* if switch_qspi_clk is set then this value will be programmed */
102 __le16 qspi_uart_clock_reg_config;
103} __packed;
104
105#define RSI_SWITCH_TASS_CLK BIT(0)
106#define RSI_SWITCH_QSPI_CLK BIT(1)
107#define RSI_SWITCH_SLP_CLK_2_32 BIT(2)
108#define RSI_SWITCH_WLAN_BBP_LMAC_CLK_REG BIT(3)
109#define RSI_SWITCH_ZBBT_BBP_LMAC_CLK_REG BIT(4)
110#define RSI_SWITCH_BBP_LMAC_CLK_REG BIT(5)
111#define RSI_MODEM_CLK_160MHZ BIT(6)
112
113struct switch_clk_9116 {
114 __le32 switch_clk_info;
115 __le32 tass_clock_reg;
116 __le32 wlan_bbp_lmac_clk_reg_val;
117 __le32 zbbt_bbp_lmac_clk_reg_val;
118 __le32 bbp_lmac_clk_en_val;
119} __packed;
120
121struct device_clk_info {
122 struct pll_config pll_config_g;
123 struct switch_clk switch_clk_g;
124} __packed;
125
126struct device_clk_info_9116 {
127 struct pll_config_9116 pll_config_9116_g;
128 struct switch_clk_9116 switch_clk_9116_g;
129} __packed;
130
131struct bootup_params {
132 __le16 magic_number;
133 __le16 crystal_good_time;
134 __le32 valid;
135 __le32 reserved_for_valids;
136 __le16 bootup_mode_info;
137 /* configuration used for digital loop back */
138 __le16 digital_loop_back_params;
139 __le16 rtls_timestamp_en;
140 __le16 host_spi_intr_cfg;
141 struct device_clk_info device_clk_info[3];
142 /* ulp buckboost wait time */
143 __le32 buckboost_wakeup_cnt;
144 /* pmu wakeup wait time & WDT EN info */
145 __le16 pmu_wakeup_wait;
146 u8 shutdown_wait_time;
147 /* Sleep clock source selection */
148 u8 pmu_slp_clkout_sel;
149 /* WDT programming values */
150 __le32 wdt_prog_value;
151 /* WDT soc reset delay */
152 __le32 wdt_soc_rst_delay;
153 /* dcdc modes configs */
154 __le32 dcdc_operation_mode;
155 __le32 soc_reset_wait_cnt;
156 __le32 waiting_time_at_fresh_sleep;
157 __le32 max_threshold_to_avoid_sleep;
158 u8 beacon_resedue_alg_en;
159} __packed;
160
161struct bootup_params_9116 {
162 __le16 magic_number;
163#define LOADED_TOKEN 0x5AA5 /* Bootup params are installed by host
164 * or OTP/FLASH (Bootloader)
165 */
166#define ROM_TOKEN 0x55AA /* Bootup params are taken from ROM
167 * itself in MCU mode.
168 */
169 __le16 crystal_good_time;
170 __le32 valid;
171 __le32 reserved_for_valids;
172 __le16 bootup_mode_info;
173#define BT_COEXIST BIT(0)
174#define BOOTUP_MODE (BIT(2) | BIT(1))
175#define CUR_DEV_MODE_9116 (bootup_params_9116.bootup_mode_info >> 1)
176 __le16 digital_loop_back_params;
177 __le16 rtls_timestamp_en;
178 __le16 host_spi_intr_cfg;
179 struct device_clk_info_9116 device_clk_info_9116[1];
180 __le32 buckboost_wakeup_cnt;
181 __le16 pmu_wakeup_wait;
182 u8 shutdown_wait_time;
183 u8 pmu_slp_clkout_sel;
184 __le32 wdt_prog_value;
185 __le32 wdt_soc_rst_delay;
186 __le32 dcdc_operation_mode;
187 __le32 soc_reset_wait_cnt;
188 __le32 waiting_time_at_fresh_sleep;
189 __le32 max_threshold_to_avoid_sleep;
190 u8 beacon_resedue_alg_en;
191} __packed;
192
193#endif
194

source code of linux/drivers/net/wireless/rsi/rsi_boot_params.h