1 | /* |
2 | * @section LICENSE |
3 | * Copyright (c) 2014 Redpine Signals Inc. |
4 | * |
5 | * Permission to use, copy, modify, and/or distribute this software for any |
6 | * purpose with or without fee is hereby granted, provided that the above |
7 | * copyright notice and this permission notice appear in all copies. |
8 | * |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
16 | * |
17 | */ |
18 | |
19 | #ifndef __RSI_SDIO_INTF__ |
20 | #define __RSI_SDIO_INTF__ |
21 | |
22 | #include <linux/mmc/card.h> |
23 | #include <linux/mmc/mmc.h> |
24 | #include <linux/mmc/host.h> |
25 | #include <linux/mmc/sdio_func.h> |
26 | #include <linux/mmc/sdio.h> |
27 | #include <linux/mmc/sd.h> |
28 | #include <linux/mmc/sdio_ids.h> |
29 | #include "rsi_main.h" |
30 | |
31 | enum sdio_interrupt_type { |
32 | BUFFER_FULL = 0x0, |
33 | BUFFER_AVAILABLE = 0x2, |
34 | FIRMWARE_ASSERT_IND = 0x3, |
35 | MSDU_PACKET_PENDING = 0x4, |
36 | UNKNOWN_INT = 0XE |
37 | }; |
38 | |
39 | /* Buffer status register related info */ |
40 | #define PKT_BUFF_SEMI_FULL 0 |
41 | #define PKT_BUFF_FULL 1 |
42 | #define PKT_MGMT_BUFF_FULL 2 |
43 | #define MSDU_PKT_PENDING 3 |
44 | #define RECV_NUM_BLOCKS 4 |
45 | /* Interrupt Bit Related Macros */ |
46 | #define PKT_BUFF_AVAILABLE 1 |
47 | #define FW_ASSERT_IND 2 |
48 | |
49 | #define RSI_MASTER_REG_BUF_SIZE 12 |
50 | |
51 | #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3 |
52 | #define RSI_FN1_INT_REGISTER 0xf9 |
53 | #define RSI_INT_ENABLE_REGISTER 0x04 |
54 | #define RSI_INT_ENABLE_MASK 0xfc |
55 | #define RSI_SD_REQUEST_MASTER 0x10000 |
56 | |
57 | /* FOR SD CARD ONLY */ |
58 | #define SDIO_RX_NUM_BLOCKS_REG 0x000F1 |
59 | #define SDIO_FW_STATUS_REG 0x000F2 |
60 | #define SDIO_NXT_RD_DELAY2 0x000F5 |
61 | #define SDIO_MASTER_ACCESS_MSBYTE 0x000FA |
62 | #define SDIO_MASTER_ACCESS_LSBYTE 0x000FB |
63 | #define SDIO_READ_START_LVL 0x000FC |
64 | #define SDIO_READ_FIFO_CTL 0x000FD |
65 | #define SDIO_WRITE_FIFO_CTL 0x000FE |
66 | #define SDIO_WAKEUP_REG 0x000FF |
67 | #define SDIO_FUN1_INTR_CLR_REG 0x0008 |
68 | #define SDIO_REG_HIGH_SPEED 0x0013 |
69 | |
70 | #define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE) \ |
71 | { \ |
72 | TYPE = \ |
73 | (_I & (1 << PKT_BUFF_AVAILABLE)) ? \ |
74 | BUFFER_AVAILABLE : \ |
75 | (_I & (1 << MSDU_PKT_PENDING)) ? \ |
76 | MSDU_PACKET_PENDING : \ |
77 | (_I & (1 << FW_ASSERT_IND)) ? \ |
78 | FIRMWARE_ASSERT_IND : UNKNOWN_INT; \ |
79 | } |
80 | |
81 | /* common registers in SDIO function1 */ |
82 | #define TA_SOFT_RESET_REG 0x0004 |
83 | #define TA_TH0_PC_REG 0x0400 |
84 | #define TA_HOLD_THREAD_REG 0x0844 |
85 | #define TA_RELEASE_THREAD_REG 0x0848 |
86 | |
87 | #define TA_SOFT_RST_CLR 0 |
88 | #define TA_SOFT_RST_SET BIT(0) |
89 | #define TA_PC_ZERO 0 |
90 | #define TA_HOLD_THREAD_VALUE 0xF |
91 | #define TA_RELEASE_THREAD_VALUE 0xF |
92 | #define TA_BASE_ADDR 0x2200 |
93 | #define MISC_CFG_BASE_ADDR 0x4105 |
94 | |
95 | struct receive_info { |
96 | bool buffer_full; |
97 | bool semi_buffer_full; |
98 | bool mgmt_buffer_full; |
99 | u32 mgmt_buf_full_counter; |
100 | u32 buf_semi_full_counter; |
101 | u8 watch_bufferfull_count; |
102 | u32 sdio_intr_status_zero; |
103 | u32 sdio_int_counter; |
104 | u32 total_sdio_msdu_pending_intr; |
105 | u32 total_sdio_unknown_intr; |
106 | u32 buf_full_counter; |
107 | u32 buf_available_counter; |
108 | }; |
109 | |
110 | struct rsi_91x_sdiodev { |
111 | struct sdio_func *pfunction; |
112 | struct task_struct *sdio_irq_task; |
113 | struct receive_info rx_info; |
114 | u32 next_read_delay; |
115 | u32 sdio_high_speed_enable; |
116 | u8 sdio_clock_speed; |
117 | u32 cardcapability; |
118 | u8 prev_desc[16]; |
119 | u16 tx_blk_size; |
120 | u8 write_fail; |
121 | bool buff_status_updated; |
122 | struct rsi_thread rx_thread; |
123 | u8 pktbuffer[8192] __aligned(4); |
124 | }; |
125 | |
126 | int rsi_init_sdio_slave_regs(struct rsi_hw *adapter); |
127 | int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data); |
128 | int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length); |
129 | int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function, |
130 | u32 addr, u8 *data); |
131 | int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr, |
132 | u8 *data, u16 count); |
133 | int rsi_sdio_master_access_msword(struct rsi_hw *adapter, u16 ms_word); |
134 | void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit); |
135 | int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter); |
136 | int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num); |
137 | void rsi_sdio_rx_thread(struct rsi_common *common); |
138 | #endif |
139 | |