1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * This file is part of wl1251 |
4 | * |
5 | * Copyright (c) 1998-2007 Texas Instruments Incorporated |
6 | * Copyright (C) 2008-2009 Nokia Corporation |
7 | */ |
8 | |
9 | #ifndef __WL1251_H__ |
10 | #define __WL1251_H__ |
11 | |
12 | #include <linux/mutex.h> |
13 | #include <linux/list.h> |
14 | #include <linux/bitops.h> |
15 | #include <net/mac80211.h> |
16 | |
17 | #define DRIVER_NAME "wl1251" |
18 | #define DRIVER_PREFIX DRIVER_NAME ": " |
19 | |
20 | enum { |
21 | DEBUG_NONE = 0, |
22 | DEBUG_IRQ = BIT(0), |
23 | DEBUG_SPI = BIT(1), |
24 | DEBUG_BOOT = BIT(2), |
25 | DEBUG_MAILBOX = BIT(3), |
26 | DEBUG_NETLINK = BIT(4), |
27 | DEBUG_EVENT = BIT(5), |
28 | DEBUG_TX = BIT(6), |
29 | DEBUG_RX = BIT(7), |
30 | DEBUG_SCAN = BIT(8), |
31 | DEBUG_CRYPT = BIT(9), |
32 | DEBUG_PSM = BIT(10), |
33 | DEBUG_MAC80211 = BIT(11), |
34 | DEBUG_CMD = BIT(12), |
35 | DEBUG_ACX = BIT(13), |
36 | DEBUG_ALL = ~0, |
37 | }; |
38 | |
39 | #define DEBUG_LEVEL (DEBUG_NONE) |
40 | |
41 | #define DEBUG_DUMP_LIMIT 1024 |
42 | |
43 | #define wl1251_error(fmt, arg...) \ |
44 | printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) |
45 | |
46 | #define wl1251_warning(fmt, arg...) \ |
47 | printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) |
48 | |
49 | #define wl1251_notice(fmt, arg...) \ |
50 | printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) |
51 | |
52 | #define wl1251_info(fmt, arg...) \ |
53 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) |
54 | |
55 | #define wl1251_debug(level, fmt, arg...) \ |
56 | do { \ |
57 | if (level & DEBUG_LEVEL) \ |
58 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ |
59 | } while (0) |
60 | |
61 | #define wl1251_dump(level, prefix, buf, len) \ |
62 | do { \ |
63 | if (level & DEBUG_LEVEL) \ |
64 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ |
65 | DUMP_PREFIX_OFFSET, 16, 1, \ |
66 | buf, \ |
67 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ |
68 | 0); \ |
69 | } while (0) |
70 | |
71 | #define wl1251_dump_ascii(level, prefix, buf, len) \ |
72 | do { \ |
73 | if (level & DEBUG_LEVEL) \ |
74 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ |
75 | DUMP_PREFIX_OFFSET, 16, 1, \ |
76 | buf, \ |
77 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ |
78 | true); \ |
79 | } while (0) |
80 | |
81 | #define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ |
82 | CFG_MC_FILTER_EN | \ |
83 | CFG_BSSID_FILTER_EN) |
84 | |
85 | #define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \ |
86 | CFG_RX_MGMT_EN | \ |
87 | CFG_RX_DATA_EN | \ |
88 | CFG_RX_CTL_EN | \ |
89 | CFG_RX_BCN_EN | \ |
90 | CFG_RX_AUTH_EN | \ |
91 | CFG_RX_ASSOC_EN) |
92 | |
93 | #define WL1251_BUSY_WORD_LEN 8 |
94 | |
95 | struct boot_attr { |
96 | u32 radio_type; |
97 | u8 mac_clock; |
98 | u8 arm_clock; |
99 | int firmware_debug; |
100 | u32 minor; |
101 | u32 major; |
102 | u32 bugfix; |
103 | }; |
104 | |
105 | enum wl1251_state { |
106 | WL1251_STATE_OFF, |
107 | WL1251_STATE_ON, |
108 | WL1251_STATE_PLT, |
109 | }; |
110 | |
111 | enum wl1251_partition_type { |
112 | PART_DOWN, |
113 | PART_WORK, |
114 | PART_DRPW, |
115 | |
116 | PART_TABLE_LEN |
117 | }; |
118 | |
119 | enum wl1251_station_mode { |
120 | STATION_ACTIVE_MODE, |
121 | STATION_POWER_SAVE_MODE, |
122 | STATION_IDLE, |
123 | }; |
124 | |
125 | struct wl1251_partition { |
126 | u32 size; |
127 | u32 start; |
128 | }; |
129 | |
130 | struct wl1251_partition_set { |
131 | struct wl1251_partition mem; |
132 | struct wl1251_partition reg; |
133 | }; |
134 | |
135 | struct wl1251; |
136 | |
137 | struct wl1251_stats { |
138 | struct acx_statistics *fw_stats; |
139 | unsigned long fw_stats_update; |
140 | |
141 | unsigned int retry_count; |
142 | unsigned int excessive_retries; |
143 | }; |
144 | |
145 | struct wl1251_debugfs { |
146 | struct dentry *rootdir; |
147 | struct dentry *fw_statistics; |
148 | |
149 | struct dentry *tx_internal_desc_overflow; |
150 | |
151 | struct dentry *rx_out_of_mem; |
152 | struct dentry *rx_hdr_overflow; |
153 | struct dentry *rx_hw_stuck; |
154 | struct dentry *rx_dropped; |
155 | struct dentry *rx_fcs_err; |
156 | struct dentry *rx_xfr_hint_trig; |
157 | struct dentry *rx_path_reset; |
158 | struct dentry *rx_reset_counter; |
159 | |
160 | struct dentry *dma_rx_requested; |
161 | struct dentry *dma_rx_errors; |
162 | struct dentry *dma_tx_requested; |
163 | struct dentry *dma_tx_errors; |
164 | |
165 | struct dentry *isr_cmd_cmplt; |
166 | struct dentry *isr_fiqs; |
167 | struct dentry *; |
168 | struct dentry *isr_rx_mem_overflow; |
169 | struct dentry *isr_rx_rdys; |
170 | struct dentry *isr_irqs; |
171 | struct dentry *isr_tx_procs; |
172 | struct dentry *isr_decrypt_done; |
173 | struct dentry *isr_dma0_done; |
174 | struct dentry *isr_dma1_done; |
175 | struct dentry *isr_tx_exch_complete; |
176 | struct dentry *isr_commands; |
177 | struct dentry *isr_rx_procs; |
178 | struct dentry *isr_hw_pm_mode_changes; |
179 | struct dentry *isr_host_acknowledges; |
180 | struct dentry *isr_pci_pm; |
181 | struct dentry *isr_wakeups; |
182 | struct dentry *; |
183 | |
184 | struct dentry *wep_addr_key_count; |
185 | struct dentry *wep_default_key_count; |
186 | /* skipping wep.reserved */ |
187 | struct dentry *wep_key_not_found; |
188 | struct dentry *wep_decrypt_fail; |
189 | struct dentry *wep_packets; |
190 | struct dentry *wep_interrupt; |
191 | |
192 | struct dentry *pwr_ps_enter; |
193 | struct dentry *pwr_elp_enter; |
194 | struct dentry *pwr_missing_bcns; |
195 | struct dentry *pwr_wake_on_host; |
196 | struct dentry *pwr_wake_on_timer_exp; |
197 | struct dentry *pwr_tx_with_ps; |
198 | struct dentry *pwr_tx_without_ps; |
199 | struct dentry *pwr_rcvd_beacons; |
200 | struct dentry *pwr_power_save_off; |
201 | struct dentry *pwr_enable_ps; |
202 | struct dentry *pwr_disable_ps; |
203 | struct dentry *pwr_fix_tsf_ps; |
204 | /* skipping cont_miss_bcns_spread for now */ |
205 | struct dentry *pwr_rcvd_awake_beacons; |
206 | |
207 | struct dentry *mic_rx_pkts; |
208 | struct dentry *mic_calc_failure; |
209 | |
210 | struct dentry *aes_encrypt_fail; |
211 | struct dentry *aes_decrypt_fail; |
212 | struct dentry *aes_encrypt_packets; |
213 | struct dentry *aes_decrypt_packets; |
214 | struct dentry *aes_encrypt_interrupt; |
215 | struct dentry *aes_decrypt_interrupt; |
216 | |
217 | struct dentry *event_heart_beat; |
218 | struct dentry *event_calibration; |
219 | struct dentry *event_rx_mismatch; |
220 | struct dentry *event_rx_mem_empty; |
221 | struct dentry *event_rx_pool; |
222 | struct dentry *event_oom_late; |
223 | struct dentry *event_phy_transmit_error; |
224 | struct dentry *event_tx_stuck; |
225 | |
226 | struct dentry *ps_pspoll_timeouts; |
227 | struct dentry *ps_upsd_timeouts; |
228 | struct dentry *ps_upsd_max_sptime; |
229 | struct dentry *ps_upsd_max_apturn; |
230 | struct dentry *ps_pspoll_max_apturn; |
231 | struct dentry *ps_pspoll_utilization; |
232 | struct dentry *ps_upsd_utilization; |
233 | |
234 | struct dentry *rxpipe_rx_prep_beacon_drop; |
235 | struct dentry *rxpipe_descr_host_int_trig_rx_data; |
236 | struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; |
237 | struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; |
238 | struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; |
239 | |
240 | struct dentry *tx_queue_len; |
241 | struct dentry *tx_queue_status; |
242 | |
243 | struct dentry *retry_count; |
244 | struct dentry *excessive_retries; |
245 | }; |
246 | |
247 | struct wl1251_if_operations { |
248 | void (*read)(struct wl1251 *wl, int addr, void *buf, size_t len); |
249 | void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len); |
250 | void (*read_elp)(struct wl1251 *wl, int addr, u32 *val); |
251 | void (*write_elp)(struct wl1251 *wl, int addr, u32 val); |
252 | int (*power)(struct wl1251 *wl, bool enable); |
253 | void (*reset)(struct wl1251 *wl); |
254 | void (*enable_irq)(struct wl1251 *wl); |
255 | void (*disable_irq)(struct wl1251 *wl); |
256 | }; |
257 | |
258 | struct wl1251 { |
259 | struct ieee80211_hw *hw; |
260 | bool mac80211_registered; |
261 | |
262 | void *if_priv; |
263 | const struct wl1251_if_operations *if_ops; |
264 | |
265 | int irq; |
266 | bool use_eeprom; |
267 | |
268 | struct regulator *vio; |
269 | |
270 | spinlock_t wl_lock; |
271 | |
272 | enum wl1251_state state; |
273 | struct mutex mutex; |
274 | |
275 | int physical_mem_addr; |
276 | int physical_reg_addr; |
277 | int virtual_mem_addr; |
278 | int virtual_reg_addr; |
279 | |
280 | int cmd_box_addr; |
281 | int event_box_addr; |
282 | struct boot_attr boot_attr; |
283 | |
284 | u8 *fw; |
285 | size_t fw_len; |
286 | u8 *nvs; |
287 | size_t nvs_len; |
288 | |
289 | u8 bssid[ETH_ALEN]; |
290 | u8 mac_addr[ETH_ALEN]; |
291 | u8 bss_type; |
292 | u8 listen_int; |
293 | int channel; |
294 | bool monitor_present; |
295 | bool joined; |
296 | |
297 | void *target_mem_map; |
298 | struct acx_data_path_params_resp *data_path; |
299 | |
300 | /* Number of TX packets transferred to the FW, modulo 16 */ |
301 | u32 data_in_count; |
302 | |
303 | /* Frames scheduled for transmission, not handled yet */ |
304 | struct sk_buff_head tx_queue; |
305 | bool tx_queue_stopped; |
306 | |
307 | struct work_struct tx_work; |
308 | |
309 | /* Pending TX frames */ |
310 | struct sk_buff *tx_frames[16]; |
311 | |
312 | /* |
313 | * Index pointing to the next TX complete entry |
314 | * in the cyclic XT complete array we get from |
315 | * the FW. |
316 | */ |
317 | u32 next_tx_complete; |
318 | |
319 | /* FW Rx counter */ |
320 | u32 rx_counter; |
321 | |
322 | /* Rx frames handled */ |
323 | u32 rx_handled; |
324 | |
325 | /* Current double buffer */ |
326 | u32 rx_current_buffer; |
327 | u32 rx_last_id; |
328 | |
329 | /* The target interrupt mask */ |
330 | u32 intr_mask; |
331 | struct work_struct irq_work; |
332 | |
333 | /* The mbox event mask */ |
334 | u32 event_mask; |
335 | |
336 | /* Mailbox pointers */ |
337 | u32 mbox_ptr[2]; |
338 | |
339 | /* Are we currently scanning */ |
340 | bool scanning; |
341 | |
342 | /* Default key (for WEP) */ |
343 | u32 default_key; |
344 | |
345 | unsigned int tx_mgmt_frm_rate; |
346 | unsigned int tx_mgmt_frm_mod; |
347 | |
348 | unsigned int rx_config; |
349 | unsigned int rx_filter; |
350 | |
351 | /* is firmware in elp mode */ |
352 | bool elp; |
353 | |
354 | struct delayed_work elp_work; |
355 | |
356 | enum wl1251_station_mode station_mode; |
357 | |
358 | /* PSM mode requested */ |
359 | bool psm_requested; |
360 | |
361 | /* retry counter for PSM entries */ |
362 | u8 psm_entry_retry; |
363 | |
364 | u16 beacon_int; |
365 | u8 dtim_period; |
366 | |
367 | /* in dBm */ |
368 | int power_level; |
369 | |
370 | int ; |
371 | |
372 | struct wl1251_stats stats; |
373 | struct wl1251_debugfs debugfs; |
374 | |
375 | __le32 buffer_32; |
376 | u32 buffer_cmd; |
377 | u8 buffer_busyword[WL1251_BUSY_WORD_LEN]; |
378 | struct wl1251_rx_descriptor *rx_descriptor; |
379 | |
380 | struct ieee80211_vif *vif; |
381 | |
382 | u32 chip_id; |
383 | char fw_ver[21]; |
384 | |
385 | /* Most recently reported noise in dBm */ |
386 | s8 noise; |
387 | }; |
388 | |
389 | int wl1251_plt_start(struct wl1251 *wl); |
390 | int wl1251_plt_stop(struct wl1251 *wl); |
391 | |
392 | struct ieee80211_hw *wl1251_alloc_hw(void); |
393 | int wl1251_free_hw(struct wl1251 *wl); |
394 | int wl1251_init_ieee80211(struct wl1251 *wl); |
395 | void wl1251_enable_interrupts(struct wl1251 *wl); |
396 | void wl1251_disable_interrupts(struct wl1251 *wl); |
397 | |
398 | #define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */ |
399 | #define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS |
400 | #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ |
401 | |
402 | #define WL1251_DEFAULT_POWER_LEVEL 20 |
403 | |
404 | #define WL1251_TX_QUEUE_LOW_WATERMARK 10 |
405 | #define WL1251_TX_QUEUE_HIGH_WATERMARK 25 |
406 | |
407 | #define WL1251_DEFAULT_BEACON_INT 100 |
408 | #define WL1251_DEFAULT_DTIM_PERIOD 1 |
409 | |
410 | #define WL1251_DEFAULT_CHANNEL 0 |
411 | |
412 | #define WL1251_DEFAULT_BET_CONSECUTIVE 10 |
413 | |
414 | #define CHIP_ID_1251_PG10 (0x7010101) |
415 | #define CHIP_ID_1251_PG11 (0x7020101) |
416 | #define CHIP_ID_1251_PG12 (0x7030101) |
417 | #define CHIP_ID_1271_PG10 (0x4030101) |
418 | #define CHIP_ID_1271_PG20 (0x4030111) |
419 | |
420 | #define WL1251_FW_NAME "ti-connectivity/wl1251-fw.bin" |
421 | #define WL1251_NVS_NAME "ti-connectivity/wl1251-nvs.bin" |
422 | |
423 | #define WL1251_POWER_ON_SLEEP 10 /* in milliseconds */ |
424 | |
425 | #define WL1251_PART_DOWN_MEM_START 0x0 |
426 | #define WL1251_PART_DOWN_MEM_SIZE 0x16800 |
427 | #define WL1251_PART_DOWN_REG_START REGISTERS_BASE |
428 | #define WL1251_PART_DOWN_REG_SIZE REGISTERS_DOWN_SIZE |
429 | |
430 | #define WL1251_PART_WORK_MEM_START 0x28000 |
431 | #define WL1251_PART_WORK_MEM_SIZE 0x14000 |
432 | #define WL1251_PART_WORK_REG_START REGISTERS_BASE |
433 | #define WL1251_PART_WORK_REG_SIZE REGISTERS_WORK_SIZE |
434 | |
435 | #define 10 |
436 | #define 10 |
437 | |
438 | #endif |
439 | |