1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * This file is part of wl18xx |
4 | * |
5 | * Copyright (C) 2011 Texas Instruments. All rights reserved. |
6 | */ |
7 | |
8 | #ifndef __WL18XX_ACX_H__ |
9 | #define __WL18XX_ACX_H__ |
10 | |
11 | #include "../wlcore/wlcore.h" |
12 | #include "../wlcore/acx.h" |
13 | |
14 | enum { |
15 | ACX_NS_IPV6_FILTER = 0x0050, |
16 | ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051, |
17 | ACX_CSUM_CONFIG = 0x0052, |
18 | ACX_SIM_CONFIG = 0x0053, |
19 | ACX_CLEAR_STATISTICS = 0x0054, |
20 | ACX_AUTO_RX_STREAMING = 0x0055, |
21 | ACX_PEER_CAP = 0x0056, |
22 | ACX_INTERRUPT_NOTIFY = 0x0057, |
23 | ACX_RX_BA_FILTER = 0x0058, |
24 | ACX_AP_SLEEP_CFG = 0x0059, |
25 | ACX_DYNAMIC_TRACES_CFG = 0x005A, |
26 | ACX_TIME_SYNC_CFG = 0x005B, |
27 | }; |
28 | |
29 | /* numbers of bits the length field takes (add 1 for the actual number) */ |
30 | #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15 |
31 | |
32 | #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ |
33 | WL1271_ACX_INTR_INIT_COMPLETE | \ |
34 | WL1271_ACX_INTR_EVENT_A | \ |
35 | WL1271_ACX_INTR_EVENT_B | \ |
36 | WL1271_ACX_INTR_CMD_COMPLETE | \ |
37 | WL1271_ACX_INTR_HW_AVAILABLE | \ |
38 | WL1271_ACX_INTR_DATA | \ |
39 | WL1271_ACX_SW_INTR_WATCHDOG) |
40 | |
41 | #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ |
42 | WL1271_ACX_INTR_EVENT_A | \ |
43 | WL1271_ACX_INTR_EVENT_B | \ |
44 | WL1271_ACX_INTR_HW_AVAILABLE | \ |
45 | WL1271_ACX_INTR_DATA | \ |
46 | WL1271_ACX_SW_INTR_WATCHDOG) |
47 | |
48 | struct wl18xx_acx_host_config_bitmap { |
49 | struct acx_header ; |
50 | |
51 | __le32 host_cfg_bitmap; |
52 | |
53 | __le32 host_sdio_block_size; |
54 | |
55 | /* extra mem blocks per frame in TX. */ |
56 | __le32 ; |
57 | |
58 | /* |
59 | * number of bits of the length field in the first TX word |
60 | * (up to 15 - for using the entire 16 bits). |
61 | */ |
62 | __le32 length_field_size; |
63 | |
64 | } __packed; |
65 | |
66 | enum { |
67 | CHECKSUM_OFFLOAD_DISABLED = 0, |
68 | CHECKSUM_OFFLOAD_ENABLED = 1, |
69 | CHECKSUM_OFFLOAD_FAKE_RX = 2, |
70 | CHECKSUM_OFFLOAD_INVALID = 0xFF |
71 | }; |
72 | |
73 | struct wl18xx_acx_checksum_state { |
74 | struct acx_header ; |
75 | |
76 | /* enum acx_checksum_state */ |
77 | u8 checksum_state; |
78 | u8 pad[3]; |
79 | } __packed; |
80 | |
81 | |
82 | struct wl18xx_acx_error_stats { |
83 | u32 error_frame_non_ctrl; |
84 | u32 error_frame_ctrl; |
85 | u32 error_frame_during_protection; |
86 | u32 null_frame_tx_start; |
87 | u32 null_frame_cts_start; |
88 | u32 bar_retry; |
89 | u32 num_frame_cts_nul_flid; |
90 | u32 tx_abort_failure; |
91 | u32 tx_resume_failure; |
92 | u32 rx_cmplt_db_overflow_cnt; |
93 | u32 elp_while_rx_exch; |
94 | u32 elp_while_tx_exch; |
95 | u32 elp_while_tx; |
96 | u32 elp_while_nvic_pending; |
97 | u32 rx_excessive_frame_len; |
98 | u32 burst_mismatch; |
99 | u32 tbc_exch_mismatch; |
100 | } __packed; |
101 | |
102 | #define NUM_OF_RATES_INDEXES 30 |
103 | struct wl18xx_acx_tx_stats { |
104 | u32 tx_prepared_descs; |
105 | u32 tx_cmplt; |
106 | u32 tx_template_prepared; |
107 | u32 tx_data_prepared; |
108 | u32 tx_template_programmed; |
109 | u32 tx_data_programmed; |
110 | u32 tx_burst_programmed; |
111 | u32 tx_starts; |
112 | u32 tx_stop; |
113 | u32 tx_start_templates; |
114 | u32 tx_start_int_templates; |
115 | u32 tx_start_fw_gen; |
116 | u32 tx_start_data; |
117 | u32 tx_start_null_frame; |
118 | u32 tx_exch; |
119 | u32 tx_retry_template; |
120 | u32 tx_retry_data; |
121 | u32 tx_retry_per_rate[NUM_OF_RATES_INDEXES]; |
122 | u32 tx_exch_pending; |
123 | u32 tx_exch_expiry; |
124 | u32 tx_done_template; |
125 | u32 tx_done_data; |
126 | u32 tx_done_int_template; |
127 | u32 tx_cfe1; |
128 | u32 tx_cfe2; |
129 | u32 frag_called; |
130 | u32 frag_mpdu_alloc_failed; |
131 | u32 frag_init_called; |
132 | u32 frag_in_process_called; |
133 | u32 frag_tkip_called; |
134 | u32 frag_key_not_found; |
135 | u32 frag_need_fragmentation; |
136 | u32 frag_bad_mblk_num; |
137 | u32 frag_failed; |
138 | u32 frag_cache_hit; |
139 | u32 frag_cache_miss; |
140 | } __packed; |
141 | |
142 | struct wl18xx_acx_rx_stats { |
143 | u32 rx_beacon_early_term; |
144 | u32 rx_out_of_mpdu_nodes; |
145 | u32 rx_hdr_overflow; |
146 | u32 rx_dropped_frame; |
147 | u32 rx_done_stage; |
148 | u32 rx_done; |
149 | u32 rx_defrag; |
150 | u32 rx_defrag_end; |
151 | u32 rx_cmplt; |
152 | u32 rx_pre_complt; |
153 | u32 rx_cmplt_task; |
154 | u32 rx_phy_hdr; |
155 | u32 rx_timeout; |
156 | u32 rx_rts_timeout; |
157 | u32 rx_timeout_wa; |
158 | u32 defrag_called; |
159 | u32 defrag_init_called; |
160 | u32 defrag_in_process_called; |
161 | u32 defrag_tkip_called; |
162 | u32 defrag_need_defrag; |
163 | u32 defrag_decrypt_failed; |
164 | u32 decrypt_key_not_found; |
165 | u32 defrag_need_decrypt; |
166 | u32 rx_tkip_replays; |
167 | u32 rx_xfr; |
168 | } __packed; |
169 | |
170 | struct wl18xx_acx_isr_stats { |
171 | u32 irqs; |
172 | } __packed; |
173 | |
174 | #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10 |
175 | |
176 | struct wl18xx_acx_pwr_stats { |
177 | u32 missing_bcns_cnt; |
178 | u32 rcvd_bcns_cnt; |
179 | u32 connection_out_of_sync; |
180 | u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD]; |
181 | u32 rcvd_awake_bcns_cnt; |
182 | u32 sleep_time_count; |
183 | u32 sleep_time_avg; |
184 | u32 sleep_cycle_avg; |
185 | u32 sleep_percent; |
186 | u32 ap_sleep_active_conf; |
187 | u32 ap_sleep_user_conf; |
188 | u32 ap_sleep_counter; |
189 | } __packed; |
190 | |
191 | struct wl18xx_acx_rx_filter_stats { |
192 | u32 beacon_filter; |
193 | u32 arp_filter; |
194 | u32 mc_filter; |
195 | u32 dup_filter; |
196 | u32 data_filter; |
197 | u32 ibss_filter; |
198 | u32 protection_filter; |
199 | u32 accum_arp_pend_requests; |
200 | u32 max_arp_queue_dep; |
201 | } __packed; |
202 | |
203 | struct wl18xx_acx_rx_rate_stats { |
204 | u32 rx_frames_per_rates[50]; |
205 | } __packed; |
206 | |
207 | #define AGGR_STATS_TX_AGG 16 |
208 | #define AGGR_STATS_RX_SIZE_LEN 16 |
209 | |
210 | struct wl18xx_acx_aggr_stats { |
211 | u32 tx_agg_rate[AGGR_STATS_TX_AGG]; |
212 | u32 tx_agg_len[AGGR_STATS_TX_AGG]; |
213 | u32 rx_size[AGGR_STATS_RX_SIZE_LEN]; |
214 | } __packed; |
215 | |
216 | #define PIPE_STATS_HW_FIFO 11 |
217 | |
218 | struct wl18xx_acx_pipeline_stats { |
219 | u32 hs_tx_stat_fifo_int; |
220 | u32 hs_rx_stat_fifo_int; |
221 | u32 enc_tx_stat_fifo_int; |
222 | u32 enc_rx_stat_fifo_int; |
223 | u32 rx_complete_stat_fifo_int; |
224 | u32 pre_proc_swi; |
225 | u32 post_proc_swi; |
226 | u32 sec_frag_swi; |
227 | u32 pre_to_defrag_swi; |
228 | u32 defrag_to_rx_xfer_swi; |
229 | u32 dec_packet_in; |
230 | u32 dec_packet_in_fifo_full; |
231 | u32 dec_packet_out; |
232 | u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO]; |
233 | u16 padding; |
234 | } __packed; |
235 | |
236 | #define DIVERSITY_STATS_NUM_OF_ANT 2 |
237 | |
238 | struct wl18xx_acx_diversity_stats { |
239 | u32 num_of_packets_per_ant[DIVERSITY_STATS_NUM_OF_ANT]; |
240 | u32 total_num_of_toggles; |
241 | } __packed; |
242 | |
243 | struct wl18xx_acx_thermal_stats { |
244 | u16 irq_thr_low; |
245 | u16 irq_thr_high; |
246 | u16 tx_stop; |
247 | u16 tx_resume; |
248 | u16 false_irq; |
249 | u16 adc_source_unexpected; |
250 | } __packed; |
251 | |
252 | #define WL18XX_NUM_OF_CALIBRATIONS_ERRORS 18 |
253 | struct wl18xx_acx_calib_failure_stats { |
254 | u16 fail_count[WL18XX_NUM_OF_CALIBRATIONS_ERRORS]; |
255 | u32 calib_count; |
256 | } __packed; |
257 | |
258 | struct wl18xx_roaming_stats { |
259 | s32 ; |
260 | } __packed; |
261 | |
262 | struct wl18xx_dfs_stats { |
263 | u32 num_of_radar_detections; |
264 | } __packed; |
265 | |
266 | struct wl18xx_acx_statistics { |
267 | struct acx_header ; |
268 | |
269 | struct wl18xx_acx_error_stats error; |
270 | struct wl18xx_acx_tx_stats tx; |
271 | struct wl18xx_acx_rx_stats rx; |
272 | struct wl18xx_acx_isr_stats isr; |
273 | struct wl18xx_acx_pwr_stats pwr; |
274 | struct wl18xx_acx_rx_filter_stats rx_filter; |
275 | struct wl18xx_acx_rx_rate_stats rx_rate; |
276 | struct wl18xx_acx_aggr_stats aggr_size; |
277 | struct wl18xx_acx_pipeline_stats pipeline; |
278 | struct wl18xx_acx_diversity_stats diversity; |
279 | struct wl18xx_acx_thermal_stats thermal; |
280 | struct wl18xx_acx_calib_failure_stats calib; |
281 | struct wl18xx_roaming_stats roaming; |
282 | struct wl18xx_dfs_stats dfs; |
283 | } __packed; |
284 | |
285 | struct wl18xx_acx_clear_statistics { |
286 | struct acx_header ; |
287 | }; |
288 | |
289 | enum wlcore_bandwidth { |
290 | WLCORE_BANDWIDTH_20MHZ, |
291 | WLCORE_BANDWIDTH_40MHZ, |
292 | }; |
293 | |
294 | struct wlcore_peer_ht_operation_mode { |
295 | struct acx_header ; |
296 | |
297 | u8 hlid; |
298 | u8 bandwidth; /* enum wlcore_bandwidth */ |
299 | u8 padding[2]; |
300 | }; |
301 | |
302 | /* |
303 | * ACX_PEER_CAP |
304 | * this struct is very similar to wl1271_acx_ht_capabilities, with the |
305 | * addition of supported rates |
306 | */ |
307 | struct wlcore_acx_peer_cap { |
308 | struct acx_header ; |
309 | |
310 | /* bitmask of capability bits supported by the peer */ |
311 | __le32 ht_capabilites; |
312 | |
313 | /* rates supported by the remote peer */ |
314 | __le32 supported_rates; |
315 | |
316 | /* Indicates to which link these capabilities apply. */ |
317 | u8 hlid; |
318 | |
319 | /* |
320 | * This the maximum A-MPDU length supported by the AP. The FW may not |
321 | * exceed this length when sending A-MPDUs |
322 | */ |
323 | u8 ampdu_max_length; |
324 | |
325 | /* This is the minimal spacing required when sending A-MPDUs to the AP*/ |
326 | u8 ampdu_min_spacing; |
327 | |
328 | u8 padding; |
329 | } __packed; |
330 | |
331 | /* |
332 | * ACX_INTERRUPT_NOTIFY |
333 | * enable/disable fast-link/PSM notification from FW |
334 | */ |
335 | struct wl18xx_acx_interrupt_notify { |
336 | struct acx_header ; |
337 | u32 enable; |
338 | }; |
339 | |
340 | /* |
341 | * ACX_RX_BA_FILTER |
342 | * enable/disable RX BA filtering in FW |
343 | */ |
344 | struct wl18xx_acx_rx_ba_filter { |
345 | struct acx_header ; |
346 | u32 enable; |
347 | }; |
348 | |
349 | struct acx_ap_sleep_cfg { |
350 | struct acx_header ; |
351 | /* Duty Cycle (20-80% of staying Awake) for IDLE AP |
352 | * (0: disable) |
353 | */ |
354 | u8 idle_duty_cycle; |
355 | /* Duty Cycle (20-80% of staying Awake) for Connected AP |
356 | * (0: disable) |
357 | */ |
358 | u8 connected_duty_cycle; |
359 | /* Maximum stations that are allowed to be connected to AP |
360 | * (255: no limit) |
361 | */ |
362 | u8 max_stations_thresh; |
363 | /* Timeout till enabling the Sleep Mechanism after data stops |
364 | * [unit: 100 msec] |
365 | */ |
366 | u8 idle_conn_thresh; |
367 | } __packed; |
368 | |
369 | /* |
370 | * ACX_DYNAMIC_TRACES_CFG |
371 | * configure the FW dynamic traces |
372 | */ |
373 | struct acx_dynamic_fw_traces_cfg { |
374 | struct acx_header ; |
375 | __le32 dynamic_fw_traces; |
376 | } __packed; |
377 | |
378 | /* |
379 | * ACX_TIME_SYNC_CFG |
380 | * configure the time sync parameters |
381 | */ |
382 | struct acx_time_sync_cfg { |
383 | struct acx_header ; |
384 | u8 sync_mode; |
385 | u8 zone_mac_addr[ETH_ALEN]; |
386 | u8 padding[1]; |
387 | } __packed; |
388 | |
389 | int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap, |
390 | u32 sdio_blk_size, u32 , |
391 | u32 len_field_size); |
392 | int wl18xx_acx_set_checksum_state(struct wl1271 *wl); |
393 | int wl18xx_acx_clear_statistics(struct wl1271 *wl); |
394 | int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide); |
395 | int wl18xx_acx_set_peer_cap(struct wl1271 *wl, |
396 | struct ieee80211_sta_ht_cap *ht_cap, |
397 | bool allow_ht_operation, |
398 | u32 rate_set, u8 hlid); |
399 | int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action); |
400 | int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action); |
401 | int wl18xx_acx_ap_sleep(struct wl1271 *wl); |
402 | int wl18xx_acx_dynamic_fw_traces(struct wl1271 *wl); |
403 | int wl18xx_acx_time_sync_cfg(struct wl1271 *wl); |
404 | |
405 | #endif /* __WL18XX_ACX_H__ */ |
406 | |