1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * This file is part of wlcore |
4 | * |
5 | * Copyright (C) 2011 Texas Instruments Inc. |
6 | */ |
7 | |
8 | #ifndef __REG_H__ |
9 | #define __REG_H__ |
10 | |
11 | #define WL18XX_REGISTERS_BASE 0x00800000 |
12 | #define WL18XX_CODE_BASE 0x00000000 |
13 | #define WL18XX_DATA_BASE 0x00400000 |
14 | #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000 |
15 | #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000 |
16 | #define WL18XX_PHY_BASE 0x00900000 |
17 | #define WL18XX_TOP_OCP_BASE 0x00A00000 |
18 | #define WL18XX_PACKET_RAM_BASE 0x00B00000 |
19 | #define WL18XX_HOST_BASE 0x00C00000 |
20 | |
21 | #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000 |
22 | |
23 | #define WL18XX_REG_BOOT_PART_START 0x00802000 |
24 | #define WL18XX_REG_BOOT_PART_SIZE 0x00014578 |
25 | |
26 | #define WL18XX_PHY_INIT_MEM_ADDR 0x80926000 |
27 | #define WL18XX_PHY_END_MEM_ADDR 0x8093CA44 |
28 | #define WL18XX_PHY_INIT_MEM_SIZE \ |
29 | (WL18XX_PHY_END_MEM_ADDR - WL18XX_PHY_INIT_MEM_ADDR) |
30 | |
31 | #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE) |
32 | #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000) |
33 | #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000) |
34 | #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000) |
35 | #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000) |
36 | #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000) |
37 | #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000) |
38 | #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000) |
39 | #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000) |
40 | #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000) |
41 | #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800) |
42 | #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00) |
43 | #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000) |
44 | #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400) |
45 | |
46 | #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004) |
47 | #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8) |
48 | #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0) |
49 | #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074) |
50 | #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078) |
51 | #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC) |
52 | |
53 | #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C) |
54 | |
55 | #define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018) |
56 | #define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008) |
57 | |
58 | /* Scratch Pad registers*/ |
59 | #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC) |
60 | #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0) |
61 | #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4) |
62 | #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8) |
63 | #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC) |
64 | #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504) |
65 | #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500) |
66 | #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508) |
67 | #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510) |
68 | #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C) |
69 | #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514) |
70 | #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518) |
71 | #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C) |
72 | #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520) |
73 | |
74 | /* Spare registers*/ |
75 | #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194) |
76 | #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198) |
77 | #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C) |
78 | #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0) |
79 | #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4) |
80 | #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8) |
81 | #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC) |
82 | #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0) |
83 | #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524) |
84 | #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528) |
85 | #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C) |
86 | #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530) |
87 | #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534) |
88 | #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538) |
89 | #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C) |
90 | #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540) |
91 | |
92 | #define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0) |
93 | #define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1) |
94 | #define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4) |
95 | |
96 | #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100) |
97 | #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C) |
98 | #define TOP_FN0_CCCR_REG_32 (WL18XX_TOP_OCP_BASE + 0x64) |
99 | |
100 | /* PRCM registers */ |
101 | #define PLATFORM_DETECTION 0xA0E3E0 |
102 | #define OCS_EN 0xA02080 |
103 | #define PRIMARY_CLK_DETECT 0xA020A6 |
104 | #define PLLSH_COEX_PLL_N 0xA02384 |
105 | #define PLLSH_COEX_PLL_M 0xA02382 |
106 | #define PLLSH_COEX_PLL_SWALLOW_EN 0xA0238E |
107 | #define PLLSH_WL_PLL_SEL 0xA02398 |
108 | |
109 | #define PLLSH_WCS_PLL_N 0xA02362 |
110 | #define PLLSH_WCS_PLL_M 0xA02360 |
111 | #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 0xA02364 |
112 | #define PLLSH_WCS_PLL_Q_FACTOR_CFG_2 0xA02366 |
113 | #define PLLSH_WCS_PLL_P_FACTOR_CFG_1 0xA02368 |
114 | #define PLLSH_WCS_PLL_P_FACTOR_CFG_2 0xA0236A |
115 | #define PLLSH_WCS_PLL_SWALLOW_EN 0xA0236C |
116 | #define PLLSH_WL_PLL_EN 0xA02392 |
117 | |
118 | #define PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK 0xFFFF |
119 | #define PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK 0x007F |
120 | #define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK 0xFFFF |
121 | #define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK 0x000F |
122 | |
123 | #define PLLSH_WL_PLL_EN_VAL1 0x7 |
124 | #define PLLSH_WL_PLL_EN_VAL2 0x2 |
125 | #define PLLSH_COEX_PLL_SWALLOW_EN_VAL1 0x2 |
126 | #define PLLSH_COEX_PLL_SWALLOW_EN_VAL2 0x11 |
127 | |
128 | #define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 0x1 |
129 | #define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 0x12 |
130 | |
131 | #define PLLSH_WL_PLL_SEL_WCS_PLL 0x0 |
132 | #define PLLSH_WL_PLL_SEL_COEX_PLL 0x1 |
133 | |
134 | #define WL18XX_REG_FUSE_DATA_1_3 0xA0260C |
135 | #define WL18XX_PG_VER_MASK 0x70 |
136 | #define WL18XX_PG_VER_OFFSET 4 |
137 | #define WL18XX_ROM_VER_MASK 0x3e00 |
138 | #define WL18XX_ROM_VER_OFFSET 9 |
139 | #define WL18XX_METAL_VER_MASK 0xC |
140 | #define WL18XX_METAL_VER_OFFSET 2 |
141 | #define WL18XX_NEW_METAL_VER_MASK 0x180 |
142 | #define WL18XX_NEW_METAL_VER_OFFSET 7 |
143 | |
144 | #define WL18XX_PACKAGE_TYPE_OFFSET 13 |
145 | #define WL18XX_PACKAGE_TYPE_WSP 0 |
146 | |
147 | #define WL18XX_REG_FUSE_DATA_2_3 0xA02614 |
148 | #define WL18XX_RDL_VER_MASK 0x1f00 |
149 | #define WL18XX_RDL_VER_OFFSET 8 |
150 | |
151 | #define WL18XX_REG_FUSE_BD_ADDR_1 0xA02602 |
152 | #define WL18XX_REG_FUSE_BD_ADDR_2 0xA02606 |
153 | |
154 | #define WL18XX_CMD_MBOX_ADDRESS 0xB007B4 |
155 | |
156 | #define WL18XX_FW_STATUS_ADDR 0x50F8 |
157 | |
158 | #define CHIP_ID_185x_PG10 (0x06030101) |
159 | #define CHIP_ID_185x_PG20 (0x06030111) |
160 | |
161 | /* |
162 | * Host Command Interrupt. Setting this bit masks |
163 | * the interrupt that the host issues to inform |
164 | * the FW that it has sent a command |
165 | * to the Wlan hardware Command Mailbox. |
166 | */ |
167 | #define WL18XX_INTR_TRIG_CMD BIT(28) |
168 | |
169 | /* |
170 | * Host Event Acknowlegde Interrupt. The host |
171 | * sets this bit to acknowledge that it received |
172 | * the unsolicited information from the event |
173 | * mailbox. |
174 | */ |
175 | #define WL18XX_INTR_TRIG_EVENT_ACK BIT(29) |
176 | |
177 | /* |
178 | * To boot the firmware in PLT mode we need to write this value in |
179 | * SCR_PAD8 before starting. |
180 | */ |
181 | #define WL18XX_SCR_PAD8_PLT 0xBABABEBE |
182 | |
183 | enum { |
184 | COMPONENT_NO_SWITCH = 0x0, |
185 | COMPONENT_2_WAY_SWITCH = 0x1, |
186 | COMPONENT_3_WAY_SWITCH = 0x2, |
187 | COMPONENT_MATCHING = 0x3, |
188 | }; |
189 | |
190 | enum { |
191 | FEM_NONE = 0x0, |
192 | FEM_VENDOR_1 = 0x1, |
193 | FEM_VENDOR_2 = 0x2, |
194 | FEM_VENDOR_3 = 0x3, |
195 | }; |
196 | |
197 | enum { |
198 | BOARD_TYPE_EVB_18XX = 0, |
199 | BOARD_TYPE_DVP_18XX = 1, |
200 | BOARD_TYPE_HDK_18XX = 2, |
201 | BOARD_TYPE_FPGA_18XX = 3, |
202 | BOARD_TYPE_COM8_18XX = 4, |
203 | |
204 | NUM_BOARD_TYPES, |
205 | }; |
206 | |
207 | enum wl18xx_rdl_num { |
208 | RDL_NONE = 0, |
209 | RDL_1_HP = 1, |
210 | RDL_2_SP = 2, |
211 | RDL_3_HP = 3, |
212 | RDL_4_SP = 4, |
213 | RDL_5_SP = 0x11, |
214 | RDL_6_SP = 0x12, |
215 | RDL_7_SP = 0x13, |
216 | RDL_8_SP = 0x14, |
217 | |
218 | _RDL_LAST, |
219 | RDL_MAX = _RDL_LAST - 1, |
220 | }; |
221 | |
222 | |
223 | /* FPGA_SPARE_1 register - used to change the PHY ATPG clock at boot time */ |
224 | #define WL18XX_PHY_FPGA_SPARE_1 0x8093CA40 |
225 | |
226 | /* command to disable FDSP clock */ |
227 | #define MEM_FDSP_CLK_120_DISABLE 0x80000000 |
228 | |
229 | /* command to set ATPG clock toward FDSP Code RAM rather than its own clock */ |
230 | #define MEM_FDSP_CODERAM_FUNC_CLK_SEL 0xC0000000 |
231 | |
232 | /* command to re-enable FDSP clock */ |
233 | #define MEM_FDSP_CLK_120_ENABLE 0x40000000 |
234 | |
235 | #endif /* __REG_H__ */ |
236 | |