1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/* ZD1211 USB-WLAN driver for Linux
3	*
4	* Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5	* Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
6	*/
7
8	/* This file implements all the hardware specific functions for the ZD1211
9	* and ZD1211B chips. Support for the ZD1211B was possible after Timothy
10	* Legge sent me a ZD1211B device. Thank you Tim. -- Uli
11	*/
12
13	#include <linux/kernel.h>
14	#include <linux/errno.h>
15	#include <linux/slab.h>
16
17	#include "zd_def.h"
18	#include "zd_chip.h"
19	#include "zd_mac.h"
20	#include "zd_rf.h"
21
22	void zd_chip_init(struct zd_chip *chip,
23	struct ieee80211_hw *hw,
24	struct usb_interface *intf)
25	{
26	memset(chip, 0, sizeof(*chip));
27	mutex_init(&chip->mutex);
28	zd_usb_init(usb: &chip->usb, hw, intf);
29	zd_rf_init(rf: &chip->rf);
30	}
31
32	void zd_chip_clear(struct zd_chip *chip)
33	{
34	ZD_ASSERT(!mutex_is_locked(&chip->mutex));
35	zd_usb_clear(usb: &chip->usb);
36	zd_rf_clear(rf: &chip->rf);
37	mutex_destroy(lock: &chip->mutex);
38	ZD_MEMCLEAR(chip, sizeof(*chip));
39	}
40
41	static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
42	{
43	u8 *addr = zd_mac_get_perm_addr(mac: zd_chip_to_mac(chip));
44	return scnprintf(buf: buffer, size, fmt: "%3phD", addr);
45	}
46
47	/* Prints an identifier line, which will support debugging. */
48	static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
49	{
50	int i = 0;
51
52	i = scnprintf(buf: buffer, size, fmt: "zd1211%s chip ",
53	zd_chip_is_zd1211b(chip) ? "b" : "");
54	i += zd_usb_scnprint_id(usb: &chip->usb, buffer: buffer+i, size: size-i);
55	i += scnprintf(buf: buffer+i, size: size-i, fmt: " ");
56	i += scnprint_mac_oui(chip, buffer: buffer+i, size: size-i);
57	i += scnprintf(buf: buffer+i, size: size-i, fmt: " ");
58	i += zd_rf_scnprint_id(rf: &chip->rf, buffer: buffer+i, size: size-i);
59	i += scnprintf(buf: buffer+i, size: size-i, fmt: " pa%1x %c%c%c%c%c", chip->pa_type,
60	chip->patch_cck_gain ? 'g' : '-',
61	chip->patch_cr157 ? '7' : '-',
62	chip->patch_6m_band_edge ? '6' : '-',
63	chip->new_phy_layout ? 'N' : '-',
64	chip->al2230s_bit ? 'S' : '-');
65	return i;
66	}
67
68	static void print_id(struct zd_chip *chip)
69	{
70	char buffer[80];
71
72	scnprint_id(chip, buffer, size: sizeof(buffer));
73	buffer[sizeof(buffer)-1] = 0;
74	dev_info(zd_chip_dev(chip), "%s\n", buffer);
75	}
76
77	static zd_addr_t inc_addr(zd_addr_t addr)
78	{
79	u16 a = (u16)addr;
80	/* Control registers use byte addressing, but everything else uses word
81	* addressing. */
82	if ((a & 0xf000) == CR_START)
83	a += 2;
84	else
85	a += 1;
86	return (zd_addr_t)a;
87	}
88
89	/* Read a variable number of 32-bit values. Parameter count is not allowed to
90	* exceed USB_MAX_IOREAD32_COUNT.
91	*/
92	int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
93	unsigned int count)
94	{
95	int r;
96	int i;
97	zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2];
98	u16 v16[USB_MAX_IOREAD32_COUNT * 2];
99	unsigned int count16;
100
101	if (count > USB_MAX_IOREAD32_COUNT)
102	return -EINVAL;
103
104	/* Use stack for values and addresses. */
105	count16 = 2 * count;
106	BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16));
107	BUG_ON(count16 * sizeof(u16) > sizeof(v16));
108
109	for (i = 0; i < count; i++) {
110	int j = 2*i;
111	/* We read the high word always first. */
112	a16[j] = inc_addr(addr: addr[i]);
113	a16[j+1] = addr[i];
114	}
115
116	r = zd_ioread16v_locked(chip, values: v16, addresses: a16, count: count16);
117	if (r) {
118	dev_dbg_f(zd_chip_dev(chip),
119	"error: %s. Error number %d\n", __func__, r);
120	return r;
121	}
122
123	for (i = 0; i < count; i++) {
124	int j = 2*i;
125	values[i] = (v16[j] << 16) | v16[j+1];
126	}
127
128	return 0;
129	}
130
131	static int _zd_iowrite32v_async_locked(struct zd_chip *chip,
132	const struct zd_ioreq32 *ioreqs,
133	unsigned int count)
134	{
135	int i, j, r;
136	struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2];
137	unsigned int count16;
138
139	/* Use stack for values and addresses. */
140
141	ZD_ASSERT(mutex_is_locked(&chip->mutex));
142
143	if (count == 0)
144	return 0;
145	if (count > USB_MAX_IOWRITE32_COUNT)
146	return -EINVAL;
147
148	count16 = 2 * count;
149	BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16));
150
151	for (i = 0; i < count; i++) {
152	j = 2*i;
153	/* We write the high word always first. */
154	ioreqs16[j].value = ioreqs[i].value >> 16;
155	ioreqs16[j].addr = inc_addr(addr: ioreqs[i].addr);
156	ioreqs16[j+1].value = ioreqs[i].value;
157	ioreqs16[j+1].addr = ioreqs[i].addr;
158	}
159
160	r = zd_usb_iowrite16v_async(usb: &chip->usb, ioreqs: ioreqs16, count: count16);
161	#ifdef DEBUG
162	if (r) {
163	dev_dbg_f(zd_chip_dev(chip),
164	"error %d in zd_usb_write16v\n", r);
165	}
166	#endif /* DEBUG */
167	return r;
168	}
169
170	int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
171	unsigned int count)
172	{
173	int r;
174
175	zd_usb_iowrite16v_async_start(usb: &chip->usb);
176	r = _zd_iowrite32v_async_locked(chip, ioreqs, count);
177	if (r) {
178	zd_usb_iowrite16v_async_end(usb: &chip->usb, timeout: 0);
179	return r;
180	}
181	return zd_usb_iowrite16v_async_end(usb: &chip->usb, timeout: 50 /* ms */);
182	}
183
184	int zd_iowrite16a_locked(struct zd_chip *chip,
185	const struct zd_ioreq16 *ioreqs, unsigned int count)
186	{
187	int r;
188	unsigned int i, j, t, max;
189
190	ZD_ASSERT(mutex_is_locked(&chip->mutex));
191	zd_usb_iowrite16v_async_start(usb: &chip->usb);
192
193	for (i = 0; i < count; i += j + t) {
194	t = 0;
195	max = count-i;
196	if (max > USB_MAX_IOWRITE16_COUNT)
197	max = USB_MAX_IOWRITE16_COUNT;
198	for (j = 0; j < max; j++) {
199	if (!ioreqs[i+j].addr) {
200	t = 1;
201	break;
202	}
203	}
204
205	r = zd_usb_iowrite16v_async(usb: &chip->usb, ioreqs: &ioreqs[i], count: j);
206	if (r) {
207	zd_usb_iowrite16v_async_end(usb: &chip->usb, timeout: 0);
208	dev_dbg_f(zd_chip_dev(chip),
209	"error zd_usb_iowrite16v. Error number %d\n",
210	r);
211	return r;
212	}
213	}
214
215	return zd_usb_iowrite16v_async_end(usb: &chip->usb, timeout: 50 /* ms */);
216	}
217
218	/* Writes a variable number of 32 bit registers. The functions will split
219	* that in several USB requests. A split can be forced by inserting an IO
220	* request with an zero address field.
221	*/
222	int zd_iowrite32a_locked(struct zd_chip *chip,
223	const struct zd_ioreq32 *ioreqs, unsigned int count)
224	{
225	int r;
226	unsigned int i, j, t, max;
227
228	zd_usb_iowrite16v_async_start(usb: &chip->usb);
229
230	for (i = 0; i < count; i += j + t) {
231	t = 0;
232	max = count-i;
233	if (max > USB_MAX_IOWRITE32_COUNT)
234	max = USB_MAX_IOWRITE32_COUNT;
235	for (j = 0; j < max; j++) {
236	if (!ioreqs[i+j].addr) {
237	t = 1;
238	break;
239	}
240	}
241
242	r = _zd_iowrite32v_async_locked(chip, ioreqs: &ioreqs[i], count: j);
243	if (r) {
244	zd_usb_iowrite16v_async_end(usb: &chip->usb, timeout: 0);
245	dev_dbg_f(zd_chip_dev(chip),
246	"error _%s. Error number %d\n", __func__,
247	r);
248	return r;
249	}
250	}
251
252	return zd_usb_iowrite16v_async_end(usb: &chip->usb, timeout: 50 /* ms */);
253	}
254
255	int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
256	{
257	int r;
258
259	mutex_lock(&chip->mutex);
260	r = zd_ioread16_locked(chip, value, addr);
261	mutex_unlock(lock: &chip->mutex);
262	return r;
263	}
264
265	int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
266	{
267	int r;
268
269	mutex_lock(&chip->mutex);
270	r = zd_ioread32_locked(chip, value, addr);
271	mutex_unlock(lock: &chip->mutex);
272	return r;
273	}
274
275	int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
276	{
277	int r;
278
279	mutex_lock(&chip->mutex);
280	r = zd_iowrite16_locked(chip, value, addr);
281	mutex_unlock(lock: &chip->mutex);
282	return r;
283	}
284
285	int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
286	{
287	int r;
288
289	mutex_lock(&chip->mutex);
290	r = zd_iowrite32_locked(chip, value, addr);
291	mutex_unlock(lock: &chip->mutex);
292	return r;
293	}
294
295	int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
296	u32 *values, unsigned int count)
297	{
298	int r;
299
300	mutex_lock(&chip->mutex);
301	r = zd_ioread32v_locked(chip, values, addr: addresses, count);
302	mutex_unlock(lock: &chip->mutex);
303	return r;
304	}
305
306	int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
307	unsigned int count)
308	{
309	int r;
310
311	mutex_lock(&chip->mutex);
312	r = zd_iowrite32a_locked(chip, ioreqs, count);
313	mutex_unlock(lock: &chip->mutex);
314	return r;
315	}
316
317	static int read_pod(struct zd_chip *chip, u8 *rf_type)
318	{
319	int r;
320	u32 value;
321
322	ZD_ASSERT(mutex_is_locked(&chip->mutex));
323	r = zd_ioread32_locked(chip, value: &value, E2P_POD);
324	if (r)
325	goto error;
326	dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
327
328	/* FIXME: AL2230 handling (Bit 7 in POD) */
329	*rf_type = value & 0x0f;
330	chip->pa_type = (value >> 16) & 0x0f;
331	chip->patch_cck_gain = (value >> 8) & 0x1;
332	chip->patch_cr157 = (value >> 13) & 0x1;
333	chip->patch_6m_band_edge = (value >> 21) & 0x1;
334	chip->new_phy_layout = (value >> 31) & 0x1;
335	chip->al2230s_bit = (value >> 7) & 0x1;
336	chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
337	chip->supports_tx_led = 1;
338	if (value & (1 << 24)) { /* LED scenario */
339	if (value & (1 << 29))
340	chip->supports_tx_led = 0;
341	}
342
343	dev_dbg_f(zd_chip_dev(chip),
344	"RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
345	"patch 6M %d new PHY %d link LED%d tx led %d\n",
346	zd_rf_name(*rf_type), *rf_type,
347	chip->pa_type, chip->patch_cck_gain,
348	chip->patch_cr157, chip->patch_6m_band_edge,
349	chip->new_phy_layout,
350	chip->link_led == LED1 ? 1 : 2,
351	chip->supports_tx_led);
352	return 0;
353	error:
354	*rf_type = 0;
355	chip->pa_type = 0;
356	chip->patch_cck_gain = 0;
357	chip->patch_cr157 = 0;
358	chip->patch_6m_band_edge = 0;
359	chip->new_phy_layout = 0;
360	return r;
361	}
362
363	static int zd_write_mac_addr_common(struct zd_chip *chip, const u8 *mac_addr,
364	const struct zd_ioreq32 *in_reqs,
365	const char *type)
366	{
367	int r;
368	struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]};
369
370	if (mac_addr) {
371	reqs[0].value = (mac_addr[3] << 24)
372	| (mac_addr[2] << 16)
373	| (mac_addr[1] << 8)
374	| mac_addr[0];
375	reqs[1].value = (mac_addr[5] << 8)
376	| mac_addr[4];
377	dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr);
378	} else {
379	dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type);
380	}
381
382	mutex_lock(&chip->mutex);
383	r = zd_iowrite32a_locked(chip, ioreqs: reqs, ARRAY_SIZE(reqs));
384	mutex_unlock(lock: &chip->mutex);
385	return r;
386	}
387
388	/* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
389	* CR_MAC_ADDR_P2 must be overwritten
390	*/
391	int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
392	{
393	static const struct zd_ioreq32 reqs[2] = {
394	[0] = { .addr = CR_MAC_ADDR_P1 },
395	[1] = { .addr = CR_MAC_ADDR_P2 },
396	};
397
398	return zd_write_mac_addr_common(chip, mac_addr, in_reqs: reqs, type: "mac");
399	}
400
401	int zd_write_bssid(struct zd_chip *chip, const u8 *bssid)
402	{
403	static const struct zd_ioreq32 reqs[2] = {
404	[0] = { .addr = CR_BSSID_P1 },
405	[1] = { .addr = CR_BSSID_P2 },
406	};
407
408	return zd_write_mac_addr_common(chip, mac_addr: bssid, in_reqs: reqs, type: "bssid");
409	}
410
411	int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
412	{
413	int r;
414	u32 value;
415
416	mutex_lock(&chip->mutex);
417	r = zd_ioread32_locked(chip, value: &value, E2P_SUBID);
418	mutex_unlock(lock: &chip->mutex);
419	if (r)
420	return r;
421
422	*regdomain = value >> 16;
423	dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
424
425	return 0;
426	}
427
428	static int read_values(struct zd_chip *chip, u8 *values, size_t count,
429	zd_addr_t e2p_addr, u32 guard)
430	{
431	int r;
432	int i;
433	u32 v;
434
435	ZD_ASSERT(mutex_is_locked(&chip->mutex));
436	for (i = 0;;) {
437	r = zd_ioread32_locked(chip, value: &v,
438	addr: (zd_addr_t)((u16)e2p_addr+i/2));
439	if (r)
440	return r;
441	v -= guard;
442	if (i+4 < count) {
443	values[i++] = v;
444	values[i++] = v >> 8;
445	values[i++] = v >> 16;
446	values[i++] = v >> 24;
447	continue;
448	}
449	for (;i < count; i++)
450	values[i] = v >> (8*(i%3));
451	return 0;
452	}
453	}
454
455	static int read_pwr_cal_values(struct zd_chip *chip)
456	{
457	return read_values(chip, values: chip->pwr_cal_values,
458	E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
459	guard: 0);
460	}
461
462	static int read_pwr_int_values(struct zd_chip *chip)
463	{
464	return read_values(chip, values: chip->pwr_int_values,
465	E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
466	E2P_PWR_INT_GUARD);
467	}
468
469	static int read_ofdm_cal_values(struct zd_chip *chip)
470	{
471	int r;
472	int i;
473	static const zd_addr_t addresses[] = {
474	E2P_36M_CAL_VALUE1,
475	E2P_48M_CAL_VALUE1,
476	E2P_54M_CAL_VALUE1,
477	};
478
479	for (i = 0; i < 3; i++) {
480	r = read_values(chip, values: chip->ofdm_cal_values[i],
481	E2P_CHANNEL_COUNT, e2p_addr: addresses[i], guard: 0);
482	if (r)
483	return r;
484	}
485	return 0;
486	}
487
488	static int read_cal_int_tables(struct zd_chip *chip)
489	{
490	int r;
491
492	r = read_pwr_cal_values(chip);
493	if (r)
494	return r;
495	r = read_pwr_int_values(chip);
496	if (r)
497	return r;
498	r = read_ofdm_cal_values(chip);
499	if (r)
500	return r;
501	return 0;
502	}
503
504	/* phy means physical registers */
505	int zd_chip_lock_phy_regs(struct zd_chip *chip)
506	{
507	int r;
508	u32 tmp;
509
510	ZD_ASSERT(mutex_is_locked(&chip->mutex));
511	r = zd_ioread32_locked(chip, value: &tmp, CR_REG1);
512	if (r) {
513	dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
514	return r;
515	}
516
517	tmp &= ~UNLOCK_PHY_REGS;
518
519	r = zd_iowrite32_locked(chip, value: tmp, CR_REG1);
520	if (r)
521	dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
522	return r;
523	}
524
525	int zd_chip_unlock_phy_regs(struct zd_chip *chip)
526	{
527	int r;
528	u32 tmp;
529
530	ZD_ASSERT(mutex_is_locked(&chip->mutex));
531	r = zd_ioread32_locked(chip, value: &tmp, CR_REG1);
532	if (r) {
533	dev_err(zd_chip_dev(chip),
534	"error ioread32(CR_REG1): %d\n", r);
535	return r;
536	}
537
538	tmp |= UNLOCK_PHY_REGS;
539
540	r = zd_iowrite32_locked(chip, value: tmp, CR_REG1);
541	if (r)
542	dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
543	return r;
544	}
545
546	/* ZD_CR157 can be optionally patched by the EEPROM for original ZD1211 */
547	static int patch_cr157(struct zd_chip *chip)
548	{
549	int r;
550	u16 value;
551
552	if (!chip->patch_cr157)
553	return 0;
554
555	r = zd_ioread16_locked(chip, value: &value, E2P_PHY_REG);
556	if (r)
557	return r;
558
559	dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
560	return zd_iowrite32_locked(chip, value: value >> 8, ZD_CR157);
561	}
562
563	/*
564	* 6M band edge can be optionally overwritten for certain RF's
565	* Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
566	* bit (for AL2230, AL2230S)
567	*/
568	static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
569	{
570	ZD_ASSERT(mutex_is_locked(&chip->mutex));
571	if (!chip->patch_6m_band_edge)
572	return 0;
573
574	return zd_rf_patch_6m_band_edge(rf: &chip->rf, channel);
575	}
576
577	/* Generic implementation of 6M band edge patching, used by most RFs via
578	* zd_rf_generic_patch_6m() */
579	int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
580	{
581	struct zd_ioreq16 ioreqs[] = {
582	{ ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
583	{ ZD_CR47, 0x1e },
584	};
585
586	/* FIXME: Channel 11 is not the edge for all regulatory domains. */
587	if (channel == 1 || channel == 11)
588	ioreqs[0].value = 0x12;
589
590	dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
591	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
592	}
593
594	static int zd1211_hw_reset_phy(struct zd_chip *chip)
595	{
596	static const struct zd_ioreq16 ioreqs[] = {
597	{ ZD_CR0, 0x0a }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 },
598	{ ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xa0 },
599	{ ZD_CR10, 0x81 }, { ZD_CR11, 0x00 }, { ZD_CR12, 0x7f },
600	{ ZD_CR13, 0x8c }, { ZD_CR14, 0x80 }, { ZD_CR15, 0x3d },
601	{ ZD_CR16, 0x20 }, { ZD_CR17, 0x1e }, { ZD_CR18, 0x0a },
602	{ ZD_CR19, 0x48 }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0c },
603	{ ZD_CR22, 0x23 }, { ZD_CR23, 0x90 }, { ZD_CR24, 0x14 },
604	{ ZD_CR25, 0x40 }, { ZD_CR26, 0x10 }, { ZD_CR27, 0x19 },
605	{ ZD_CR28, 0x7f }, { ZD_CR29, 0x80 }, { ZD_CR30, 0x4b },
606	{ ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 },
607	{ ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 },
608	{ ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c },
609	{ ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 },
610	{ ZD_CR43, 0x10 }, { ZD_CR44, 0x12 }, { ZD_CR46, 0xff },
611	{ ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b },
612	{ ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 },
613	{ ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 },
614	{ ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff },
615	{ ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 },
616	{ ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 },
617	{ ZD_CR79, 0x68 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 },
618	{ ZD_CR82, 0x00 }, { ZD_CR83, 0x00 }, { ZD_CR84, 0x00 },
619	{ ZD_CR85, 0x02 }, { ZD_CR86, 0x00 }, { ZD_CR87, 0x00 },
620	{ ZD_CR88, 0xff }, { ZD_CR89, 0xfc }, { ZD_CR90, 0x00 },
621	{ ZD_CR91, 0x00 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x08 },
622	{ ZD_CR94, 0x00 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0xff },
623	{ ZD_CR97, 0xe7 }, { ZD_CR98, 0x00 }, { ZD_CR99, 0x00 },
624	{ ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 },
625	{ ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 },
626	{ ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a },
627	{ ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 },
628	{ ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e },
629	{ ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
630	{ },
631	{ ZD_CR5, 0x00 }, { ZD_CR6, 0x00 }, { ZD_CR7, 0x00 },
632	{ ZD_CR8, 0x00 }, { ZD_CR9, 0x20 }, { ZD_CR12, 0xf0 },
633	{ ZD_CR20, 0x0e }, { ZD_CR21, 0x0e }, { ZD_CR27, 0x10 },
634	{ ZD_CR44, 0x33 }, { ZD_CR47, 0x1E }, { ZD_CR83, 0x24 },
635	{ ZD_CR84, 0x04 }, { ZD_CR85, 0x00 }, { ZD_CR86, 0x0C },
636	{ ZD_CR87, 0x12 }, { ZD_CR88, 0x0C }, { ZD_CR89, 0x00 },
637	{ ZD_CR90, 0x10 }, { ZD_CR91, 0x08 }, { ZD_CR93, 0x00 },
638	{ ZD_CR94, 0x01 }, { ZD_CR95, 0x00 }, { ZD_CR96, 0x50 },
639	{ ZD_CR97, 0x37 }, { ZD_CR98, 0x35 }, { ZD_CR101, 0x13 },
640	{ ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
641	{ ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
642	{ ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
643	{ ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
644	{ ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f },
645	{ ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 },
646	{ ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C },
647	{ ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 },
648	{ ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 },
649	{ ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c },
650	{ ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 },
651	{ ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe },
652	{ ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
653	{ ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
654	{ ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
655	{ ZD_CR170, 0xba }, { ZD_CR171, 0xba },
656	/* Note: ZD_CR204 must lead the ZD_CR203 */
657	{ ZD_CR204, 0x7d },
658	{ },
659	{ ZD_CR203, 0x30 },
660	};
661
662	int r, t;
663
664	dev_dbg_f(zd_chip_dev(chip), "\n");
665
666	r = zd_chip_lock_phy_regs(chip);
667	if (r)
668	goto out;
669
670	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
671	if (r)
672	goto unlock;
673
674	r = patch_cr157(chip);
675	unlock:
676	t = zd_chip_unlock_phy_regs(chip);
677	if (t && !r)
678	r = t;
679	out:
680	return r;
681	}
682
683	static int zd1211b_hw_reset_phy(struct zd_chip *chip)
684	{
685	static const struct zd_ioreq16 ioreqs[] = {
686	{ ZD_CR0, 0x14 }, { ZD_CR1, 0x06 }, { ZD_CR2, 0x26 },
687	{ ZD_CR3, 0x38 }, { ZD_CR4, 0x80 }, { ZD_CR9, 0xe0 },
688	{ ZD_CR10, 0x81 },
689	/* power control { { ZD_CR11, 1 << 6 }, */
690	{ ZD_CR11, 0x00 },
691	{ ZD_CR12, 0xf0 }, { ZD_CR13, 0x8c }, { ZD_CR14, 0x80 },
692	{ ZD_CR15, 0x3d }, { ZD_CR16, 0x20 }, { ZD_CR17, 0x1e },
693	{ ZD_CR18, 0x0a }, { ZD_CR19, 0x48 },
694	{ ZD_CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
695	{ ZD_CR21, 0x0e }, { ZD_CR22, 0x23 }, { ZD_CR23, 0x90 },
696	{ ZD_CR24, 0x14 }, { ZD_CR25, 0x40 }, { ZD_CR26, 0x10 },
697	{ ZD_CR27, 0x10 }, { ZD_CR28, 0x7f }, { ZD_CR29, 0x80 },
698	{ ZD_CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
699	{ ZD_CR31, 0x60 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x08 },
700	{ ZD_CR34, 0x06 }, { ZD_CR35, 0x0a }, { ZD_CR36, 0x00 },
701	{ ZD_CR37, 0x00 }, { ZD_CR38, 0x38 }, { ZD_CR39, 0x0c },
702	{ ZD_CR40, 0x84 }, { ZD_CR41, 0x2a }, { ZD_CR42, 0x80 },
703	{ ZD_CR43, 0x10 }, { ZD_CR44, 0x33 }, { ZD_CR46, 0xff },
704	{ ZD_CR47, 0x1E }, { ZD_CR48, 0x26 }, { ZD_CR49, 0x5b },
705	{ ZD_CR64, 0xd0 }, { ZD_CR65, 0x04 }, { ZD_CR66, 0x58 },
706	{ ZD_CR67, 0xc9 }, { ZD_CR68, 0x88 }, { ZD_CR69, 0x41 },
707	{ ZD_CR70, 0x23 }, { ZD_CR71, 0x10 }, { ZD_CR72, 0xff },
708	{ ZD_CR73, 0x32 }, { ZD_CR74, 0x30 }, { ZD_CR75, 0x65 },
709	{ ZD_CR76, 0x41 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x30 },
710	{ ZD_CR79, 0xf0 }, { ZD_CR80, 0x64 }, { ZD_CR81, 0x64 },
711	{ ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 },
712	{ ZD_CR85, 0x00 }, { ZD_CR86, 0x0c }, { ZD_CR87, 0x12 },
713	{ ZD_CR88, 0x0c }, { ZD_CR89, 0x00 }, { ZD_CR90, 0x58 },
714	{ ZD_CR91, 0x04 }, { ZD_CR92, 0x00 }, { ZD_CR93, 0x00 },
715	{ ZD_CR94, 0x01 },
716	{ ZD_CR95, 0x20 }, /* ZD1211B */
717	{ ZD_CR96, 0x50 }, { ZD_CR97, 0x37 }, { ZD_CR98, 0x35 },
718	{ ZD_CR99, 0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 },
719	{ ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
720	{ ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 },
721	{ ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
722	{ ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
723	{ ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
724	{ ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e },
725	{ ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
726	{ ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
727	{ ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 },
728	{ ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 },
729	{ ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c },
730	{ ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 },
731	{ ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
732	{ ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
733	{ ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe },
734	{ ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
735	{ ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
736	{ ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
737	{ ZD_CR170, 0xba }, { ZD_CR171, 0xba },
738	/* Note: ZD_CR204 must lead the ZD_CR203 */
739	{ ZD_CR204, 0x7d },
740	{},
741	{ ZD_CR203, 0x30 },
742	};
743
744	int r, t;
745
746	dev_dbg_f(zd_chip_dev(chip), "\n");
747
748	r = zd_chip_lock_phy_regs(chip);
749	if (r)
750	goto out;
751
752	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
753	t = zd_chip_unlock_phy_regs(chip);
754	if (t && !r)
755	r = t;
756	out:
757	return r;
758	}
759
760	static int hw_reset_phy(struct zd_chip *chip)
761	{
762	return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
763	zd1211_hw_reset_phy(chip);
764	}
765
766	static int zd1211_hw_init_hmac(struct zd_chip *chip)
767	{
768	static const struct zd_ioreq32 ioreqs[] = {
769	{ CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT },
770	{ CR_RX_THRESHOLD, 0x000c0640 },
771	};
772
773	dev_dbg_f(zd_chip_dev(chip), "\n");
774	ZD_ASSERT(mutex_is_locked(&chip->mutex));
775	return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
776	}
777
778	static int zd1211b_hw_init_hmac(struct zd_chip *chip)
779	{
780	static const struct zd_ioreq32 ioreqs[] = {
781	{ CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT },
782	{ CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
783	{ CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
784	{ CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
785	{ CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
786	{ CR_ZD1211B_AIFS_CTL1, 0x00280028 },
787	{ CR_ZD1211B_AIFS_CTL2, 0x008C003C },
788	{ CR_ZD1211B_TXOP, 0x01800824 },
789	{ CR_RX_THRESHOLD, 0x000c0eff, },
790	};
791
792	dev_dbg_f(zd_chip_dev(chip), "\n");
793	ZD_ASSERT(mutex_is_locked(&chip->mutex));
794	return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
795	}
796
797	static int hw_init_hmac(struct zd_chip *chip)
798	{
799	int r;
800	static const struct zd_ioreq32 ioreqs[] = {
801	{ CR_ACK_TIMEOUT_EXT, 0x20 },
802	{ CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
803	{ CR_SNIFFER_ON, 0 },
804	{ CR_RX_FILTER, STA_RX_FILTER },
805	{ CR_GROUP_HASH_P1, 0x00 },
806	{ CR_GROUP_HASH_P2, 0x80000000 },
807	{ CR_REG1, 0xa4 },
808	{ CR_ADDA_PWR_DWN, 0x7f },
809	{ CR_BCN_PLCP_CFG, 0x00f00401 },
810	{ CR_PHY_DELAY, 0x00 },
811	{ CR_ACK_TIMEOUT_EXT, 0x80 },
812	{ CR_ADDA_PWR_DWN, 0x00 },
813	{ CR_ACK_TIME_80211, 0x100 },
814	{ CR_RX_PE_DELAY, 0x70 },
815	{ CR_PS_CTRL, 0x10000000 },
816	{ CR_RTS_CTS_RATE, 0x02030203 },
817	{ CR_AFTER_PNP, 0x1 },
818	{ CR_WEP_PROTECT, 0x114 },
819	{ CR_IFS_VALUE, IFS_VALUE_DEFAULT },
820	{ CR_CAM_MODE, MODE_AP_WDS},
821	};
822
823	ZD_ASSERT(mutex_is_locked(&chip->mutex));
824	r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
825	if (r)
826	return r;
827
828	return zd_chip_is_zd1211b(chip) ?
829	zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
830	}
831
832	struct aw_pt_bi {
833	u32 atim_wnd_period;
834	u32 pre_tbtt;
835	u32 beacon_interval;
836	};
837
838	static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
839	{
840	int r;
841	static const zd_addr_t aw_pt_bi_addr[] =
842	{ CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
843	u32 values[3];
844
845	r = zd_ioread32v_locked(chip, values, addr: (const zd_addr_t *)aw_pt_bi_addr,
846	ARRAY_SIZE(aw_pt_bi_addr));
847	if (r) {
848	memset(s, 0, sizeof(*s));
849	return r;
850	}
851
852	s->atim_wnd_period = values[0];
853	s->pre_tbtt = values[1];
854	s->beacon_interval = values[2];
855	return 0;
856	}
857
858	static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
859	{
860	struct zd_ioreq32 reqs[3];
861	u16 b_interval = s->beacon_interval & 0xffff;
862
863	if (b_interval <= 5)
864	b_interval = 5;
865	if (s->pre_tbtt < 4 || s->pre_tbtt >= b_interval)
866	s->pre_tbtt = b_interval - 1;
867	if (s->atim_wnd_period >= s->pre_tbtt)
868	s->atim_wnd_period = s->pre_tbtt - 1;
869
870	reqs[0].addr = CR_ATIM_WND_PERIOD;
871	reqs[0].value = s->atim_wnd_period;
872	reqs[1].addr = CR_PRE_TBTT;
873	reqs[1].value = s->pre_tbtt;
874	reqs[2].addr = CR_BCN_INTERVAL;
875	reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval;
876
877	return zd_iowrite32a_locked(chip, ioreqs: reqs, ARRAY_SIZE(reqs));
878	}
879
880
881	static int set_beacon_interval(struct zd_chip *chip, u16 interval,
882	u8 dtim_period, int type)
883	{
884	int r;
885	struct aw_pt_bi s;
886	u32 b_interval, mode_flag;
887
888	ZD_ASSERT(mutex_is_locked(&chip->mutex));
889
890	if (interval > 0) {
891	switch (type) {
892	case NL80211_IFTYPE_ADHOC:
893	case NL80211_IFTYPE_MESH_POINT:
894	mode_flag = BCN_MODE_IBSS;
895	break;
896	case NL80211_IFTYPE_AP:
897	mode_flag = BCN_MODE_AP;
898	break;
899	default:
900	mode_flag = 0;
901	break;
902	}
903	} else {
904	dtim_period = 0;
905	mode_flag = 0;
906	}
907
908	b_interval = mode_flag | (dtim_period << 16) | interval;
909
910	r = zd_iowrite32_locked(chip, value: b_interval, CR_BCN_INTERVAL);
911	if (r)
912	return r;
913	r = get_aw_pt_bi(chip, s: &s);
914	if (r)
915	return r;
916	return set_aw_pt_bi(chip, s: &s);
917	}
918
919	int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period,
920	int type)
921	{
922	int r;
923
924	mutex_lock(&chip->mutex);
925	r = set_beacon_interval(chip, interval, dtim_period, type);
926	mutex_unlock(lock: &chip->mutex);
927	return r;
928	}
929
930	static int hw_init(struct zd_chip *chip)
931	{
932	int r;
933
934	dev_dbg_f(zd_chip_dev(chip), "\n");
935	ZD_ASSERT(mutex_is_locked(&chip->mutex));
936	r = hw_reset_phy(chip);
937	if (r)
938	return r;
939
940	r = hw_init_hmac(chip);
941	if (r)
942	return r;
943
944	return set_beacon_interval(chip, interval: 100, dtim_period: 0, type: NL80211_IFTYPE_UNSPECIFIED);
945	}
946
947	static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
948	{
949	return (zd_addr_t)((u16)chip->fw_regs_base + offset);
950	}
951
952	#ifdef DEBUG
953	static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
954	const char *addr_string)
955	{
956	int r;
957	u32 value;
958
959	r = zd_ioread32_locked(chip, value: &value, addr);
960	if (r) {
961	dev_dbg_f(zd_chip_dev(chip),
962	"error reading %s. Error number %d\n", addr_string, r);
963	return r;
964	}
965
966	dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
967	addr_string, (unsigned int)value);
968	return 0;
969	}
970
971	static int test_init(struct zd_chip *chip)
972	{
973	int r;
974
975	r = dump_cr(chip, CR_AFTER_PNP, addr_string: "CR_AFTER_PNP");
976	if (r)
977	return r;
978	r = dump_cr(chip, CR_GPI_EN, addr_string: "CR_GPI_EN");
979	if (r)
980	return r;
981	return dump_cr(chip, CR_INTERRUPT, addr_string: "CR_INTERRUPT");
982	}
983
984	static void dump_fw_registers(struct zd_chip *chip)
985	{
986	const zd_addr_t addr[4] = {
987	fw_reg_addr(chip, offset: FW_REG_FIRMWARE_VER),
988	fw_reg_addr(chip, offset: FW_REG_USB_SPEED),
989	fw_reg_addr(chip, offset: FW_REG_FIX_TX_RATE),
990	fw_reg_addr(chip, offset: FW_REG_LED_LINK_STATUS),
991	};
992
993	int r;
994	u16 values[4];
995
996	r = zd_ioread16v_locked(chip, values, addresses: (const zd_addr_t*)addr,
997	ARRAY_SIZE(addr));
998	if (r) {
999	dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1000	r);
1001	return;
1002	}
1003
1004	dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1005	dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1006	dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1007	dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1008	}
1009	#endif /* DEBUG */
1010
1011	static int print_fw_version(struct zd_chip *chip)
1012	{
1013	struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy;
1014	int r;
1015	u16 version;
1016
1017	r = zd_ioread16_locked(chip, value: &version,
1018	addr: fw_reg_addr(chip, offset: FW_REG_FIRMWARE_VER));
1019	if (r)
1020	return r;
1021
1022	dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1023
1024	snprintf(buf: wiphy->fw_version, size: sizeof(wiphy->fw_version),
1025	fmt: "%04hx", version);
1026
1027	return 0;
1028	}
1029
1030	static int set_mandatory_rates(struct zd_chip *chip, int gmode)
1031	{
1032	u32 rates;
1033	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1034	/* This sets the mandatory rates, which only depend from the standard
1035	* that the device is supporting. Until further notice we should try
1036	* to support 802.11g also for full speed USB.
1037	*/
1038	if (!gmode)
1039	rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1040	else
1041	rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1042	CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1043
1044	return zd_iowrite32_locked(chip, value: rates, CR_MANDATORY_RATE_TBL);
1045	}
1046
1047	int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1048	int preamble)
1049	{
1050	u32 value = 0;
1051
1052	dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1053	value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1054	value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1055
1056	/* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1057	value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1058	value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1059	value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1060	value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1061
1062	return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1063	}
1064
1065	int zd_chip_enable_hwint(struct zd_chip *chip)
1066	{
1067	int r;
1068
1069	mutex_lock(&chip->mutex);
1070	r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1071	mutex_unlock(lock: &chip->mutex);
1072	return r;
1073	}
1074
1075	static int disable_hwint(struct zd_chip *chip)
1076	{
1077	return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1078	}
1079
1080	int zd_chip_disable_hwint(struct zd_chip *chip)
1081	{
1082	int r;
1083
1084	mutex_lock(&chip->mutex);
1085	r = disable_hwint(chip);
1086	mutex_unlock(lock: &chip->mutex);
1087	return r;
1088	}
1089
1090	static int read_fw_regs_offset(struct zd_chip *chip)
1091	{
1092	int r;
1093
1094	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1095	r = zd_ioread16_locked(chip, value: (u16*)&chip->fw_regs_base,
1096	FWRAW_REGS_ADDR);
1097	if (r)
1098	return r;
1099	dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1100	(u16)chip->fw_regs_base);
1101
1102	return 0;
1103	}
1104
1105	/* Read mac address using pre-firmware interface */
1106	int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1107	{
1108	dev_dbg_f(zd_chip_dev(chip), "\n");
1109	return zd_usb_read_fw(usb: &chip->usb, E2P_MAC_ADDR_P1, data: addr,
1110	ETH_ALEN);
1111	}
1112
1113	int zd_chip_init_hw(struct zd_chip *chip)
1114	{
1115	int r;
1116	u8 rf_type;
1117
1118	dev_dbg_f(zd_chip_dev(chip), "\n");
1119
1120	mutex_lock(&chip->mutex);
1121
1122	#ifdef DEBUG
1123	r = test_init(chip);
1124	if (r)
1125	goto out;
1126	#endif
1127	r = zd_iowrite32_locked(chip, value: 1, CR_AFTER_PNP);
1128	if (r)
1129	goto out;
1130
1131	r = read_fw_regs_offset(chip);
1132	if (r)
1133	goto out;
1134
1135	/* GPI is always disabled, also in the other driver.
1136	*/
1137	r = zd_iowrite32_locked(chip, value: 0, CR_GPI_EN);
1138	if (r)
1139	goto out;
1140	r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1141	if (r)
1142	goto out;
1143	/* Currently we support IEEE 802.11g for full and high speed USB.
1144	* It might be discussed, whether we should support pure b mode for
1145	* full speed USB.
1146	*/
1147	r = set_mandatory_rates(chip, gmode: 1);
1148	if (r)
1149	goto out;
1150	/* Disabling interrupts is certainly a smart thing here.
1151	*/
1152	r = disable_hwint(chip);
1153	if (r)
1154	goto out;
1155	r = read_pod(chip, rf_type: &rf_type);
1156	if (r)
1157	goto out;
1158	r = hw_init(chip);
1159	if (r)
1160	goto out;
1161	r = zd_rf_init_hw(rf: &chip->rf, type: rf_type);
1162	if (r)
1163	goto out;
1164
1165	r = print_fw_version(chip);
1166	if (r)
1167	goto out;
1168
1169	#ifdef DEBUG
1170	dump_fw_registers(chip);
1171	r = test_init(chip);
1172	if (r)
1173	goto out;
1174	#endif /* DEBUG */
1175
1176	r = read_cal_int_tables(chip);
1177	if (r)
1178	goto out;
1179
1180	print_id(chip);
1181	out:
1182	mutex_unlock(lock: &chip->mutex);
1183	return r;
1184	}
1185
1186	static int update_pwr_int(struct zd_chip *chip, u8 channel)
1187	{
1188	u8 value = chip->pwr_int_values[channel - 1];
1189	return zd_iowrite16_locked(chip, value, ZD_CR31);
1190	}
1191
1192	static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1193	{
1194	u8 value = chip->pwr_cal_values[channel-1];
1195	return zd_iowrite16_locked(chip, value, ZD_CR68);
1196	}
1197
1198	static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1199	{
1200	struct zd_ioreq16 ioreqs[3];
1201
1202	ioreqs[0].addr = ZD_CR67;
1203	ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1204	ioreqs[1].addr = ZD_CR66;
1205	ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1206	ioreqs[2].addr = ZD_CR65;
1207	ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1208
1209	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1210	}
1211
1212	static int update_channel_integration_and_calibration(struct zd_chip *chip,
1213	u8 channel)
1214	{
1215	int r;
1216
1217	if (!zd_rf_should_update_pwr_int(rf: &chip->rf))
1218	return 0;
1219
1220	r = update_pwr_int(chip, channel);
1221	if (r)
1222	return r;
1223	if (zd_chip_is_zd1211b(chip)) {
1224	static const struct zd_ioreq16 ioreqs[] = {
1225	{ ZD_CR69, 0x28 },
1226	{},
1227	{ ZD_CR69, 0x2a },
1228	};
1229
1230	r = update_ofdm_cal(chip, channel);
1231	if (r)
1232	return r;
1233	r = update_pwr_cal(chip, channel);
1234	if (r)
1235	return r;
1236	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1237	if (r)
1238	return r;
1239	}
1240
1241	return 0;
1242	}
1243
1244	/* The CCK baseband gain can be optionally patched by the EEPROM */
1245	static int patch_cck_gain(struct zd_chip *chip)
1246	{
1247	int r;
1248	u32 value;
1249
1250	if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(rf: &chip->rf))
1251	return 0;
1252
1253	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1254	r = zd_ioread32_locked(chip, value: &value, E2P_PHY_REG);
1255	if (r)
1256	return r;
1257	dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1258	return zd_iowrite16_locked(chip, value: value & 0xff, ZD_CR47);
1259	}
1260
1261	int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1262	{
1263	int r, t;
1264
1265	mutex_lock(&chip->mutex);
1266	r = zd_chip_lock_phy_regs(chip);
1267	if (r)
1268	goto out;
1269	r = zd_rf_set_channel(rf: &chip->rf, channel);
1270	if (r)
1271	goto unlock;
1272	r = update_channel_integration_and_calibration(chip, channel);
1273	if (r)
1274	goto unlock;
1275	r = patch_cck_gain(chip);
1276	if (r)
1277	goto unlock;
1278	r = patch_6m_band_edge(chip, channel);
1279	if (r)
1280	goto unlock;
1281	r = zd_iowrite32_locked(chip, value: 0, CR_CONFIG_PHILIPS);
1282	unlock:
1283	t = zd_chip_unlock_phy_regs(chip);
1284	if (t && !r)
1285	r = t;
1286	out:
1287	mutex_unlock(lock: &chip->mutex);
1288	return r;
1289	}
1290
1291	u8 zd_chip_get_channel(struct zd_chip *chip)
1292	{
1293	u8 channel;
1294
1295	mutex_lock(&chip->mutex);
1296	channel = chip->rf.channel;
1297	mutex_unlock(lock: &chip->mutex);
1298	return channel;
1299	}
1300
1301	int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1302	{
1303	const zd_addr_t a[] = {
1304	fw_reg_addr(chip, offset: FW_REG_LED_LINK_STATUS),
1305	CR_LED,
1306	};
1307
1308	int r;
1309	u16 v[ARRAY_SIZE(a)];
1310	struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1311	[0] = { fw_reg_addr(chip, offset: FW_REG_LED_LINK_STATUS) },
1312	[1] = { CR_LED },
1313	};
1314	u16 other_led;
1315
1316	mutex_lock(&chip->mutex);
1317	r = zd_ioread16v_locked(chip, values: v, addresses: (const zd_addr_t *)a, ARRAY_SIZE(a));
1318	if (r)
1319	goto out;
1320
1321	other_led = chip->link_led == LED1 ? LED2 : LED1;
1322
1323	switch (status) {
1324	case ZD_LED_OFF:
1325	ioreqs[0].value = FW_LINK_OFF;
1326	ioreqs[1].value = v[1] & ~(LED1|LED2);
1327	break;
1328	case ZD_LED_SCANNING:
1329	ioreqs[0].value = FW_LINK_OFF;
1330	ioreqs[1].value = v[1] & ~other_led;
1331	if ((u32)ktime_get_seconds() % 3 == 0) {
1332	ioreqs[1].value &= ~chip->link_led;
1333	} else {
1334	ioreqs[1].value |= chip->link_led;
1335	}
1336	break;
1337	case ZD_LED_ASSOCIATED:
1338	ioreqs[0].value = FW_LINK_TX;
1339	ioreqs[1].value = v[1] & ~other_led;
1340	ioreqs[1].value |= chip->link_led;
1341	break;
1342	default:
1343	r = -EINVAL;
1344	goto out;
1345	}
1346
1347	if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1348	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1349	if (r)
1350	goto out;
1351	}
1352	r = 0;
1353	out:
1354	mutex_unlock(lock: &chip->mutex);
1355	return r;
1356	}
1357
1358	int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1359	{
1360	int r;
1361
1362	if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1363	return -EINVAL;
1364
1365	mutex_lock(&chip->mutex);
1366	r = zd_iowrite32_locked(chip, value: cr_rates, CR_BASIC_RATE_TBL);
1367	mutex_unlock(lock: &chip->mutex);
1368	return r;
1369	}
1370
1371	static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1372	{
1373	return ZD_OFDM | zd_ofdm_plcp_header_rate(header: rx_frame);
1374	}
1375
1376	/**
1377	* zd_rx_rate - report zd-rate
1378	* @rx_frame: received frame
1379	* @status: rx_status as given by the device
1380	*
1381	* This function converts the rate as encoded in the received packet to the
1382	* zd-rate, we are using on other places in the driver.
1383	*/
1384	u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1385	{
1386	u8 zd_rate;
1387	if (status->frame_status & ZD_RX_OFDM) {
1388	zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1389	} else {
1390	switch (zd_cck_plcp_header_signal(header: rx_frame)) {
1391	case ZD_CCK_PLCP_SIGNAL_1M:
1392	zd_rate = ZD_CCK_RATE_1M;
1393	break;
1394	case ZD_CCK_PLCP_SIGNAL_2M:
1395	zd_rate = ZD_CCK_RATE_2M;
1396	break;
1397	case ZD_CCK_PLCP_SIGNAL_5M5:
1398	zd_rate = ZD_CCK_RATE_5_5M;
1399	break;
1400	case ZD_CCK_PLCP_SIGNAL_11M:
1401	zd_rate = ZD_CCK_RATE_11M;
1402	break;
1403	default:
1404	zd_rate = 0;
1405	}
1406	}
1407
1408	return zd_rate;
1409	}
1410
1411	int zd_chip_switch_radio_on(struct zd_chip *chip)
1412	{
1413	int r;
1414
1415	mutex_lock(&chip->mutex);
1416	r = zd_switch_radio_on(rf: &chip->rf);
1417	mutex_unlock(lock: &chip->mutex);
1418	return r;
1419	}
1420
1421	int zd_chip_switch_radio_off(struct zd_chip *chip)
1422	{
1423	int r;
1424
1425	mutex_lock(&chip->mutex);
1426	r = zd_switch_radio_off(rf: &chip->rf);
1427	mutex_unlock(lock: &chip->mutex);
1428	return r;
1429	}
1430
1431	int zd_chip_enable_int(struct zd_chip *chip)
1432	{
1433	int r;
1434
1435	mutex_lock(&chip->mutex);
1436	r = zd_usb_enable_int(usb: &chip->usb);
1437	mutex_unlock(lock: &chip->mutex);
1438	return r;
1439	}
1440
1441	void zd_chip_disable_int(struct zd_chip *chip)
1442	{
1443	mutex_lock(&chip->mutex);
1444	zd_usb_disable_int(usb: &chip->usb);
1445	mutex_unlock(lock: &chip->mutex);
1446
1447	/* cancel pending interrupt work */
1448	cancel_work_sync(work: &zd_chip_to_mac(chip)->process_intr);
1449	}
1450
1451	int zd_chip_enable_rxtx(struct zd_chip *chip)
1452	{
1453	int r;
1454
1455	mutex_lock(&chip->mutex);
1456	zd_usb_enable_tx(usb: &chip->usb);
1457	r = zd_usb_enable_rx(usb: &chip->usb);
1458	zd_tx_watchdog_enable(usb: &chip->usb);
1459	mutex_unlock(lock: &chip->mutex);
1460	return r;
1461	}
1462
1463	void zd_chip_disable_rxtx(struct zd_chip *chip)
1464	{
1465	mutex_lock(&chip->mutex);
1466	zd_tx_watchdog_disable(usb: &chip->usb);
1467	zd_usb_disable_rx(usb: &chip->usb);
1468	zd_usb_disable_tx(usb: &chip->usb);
1469	mutex_unlock(lock: &chip->mutex);
1470	}
1471
1472	int zd_rfwritev_locked(struct zd_chip *chip,
1473	const u32* values, unsigned int count, u8 bits)
1474	{
1475	int r;
1476	unsigned int i;
1477
1478	for (i = 0; i < count; i++) {
1479	r = zd_rfwrite_locked(chip, value: values[i], bits);
1480	if (r)
1481	return r;
1482	}
1483
1484	return 0;
1485	}
1486
1487	/*
1488	* We can optionally program the RF directly through CR regs, if supported by
1489	* the hardware. This is much faster than the older method.
1490	*/
1491	int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1492	{
1493	const struct zd_ioreq16 ioreqs[] = {
1494	{ ZD_CR244, (value >> 16) & 0xff },
1495	{ ZD_CR243, (value >> 8) & 0xff },
1496	{ ZD_CR242, value & 0xff },
1497	};
1498	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1499	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1500	}
1501
1502	int zd_rfwritev_cr_locked(struct zd_chip *chip,
1503	const u32 *values, unsigned int count)
1504	{
1505	int r;
1506	unsigned int i;
1507
1508	for (i = 0; i < count; i++) {
1509	r = zd_rfwrite_cr_locked(chip, value: values[i]);
1510	if (r)
1511	return r;
1512	}
1513
1514	return 0;
1515	}
1516
1517	int zd_chip_set_multicast_hash(struct zd_chip *chip,
1518	struct zd_mc_hash *hash)
1519	{
1520	const struct zd_ioreq32 ioreqs[] = {
1521	{ CR_GROUP_HASH_P1, hash->low },
1522	{ CR_GROUP_HASH_P2, hash->high },
1523	};
1524
1525	return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1526	}
1527
1528	u64 zd_chip_get_tsf(struct zd_chip *chip)
1529	{
1530	int r;
1531	static const zd_addr_t aw_pt_bi_addr[] =
1532	{ CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1533	u32 values[2];
1534	u64 tsf;
1535
1536	mutex_lock(&chip->mutex);
1537	r = zd_ioread32v_locked(chip, values, addr: (const zd_addr_t *)aw_pt_bi_addr,
1538	ARRAY_SIZE(aw_pt_bi_addr));
1539	mutex_unlock(lock: &chip->mutex);
1540	if (r)
1541	return 0;
1542
1543	tsf = values[1];
1544	tsf = (tsf << 32) | values[0];
1545
1546	return tsf;
1547	}
1548