1/*
2 * i.MX6 OCOTP fusebox driver
3 *
4 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
5 *
6 * Based on the barebox ocotp driver,
7 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
8 * Orex Computed Radiography
9 *
10 * Write support based on the fsl_otp driver,
11 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2
15 * as published by the Free Software Foundation.
16 *
17 * http://www.opensource.org/licenses/gpl-license.html
18 * http://www.gnu.org/copyleft/gpl.html
19 */
20
21#include <linux/clk.h>
22#include <linux/device.h>
23#include <linux/io.h>
24#include <linux/module.h>
25#include <linux/nvmem-provider.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31
32#define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
33 * OTP Bank0 Word0
34 */
35#define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
36 * of two consecutive OTP words.
37 */
38
39#define IMX_OCOTP_ADDR_CTRL 0x0000
40#define IMX_OCOTP_ADDR_CTRL_SET 0x0004
41#define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
42#define IMX_OCOTP_ADDR_TIMING 0x0010
43#define IMX_OCOTP_ADDR_DATA0 0x0020
44#define IMX_OCOTP_ADDR_DATA1 0x0030
45#define IMX_OCOTP_ADDR_DATA2 0x0040
46#define IMX_OCOTP_ADDR_DATA3 0x0050
47
48#define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F
49#define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
50#define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
51#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
52
53#define DEF_RELAX 20 /* > 16.5ns */
54#define DEF_FSOURCE 1001 /* > 1000 ns */
55#define DEF_STROBE_PROG 10000 /* IPG clocks */
56#define IMX_OCOTP_WR_UNLOCK 0x3E770000
57#define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
58
59static DEFINE_MUTEX(ocotp_mutex);
60
61struct ocotp_priv {
62 struct device *dev;
63 struct clk *clk;
64 void __iomem *base;
65 const struct ocotp_params *params;
66 struct nvmem_config *config;
67};
68
69struct ocotp_params {
70 unsigned int nregs;
71 unsigned int bank_address_words;
72 void (*set_timing)(struct ocotp_priv *priv);
73};
74
75static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags)
76{
77 int count;
78 u32 c, mask;
79
80 mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags;
81
82 for (count = 10000; count >= 0; count--) {
83 c = readl(base + IMX_OCOTP_ADDR_CTRL);
84 if (!(c & mask))
85 break;
86 cpu_relax();
87 }
88
89 if (count < 0) {
90 /* HW_OCOTP_CTRL[ERROR] will be set under the following
91 * conditions:
92 * - A write is performed to a shadow register during a shadow
93 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
94 * set. In addition, the contents of the shadow register shall
95 * not be updated.
96 * - A write is performed to a shadow register which has been
97 * locked.
98 * - A read is performed to from a shadow register which has
99 * been read locked.
100 * - A program is performed to a fuse word which has been locked
101 * - A read is performed to from a fuse word which has been read
102 * locked.
103 */
104 if (c & IMX_OCOTP_BM_CTRL_ERROR)
105 return -EPERM;
106 return -ETIMEDOUT;
107 }
108
109 return 0;
110}
111
112static void imx_ocotp_clr_err_if_set(void __iomem *base)
113{
114 u32 c;
115
116 c = readl(base + IMX_OCOTP_ADDR_CTRL);
117 if (!(c & IMX_OCOTP_BM_CTRL_ERROR))
118 return;
119
120 writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR);
121}
122
123static int imx_ocotp_read(void *context, unsigned int offset,
124 void *val, size_t bytes)
125{
126 struct ocotp_priv *priv = context;
127 unsigned int count;
128 u32 *buf = val;
129 int i, ret;
130 u32 index;
131
132 index = offset >> 2;
133 count = bytes >> 2;
134
135 if (count > (priv->params->nregs - index))
136 count = priv->params->nregs - index;
137
138 mutex_lock(&ocotp_mutex);
139
140 ret = clk_prepare_enable(priv->clk);
141 if (ret < 0) {
142 mutex_unlock(&ocotp_mutex);
143 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
144 return ret;
145 }
146
147 ret = imx_ocotp_wait_for_busy(priv->base, 0);
148 if (ret < 0) {
149 dev_err(priv->dev, "timeout during read setup\n");
150 goto read_end;
151 }
152
153 for (i = index; i < (index + count); i++) {
154 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
155 i * IMX_OCOTP_OFFSET_PER_WORD);
156
157 /* 47.3.1.2
158 * For "read locked" registers 0xBADABADA will be returned and
159 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
160 * software before any new write, read or reload access can be
161 * issued
162 */
163 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
164 imx_ocotp_clr_err_if_set(priv->base);
165 }
166 ret = 0;
167
168read_end:
169 clk_disable_unprepare(priv->clk);
170 mutex_unlock(&ocotp_mutex);
171 return ret;
172}
173
174static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
175{
176 unsigned long clk_rate = 0;
177 unsigned long strobe_read, relax, strobe_prog;
178 u32 timing = 0;
179
180 /* 47.3.1.3.1
181 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
182 * fields with timing values to match the current frequency of the
183 * ipg_clk. OTP writes will work at maximum bus frequencies as long
184 * as the HW_OCOTP_TIMING parameters are set correctly.
185 */
186 clk_rate = clk_get_rate(priv->clk);
187
188 relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
189 strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
190 strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
191
192 timing = strobe_prog & 0x00000FFF;
193 timing |= (relax << 12) & 0x0000F000;
194 timing |= (strobe_read << 16) & 0x003F0000;
195
196 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
197}
198
199static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
200{
201 unsigned long clk_rate = 0;
202 u64 fsource, strobe_prog;
203 u32 timing = 0;
204
205 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
206 * 6.4.3.3
207 */
208 clk_rate = clk_get_rate(priv->clk);
209 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
210 NSEC_PER_SEC) + 1;
211 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
212 NSEC_PER_SEC) + 1;
213
214 timing = strobe_prog & 0x00000FFF;
215 timing |= (fsource << 12) & 0x000FF000;
216
217 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
218}
219
220static int imx_ocotp_write(void *context, unsigned int offset, void *val,
221 size_t bytes)
222{
223 struct ocotp_priv *priv = context;
224 u32 *buf = val;
225 int ret;
226
227 u32 ctrl;
228 u8 waddr;
229 u8 word = 0;
230
231 /* allow only writing one complete OTP word at a time */
232 if ((bytes != priv->config->word_size) ||
233 (offset % priv->config->word_size))
234 return -EINVAL;
235
236 mutex_lock(&ocotp_mutex);
237
238 ret = clk_prepare_enable(priv->clk);
239 if (ret < 0) {
240 mutex_unlock(&ocotp_mutex);
241 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
242 return ret;
243 }
244
245 /* Setup the write timing values */
246 priv->params->set_timing(priv);
247
248 /* 47.3.1.3.2
249 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
250 * Overlapped accesses are not supported by the controller. Any pending
251 * write or reload must be completed before a write access can be
252 * requested.
253 */
254 ret = imx_ocotp_wait_for_busy(priv->base, 0);
255 if (ret < 0) {
256 dev_err(priv->dev, "timeout during timing setup\n");
257 goto write_end;
258 }
259
260 /* 47.3.1.3.3
261 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
262 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
263 * for each write access. The lock code is documented in the register
264 * description. Both the unlock code and address can be written in the
265 * same operation.
266 */
267 if (priv->params->bank_address_words != 0) {
268 /*
269 * In banked/i.MX7 mode the OTP register bank goes into waddr
270 * see i.MX 7Solo Applications Processor Reference Manual, Rev.
271 * 0.1 section 6.4.3.1
272 */
273 offset = offset / priv->config->word_size;
274 waddr = offset / priv->params->bank_address_words;
275 word = offset & (priv->params->bank_address_words - 1);
276 } else {
277 /*
278 * Non-banked i.MX6 mode.
279 * OTP write/read address specifies one of 128 word address
280 * locations
281 */
282 waddr = offset / 4;
283 }
284
285 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
286 ctrl &= ~IMX_OCOTP_BM_CTRL_ADDR;
287 ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR;
288 ctrl |= IMX_OCOTP_WR_UNLOCK;
289
290 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
291
292 /* 47.3.1.3.4
293 * Write the data to the HW_OCOTP_DATA register. This will automatically
294 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
295 * protect programming same OTP bit twice, before program OCOTP will
296 * automatically read fuse value in OTP and use read value to mask
297 * program data. The controller will use masked program data to program
298 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
299 * fields with 1's will result in that OTP bit being programmed. Bit
300 * fields with 0's will be ignored. At the same time that the write is
301 * accepted, the controller makes an internal copy of
302 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
303 * sequence is initiated. This copy guarantees that erroneous writes to
304 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
305 * should also be noted that during the programming HW_OCOTP_DATA will
306 * shift right (with zero fill). This shifting is required to program
307 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
308 * modified.
309 * Note: on i.MX7 there are four data fields to write for banked write
310 * with the fuse blowing operation only taking place after data0
311 * has been written. This is why data0 must always be the last
312 * register written.
313 */
314 if (priv->params->bank_address_words != 0) {
315 /* Banked/i.MX7 mode */
316 switch (word) {
317 case 0:
318 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
319 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
320 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
321 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
322 break;
323 case 1:
324 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
325 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
326 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
327 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
328 break;
329 case 2:
330 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
331 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
332 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
333 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
334 break;
335 case 3:
336 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
337 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
338 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
339 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
340 break;
341 }
342 } else {
343 /* Non-banked i.MX6 mode */
344 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
345 }
346
347 /* 47.4.1.4.5
348 * Once complete, the controller will clear BUSY. A write request to a
349 * protected or locked region will result in no OTP access and no
350 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
351 * be set. It must be cleared by software before any new write access
352 * can be issued.
353 */
354 ret = imx_ocotp_wait_for_busy(priv->base, 0);
355 if (ret < 0) {
356 if (ret == -EPERM) {
357 dev_err(priv->dev, "failed write to locked region");
358 imx_ocotp_clr_err_if_set(priv->base);
359 } else {
360 dev_err(priv->dev, "timeout during data write\n");
361 }
362 goto write_end;
363 }
364
365 /* 47.3.1.4
366 * Write Postamble: Due to internal electrical characteristics of the
367 * OTP during writes, all OTP operations following a write must be
368 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
369 * the write.
370 */
371 udelay(2);
372
373 /* reload all shadow registers */
374 writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS,
375 priv->base + IMX_OCOTP_ADDR_CTRL_SET);
376 ret = imx_ocotp_wait_for_busy(priv->base,
377 IMX_OCOTP_BM_CTRL_REL_SHADOWS);
378 if (ret < 0) {
379 dev_err(priv->dev, "timeout during shadow register reload\n");
380 goto write_end;
381 }
382
383write_end:
384 clk_disable_unprepare(priv->clk);
385 mutex_unlock(&ocotp_mutex);
386 if (ret < 0)
387 return ret;
388 return bytes;
389}
390
391static struct nvmem_config imx_ocotp_nvmem_config = {
392 .name = "imx-ocotp",
393 .read_only = false,
394 .word_size = 4,
395 .stride = 4,
396 .reg_read = imx_ocotp_read,
397 .reg_write = imx_ocotp_write,
398};
399
400static const struct ocotp_params imx6q_params = {
401 .nregs = 128,
402 .bank_address_words = 0,
403 .set_timing = imx_ocotp_set_imx6_timing,
404};
405
406static const struct ocotp_params imx6sl_params = {
407 .nregs = 64,
408 .bank_address_words = 0,
409 .set_timing = imx_ocotp_set_imx6_timing,
410};
411
412static const struct ocotp_params imx6sll_params = {
413 .nregs = 128,
414 .bank_address_words = 0,
415 .set_timing = imx_ocotp_set_imx6_timing,
416};
417
418static const struct ocotp_params imx6sx_params = {
419 .nregs = 128,
420 .bank_address_words = 0,
421 .set_timing = imx_ocotp_set_imx6_timing,
422};
423
424static const struct ocotp_params imx6ul_params = {
425 .nregs = 128,
426 .bank_address_words = 0,
427 .set_timing = imx_ocotp_set_imx6_timing,
428};
429
430static const struct ocotp_params imx6ull_params = {
431 .nregs = 64,
432 .bank_address_words = 0,
433 .set_timing = imx_ocotp_set_imx6_timing,
434};
435
436static const struct ocotp_params imx7d_params = {
437 .nregs = 64,
438 .bank_address_words = 4,
439 .set_timing = imx_ocotp_set_imx7_timing,
440};
441
442static const struct ocotp_params imx7ulp_params = {
443 .nregs = 256,
444 .bank_address_words = 0,
445};
446
447static const struct of_device_id imx_ocotp_dt_ids[] = {
448 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
449 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
450 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
451 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
452 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
453 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
454 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
455 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
456 { },
457};
458MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
459
460static int imx_ocotp_probe(struct platform_device *pdev)
461{
462 struct device *dev = &pdev->dev;
463 struct resource *res;
464 struct ocotp_priv *priv;
465 struct nvmem_device *nvmem;
466
467 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
468 if (!priv)
469 return -ENOMEM;
470
471 priv->dev = dev;
472
473 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474 priv->base = devm_ioremap_resource(dev, res);
475 if (IS_ERR(priv->base))
476 return PTR_ERR(priv->base);
477
478 priv->clk = devm_clk_get(dev, NULL);
479 if (IS_ERR(priv->clk))
480 return PTR_ERR(priv->clk);
481
482 priv->params = of_device_get_match_data(&pdev->dev);
483 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
484 imx_ocotp_nvmem_config.dev = dev;
485 imx_ocotp_nvmem_config.priv = priv;
486 priv->config = &imx_ocotp_nvmem_config;
487 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
488
489
490 return PTR_ERR_OR_ZERO(nvmem);
491}
492
493static struct platform_driver imx_ocotp_driver = {
494 .probe = imx_ocotp_probe,
495 .driver = {
496 .name = "imx_ocotp",
497 .of_match_table = imx_ocotp_dt_ids,
498 },
499};
500module_platform_driver(imx_ocotp_driver);
501
502MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
503MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
504MODULE_LICENSE("GPL v2");
505