1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * i.MX6 OCOTP fusebox driver |
4 | * |
5 | * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> |
6 | * |
7 | * Copyright 2019 NXP |
8 | * |
9 | * Based on the barebox ocotp driver, |
10 | * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, |
11 | * Orex Computed Radiography |
12 | * |
13 | * Write support based on the fsl_otp driver, |
14 | * Copyright (C) 2010-2013 Freescale Semiconductor, Inc |
15 | */ |
16 | |
17 | #include <linux/clk.h> |
18 | #include <linux/device.h> |
19 | #include <linux/io.h> |
20 | #include <linux/module.h> |
21 | #include <linux/nvmem-provider.h> |
22 | #include <linux/of.h> |
23 | #include <linux/platform_device.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/delay.h> |
26 | |
27 | #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the |
28 | * OTP Bank0 Word0 |
29 | */ |
30 | #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr |
31 | * of two consecutive OTP words. |
32 | */ |
33 | |
34 | #define IMX_OCOTP_ADDR_CTRL 0x0000 |
35 | #define IMX_OCOTP_ADDR_CTRL_SET 0x0004 |
36 | #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008 |
37 | #define IMX_OCOTP_ADDR_TIMING 0x0010 |
38 | #define IMX_OCOTP_ADDR_DATA0 0x0020 |
39 | #define IMX_OCOTP_ADDR_DATA1 0x0030 |
40 | #define IMX_OCOTP_ADDR_DATA2 0x0040 |
41 | #define IMX_OCOTP_ADDR_DATA3 0x0050 |
42 | |
43 | #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF |
44 | #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 |
45 | #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 |
46 | #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 |
47 | |
48 | #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF |
49 | #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200 |
50 | #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400 |
51 | #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800 |
52 | |
53 | #define IMX_OCOTP_BM_CTRL_DEFAULT \ |
54 | { \ |
55 | .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \ |
56 | .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \ |
57 | .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \ |
58 | .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\ |
59 | } |
60 | |
61 | #define IMX_OCOTP_BM_CTRL_8MP \ |
62 | { \ |
63 | .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \ |
64 | .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \ |
65 | .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \ |
66 | .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\ |
67 | } |
68 | |
69 | #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ |
70 | #define TIMING_STROBE_READ_NS 37 /* Min time before read */ |
71 | #define TIMING_RELAX_NS 17 |
72 | #define DEF_FSOURCE 1001 /* > 1000 ns */ |
73 | #define DEF_STROBE_PROG 10000 /* IPG clocks */ |
74 | #define IMX_OCOTP_WR_UNLOCK 0x3E770000 |
75 | #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA |
76 | |
77 | static DEFINE_MUTEX(ocotp_mutex); |
78 | |
79 | struct ocotp_priv { |
80 | struct device *dev; |
81 | struct clk *clk; |
82 | void __iomem *base; |
83 | const struct ocotp_params *params; |
84 | struct nvmem_config *config; |
85 | }; |
86 | |
87 | struct ocotp_ctrl_reg { |
88 | u32 bm_addr; |
89 | u32 bm_busy; |
90 | u32 bm_error; |
91 | u32 bm_rel_shadows; |
92 | }; |
93 | |
94 | struct ocotp_params { |
95 | unsigned int nregs; |
96 | unsigned int bank_address_words; |
97 | void (*set_timing)(struct ocotp_priv *priv); |
98 | struct ocotp_ctrl_reg ctrl; |
99 | }; |
100 | |
101 | static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) |
102 | { |
103 | int count; |
104 | u32 c, mask; |
105 | u32 bm_ctrl_busy, bm_ctrl_error; |
106 | void __iomem *base = priv->base; |
107 | |
108 | bm_ctrl_busy = priv->params->ctrl.bm_busy; |
109 | bm_ctrl_error = priv->params->ctrl.bm_error; |
110 | |
111 | mask = bm_ctrl_busy | bm_ctrl_error | flags; |
112 | |
113 | for (count = 10000; count >= 0; count--) { |
114 | c = readl(addr: base + IMX_OCOTP_ADDR_CTRL); |
115 | if (!(c & mask)) |
116 | break; |
117 | cpu_relax(); |
118 | } |
119 | |
120 | if (count < 0) { |
121 | /* HW_OCOTP_CTRL[ERROR] will be set under the following |
122 | * conditions: |
123 | * - A write is performed to a shadow register during a shadow |
124 | * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is |
125 | * set. In addition, the contents of the shadow register shall |
126 | * not be updated. |
127 | * - A write is performed to a shadow register which has been |
128 | * locked. |
129 | * - A read is performed to from a shadow register which has |
130 | * been read locked. |
131 | * - A program is performed to a fuse word which has been locked |
132 | * - A read is performed to from a fuse word which has been read |
133 | * locked. |
134 | */ |
135 | if (c & bm_ctrl_error) |
136 | return -EPERM; |
137 | return -ETIMEDOUT; |
138 | } |
139 | |
140 | return 0; |
141 | } |
142 | |
143 | static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv) |
144 | { |
145 | u32 c, bm_ctrl_error; |
146 | void __iomem *base = priv->base; |
147 | |
148 | bm_ctrl_error = priv->params->ctrl.bm_error; |
149 | |
150 | c = readl(addr: base + IMX_OCOTP_ADDR_CTRL); |
151 | if (!(c & bm_ctrl_error)) |
152 | return; |
153 | |
154 | writel(val: bm_ctrl_error, addr: base + IMX_OCOTP_ADDR_CTRL_CLR); |
155 | } |
156 | |
157 | static int imx_ocotp_read(void *context, unsigned int offset, |
158 | void *val, size_t bytes) |
159 | { |
160 | struct ocotp_priv *priv = context; |
161 | unsigned int count; |
162 | u8 *buf, *p; |
163 | int i, ret; |
164 | u32 index, num_bytes; |
165 | |
166 | index = offset >> 2; |
167 | num_bytes = round_up((offset % 4) + bytes, 4); |
168 | count = num_bytes >> 2; |
169 | |
170 | if (count > (priv->params->nregs - index)) |
171 | count = priv->params->nregs - index; |
172 | |
173 | p = kzalloc(size: num_bytes, GFP_KERNEL); |
174 | if (!p) |
175 | return -ENOMEM; |
176 | |
177 | mutex_lock(&ocotp_mutex); |
178 | |
179 | buf = p; |
180 | |
181 | ret = clk_prepare_enable(clk: priv->clk); |
182 | if (ret < 0) { |
183 | mutex_unlock(lock: &ocotp_mutex); |
184 | dev_err(priv->dev, "failed to prepare/enable ocotp clk\n" ); |
185 | kfree(objp: p); |
186 | return ret; |
187 | } |
188 | |
189 | ret = imx_ocotp_wait_for_busy(priv, flags: 0); |
190 | if (ret < 0) { |
191 | dev_err(priv->dev, "timeout during read setup\n" ); |
192 | goto read_end; |
193 | } |
194 | |
195 | for (i = index; i < (index + count); i++) { |
196 | *(u32 *)buf = readl(addr: priv->base + IMX_OCOTP_OFFSET_B0W0 + |
197 | i * IMX_OCOTP_OFFSET_PER_WORD); |
198 | |
199 | /* 47.3.1.2 |
200 | * For "read locked" registers 0xBADABADA will be returned and |
201 | * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by |
202 | * software before any new write, read or reload access can be |
203 | * issued |
204 | */ |
205 | if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL) |
206 | imx_ocotp_clr_err_if_set(priv); |
207 | |
208 | buf += 4; |
209 | } |
210 | |
211 | index = offset % 4; |
212 | memcpy(val, &p[index], bytes); |
213 | |
214 | read_end: |
215 | clk_disable_unprepare(clk: priv->clk); |
216 | mutex_unlock(lock: &ocotp_mutex); |
217 | |
218 | kfree(objp: p); |
219 | |
220 | return ret; |
221 | } |
222 | |
223 | static int imx_ocotp_cell_pp(void *context, const char *id, int index, |
224 | unsigned int offset, void *data, size_t bytes) |
225 | { |
226 | u8 *buf = data; |
227 | int i; |
228 | |
229 | /* Deal with some post processing of nvmem cell data */ |
230 | if (id && !strcmp(id, "mac-address" )) |
231 | for (i = 0; i < bytes / 2; i++) |
232 | swap(buf[i], buf[bytes - i - 1]); |
233 | |
234 | return 0; |
235 | } |
236 | |
237 | static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) |
238 | { |
239 | unsigned long clk_rate; |
240 | unsigned long strobe_read, relax, strobe_prog; |
241 | u32 timing; |
242 | |
243 | /* 47.3.1.3.1 |
244 | * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] |
245 | * fields with timing values to match the current frequency of the |
246 | * ipg_clk. OTP writes will work at maximum bus frequencies as long |
247 | * as the HW_OCOTP_TIMING parameters are set correctly. |
248 | * |
249 | * Note: there are minimum timings required to ensure an OTP fuse burns |
250 | * correctly that are independent of the ipg_clk. Those values are not |
251 | * formally documented anywhere however, working from the minimum |
252 | * timings given in u-boot we can say: |
253 | * |
254 | * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 |
255 | * microseconds feels about right as representative of a minimum time |
256 | * to physically burn out a fuse. |
257 | * |
258 | * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before |
259 | * performing another read is 37 nanoseconds |
260 | * |
261 | * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum |
262 | * timing is not entirely clear the documentation says "This |
263 | * count value specifies the time to add to all default timing |
264 | * parameters other than the Tpgm and Trd. It is given in number |
265 | * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG |
266 | * and STROBE_READ respectively. What the other timing parameters |
267 | * are though, is not specified. Experience shows a zero RELAX |
268 | * value will mess up a re-load of the shadow registers post OTP |
269 | * burn. |
270 | */ |
271 | clk_rate = clk_get_rate(clk: priv->clk); |
272 | |
273 | relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; |
274 | strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, |
275 | 1000000000); |
276 | strobe_read += 2 * (relax + 1) - 1; |
277 | strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, |
278 | 1000000); |
279 | strobe_prog += 2 * (relax + 1) - 1; |
280 | |
281 | timing = readl(addr: priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; |
282 | timing |= strobe_prog & 0x00000FFF; |
283 | timing |= (relax << 12) & 0x0000F000; |
284 | timing |= (strobe_read << 16) & 0x003F0000; |
285 | |
286 | writel(val: timing, addr: priv->base + IMX_OCOTP_ADDR_TIMING); |
287 | } |
288 | |
289 | static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) |
290 | { |
291 | unsigned long clk_rate; |
292 | u64 fsource, strobe_prog; |
293 | u32 timing; |
294 | |
295 | /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 |
296 | * 6.4.3.3 |
297 | */ |
298 | clk_rate = clk_get_rate(clk: priv->clk); |
299 | fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, |
300 | NSEC_PER_SEC) + 1; |
301 | strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, |
302 | NSEC_PER_SEC) + 1; |
303 | |
304 | timing = strobe_prog & 0x00000FFF; |
305 | timing |= (fsource << 12) & 0x000FF000; |
306 | |
307 | writel(val: timing, addr: priv->base + IMX_OCOTP_ADDR_TIMING); |
308 | } |
309 | |
310 | static int imx_ocotp_write(void *context, unsigned int offset, void *val, |
311 | size_t bytes) |
312 | { |
313 | struct ocotp_priv *priv = context; |
314 | u32 *buf = val; |
315 | int ret; |
316 | |
317 | u32 ctrl; |
318 | u8 waddr; |
319 | u8 word = 0; |
320 | |
321 | /* allow only writing one complete OTP word at a time */ |
322 | if ((bytes != priv->config->word_size) || |
323 | (offset % priv->config->word_size)) |
324 | return -EINVAL; |
325 | |
326 | mutex_lock(&ocotp_mutex); |
327 | |
328 | ret = clk_prepare_enable(clk: priv->clk); |
329 | if (ret < 0) { |
330 | mutex_unlock(lock: &ocotp_mutex); |
331 | dev_err(priv->dev, "failed to prepare/enable ocotp clk\n" ); |
332 | return ret; |
333 | } |
334 | |
335 | /* Setup the write timing values */ |
336 | priv->params->set_timing(priv); |
337 | |
338 | /* 47.3.1.3.2 |
339 | * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. |
340 | * Overlapped accesses are not supported by the controller. Any pending |
341 | * write or reload must be completed before a write access can be |
342 | * requested. |
343 | */ |
344 | ret = imx_ocotp_wait_for_busy(priv, flags: 0); |
345 | if (ret < 0) { |
346 | dev_err(priv->dev, "timeout during timing setup\n" ); |
347 | goto write_end; |
348 | } |
349 | |
350 | /* 47.3.1.3.3 |
351 | * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the |
352 | * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed |
353 | * for each write access. The lock code is documented in the register |
354 | * description. Both the unlock code and address can be written in the |
355 | * same operation. |
356 | */ |
357 | if (priv->params->bank_address_words != 0) { |
358 | /* |
359 | * In banked/i.MX7 mode the OTP register bank goes into waddr |
360 | * see i.MX 7Solo Applications Processor Reference Manual, Rev. |
361 | * 0.1 section 6.4.3.1 |
362 | */ |
363 | offset = offset / priv->config->word_size; |
364 | waddr = offset / priv->params->bank_address_words; |
365 | word = offset & (priv->params->bank_address_words - 1); |
366 | } else { |
367 | /* |
368 | * Non-banked i.MX6 mode. |
369 | * OTP write/read address specifies one of 128 word address |
370 | * locations |
371 | */ |
372 | waddr = offset / 4; |
373 | } |
374 | |
375 | ctrl = readl(addr: priv->base + IMX_OCOTP_ADDR_CTRL); |
376 | ctrl &= ~priv->params->ctrl.bm_addr; |
377 | ctrl |= waddr & priv->params->ctrl.bm_addr; |
378 | ctrl |= IMX_OCOTP_WR_UNLOCK; |
379 | |
380 | writel(val: ctrl, addr: priv->base + IMX_OCOTP_ADDR_CTRL); |
381 | |
382 | /* 47.3.1.3.4 |
383 | * Write the data to the HW_OCOTP_DATA register. This will automatically |
384 | * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To |
385 | * protect programming same OTP bit twice, before program OCOTP will |
386 | * automatically read fuse value in OTP and use read value to mask |
387 | * program data. The controller will use masked program data to program |
388 | * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit |
389 | * fields with 1's will result in that OTP bit being programmed. Bit |
390 | * fields with 0's will be ignored. At the same time that the write is |
391 | * accepted, the controller makes an internal copy of |
392 | * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write |
393 | * sequence is initiated. This copy guarantees that erroneous writes to |
394 | * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It |
395 | * should also be noted that during the programming HW_OCOTP_DATA will |
396 | * shift right (with zero fill). This shifting is required to program |
397 | * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be |
398 | * modified. |
399 | * Note: on i.MX7 there are four data fields to write for banked write |
400 | * with the fuse blowing operation only taking place after data0 |
401 | * has been written. This is why data0 must always be the last |
402 | * register written. |
403 | */ |
404 | if (priv->params->bank_address_words != 0) { |
405 | /* Banked/i.MX7 mode */ |
406 | switch (word) { |
407 | case 0: |
408 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA1); |
409 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA2); |
410 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA3); |
411 | writel(val: *buf, addr: priv->base + IMX_OCOTP_ADDR_DATA0); |
412 | break; |
413 | case 1: |
414 | writel(val: *buf, addr: priv->base + IMX_OCOTP_ADDR_DATA1); |
415 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA2); |
416 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA3); |
417 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA0); |
418 | break; |
419 | case 2: |
420 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA1); |
421 | writel(val: *buf, addr: priv->base + IMX_OCOTP_ADDR_DATA2); |
422 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA3); |
423 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA0); |
424 | break; |
425 | case 3: |
426 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA1); |
427 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA2); |
428 | writel(val: *buf, addr: priv->base + IMX_OCOTP_ADDR_DATA3); |
429 | writel(val: 0, addr: priv->base + IMX_OCOTP_ADDR_DATA0); |
430 | break; |
431 | } |
432 | } else { |
433 | /* Non-banked i.MX6 mode */ |
434 | writel(val: *buf, addr: priv->base + IMX_OCOTP_ADDR_DATA0); |
435 | } |
436 | |
437 | /* 47.4.1.4.5 |
438 | * Once complete, the controller will clear BUSY. A write request to a |
439 | * protected or locked region will result in no OTP access and no |
440 | * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will |
441 | * be set. It must be cleared by software before any new write access |
442 | * can be issued. |
443 | */ |
444 | ret = imx_ocotp_wait_for_busy(priv, flags: 0); |
445 | if (ret < 0) { |
446 | if (ret == -EPERM) { |
447 | dev_err(priv->dev, "failed write to locked region" ); |
448 | imx_ocotp_clr_err_if_set(priv); |
449 | } else { |
450 | dev_err(priv->dev, "timeout during data write\n" ); |
451 | } |
452 | goto write_end; |
453 | } |
454 | |
455 | /* 47.3.1.4 |
456 | * Write Postamble: Due to internal electrical characteristics of the |
457 | * OTP during writes, all OTP operations following a write must be |
458 | * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following |
459 | * the write. |
460 | */ |
461 | udelay(2); |
462 | |
463 | /* reload all shadow registers */ |
464 | writel(val: priv->params->ctrl.bm_rel_shadows, |
465 | addr: priv->base + IMX_OCOTP_ADDR_CTRL_SET); |
466 | ret = imx_ocotp_wait_for_busy(priv, |
467 | flags: priv->params->ctrl.bm_rel_shadows); |
468 | if (ret < 0) |
469 | dev_err(priv->dev, "timeout during shadow register reload\n" ); |
470 | |
471 | write_end: |
472 | clk_disable_unprepare(clk: priv->clk); |
473 | mutex_unlock(lock: &ocotp_mutex); |
474 | return ret < 0 ? ret : bytes; |
475 | } |
476 | |
477 | static struct nvmem_config imx_ocotp_nvmem_config = { |
478 | .name = "imx-ocotp" , |
479 | .read_only = false, |
480 | .word_size = 4, |
481 | .stride = 1, |
482 | .reg_read = imx_ocotp_read, |
483 | .reg_write = imx_ocotp_write, |
484 | }; |
485 | |
486 | static const struct ocotp_params imx6q_params = { |
487 | .nregs = 128, |
488 | .bank_address_words = 0, |
489 | .set_timing = imx_ocotp_set_imx6_timing, |
490 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
491 | }; |
492 | |
493 | static const struct ocotp_params imx6sl_params = { |
494 | .nregs = 64, |
495 | .bank_address_words = 0, |
496 | .set_timing = imx_ocotp_set_imx6_timing, |
497 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
498 | }; |
499 | |
500 | static const struct ocotp_params imx6sll_params = { |
501 | .nregs = 80, |
502 | .bank_address_words = 0, |
503 | .set_timing = imx_ocotp_set_imx6_timing, |
504 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
505 | }; |
506 | |
507 | static const struct ocotp_params imx6sx_params = { |
508 | .nregs = 128, |
509 | .bank_address_words = 0, |
510 | .set_timing = imx_ocotp_set_imx6_timing, |
511 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
512 | }; |
513 | |
514 | static const struct ocotp_params imx6ul_params = { |
515 | .nregs = 144, |
516 | .bank_address_words = 0, |
517 | .set_timing = imx_ocotp_set_imx6_timing, |
518 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
519 | }; |
520 | |
521 | static const struct ocotp_params imx6ull_params = { |
522 | .nregs = 80, |
523 | .bank_address_words = 0, |
524 | .set_timing = imx_ocotp_set_imx6_timing, |
525 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
526 | }; |
527 | |
528 | static const struct ocotp_params imx7d_params = { |
529 | .nregs = 64, |
530 | .bank_address_words = 4, |
531 | .set_timing = imx_ocotp_set_imx7_timing, |
532 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
533 | }; |
534 | |
535 | static const struct ocotp_params imx7ulp_params = { |
536 | .nregs = 256, |
537 | .bank_address_words = 0, |
538 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
539 | }; |
540 | |
541 | static const struct ocotp_params imx8mq_params = { |
542 | .nregs = 256, |
543 | .bank_address_words = 0, |
544 | .set_timing = imx_ocotp_set_imx6_timing, |
545 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
546 | }; |
547 | |
548 | static const struct ocotp_params imx8mm_params = { |
549 | .nregs = 256, |
550 | .bank_address_words = 0, |
551 | .set_timing = imx_ocotp_set_imx6_timing, |
552 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
553 | }; |
554 | |
555 | static const struct ocotp_params imx8mn_params = { |
556 | .nregs = 256, |
557 | .bank_address_words = 0, |
558 | .set_timing = imx_ocotp_set_imx6_timing, |
559 | .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, |
560 | }; |
561 | |
562 | static const struct ocotp_params imx8mp_params = { |
563 | .nregs = 384, |
564 | .bank_address_words = 0, |
565 | .set_timing = imx_ocotp_set_imx6_timing, |
566 | .ctrl = IMX_OCOTP_BM_CTRL_8MP, |
567 | }; |
568 | |
569 | static const struct of_device_id imx_ocotp_dt_ids[] = { |
570 | { .compatible = "fsl,imx6q-ocotp" , .data = &imx6q_params }, |
571 | { .compatible = "fsl,imx6sl-ocotp" , .data = &imx6sl_params }, |
572 | { .compatible = "fsl,imx6sx-ocotp" , .data = &imx6sx_params }, |
573 | { .compatible = "fsl,imx6ul-ocotp" , .data = &imx6ul_params }, |
574 | { .compatible = "fsl,imx6ull-ocotp" , .data = &imx6ull_params }, |
575 | { .compatible = "fsl,imx7d-ocotp" , .data = &imx7d_params }, |
576 | { .compatible = "fsl,imx6sll-ocotp" , .data = &imx6sll_params }, |
577 | { .compatible = "fsl,imx7ulp-ocotp" , .data = &imx7ulp_params }, |
578 | { .compatible = "fsl,imx8mq-ocotp" , .data = &imx8mq_params }, |
579 | { .compatible = "fsl,imx8mm-ocotp" , .data = &imx8mm_params }, |
580 | { .compatible = "fsl,imx8mn-ocotp" , .data = &imx8mn_params }, |
581 | { .compatible = "fsl,imx8mp-ocotp" , .data = &imx8mp_params }, |
582 | { }, |
583 | }; |
584 | MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); |
585 | |
586 | static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem, |
587 | struct nvmem_layout *layout, |
588 | struct nvmem_cell_info *cell) |
589 | { |
590 | cell->read_post_process = imx_ocotp_cell_pp; |
591 | } |
592 | |
593 | static struct nvmem_layout imx_ocotp_layout = { |
594 | .fixup_cell_info = imx_ocotp_fixup_cell_info, |
595 | }; |
596 | |
597 | static int imx_ocotp_probe(struct platform_device *pdev) |
598 | { |
599 | struct device *dev = &pdev->dev; |
600 | struct ocotp_priv *priv; |
601 | struct nvmem_device *nvmem; |
602 | |
603 | priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL); |
604 | if (!priv) |
605 | return -ENOMEM; |
606 | |
607 | priv->dev = dev; |
608 | |
609 | priv->base = devm_platform_ioremap_resource(pdev, index: 0); |
610 | if (IS_ERR(ptr: priv->base)) |
611 | return PTR_ERR(ptr: priv->base); |
612 | |
613 | priv->clk = devm_clk_get(dev, NULL); |
614 | if (IS_ERR(ptr: priv->clk)) |
615 | return PTR_ERR(ptr: priv->clk); |
616 | |
617 | priv->params = of_device_get_match_data(dev: &pdev->dev); |
618 | imx_ocotp_nvmem_config.add_legacy_fixed_of_cells = true; |
619 | imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; |
620 | imx_ocotp_nvmem_config.dev = dev; |
621 | imx_ocotp_nvmem_config.priv = priv; |
622 | imx_ocotp_nvmem_config.layout = &imx_ocotp_layout; |
623 | |
624 | priv->config = &imx_ocotp_nvmem_config; |
625 | |
626 | clk_prepare_enable(clk: priv->clk); |
627 | imx_ocotp_clr_err_if_set(priv); |
628 | clk_disable_unprepare(clk: priv->clk); |
629 | |
630 | nvmem = devm_nvmem_register(dev, cfg: &imx_ocotp_nvmem_config); |
631 | |
632 | return PTR_ERR_OR_ZERO(ptr: nvmem); |
633 | } |
634 | |
635 | static struct platform_driver imx_ocotp_driver = { |
636 | .probe = imx_ocotp_probe, |
637 | .driver = { |
638 | .name = "imx_ocotp" , |
639 | .of_match_table = imx_ocotp_dt_ids, |
640 | }, |
641 | }; |
642 | module_platform_driver(imx_ocotp_driver); |
643 | |
644 | MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>" ); |
645 | MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver" ); |
646 | MODULE_LICENSE("GPL v2" ); |
647 | |