1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2016-2018 Broadcom |
4 | */ |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/delay.h> |
8 | #include <linux/io.h> |
9 | #include <linux/module.h> |
10 | #include <linux/mfd/syscon.h> |
11 | #include <linux/of.h> |
12 | #include <linux/phy/phy.h> |
13 | #include <linux/platform_device.h> |
14 | #include <linux/regmap.h> |
15 | |
16 | /* we have up to 8 PAXB based RC. The 9th one is always PAXC */ |
17 | #define SR_NR_PCIE_PHYS 9 |
18 | #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1) |
19 | |
20 | #define PCIE_PIPEMUX_CFG_OFFSET 0x10c |
21 | #define PCIE_PIPEMUX_SELECT_STRAP 0xf |
22 | |
23 | #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c |
24 | #define PCIE_PIPEMUX_SHIFT 19 |
25 | #define PCIE_PIPEMUX_MASK 0xf |
26 | |
27 | #define MHB_MEM_PW_PAXC_OFFSET 0x1c0 |
28 | #define MHB_PWR_ARR_POWERON 0x8 |
29 | #define MHB_PWR_ARR_POWEROK 0x4 |
30 | #define MHB_PWR_POWERON 0x2 |
31 | #define MHB_PWR_POWEROK 0x1 |
32 | #define MHB_PWR_STATUS_MASK (MHB_PWR_ARR_POWERON | \ |
33 | MHB_PWR_ARR_POWEROK | \ |
34 | MHB_PWR_POWERON | \ |
35 | MHB_PWR_POWEROK) |
36 | |
37 | struct sr_pcie_phy_core; |
38 | |
39 | /** |
40 | * struct sr_pcie_phy - Stingray PCIe PHY |
41 | * |
42 | * @core: pointer to the Stingray PCIe PHY core control |
43 | * @index: PHY index |
44 | * @phy: pointer to the kernel PHY device |
45 | */ |
46 | struct sr_pcie_phy { |
47 | struct sr_pcie_phy_core *core; |
48 | unsigned int index; |
49 | struct phy *phy; |
50 | }; |
51 | |
52 | /** |
53 | * struct sr_pcie_phy_core - Stingray PCIe PHY core control |
54 | * |
55 | * @dev: pointer to device |
56 | * @base: base register of PCIe SS |
57 | * @cdru: regmap to the CDRU device |
58 | * @mhb: regmap to the MHB device |
59 | * @pipemux: pipemuex strap |
60 | * @phys: array of PCIe PHYs |
61 | */ |
62 | struct sr_pcie_phy_core { |
63 | struct device *dev; |
64 | void __iomem *base; |
65 | struct regmap *cdru; |
66 | struct regmap *mhb; |
67 | u32 pipemux; |
68 | struct sr_pcie_phy phys[SR_NR_PCIE_PHYS]; |
69 | }; |
70 | |
71 | /* |
72 | * PCIe PIPEMUX lookup table |
73 | * |
74 | * Each array index represents a PIPEMUX strap setting |
75 | * The array element represents a bitmap where a set bit means the PCIe |
76 | * core and associated serdes has been enabled as RC and is available for use |
77 | */ |
78 | static const u8 pipemux_table[] = { |
79 | /* PIPEMUX = 0, EP 1x16 */ |
80 | 0x00, |
81 | /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */ |
82 | 0x80, |
83 | /* PIPEMUX = 2, EP 4x4 */ |
84 | 0x00, |
85 | /* PIPEMUX = 3, RC 2x8, cores 0, 7 */ |
86 | 0x81, |
87 | /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */ |
88 | 0xc3, |
89 | /* PIPEMUX = 5, RC 8x2, all 8 cores */ |
90 | 0xff, |
91 | /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */ |
92 | 0xcd, |
93 | /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */ |
94 | 0xfd, |
95 | /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */ |
96 | 0xf0, |
97 | /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */ |
98 | 0xc0, |
99 | /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */ |
100 | 0x42, |
101 | /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */ |
102 | 0x3c, |
103 | /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */ |
104 | 0xfc, |
105 | /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */ |
106 | 0x4c, |
107 | }; |
108 | |
109 | /* |
110 | * Return true if the strap setting is valid |
111 | */ |
112 | static bool pipemux_strap_is_valid(u32 pipemux) |
113 | { |
114 | return !!(pipemux < ARRAY_SIZE(pipemux_table)); |
115 | } |
116 | |
117 | /* |
118 | * Read the PCIe PIPEMUX from strap |
119 | */ |
120 | static u32 pipemux_strap_read(struct sr_pcie_phy_core *core) |
121 | { |
122 | u32 pipemux; |
123 | |
124 | /* |
125 | * Read PIPEMUX configuration register to determine the pipemux setting |
126 | * |
127 | * In the case when the value indicates using HW strap, fall back to |
128 | * use HW strap |
129 | */ |
130 | pipemux = readl(addr: core->base + PCIE_PIPEMUX_CFG_OFFSET); |
131 | pipemux &= PCIE_PIPEMUX_MASK; |
132 | if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) { |
133 | regmap_read(map: core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, val: &pipemux); |
134 | pipemux >>= PCIE_PIPEMUX_SHIFT; |
135 | pipemux &= PCIE_PIPEMUX_MASK; |
136 | } |
137 | |
138 | return pipemux; |
139 | } |
140 | |
141 | /* |
142 | * Given a PIPEMUX strap and PCIe core index, this function returns true if the |
143 | * PCIe core needs to be enabled |
144 | */ |
145 | static bool pcie_core_is_for_rc(struct sr_pcie_phy *phy) |
146 | { |
147 | struct sr_pcie_phy_core *core = phy->core; |
148 | unsigned int core_idx = phy->index; |
149 | |
150 | return !!((pipemux_table[core->pipemux] >> core_idx) & 0x1); |
151 | } |
152 | |
153 | static int sr_pcie_phy_init(struct phy *p) |
154 | { |
155 | struct sr_pcie_phy *phy = phy_get_drvdata(phy: p); |
156 | |
157 | /* |
158 | * Check whether this PHY is for root complex or not. If yes, return |
159 | * zero so the host driver can proceed to enumeration. If not, return |
160 | * an error and that will force the host driver to bail out |
161 | */ |
162 | if (pcie_core_is_for_rc(phy)) |
163 | return 0; |
164 | |
165 | return -ENODEV; |
166 | } |
167 | |
168 | static int sr_paxc_phy_init(struct phy *p) |
169 | { |
170 | struct sr_pcie_phy *phy = phy_get_drvdata(phy: p); |
171 | struct sr_pcie_phy_core *core = phy->core; |
172 | unsigned int core_idx = phy->index; |
173 | u32 val; |
174 | |
175 | if (core_idx != SR_PAXC_PHY_IDX) |
176 | return -EINVAL; |
177 | |
178 | regmap_read(map: core->mhb, MHB_MEM_PW_PAXC_OFFSET, val: &val); |
179 | if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) { |
180 | dev_err(core->dev, "PAXC is not powered up\n" ); |
181 | return -ENODEV; |
182 | } |
183 | |
184 | return 0; |
185 | } |
186 | |
187 | static const struct phy_ops sr_pcie_phy_ops = { |
188 | .init = sr_pcie_phy_init, |
189 | .owner = THIS_MODULE, |
190 | }; |
191 | |
192 | static const struct phy_ops sr_paxc_phy_ops = { |
193 | .init = sr_paxc_phy_init, |
194 | .owner = THIS_MODULE, |
195 | }; |
196 | |
197 | static struct phy *sr_pcie_phy_xlate(struct device *dev, |
198 | const struct of_phandle_args *args) |
199 | { |
200 | struct sr_pcie_phy_core *core; |
201 | int phy_idx; |
202 | |
203 | core = dev_get_drvdata(dev); |
204 | if (!core) |
205 | return ERR_PTR(error: -EINVAL); |
206 | |
207 | phy_idx = args->args[0]; |
208 | |
209 | if (WARN_ON(phy_idx >= SR_NR_PCIE_PHYS)) |
210 | return ERR_PTR(error: -ENODEV); |
211 | |
212 | return core->phys[phy_idx].phy; |
213 | } |
214 | |
215 | static int sr_pcie_phy_probe(struct platform_device *pdev) |
216 | { |
217 | struct device *dev = &pdev->dev; |
218 | struct device_node *node = dev->of_node; |
219 | struct sr_pcie_phy_core *core; |
220 | struct phy_provider *provider; |
221 | unsigned int phy_idx = 0; |
222 | |
223 | core = devm_kzalloc(dev, size: sizeof(*core), GFP_KERNEL); |
224 | if (!core) |
225 | return -ENOMEM; |
226 | |
227 | core->dev = dev; |
228 | core->base = devm_platform_ioremap_resource(pdev, index: 0); |
229 | if (IS_ERR(ptr: core->base)) |
230 | return PTR_ERR(ptr: core->base); |
231 | |
232 | core->cdru = syscon_regmap_lookup_by_phandle(np: node, property: "brcm,sr-cdru" ); |
233 | if (IS_ERR(ptr: core->cdru)) { |
234 | dev_err(core->dev, "unable to find CDRU device\n" ); |
235 | return PTR_ERR(ptr: core->cdru); |
236 | } |
237 | |
238 | core->mhb = syscon_regmap_lookup_by_phandle(np: node, property: "brcm,sr-mhb" ); |
239 | if (IS_ERR(ptr: core->mhb)) { |
240 | dev_err(core->dev, "unable to find MHB device\n" ); |
241 | return PTR_ERR(ptr: core->mhb); |
242 | } |
243 | |
244 | /* read the PCIe PIPEMUX strap setting */ |
245 | core->pipemux = pipemux_strap_read(core); |
246 | if (!pipemux_strap_is_valid(pipemux: core->pipemux)) { |
247 | dev_err(core->dev, "invalid PCIe PIPEMUX strap %u\n" , |
248 | core->pipemux); |
249 | return -EIO; |
250 | } |
251 | |
252 | for (phy_idx = 0; phy_idx < SR_NR_PCIE_PHYS; phy_idx++) { |
253 | struct sr_pcie_phy *p = &core->phys[phy_idx]; |
254 | const struct phy_ops *ops; |
255 | |
256 | if (phy_idx == SR_PAXC_PHY_IDX) |
257 | ops = &sr_paxc_phy_ops; |
258 | else |
259 | ops = &sr_pcie_phy_ops; |
260 | |
261 | p->phy = devm_phy_create(dev, NULL, ops); |
262 | if (IS_ERR(ptr: p->phy)) { |
263 | dev_err(dev, "failed to create PCIe PHY\n" ); |
264 | return PTR_ERR(ptr: p->phy); |
265 | } |
266 | |
267 | p->core = core; |
268 | p->index = phy_idx; |
269 | phy_set_drvdata(phy: p->phy, data: p); |
270 | } |
271 | |
272 | dev_set_drvdata(dev, data: core); |
273 | |
274 | provider = devm_of_phy_provider_register(dev, sr_pcie_phy_xlate); |
275 | if (IS_ERR(ptr: provider)) { |
276 | dev_err(dev, "failed to register PHY provider\n" ); |
277 | return PTR_ERR(ptr: provider); |
278 | } |
279 | |
280 | dev_info(dev, "Stingray PCIe PHY driver initialized\n" ); |
281 | |
282 | return 0; |
283 | } |
284 | |
285 | static const struct of_device_id sr_pcie_phy_match_table[] = { |
286 | { .compatible = "brcm,sr-pcie-phy" }, |
287 | { } |
288 | }; |
289 | MODULE_DEVICE_TABLE(of, sr_pcie_phy_match_table); |
290 | |
291 | static struct platform_driver sr_pcie_phy_driver = { |
292 | .driver = { |
293 | .name = "sr-pcie-phy" , |
294 | .of_match_table = sr_pcie_phy_match_table, |
295 | }, |
296 | .probe = sr_pcie_phy_probe, |
297 | }; |
298 | module_platform_driver(sr_pcie_phy_driver); |
299 | |
300 | MODULE_AUTHOR("Ray Jui <ray.jui@broadcom.com>" ); |
301 | MODULE_DESCRIPTION("Broadcom Stingray PCIe PHY driver" ); |
302 | MODULE_LICENSE("GPL v2" ); |
303 | |