1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * UFS PHY driver data for FSD SoC |
4 | * |
5 | * Copyright (C) 2022 Samsung Electronics Co., Ltd. |
6 | * |
7 | */ |
8 | #include "phy-samsung-ufs.h" |
9 | |
10 | #define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724 |
11 | #define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 |
12 | #define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) |
13 | #define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e |
14 | |
15 | static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = { |
16 | PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), |
17 | PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), |
18 | PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), |
19 | PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY), |
20 | PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), |
21 | PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), |
22 | PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), |
23 | PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), |
24 | PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), |
25 | PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), |
26 | PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), |
27 | PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), |
28 | PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), |
29 | PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), |
30 | END_UFS_PHY_CFG |
31 | }; |
32 | |
33 | /* Calibration for HS mode series A/B */ |
34 | static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = { |
35 | END_UFS_PHY_CFG |
36 | }; |
37 | |
38 | /* Calibration for HS mode series A/B atfer PMC */ |
39 | static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = { |
40 | END_UFS_PHY_CFG |
41 | }; |
42 | |
43 | static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = { |
44 | [CFG_PRE_INIT] = fsd_pre_init_cfg, |
45 | [CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg, |
46 | [CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg, |
47 | }; |
48 | |
49 | static const char * const fsd_ufs_phy_clks[] = { |
50 | "ref_clk" , |
51 | }; |
52 | |
53 | const struct samsung_ufs_phy_drvdata fsd_ufs_phy = { |
54 | .cfgs = fsd_ufs_phy_cfgs, |
55 | .isol = { |
56 | .offset = FSD_EMBEDDED_COMBO_PHY_CTRL, |
57 | .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK, |
58 | .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN, |
59 | }, |
60 | .clk_list = fsd_ufs_phy_clks, |
61 | .num_clks = ARRAY_SIZE(fsd_ufs_phy_clks), |
62 | .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, |
63 | }; |
64 | |