1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller |
4 | * Copyright 2018, Socionext Inc. |
5 | * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
6 | */ |
7 | |
8 | #include <linux/bitops.h> |
9 | #include <linux/bitfield.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/iopoll.h> |
12 | #include <linux/mfd/syscon.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/phy/phy.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/regmap.h> |
18 | #include <linux/reset.h> |
19 | #include <linux/resource.h> |
20 | |
21 | /* PHY */ |
22 | #define PCL_PHY_CLKCTRL 0x0000 |
23 | #define PORT_SEL_MASK GENMASK(11, 9) |
24 | #define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1) |
25 | |
26 | #define PCL_PHY_TEST_I 0x2000 |
27 | #define TESTI_DAT_MASK GENMASK(13, 6) |
28 | #define TESTI_ADR_MASK GENMASK(5, 1) |
29 | #define TESTI_WR_EN BIT(0) |
30 | #define TESTIO_PHY_SHIFT 16 |
31 | |
32 | #define PCL_PHY_TEST_O 0x2004 |
33 | #define TESTO_DAT_MASK GENMASK(7, 0) |
34 | |
35 | #define PCL_PHY_RESET 0x200c |
36 | #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */ |
37 | #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */ |
38 | |
39 | /* SG */ |
40 | #define SG_USBPCIESEL 0x590 |
41 | #define SG_USBPCIESEL_PCIE BIT(0) |
42 | |
43 | /* SC */ |
44 | #define SC_US3SRCSEL 0x2244 |
45 | #define SC_US3SRCSEL_2LANE GENMASK(9, 8) |
46 | |
47 | #define PCL_PHY_R00 0 |
48 | #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ |
49 | #define PCL_PHY_R06 6 |
50 | #define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */ |
51 | #define RX_EQ_ADJ_VAL 0 |
52 | #define PCL_PHY_R26 26 |
53 | #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ |
54 | #define VCO_CTRL_INIT_VAL 5 |
55 | #define PCL_PHY_R28 28 |
56 | #define VCOPLL_CLMP GENMASK(3, 2) /* Tx VCOPLL clamp mode */ |
57 | #define VCOPLL_CLMP_VAL 0 |
58 | |
59 | struct uniphier_pciephy_priv { |
60 | void __iomem *base; |
61 | struct device *dev; |
62 | struct clk *clk, *clk_gio; |
63 | struct reset_control *rst, *rst_gio; |
64 | const struct uniphier_pciephy_soc_data *data; |
65 | }; |
66 | |
67 | struct uniphier_pciephy_soc_data { |
68 | bool is_legacy; |
69 | bool is_dual_phy; |
70 | void (*set_phymode)(struct regmap *regmap); |
71 | }; |
72 | |
73 | static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, |
74 | int id, u32 data) |
75 | { |
76 | if (id) |
77 | data <<= TESTIO_PHY_SHIFT; |
78 | |
79 | /* need to read TESTO twice after accessing TESTI */ |
80 | writel(val: data, addr: priv->base + PCL_PHY_TEST_I); |
81 | readl(addr: priv->base + PCL_PHY_TEST_O); |
82 | readl(addr: priv->base + PCL_PHY_TEST_O); |
83 | } |
84 | |
85 | static u32 uniphier_pciephy_testio_read(struct uniphier_pciephy_priv *priv, int id) |
86 | { |
87 | u32 val = readl(addr: priv->base + PCL_PHY_TEST_O); |
88 | |
89 | if (id) |
90 | val >>= TESTIO_PHY_SHIFT; |
91 | |
92 | return val & TESTO_DAT_MASK; |
93 | } |
94 | |
95 | static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv, |
96 | int id, u32 reg, u32 mask, u32 param) |
97 | { |
98 | u32 val; |
99 | |
100 | /* read previous data */ |
101 | val = FIELD_PREP(TESTI_DAT_MASK, 1); |
102 | val |= FIELD_PREP(TESTI_ADR_MASK, reg); |
103 | uniphier_pciephy_testio_write(priv, id, data: val); |
104 | val = uniphier_pciephy_testio_read(priv, id); |
105 | |
106 | /* update value */ |
107 | val &= ~mask; |
108 | val |= mask & param; |
109 | val = FIELD_PREP(TESTI_DAT_MASK, val); |
110 | val |= FIELD_PREP(TESTI_ADR_MASK, reg); |
111 | uniphier_pciephy_testio_write(priv, id, data: val); |
112 | uniphier_pciephy_testio_write(priv, id, data: val | TESTI_WR_EN); |
113 | uniphier_pciephy_testio_write(priv, id, data: val); |
114 | |
115 | /* read current data as dummy */ |
116 | val = FIELD_PREP(TESTI_DAT_MASK, 1); |
117 | val |= FIELD_PREP(TESTI_ADR_MASK, reg); |
118 | uniphier_pciephy_testio_write(priv, id, data: val); |
119 | uniphier_pciephy_testio_read(priv, id); |
120 | } |
121 | |
122 | static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv) |
123 | { |
124 | u32 val; |
125 | |
126 | val = readl(addr: priv->base + PCL_PHY_RESET); |
127 | val &= ~PCL_PHY_RESET_N; |
128 | val |= PCL_PHY_RESET_N_MNMODE; |
129 | writel(val, addr: priv->base + PCL_PHY_RESET); |
130 | } |
131 | |
132 | static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv) |
133 | { |
134 | u32 val; |
135 | |
136 | val = readl(addr: priv->base + PCL_PHY_RESET); |
137 | val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N; |
138 | writel(val, addr: priv->base + PCL_PHY_RESET); |
139 | } |
140 | |
141 | static int uniphier_pciephy_init(struct phy *phy) |
142 | { |
143 | struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); |
144 | u32 val; |
145 | int ret, id; |
146 | |
147 | ret = clk_prepare_enable(clk: priv->clk); |
148 | if (ret) |
149 | return ret; |
150 | |
151 | ret = clk_prepare_enable(clk: priv->clk_gio); |
152 | if (ret) |
153 | goto out_clk_disable; |
154 | |
155 | ret = reset_control_deassert(rstc: priv->rst); |
156 | if (ret) |
157 | goto out_clk_gio_disable; |
158 | |
159 | ret = reset_control_deassert(rstc: priv->rst_gio); |
160 | if (ret) |
161 | goto out_rst_assert; |
162 | |
163 | /* support only 1 port */ |
164 | val = readl(addr: priv->base + PCL_PHY_CLKCTRL); |
165 | val &= ~PORT_SEL_MASK; |
166 | val |= PORT_SEL_1; |
167 | writel(val, addr: priv->base + PCL_PHY_CLKCTRL); |
168 | |
169 | /* legacy controller doesn't have phy_reset and parameters */ |
170 | if (priv->data->is_legacy) |
171 | return 0; |
172 | |
173 | for (id = 0; id < (priv->data->is_dual_phy ? 2 : 1); id++) { |
174 | uniphier_pciephy_set_param(priv, id, PCL_PHY_R00, |
175 | RX_EQ_ADJ_EN, RX_EQ_ADJ_EN); |
176 | uniphier_pciephy_set_param(priv, id, PCL_PHY_R06, RX_EQ_ADJ, |
177 | FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); |
178 | uniphier_pciephy_set_param(priv, id, PCL_PHY_R26, VCO_CTRL, |
179 | FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); |
180 | uniphier_pciephy_set_param(priv, id, PCL_PHY_R28, VCOPLL_CLMP, |
181 | FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL)); |
182 | } |
183 | usleep_range(min: 1, max: 10); |
184 | |
185 | uniphier_pciephy_deassert(priv); |
186 | usleep_range(min: 1, max: 10); |
187 | |
188 | return 0; |
189 | |
190 | out_rst_assert: |
191 | reset_control_assert(rstc: priv->rst); |
192 | out_clk_gio_disable: |
193 | clk_disable_unprepare(clk: priv->clk_gio); |
194 | out_clk_disable: |
195 | clk_disable_unprepare(clk: priv->clk); |
196 | |
197 | return ret; |
198 | } |
199 | |
200 | static int uniphier_pciephy_exit(struct phy *phy) |
201 | { |
202 | struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); |
203 | |
204 | if (!priv->data->is_legacy) |
205 | uniphier_pciephy_assert(priv); |
206 | reset_control_assert(rstc: priv->rst_gio); |
207 | reset_control_assert(rstc: priv->rst); |
208 | clk_disable_unprepare(clk: priv->clk_gio); |
209 | clk_disable_unprepare(clk: priv->clk); |
210 | |
211 | return 0; |
212 | } |
213 | |
214 | static const struct phy_ops uniphier_pciephy_ops = { |
215 | .init = uniphier_pciephy_init, |
216 | .exit = uniphier_pciephy_exit, |
217 | .owner = THIS_MODULE, |
218 | }; |
219 | |
220 | static int uniphier_pciephy_probe(struct platform_device *pdev) |
221 | { |
222 | struct uniphier_pciephy_priv *priv; |
223 | struct phy_provider *phy_provider; |
224 | struct device *dev = &pdev->dev; |
225 | struct regmap *regmap; |
226 | struct phy *phy; |
227 | |
228 | priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL); |
229 | if (!priv) |
230 | return -ENOMEM; |
231 | |
232 | priv->data = of_device_get_match_data(dev); |
233 | if (WARN_ON(!priv->data)) |
234 | return -EINVAL; |
235 | |
236 | priv->dev = dev; |
237 | |
238 | priv->base = devm_platform_ioremap_resource(pdev, index: 0); |
239 | if (IS_ERR(ptr: priv->base)) |
240 | return PTR_ERR(ptr: priv->base); |
241 | |
242 | if (priv->data->is_legacy) { |
243 | priv->clk_gio = devm_clk_get(dev, id: "gio" ); |
244 | if (IS_ERR(ptr: priv->clk_gio)) |
245 | return PTR_ERR(ptr: priv->clk_gio); |
246 | |
247 | priv->rst_gio = |
248 | devm_reset_control_get_shared(dev, id: "gio" ); |
249 | if (IS_ERR(ptr: priv->rst_gio)) |
250 | return PTR_ERR(ptr: priv->rst_gio); |
251 | |
252 | priv->clk = devm_clk_get(dev, id: "link" ); |
253 | if (IS_ERR(ptr: priv->clk)) |
254 | return PTR_ERR(ptr: priv->clk); |
255 | |
256 | priv->rst = devm_reset_control_get_shared(dev, id: "link" ); |
257 | if (IS_ERR(ptr: priv->rst)) |
258 | return PTR_ERR(ptr: priv->rst); |
259 | } else { |
260 | priv->clk = devm_clk_get(dev, NULL); |
261 | if (IS_ERR(ptr: priv->clk)) |
262 | return PTR_ERR(ptr: priv->clk); |
263 | |
264 | priv->rst = devm_reset_control_get_shared(dev, NULL); |
265 | if (IS_ERR(ptr: priv->rst)) |
266 | return PTR_ERR(ptr: priv->rst); |
267 | } |
268 | |
269 | phy = devm_phy_create(dev, node: dev->of_node, ops: &uniphier_pciephy_ops); |
270 | if (IS_ERR(ptr: phy)) |
271 | return PTR_ERR(ptr: phy); |
272 | |
273 | regmap = syscon_regmap_lookup_by_phandle(np: dev->of_node, |
274 | property: "socionext,syscon" ); |
275 | if (!IS_ERR(ptr: regmap) && priv->data->set_phymode) |
276 | priv->data->set_phymode(regmap); |
277 | |
278 | phy_set_drvdata(phy, data: priv); |
279 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
280 | |
281 | return PTR_ERR_OR_ZERO(ptr: phy_provider); |
282 | } |
283 | |
284 | static void uniphier_pciephy_ld20_setmode(struct regmap *regmap) |
285 | { |
286 | regmap_update_bits(map: regmap, SG_USBPCIESEL, |
287 | SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); |
288 | } |
289 | |
290 | static void uniphier_pciephy_nx1_setmode(struct regmap *regmap) |
291 | { |
292 | regmap_update_bits(map: regmap, SC_US3SRCSEL, |
293 | SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE); |
294 | } |
295 | |
296 | static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { |
297 | .is_legacy = true, |
298 | }; |
299 | |
300 | static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { |
301 | .is_legacy = false, |
302 | .is_dual_phy = false, |
303 | .set_phymode = uniphier_pciephy_ld20_setmode, |
304 | }; |
305 | |
306 | static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { |
307 | .is_legacy = false, |
308 | .is_dual_phy = false, |
309 | }; |
310 | |
311 | static const struct uniphier_pciephy_soc_data uniphier_nx1_data = { |
312 | .is_legacy = false, |
313 | .is_dual_phy = true, |
314 | .set_phymode = uniphier_pciephy_nx1_setmode, |
315 | }; |
316 | |
317 | static const struct of_device_id uniphier_pciephy_match[] = { |
318 | { |
319 | .compatible = "socionext,uniphier-pro5-pcie-phy" , |
320 | .data = &uniphier_pro5_data, |
321 | }, |
322 | { |
323 | .compatible = "socionext,uniphier-ld20-pcie-phy" , |
324 | .data = &uniphier_ld20_data, |
325 | }, |
326 | { |
327 | .compatible = "socionext,uniphier-pxs3-pcie-phy" , |
328 | .data = &uniphier_pxs3_data, |
329 | }, |
330 | { |
331 | .compatible = "socionext,uniphier-nx1-pcie-phy" , |
332 | .data = &uniphier_nx1_data, |
333 | }, |
334 | { /* sentinel */ }, |
335 | }; |
336 | MODULE_DEVICE_TABLE(of, uniphier_pciephy_match); |
337 | |
338 | static struct platform_driver uniphier_pciephy_driver = { |
339 | .probe = uniphier_pciephy_probe, |
340 | .driver = { |
341 | .name = "uniphier-pcie-phy" , |
342 | .of_match_table = uniphier_pciephy_match, |
343 | }, |
344 | }; |
345 | module_platform_driver(uniphier_pciephy_driver); |
346 | |
347 | MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>" ); |
348 | MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller" ); |
349 | MODULE_LICENSE("GPL v2" ); |
350 | |