1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Copyright (C) 2016 IBM Corp.
4	*/
5	#include <linux/bitops.h>
6	#include <linux/init.h>
7	#include <linux/io.h>
8	#include <linux/kernel.h>
9	#include <linux/mutex.h>
10	#include <linux/of.h>
11	#include <linux/platform_device.h>
12	#include <linux/pinctrl/pinctrl.h>
13	#include <linux/pinctrl/pinmux.h>
14	#include <linux/pinctrl/pinconf.h>
15	#include <linux/pinctrl/pinconf-generic.h>
16	#include <linux/string.h>
17	#include <linux/types.h>
18
19	#include "../core.h"
20	#include "../pinctrl-utils.h"
21	#include "pinmux-aspeed.h"
22	#include "pinctrl-aspeed.h"
23
24	/* Wrap some of the common macros for clarity */
25	#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
26	SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
27
28	#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
29	#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
30
31	/*
32	* The "Multi-function Pins Mapping and Control" table in the SoC datasheet
33	* references registers by the device/offset mnemonic. The register macros
34	* below are named the same way to ease transcription and verification (as
35	* opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
36	* reference registers beyond those dedicated to pinmux, such as the system
37	* reset control and MAC clock configuration registers.
38	*/
39	#define SCU2C 0x2C /* Misc. Control Register */
40	#define SCU3C 0x3C /* System Reset Control/Status Register */
41	#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
42	#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
43	#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
44	#define SCU80 0x80 /* Multi-function Pin Control #1 */
45	#define SCU84 0x84 /* Multi-function Pin Control #2 */
46	#define SCU88 0x88 /* Multi-function Pin Control #3 */
47	#define SCU8C 0x8C /* Multi-function Pin Control #4 */
48	#define SCU90 0x90 /* Multi-function Pin Control #5 */
49	#define SCU94 0x94 /* Multi-function Pin Control #6 */
50	#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
51	#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
52	#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
53	#define SCUAC 0xAC /* Multi-function Pin Control #10 */
54	#define HW_STRAP2 0xD0 /* Strapping */
55
56	/*
57	* Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK,
58	* TIMER3 etc.
59	*
60	* Pins are defined in GPIO bank order:
61	*
62	* GPIOA0: 0
63	* ...
64	* GPIOA7: 7
65	* GPIOB0: 8
66	* ...
67	* GPIOZ7: 207
68	* GPIOAA0: 208
69	* ...
70	* GPIOAB3: 219
71	*
72	* Not all pins have their signals defined (yet).
73	*/
74
75	#define D6 0
76	SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
77
78	#define B5 1
79	SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
80
81	#define A4 2
82	SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
83
84	#define E6 3
85	SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
86
87	#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
88
89	#define C5 4
90	SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC);
91	SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
92	PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5);
93
94	FUNC_GROUP_DECL(TIMER5, C5);
95
96	#define B4 5
97	SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC);
98	SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5));
99	PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6);
100
101	FUNC_GROUP_DECL(TIMER6, B4);
102	FUNC_GROUP_DECL(I2C9, C5, B4);
103
104	#define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
105
106	#define A3 6
107	SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC);
108	SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
109	PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7);
110
111	FUNC_GROUP_DECL(TIMER7, A3);
112
113	#define D5 7
114	SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC);
115	SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
116	PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8);
117
118	FUNC_GROUP_DECL(TIMER8, D5);
119	FUNC_GROUP_DECL(MDIO2, A3, D5);
120
121	#define J21 8
122	SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8));
123
124	#define J20 9
125	SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9));
126
127	#define H18 10
128	SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10));
129
130	#define F18 11
131	SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11));
132
133	#define E19 12
134	SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
135	SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
136	SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS);
137	PIN_DECL_1(E19, GPIOB4, LPCRST);
138
139	FUNC_GROUP_DECL(LPCRST, E19);
140
141	#define H19 13
142	#define H19_DESC SIG_DESC_SET(SCU80, 13)
143	SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC);
144	SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC);
145	PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI);
146
147	FUNC_GROUP_DECL(LPCPD, H19);
148	FUNC_GROUP_DECL(LPCSMI, H19);
149
150	#define H20 14
151	SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
152
153	#define E18 15
154	SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST,
155	SIG_DESC_SET(SCU80, 15),
156	SIG_DESC_BIT(SCU90, 31, 0),
157	SIG_DESC_SET(SCU3C, 3));
158	SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1,
159	SIG_DESC_SET(SCU80, 15),
160	SIG_DESC_SET(SCU90, 31));
161	PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1);
162
163	FUNC_GROUP_DECL(EXTRST, E18);
164	FUNC_GROUP_DECL(SPICS1, E18);
165
166	#define SD1_DESC SIG_DESC_SET(SCU90, 0)
167	#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
168
169	#define C4 16
170	SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC);
171	SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC);
172	PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10);
173
174	#define B3 17
175	SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC);
176	SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC);
177	PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10);
178
179	FUNC_GROUP_DECL(I2C10, C4, B3);
180
181	#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
182
183	#define A2 18
184	SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC);
185	SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC);
186	PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11);
187
188	#define E5 19
189	SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC);
190	SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC);
191	PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11);
192
193	FUNC_GROUP_DECL(I2C11, A2, E5);
194
195	#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
196
197	#define D4 20
198	SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC);
199	SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC);
200	PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12);
201
202	#define C3 21
203	SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC);
204	SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC);
205	PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12);
206
207	FUNC_GROUP_DECL(I2C12, D4, C3);
208
209	#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
210
211	#define B2 22
212	SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC);
213	SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC);
214	PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13);
215
216	#define A1 23
217	SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC);
218	SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC);
219	PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13);
220
221	FUNC_GROUP_DECL(I2C13, B2, A1);
222	FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
223
224	#define SD2_DESC SIG_DESC_SET(SCU90, 1)
225	#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
226	#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
227
228	#define A18 24
229	SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC);
230	SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
231	SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
232	SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID);
233	PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN);
234
235	#define D16 25
236	SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC);
237	SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
238	SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
239	SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID);
240	PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT);
241
242	FUNC_GROUP_DECL(GPID0, A18, D16);
243
244	#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
245
246	#define B17 26
247	SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC);
248	SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
249	SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
250	SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID);
251	PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN);
252
253	#define A17 27
254	SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC);
255	SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
256	SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
257	SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID);
258	PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT);
259
260	FUNC_GROUP_DECL(GPID2, B17, A17);
261
262	#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
263
264	#define C16 28
265	SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC);
266	SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
267	SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
268	SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID);
269	PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN);
270
271	#define B16 29
272	SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC);
273	SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
274	SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
275	SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID);
276	PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT);
277
278	FUNC_GROUP_DECL(GPID4, C16, B16);
279
280	#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
281
282	#define A16 30
283	SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC);
284	SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
285	SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
286	SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID);
287	PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN);
288
289	#define E15 31
290	SIG_EXPR_LIST_DECL_SINGLE(E15, SD2WP, SD2, SD2_DESC);
291	SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
292	SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
293	SIG_EXPR_LIST_DECL_DUAL(E15, GPID6OUT, GPID6, GPID);
294	PIN_DECL_2(E15, GPIOD7, SD2WP, GPID6OUT);
295
296	FUNC_GROUP_DECL(GPID6, A16, E15);
297	FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15);
298	FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15);
299
300	#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
301	#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
302	#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
303	#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
304	#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
305
306	#define D15 32
307	SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
308	SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
309	SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
310	SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE);
311	PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN);
312
313	FUNC_GROUP_DECL(NCTS3, D15);
314
315	#define C15 33
316	SIG_EXPR_LIST_DECL_SINGLE(C15, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
317	SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
318	SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
319	SIG_EXPR_LIST_DECL_DUAL(C15, GPIE0OUT, GPIE0, GPIE);
320	PIN_DECL_2(C15, GPIOE1, NDCD3, GPIE0OUT);
321
322	FUNC_GROUP_DECL(NDCD3, C15);
323	FUNC_GROUP_DECL(GPIE0, D15, C15);
324
325	#define B15 34
326	SIG_EXPR_LIST_DECL_SINGLE(B15, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
327	SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
328	SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
329	SIG_EXPR_LIST_DECL_DUAL(B15, GPIE2IN, GPIE2, GPIE);
330	PIN_DECL_2(B15, GPIOE2, NDSR3, GPIE2IN);
331
332	FUNC_GROUP_DECL(NDSR3, B15);
333
334	#define A15 35
335	SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
336	SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
337	SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
338	SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE);
339	PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT);
340
341	FUNC_GROUP_DECL(NRI3, A15);
342	FUNC_GROUP_DECL(GPIE2, B15, A15);
343
344	#define E14 36
345	SIG_EXPR_LIST_DECL_SINGLE(E14, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
346	SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
347	SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
348	SIG_EXPR_LIST_DECL_DUAL(E14, GPIE4IN, GPIE4, GPIE);
349	PIN_DECL_2(E14, GPIOE4, NDTR3, GPIE4IN);
350
351	FUNC_GROUP_DECL(NDTR3, E14);
352
353	#define D14 37
354	SIG_EXPR_LIST_DECL_SINGLE(D14, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
355	SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
356	SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
357	SIG_EXPR_LIST_DECL_DUAL(D14, GPIE4OUT, GPIE4, GPIE);
358	PIN_DECL_2(D14, GPIOE5, NRTS3, GPIE4OUT);
359
360	FUNC_GROUP_DECL(NRTS3, D14);
361	FUNC_GROUP_DECL(GPIE4, E14, D14);
362
363	#define C14 38
364	SIG_EXPR_LIST_DECL_SINGLE(C14, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
365	SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
366	SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
367	SIG_EXPR_LIST_DECL_DUAL(C14, GPIE6IN, GPIE6, GPIE);
368	PIN_DECL_2(C14, GPIOE6, TXD3, GPIE6IN);
369
370	FUNC_GROUP_DECL(TXD3, C14);
371
372	#define B14 39
373	SIG_EXPR_LIST_DECL_SINGLE(B14, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
374	SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
375	SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
376	SIG_EXPR_LIST_DECL_DUAL(B14, GPIE6OUT, GPIE6, GPIE);
377	PIN_DECL_2(B14, GPIOE7, RXD3, GPIE6OUT);
378
379	FUNC_GROUP_DECL(RXD3, B14);
380	FUNC_GROUP_DECL(GPIE6, C14, B14);
381
382	#define D18 40
383	SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24));
384
385	#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0)
386
387	#define B19 41
388	SIG_EXPR_LIST_DECL_SINGLE(B19, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
389	SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12));
390	SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, ACPI_DESC);
391	SIG_EXPR_LIST_DECL_DUAL(B19, SIOPBI, SIOPBI, ACPI);
392	PIN_DECL_2(B19, GPIOF1, NDCD4, SIOPBI);
393	FUNC_GROUP_DECL(NDCD4, B19);
394	FUNC_GROUP_DECL(SIOPBI, B19);
395
396	#define A20 42
397	SIG_EXPR_LIST_DECL_SINGLE(A20, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
398	SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12));
399	SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, ACPI_DESC);
400	SIG_EXPR_LIST_DECL_DUAL(A20, SIOPWRGD, SIOPWRGD, ACPI);
401	PIN_DECL_2(A20, GPIOF2, NDSR4, SIOPWRGD);
402	FUNC_GROUP_DECL(NDSR4, A20);
403	FUNC_GROUP_DECL(SIOPWRGD, A20);
404
405	#define D17 43
406	SIG_EXPR_LIST_DECL_SINGLE(D17, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
407	SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14));
408	SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, ACPI_DESC);
409	SIG_EXPR_LIST_DECL_DUAL(D17, SIOPBO, SIOPBO, ACPI);
410	PIN_DECL_2(D17, GPIOF3, NRI4, SIOPBO);
411	FUNC_GROUP_DECL(NRI4, D17);
412	FUNC_GROUP_DECL(SIOPBO, D17);
413
414	#define B18 44
415	SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28));
416
417	#define A19 45
418	SIG_EXPR_LIST_DECL_SINGLE(A19, NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29));
419	SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15));
420	SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, ACPI_DESC);
421	SIG_EXPR_LIST_DECL_DUAL(A19, SIOSCI, SIOSCI, ACPI);
422	PIN_DECL_2(A19, GPIOF5, NDTS4, SIOSCI);
423	FUNC_GROUP_DECL(NDTS4, A19);
424	FUNC_GROUP_DECL(SIOSCI, A19);
425
426	#define E16 46
427	SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
428
429	#define C17 47
430	SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31));
431
432	#define A14 48
433	SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0));
434
435	#define E13 49
436	SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1));
437
438	#define D13 50
439	SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2));
440
441	#define C13 51
442	SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3));
443
444	#define B13 52
445	SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1));
446	SIG_EXPR_LIST_DECL_SINGLE(B13, WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4));
447	PIN_DECL_2(B13, GPIOG4, OSCCLK, WDTRST1);
448
449	FUNC_GROUP_DECL(OSCCLK, B13);
450	FUNC_GROUP_DECL(WDTRST1, B13);
451
452	#define Y21 53
453	SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
454	SIG_EXPR_LIST_DECL_SINGLE(Y21, WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5));
455	PIN_DECL_2(Y21, GPIOG5, USBCKI, WDTRST2);
456
457	FUNC_GROUP_DECL(USBCKI, Y21);
458	FUNC_GROUP_DECL(WDTRST2, Y21);
459
460	#define AA22 54
461	SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6));
462
463	#define U18 55
464	SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7));
465
466	#define UART6_DESC SIG_DESC_SET(SCU90, 7)
467	#define ROM16_DESC SIG_DESC_SET(SCU90, 6)
468	#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
469	#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
470
471	#define A8 56
472	SIG_EXPR_DECL_SINGLE(ROMD8, ROM16, ROM16_DESC);
473	SIG_EXPR_DECL_SINGLE(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
474	SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S);
475	SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC);
476	PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
477
478	#define C7 57
479	SIG_EXPR_DECL_SINGLE(ROMD9, ROM16, ROM16_DESC);
480	SIG_EXPR_DECL_SINGLE(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
481	SIG_EXPR_LIST_DECL_DUAL(C7, ROMD9, ROM16, ROM16S);
482	SIG_EXPR_LIST_DECL_SINGLE(C7, NDCD6, NDCD6, UART6_DESC);
483	PIN_DECL_2(C7, GPIOH1, ROMD9, NDCD6);
484
485	#define B7 58
486	SIG_EXPR_DECL_SINGLE(ROMD10, ROM16, ROM16_DESC);
487	SIG_EXPR_DECL_SINGLE(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
488	SIG_EXPR_LIST_DECL_DUAL(B7, ROMD10, ROM16, ROM16S);
489	SIG_EXPR_LIST_DECL_SINGLE(B7, NDSR6, NDSR6, UART6_DESC);
490	PIN_DECL_2(B7, GPIOH2, ROMD10, NDSR6);
491
492	#define A7 59
493	SIG_EXPR_DECL_SINGLE(ROMD11, ROM16, ROM16_DESC);
494	SIG_EXPR_DECL_SINGLE(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
495	SIG_EXPR_LIST_DECL_DUAL(A7, ROMD11, ROM16, ROM16S);
496	SIG_EXPR_LIST_DECL_SINGLE(A7, NRI6, NRI6, UART6_DESC);
497	PIN_DECL_2(A7, GPIOH3, ROMD11, NRI6);
498
499	#define D7 60
500	SIG_EXPR_DECL_SINGLE(ROMD12, ROM16, ROM16_DESC);
501	SIG_EXPR_DECL_SINGLE(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
502	SIG_EXPR_LIST_DECL_DUAL(D7, ROMD12, ROM16, ROM16S);
503	SIG_EXPR_LIST_DECL_SINGLE(D7, NDTR6, NDTR6, UART6_DESC);
504	PIN_DECL_2(D7, GPIOH4, ROMD12, NDTR6);
505
506	#define B6 61
507	SIG_EXPR_DECL_SINGLE(ROMD13, ROM16, ROM16_DESC);
508	SIG_EXPR_DECL_SINGLE(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
509	SIG_EXPR_LIST_DECL_DUAL(B6, ROMD13, ROM16, ROM16S);
510	SIG_EXPR_LIST_DECL_SINGLE(B6, NRTS6, NRTS6, UART6_DESC);
511	PIN_DECL_2(B6, GPIOH5, ROMD13, NRTS6);
512
513	#define A6 62
514	SIG_EXPR_DECL_SINGLE(ROMD14, ROM16, ROM16_DESC);
515	SIG_EXPR_DECL_SINGLE(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
516	SIG_EXPR_LIST_DECL_DUAL(A6, ROMD14, ROM16, ROM16S);
517	SIG_EXPR_LIST_DECL_SINGLE(A6, TXD6, TXD6, UART6_DESC);
518	PIN_DECL_2(A6, GPIOH6, ROMD14, TXD6);
519
520	#define E7 63
521	SIG_EXPR_DECL_SINGLE(ROMD15, ROM16, ROM16_DESC);
522	SIG_EXPR_DECL_SINGLE(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
523	SIG_EXPR_LIST_DECL_DUAL(E7, ROMD15, ROM16, ROM16S);
524	SIG_EXPR_LIST_DECL_SINGLE(E7, RXD6, RXD6, UART6_DESC);
525	PIN_DECL_2(E7, GPIOH7, ROMD15, RXD6);
526
527	FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
528
529	#define SPI1_DESC \
530	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
531	#define SPI1DEBUG_DESC \
532	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
533	#define SPI1PASSTHRU_DESC \
534	{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
535
536	#define C22 64
537	SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC);
538	SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
539	SIG_EXPR_LIST_DECL_DUAL(C22, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
540	PIN_DECL_1(C22, GPIOI0, SYSCS);
541
542	#define G18 65
543	SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC);
544	SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
545	SIG_EXPR_LIST_DECL_DUAL(G18, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
546	PIN_DECL_1(G18, GPIOI1, SYSCK);
547
548	#define D19 66
549	SIG_EXPR_DECL_SINGLE(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC);
550	SIG_EXPR_DECL_SINGLE(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
551	SIG_EXPR_LIST_DECL_DUAL(D19, SYSDO, SPI1DEBUG, SPI1PASSTHRU);
552	PIN_DECL_1(D19, GPIOI2, SYSDO);
553
554	#define C20 67
555	SIG_EXPR_DECL_SINGLE(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC);
556	SIG_EXPR_DECL_SINGLE(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
557	SIG_EXPR_LIST_DECL_DUAL(C20, SYSDI, SPI1DEBUG, SPI1PASSTHRU);
558	PIN_DECL_1(C20, GPIOI3, SYSDI);
559
560	#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
561
562	#define B22 68
563	SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, SPI1_DESC);
564	SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC);
565	SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
566	SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
567	SIG_EXPR_PTR(SPI1CS0, SPI1),
568	SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
569	SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
570	SIG_EXPR_LIST_ALIAS(B22, SPI1CS0, SPI1);
571	SIG_EXPR_LIST_DECL_SINGLE(B22, VBCS, VGABIOS_ROM, VB_DESC);
572	PIN_DECL_2(B22, GPIOI4, SPI1CS0, VBCS);
573
574	#define G19 69
575	SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, SPI1_DESC);
576	SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC);
577	SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
578	SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
579	SIG_EXPR_PTR(SPI1CK, SPI1),
580	SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
581	SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
582	SIG_EXPR_LIST_ALIAS(G19, SPI1CK, SPI1);
583	SIG_EXPR_LIST_DECL_SINGLE(G19, VBCK, VGABIOS_ROM, VB_DESC);
584	PIN_DECL_2(G19, GPIOI5, SPI1CK, VBCK);
585
586	#define C18 70
587	SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1, SPI1_DESC);
588	SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC);
589	SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
590	SIG_EXPR_LIST_DECL(SPI1DO, SPI1,
591	SIG_EXPR_PTR(SPI1DO, SPI1),
592	SIG_EXPR_PTR(SPI1DO, SPI1DEBUG),
593	SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU));
594	SIG_EXPR_LIST_ALIAS(C18, SPI1DO, SPI1);
595	SIG_EXPR_LIST_DECL_SINGLE(C18, VBDO, VGABIOS_ROM, VB_DESC);
596	PIN_DECL_2(C18, GPIOI6, SPI1DO, VBDO);
597
598	#define E20 71
599	SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1, SPI1_DESC);
600	SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC);
601	SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
602	SIG_EXPR_LIST_DECL(SPI1DI, SPI1,
603	SIG_EXPR_PTR(SPI1DI, SPI1),
604	SIG_EXPR_PTR(SPI1DI, SPI1DEBUG),
605	SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU));
606	SIG_EXPR_LIST_ALIAS(E20, SPI1DI, SPI1);
607	SIG_EXPR_LIST_DECL_SINGLE(E20, VBDI, VGABIOS_ROM, VB_DESC);
608	PIN_DECL_2(E20, GPIOI7, SPI1DI, VBDI);
609
610	FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20);
611	FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20);
612	FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20);
613	FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20);
614
615	#define J5 72
616	SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8));
617
618	#define J4 73
619	SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9));
620
621	#define K5 74
622	SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10));
623
624	#define J3 75
625	SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
626
627	#define T4 76
628	SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12));
629
630	#define U2 77
631	SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13));
632
633	#define T2 78
634	SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14));
635
636	#define T1 79
637	SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15));
638
639	#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
640
641	#define E3 80
642	SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC);
643	PIN_DECL_1(E3, GPIOK0, SCL5);
644
645	#define D2 81
646	SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC);
647	PIN_DECL_1(D2, GPIOK1, SDA5);
648
649	FUNC_GROUP_DECL(I2C5, E3, D2);
650
651	#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
652
653	#define C1 82
654	SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC);
655	PIN_DECL_1(C1, GPIOK2, SCL6);
656
657	#define F4 83
658	SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC);
659	PIN_DECL_1(F4, GPIOK3, SDA6);
660
661	FUNC_GROUP_DECL(I2C6, C1, F4);
662
663	#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
664
665	#define E2 84
666	SIG_EXPR_LIST_DECL_SINGLE(E2, SCL7, I2C7, I2C7_DESC);
667	PIN_DECL_1(E2, GPIOK4, SCL7);
668
669	#define D1 85
670	SIG_EXPR_LIST_DECL_SINGLE(D1, SDA7, I2C7, I2C7_DESC);
671	PIN_DECL_1(D1, GPIOK5, SDA7);
672
673	FUNC_GROUP_DECL(I2C7, E2, D1);
674
675	#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
676
677	#define G5 86
678	SIG_EXPR_LIST_DECL_SINGLE(G5, SCL8, I2C8, I2C8_DESC);
679	PIN_DECL_1(G5, GPIOK6, SCL8);
680
681	#define F3 87
682	SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC);
683	PIN_DECL_1(F3, GPIOK7, SDA8);
684
685	FUNC_GROUP_DECL(I2C8, G5, F3);
686
687	#define U1 88
688	SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
689
690	#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
691	#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
692	#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
693
694	#define T5 89
695	#define T5_DESC SIG_DESC_SET(SCU84, 17)
696	SIG_EXPR_DECL_SINGLE(VPIDE, VPI18, VPI18_DESC, T5_DESC);
697	SIG_EXPR_DECL_SINGLE(VPIDE, VPI24, VPI24_DESC, T5_DESC);
698	SIG_EXPR_DECL_SINGLE(VPIDE, VPI30, VPI30_DESC, T5_DESC);
699	SIG_EXPR_LIST_DECL(VPIDE, VPI,
700	SIG_EXPR_PTR(VPIDE, VPI18),
701	SIG_EXPR_PTR(VPIDE, VPI24),
702	SIG_EXPR_PTR(VPIDE, VPI30));
703	SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI);
704	SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC);
705	PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1);
706	FUNC_GROUP_DECL(NDCD1, T5);
707
708	#define U3 90
709	#define U3_DESC SIG_DESC_SET(SCU84, 18)
710	SIG_EXPR_DECL_SINGLE(VPIODD, VPI18, VPI18_DESC, U3_DESC);
711	SIG_EXPR_DECL_SINGLE(VPIODD, VPI24, VPI24_DESC, U3_DESC);
712	SIG_EXPR_DECL_SINGLE(VPIODD, VPI30, VPI30_DESC, U3_DESC);
713	SIG_EXPR_LIST_DECL(VPIODD, VPI,
714	SIG_EXPR_PTR(VPIODD, VPI18),
715	SIG_EXPR_PTR(VPIODD, VPI24),
716	SIG_EXPR_PTR(VPIODD, VPI30));
717	SIG_EXPR_LIST_ALIAS(U3, VPIODD, VPI);
718	SIG_EXPR_LIST_DECL_SINGLE(U3, NDSR1, NDSR1, U3_DESC);
719	PIN_DECL_2(U3, GPIOL2, VPIODD, NDSR1);
720	FUNC_GROUP_DECL(NDSR1, U3);
721
722	#define V1 91
723	#define V1_DESC SIG_DESC_SET(SCU84, 19)
724	SIG_EXPR_DECL_SINGLE(VPIHS, VPI18, VPI18_DESC, V1_DESC);
725	SIG_EXPR_DECL_SINGLE(VPIHS, VPI24, VPI24_DESC, V1_DESC);
726	SIG_EXPR_DECL_SINGLE(VPIHS, VPI30, VPI30_DESC, V1_DESC);
727	SIG_EXPR_LIST_DECL(VPIHS, VPI,
728	SIG_EXPR_PTR(VPIHS, VPI18),
729	SIG_EXPR_PTR(VPIHS, VPI24),
730	SIG_EXPR_PTR(VPIHS, VPI30));
731	SIG_EXPR_LIST_ALIAS(V1, VPIHS, VPI);
732	SIG_EXPR_LIST_DECL_SINGLE(V1, NRI1, NRI1, V1_DESC);
733	PIN_DECL_2(V1, GPIOL3, VPIHS, NRI1);
734	FUNC_GROUP_DECL(NRI1, V1);
735
736	#define U4 92
737	#define U4_DESC SIG_DESC_SET(SCU84, 20)
738	SIG_EXPR_DECL_SINGLE(VPIVS, VPI18, VPI18_DESC, U4_DESC);
739	SIG_EXPR_DECL_SINGLE(VPIVS, VPI24, VPI24_DESC, U4_DESC);
740	SIG_EXPR_DECL_SINGLE(VPIVS, VPI30, VPI30_DESC, U4_DESC);
741	SIG_EXPR_LIST_DECL(VPIVS, VPI,
742	SIG_EXPR_PTR(VPIVS, VPI18),
743	SIG_EXPR_PTR(VPIVS, VPI24),
744	SIG_EXPR_PTR(VPIVS, VPI30));
745	SIG_EXPR_LIST_ALIAS(U4, VPIVS, VPI);
746	SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC);
747	PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1);
748	FUNC_GROUP_DECL(NDTR1, U4);
749
750	#define V2 93
751	#define V2_DESC SIG_DESC_SET(SCU84, 21)
752	SIG_EXPR_DECL_SINGLE(VPICLK, VPI18, VPI18_DESC, V2_DESC);
753	SIG_EXPR_DECL_SINGLE(VPICLK, VPI24, VPI24_DESC, V2_DESC);
754	SIG_EXPR_DECL_SINGLE(VPICLK, VPI30, VPI30_DESC, V2_DESC);
755	SIG_EXPR_LIST_DECL(VPICLK, VPI,
756	SIG_EXPR_PTR(VPICLK, VPI18),
757	SIG_EXPR_PTR(VPICLK, VPI24),
758	SIG_EXPR_PTR(VPICLK, VPI30));
759	SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI);
760	SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC);
761	PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1);
762	FUNC_GROUP_DECL(NRTS1, V2);
763
764	#define W1 94
765	#define W1_DESC SIG_DESC_SET(SCU84, 22)
766	SIG_EXPR_LIST_DECL_SINGLE(W1, VPIB0, VPI30, VPI30_DESC, W1_DESC);
767	SIG_EXPR_LIST_DECL_SINGLE(W1, TXD1, TXD1, W1_DESC);
768	PIN_DECL_2(W1, GPIOL6, VPIB0, TXD1);
769	FUNC_GROUP_DECL(TXD1, W1);
770
771	#define U5 95
772	#define U5_DESC SIG_DESC_SET(SCU84, 23)
773	SIG_EXPR_LIST_DECL_SINGLE(U5, VPIB1, VPI30, VPI30_DESC, U5_DESC);
774	SIG_EXPR_LIST_DECL_SINGLE(U5, RXD1, RXD1, U5_DESC);
775	PIN_DECL_2(U5, GPIOL7, VPIB1, RXD1);
776	FUNC_GROUP_DECL(RXD1, U5);
777
778	#define V3 96
779	#define V3_DESC SIG_DESC_SET(SCU84, 24)
780	SIG_EXPR_DECL_SINGLE(VPIOB2, VPI18, VPI18_DESC, V3_DESC);
781	SIG_EXPR_DECL_SINGLE(VPIOB2, VPI24, VPI24_DESC, V3_DESC);
782	SIG_EXPR_DECL_SINGLE(VPIOB2, VPI30, VPI30_DESC, V3_DESC);
783	SIG_EXPR_LIST_DECL(VPIOB2, VPI,
784	SIG_EXPR_PTR(VPIOB2, VPI18),
785	SIG_EXPR_PTR(VPIOB2, VPI24),
786	SIG_EXPR_PTR(VPIOB2, VPI30));
787	SIG_EXPR_LIST_ALIAS(V3, VPIOB2, VPI);
788	SIG_EXPR_LIST_DECL_SINGLE(V3, NCTS2, NCTS2, V3_DESC);
789	PIN_DECL_2(V3, GPIOM0, VPIOB2, NCTS2);
790	FUNC_GROUP_DECL(NCTS2, V3);
791
792	#define W2 97
793	#define W2_DESC SIG_DESC_SET(SCU84, 25)
794	SIG_EXPR_DECL_SINGLE(VPIOB3, VPI18, VPI18_DESC, W2_DESC);
795	SIG_EXPR_DECL_SINGLE(VPIOB3, VPI24, VPI24_DESC, W2_DESC);
796	SIG_EXPR_DECL_SINGLE(VPIOB3, VPI30, VPI30_DESC, W2_DESC);
797	SIG_EXPR_LIST_DECL(VPIOB3, VPI,
798	SIG_EXPR_PTR(VPIOB3, VPI18),
799	SIG_EXPR_PTR(VPIOB3, VPI24),
800	SIG_EXPR_PTR(VPIOB3, VPI30));
801	SIG_EXPR_LIST_ALIAS(W2, VPIOB3, VPI);
802	SIG_EXPR_LIST_DECL_SINGLE(W2, NDCD2, NDCD2, W2_DESC);
803	PIN_DECL_2(W2, GPIOM1, VPIOB3, NDCD2);
804	FUNC_GROUP_DECL(NDCD2, W2);
805
806	#define Y1 98
807	#define Y1_DESC SIG_DESC_SET(SCU84, 26)
808	SIG_EXPR_DECL_SINGLE(VPIOB4, VPI18, VPI18_DESC, Y1_DESC);
809	SIG_EXPR_DECL_SINGLE(VPIOB4, VPI24, VPI24_DESC, Y1_DESC);
810	SIG_EXPR_DECL_SINGLE(VPIOB4, VPI30, VPI30_DESC, Y1_DESC);
811	SIG_EXPR_LIST_DECL(VPIOB4, VPI,
812	SIG_EXPR_PTR(VPIOB4, VPI18),
813	SIG_EXPR_PTR(VPIOB4, VPI24),
814	SIG_EXPR_PTR(VPIOB4, VPI30));
815	SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI);
816	SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC);
817	PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2);
818	FUNC_GROUP_DECL(NDSR2, Y1);
819
820	#define V4 99
821	#define V4_DESC SIG_DESC_SET(SCU84, 27)
822	SIG_EXPR_DECL_SINGLE(VPIOB5, VPI18, VPI18_DESC, V4_DESC);
823	SIG_EXPR_DECL_SINGLE(VPIOB5, VPI24, VPI24_DESC, V4_DESC);
824	SIG_EXPR_DECL_SINGLE(VPIOB5, VPI30, VPI30_DESC, V4_DESC);
825	SIG_EXPR_LIST_DECL(VPIOB5, VPI,
826	SIG_EXPR_PTR(VPIOB5, VPI18),
827	SIG_EXPR_PTR(VPIOB5, VPI24),
828	SIG_EXPR_PTR(VPIOB5, VPI30));
829	SIG_EXPR_LIST_ALIAS(V4, VPIOB5, VPI);
830	SIG_EXPR_LIST_DECL_SINGLE(V4, NRI2, NRI2, V4_DESC);
831	PIN_DECL_2(V4, GPIOM3, VPIOB5, NRI2);
832	FUNC_GROUP_DECL(NRI2, V4);
833
834	#define W3 100
835	#define W3_DESC SIG_DESC_SET(SCU84, 28)
836	SIG_EXPR_DECL_SINGLE(VPIOB6, VPI18, VPI18_DESC, W3_DESC);
837	SIG_EXPR_DECL_SINGLE(VPIOB6, VPI24, VPI24_DESC, W3_DESC);
838	SIG_EXPR_DECL_SINGLE(VPIOB6, VPI30, VPI30_DESC, W3_DESC);
839	SIG_EXPR_LIST_DECL(VPIOB6, VPI,
840	SIG_EXPR_PTR(VPIOB6, VPI18),
841	SIG_EXPR_PTR(VPIOB6, VPI24),
842	SIG_EXPR_PTR(VPIOB6, VPI30));
843	SIG_EXPR_LIST_ALIAS(W3, VPIOB6, VPI);
844	SIG_EXPR_LIST_DECL_SINGLE(W3, NDTR2, NDTR2, W3_DESC);
845	PIN_DECL_2(W3, GPIOM4, VPIOB6, NDTR2);
846	FUNC_GROUP_DECL(NDTR2, W3);
847
848	#define Y2 101
849	#define Y2_DESC SIG_DESC_SET(SCU84, 29)
850	SIG_EXPR_DECL_SINGLE(VPIOB7, VPI18, VPI18_DESC, Y2_DESC);
851	SIG_EXPR_DECL_SINGLE(VPIOB7, VPI24, VPI24_DESC, Y2_DESC);
852	SIG_EXPR_DECL_SINGLE(VPIOB7, VPI30, VPI30_DESC, Y2_DESC);
853	SIG_EXPR_LIST_DECL(VPIOB7, VPI,
854	SIG_EXPR_PTR(VPIOB7, VPI18),
855	SIG_EXPR_PTR(VPIOB7, VPI24),
856	SIG_EXPR_PTR(VPIOB7, VPI30));
857	SIG_EXPR_LIST_ALIAS(Y2, VPIOB7, VPI);
858	SIG_EXPR_LIST_DECL_SINGLE(Y2, NRTS2, NRTS2, Y2_DESC);
859	PIN_DECL_2(Y2, GPIOM5, VPIOB7, NRTS2);
860	FUNC_GROUP_DECL(NRTS2, Y2);
861
862	#define AA1 102
863	#define AA1_DESC SIG_DESC_SET(SCU84, 30)
864	SIG_EXPR_DECL_SINGLE(VPIOB8, VPI18, VPI18_DESC, AA1_DESC);
865	SIG_EXPR_DECL_SINGLE(VPIOB8, VPI24, VPI24_DESC, AA1_DESC);
866	SIG_EXPR_DECL_SINGLE(VPIOB8, VPI30, VPI30_DESC, AA1_DESC);
867	SIG_EXPR_LIST_DECL(VPIOB8, VPI,
868	SIG_EXPR_PTR(VPIOB8, VPI18),
869	SIG_EXPR_PTR(VPIOB8, VPI24),
870	SIG_EXPR_PTR(VPIOB8, VPI30));
871	SIG_EXPR_LIST_ALIAS(AA1, VPIOB8, VPI);
872	SIG_EXPR_LIST_DECL_SINGLE(AA1, TXD2, TXD2, AA1_DESC);
873	PIN_DECL_2(AA1, GPIOM6, VPIOB8, TXD2);
874	FUNC_GROUP_DECL(TXD2, AA1);
875
876	#define V5 103
877	#define V5_DESC SIG_DESC_SET(SCU84, 31)
878	SIG_EXPR_DECL_SINGLE(VPIOB9, VPI18, VPI18_DESC, V5_DESC);
879	SIG_EXPR_DECL_SINGLE(VPIOB9, VPI24, VPI24_DESC, V5_DESC);
880	SIG_EXPR_DECL_SINGLE(VPIOB9, VPI30, VPI30_DESC, V5_DESC);
881	SIG_EXPR_LIST_DECL(VPIOB9, VPI,
882	SIG_EXPR_PTR(VPIOB9, VPI18),
883	SIG_EXPR_PTR(VPIOB9, VPI24),
884	SIG_EXPR_PTR(VPIOB9, VPI30));
885	SIG_EXPR_LIST_ALIAS(V5, VPIOB9, VPI);
886	SIG_EXPR_LIST_DECL_SINGLE(V5, RXD2, RXD2, V5_DESC);
887	PIN_DECL_2(V5, GPIOM7, VPIOB9, RXD2);
888	FUNC_GROUP_DECL(RXD2, V5);
889
890	#define W4 104
891	#define W4_DESC SIG_DESC_SET(SCU88, 0)
892	SIG_EXPR_LIST_DECL_SINGLE(W4, VPIG0, VPI30, VPI30_DESC, W4_DESC);
893	SIG_EXPR_LIST_DECL_SINGLE(W4, PWM0, PWM0, W4_DESC);
894	PIN_DECL_2(W4, GPION0, VPIG0, PWM0);
895	FUNC_GROUP_DECL(PWM0, W4);
896
897	#define Y3 105
898	#define Y3_DESC SIG_DESC_SET(SCU88, 1)
899	SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG1, VPI30, VPI30_DESC, Y3_DESC);
900	SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM1, PWM1, Y3_DESC);
901	PIN_DECL_2(Y3, GPION1, VPIG1, PWM1);
902	FUNC_GROUP_DECL(PWM1, Y3);
903
904	#define AA2 106
905	#define AA2_DESC SIG_DESC_SET(SCU88, 2)
906	SIG_EXPR_DECL_SINGLE(VPIG2, VPI18, VPI18_DESC, AA2_DESC);
907	SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, AA2_DESC);
908	SIG_EXPR_DECL_SINGLE(VPIG2, VPI30, VPI30_DESC, AA2_DESC);
909	SIG_EXPR_LIST_DECL(VPIG2, VPI,
910	SIG_EXPR_PTR(VPIG2, VPI18),
911	SIG_EXPR_PTR(VPIG2, VPI24),
912	SIG_EXPR_PTR(VPIG2, VPI30));
913	SIG_EXPR_LIST_ALIAS(AA2, VPIG2, VPI);
914	SIG_EXPR_LIST_DECL_SINGLE(AA2, PWM2, PWM2, AA2_DESC);
915	PIN_DECL_2(AA2, GPION2, VPIG2, PWM2);
916	FUNC_GROUP_DECL(PWM2, AA2);
917
918	#define AB1 107
919	#define AB1_DESC SIG_DESC_SET(SCU88, 3)
920	SIG_EXPR_DECL_SINGLE(VPIG3, VPI18, VPI18_DESC, AB1_DESC);
921	SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, AB1_DESC);
922	SIG_EXPR_DECL_SINGLE(VPIG3, VPI30, VPI30_DESC, AB1_DESC);
923	SIG_EXPR_LIST_DECL(VPIG3, VPI,
924	SIG_EXPR_PTR(VPIG3, VPI18),
925	SIG_EXPR_PTR(VPIG3, VPI24),
926	SIG_EXPR_PTR(VPIG3, VPI30));
927	SIG_EXPR_LIST_ALIAS(AB1, VPIG3, VPI);
928	SIG_EXPR_LIST_DECL_SINGLE(AB1, PWM3, PWM3, AB1_DESC);
929	PIN_DECL_2(AB1, GPION3, VPIG3, PWM3);
930	FUNC_GROUP_DECL(PWM3, AB1);
931
932	#define W5 108
933	#define W5_DESC SIG_DESC_SET(SCU88, 4)
934	SIG_EXPR_DECL_SINGLE(VPIG4, VPI18, VPI18_DESC, W5_DESC);
935	SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W5_DESC);
936	SIG_EXPR_DECL_SINGLE(VPIG4, VPI30, VPI30_DESC, W5_DESC);
937	SIG_EXPR_LIST_DECL(VPIG4, VPI,
938	SIG_EXPR_PTR(VPIG4, VPI18),
939	SIG_EXPR_PTR(VPIG4, VPI24),
940	SIG_EXPR_PTR(VPIG4, VPI30));
941	SIG_EXPR_LIST_ALIAS(W5, VPIG4, VPI);
942	SIG_EXPR_LIST_DECL_SINGLE(W5, PWM4, PWM4, W5_DESC);
943	PIN_DECL_2(W5, GPION4, VPIG4, PWM4);
944	FUNC_GROUP_DECL(PWM4, W5);
945
946	#define Y4 109
947	#define Y4_DESC SIG_DESC_SET(SCU88, 5)
948	SIG_EXPR_DECL_SINGLE(VPIG5, VPI18, VPI18_DESC, Y4_DESC);
949	SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, Y4_DESC);
950	SIG_EXPR_DECL_SINGLE(VPIG5, VPI30, VPI30_DESC, Y4_DESC);
951	SIG_EXPR_LIST_DECL(VPIG5, VPI,
952	SIG_EXPR_PTR(VPIG5, VPI18),
953	SIG_EXPR_PTR(VPIG5, VPI24),
954	SIG_EXPR_PTR(VPIG5, VPI30));
955	SIG_EXPR_LIST_ALIAS(Y4, VPIG5, VPI);
956	SIG_EXPR_LIST_DECL_SINGLE(Y4, PWM5, PWM5, Y4_DESC);
957	PIN_DECL_2(Y4, GPION5, VPIG5, PWM5);
958	FUNC_GROUP_DECL(PWM5, Y4);
959
960	#define AA3 110
961	#define AA3_DESC SIG_DESC_SET(SCU88, 6)
962	SIG_EXPR_LIST_DECL_SINGLE(AA3, VPIG6, VPI30, VPI30_DESC, AA3_DESC);
963	SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM6, PWM6, AA3_DESC);
964	PIN_DECL_2(AA3, GPION6, VPIG6, PWM6);
965	FUNC_GROUP_DECL(PWM6, AA3);
966
967	#define AB2 111
968	#define AB2_DESC SIG_DESC_SET(SCU88, 7)
969	SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIG7, VPI30, VPI30_DESC, AB2_DESC);
970	SIG_EXPR_LIST_DECL_SINGLE(AB2, PWM7, PWM7, AB2_DESC);
971	PIN_DECL_2(AB2, GPION7, VPIG7, PWM7);
972	FUNC_GROUP_DECL(PWM7, AB2);
973
974	#define V6 112
975	SIG_EXPR_LIST_DECL_SINGLE(V6, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8));
976	PIN_DECL_1(V6, GPIOO0, VPIG8);
977
978	#define Y5 113
979	SIG_EXPR_LIST_DECL_SINGLE(Y5, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
980	PIN_DECL_1(Y5, GPIOO1, VPIG9);
981
982	#define AA4 114
983	SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR0, VPI30, VPI30_DESC,
984	SIG_DESC_SET(SCU88, 10));
985	PIN_DECL_1(AA4, GPIOO2, VPIR0);
986
987	#define AB3 115
988	SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR1, VPI30, VPI30_DESC,
989	SIG_DESC_SET(SCU88, 11));
990	PIN_DECL_1(AB3, GPIOO3, VPIR1);
991
992	#define W6 116
993	SIG_EXPR_LIST_DECL_SINGLE(W6, VPIR2, VPI24, VPI24_DESC,
994	SIG_DESC_SET(SCU88, 12));
995	PIN_DECL_1(W6, GPIOO4, VPIR2);
996
997	#define AA5 117
998	SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR3, VPI24, VPI24_DESC,
999	SIG_DESC_SET(SCU88, 13));
1000	PIN_DECL_1(AA5, GPIOO5, VPIR3);
1001
1002	#define AB4 118
1003	SIG_EXPR_LIST_DECL_SINGLE(AB4, VPIR4, VPI24, VPI24_DESC,
1004	SIG_DESC_SET(SCU88, 14));
1005	PIN_DECL_1(AB4, GPIOO6, VPIR4);
1006
1007	#define V7 119
1008	SIG_EXPR_LIST_DECL_SINGLE(V7, VPIR5, VPI24, VPI24_DESC,
1009	SIG_DESC_SET(SCU88, 15));
1010	PIN_DECL_1(V7, GPIOO7, VPIR5);
1011
1012	#define Y6 120
1013	SIG_EXPR_LIST_DECL_SINGLE(Y6, VPIR6, VPI24, VPI24_DESC,
1014	SIG_DESC_SET(SCU88, 16));
1015	PIN_DECL_1(Y6, GPIOP0, VPIR6);
1016
1017	#define AB5 121
1018	SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR7, VPI24, VPI24_DESC,
1019	SIG_DESC_SET(SCU88, 17));
1020	PIN_DECL_1(AB5, GPIOP1, VPIR7);
1021
1022	#define W7 122
1023	SIG_EXPR_LIST_DECL_SINGLE(W7, VPIR8, VPI24, VPI24_DESC,
1024	SIG_DESC_SET(SCU88, 18));
1025	PIN_DECL_1(W7, GPIOP2, VPIR8);
1026
1027	#define AA6 123
1028	SIG_EXPR_LIST_DECL_SINGLE(AA6, VPIR9, VPI24, VPI24_DESC,
1029	SIG_DESC_SET(SCU88, 19));
1030	PIN_DECL_1(AA6, GPIOP3, VPIR9);
1031
1032	FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
1033	AA22, W5, Y4, AA3, AB2);
1034	FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
1035	AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7,
1036	AA6);
1037	FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
1038	V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3);
1039
1040	#define AB6 124
1041	SIG_EXPR_LIST_DECL_SINGLE(AB6, GPIOP4, GPIOP4);
1042	PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(AB6, GPIOP4));
1043
1044	#define Y7 125
1045	SIG_EXPR_LIST_DECL_SINGLE(Y7, GPIOP5, GPIOP5);
1046	PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(Y7, GPIOP5));
1047
1048	#define AA7 126
1049	SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22));
1050
1051	#define AB7 127
1052	SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23));
1053
1054	#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
1055
1056	#define D3 128
1057	SIG_EXPR_LIST_DECL_SINGLE(D3, SCL3, I2C3, I2C3_DESC);
1058	PIN_DECL_1(D3, GPIOQ0, SCL3);
1059
1060	#define C2 129
1061	SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC);
1062	PIN_DECL_1(C2, GPIOQ1, SDA3);
1063
1064	FUNC_GROUP_DECL(I2C3, D3, C2);
1065
1066	#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
1067
1068	#define B1 130
1069	SIG_EXPR_LIST_DECL_SINGLE(B1, SCL4, I2C4, I2C4_DESC);
1070	PIN_DECL_1(B1, GPIOQ2, SCL4);
1071
1072	#define F5 131
1073	SIG_EXPR_LIST_DECL_SINGLE(F5, SDA4, I2C4, I2C4_DESC);
1074	PIN_DECL_1(F5, GPIOQ3, SDA4);
1075
1076	FUNC_GROUP_DECL(I2C4, B1, F5);
1077
1078	#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
1079
1080	#define H4 132
1081	SIG_EXPR_LIST_DECL_SINGLE(H4, SCL14, I2C14, I2C14_DESC);
1082	PIN_DECL_1(H4, GPIOQ4, SCL14);
1083
1084	#define H3 133
1085	SIG_EXPR_LIST_DECL_SINGLE(H3, SDA14, I2C14, I2C14_DESC);
1086	PIN_DECL_1(H3, GPIOQ5, SDA14);
1087
1088	FUNC_GROUP_DECL(I2C14, H4, H3);
1089
1090	/*
1091	* There are several opportunities to document USB port 4 in the datasheet, but
1092	* it is only mentioned in one location. Particularly, the Multi-function Pins
1093	* Mapping and Control table in the datasheet elides the signal names,
1094	* suggesting that port 4 may not actually be functional. As such we define the
1095	* signal names and control bit, but don't export the capability's function or
1096	* group.
1097	*/
1098	#define USB11H3_DESC SIG_DESC_SET(SCU90, 28)
1099
1100	#define H2 134
1101	SIG_EXPR_LIST_DECL_SINGLE(H2, USB11HDP3, USB11H3, USB11H3_DESC);
1102	PIN_DECL_1(H2, GPIOQ6, USB11HDP3);
1103
1104	#define H1 135
1105	SIG_EXPR_LIST_DECL_SINGLE(H1, USB11HDN3, USB11H3, USB11H3_DESC);
1106	PIN_DECL_1(H1, GPIOQ7, USB11HDN3);
1107
1108	#define V20 136
1109	SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24));
1110
1111	#define W21 137
1112	SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25));
1113
1114	#define Y22 138
1115	SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26));
1116
1117	#define U19 139
1118	SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27));
1119
1120	#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
1121	#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
1122	#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
1123	#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
1124	#define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 }
1125	#define VPO_24_OFF SIG_DESC_SET(SCU94, 1)
1126
1127	#define V21 140
1128	#define V21_DESC SIG_DESC_SET(SCU88, 28)
1129	SIG_EXPR_DECL_SINGLE(ROMA24, ROM8, V21_DESC, VPO_OFF_12);
1130	SIG_EXPR_DECL_SINGLE(ROMA24, ROM16, V21_DESC, VPO_OFF_12);
1131	SIG_EXPR_DECL_SINGLE(ROMA24, ROM16S, V21_DESC, VPO_OFF_12);
1132	SIG_EXPR_LIST_DECL(ROMA24, ROM,
1133	SIG_EXPR_PTR(ROMA24, ROM8),
1134	SIG_EXPR_PTR(ROMA24, ROM16),
1135	SIG_EXPR_PTR(ROMA24, ROM16S));
1136	SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM);
1137	SIG_EXPR_LIST_DECL_SINGLE(V21, VPOR6, VPO24, V21_DESC, VPO_24_OFF);
1138	PIN_DECL_2(V21, GPIOR4, ROMA24, VPOR6);
1139
1140	#define W22 141
1141	#define W22_DESC SIG_DESC_SET(SCU88, 29)
1142	SIG_EXPR_DECL_SINGLE(ROMA25, ROM8, W22_DESC, VPO_OFF_12);
1143	SIG_EXPR_DECL_SINGLE(ROMA25, ROM16, W22_DESC, VPO_OFF_12);
1144	SIG_EXPR_DECL_SINGLE(ROMA25, ROM16S, W22_DESC, VPO_OFF_12);
1145	SIG_EXPR_LIST_DECL(ROMA25, ROM,
1146	SIG_EXPR_PTR(ROMA25, ROM8),
1147	SIG_EXPR_PTR(ROMA25, ROM16),
1148	SIG_EXPR_PTR(ROMA25, ROM16S));
1149	SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM);
1150	SIG_EXPR_LIST_DECL_SINGLE(W22, VPOR7, VPO24, W22_DESC, VPO_24_OFF);
1151	PIN_DECL_2(W22, GPIOR5, ROMA25, VPOR7);
1152
1153	#define C6 142
1154	SIG_EXPR_LIST_DECL_SINGLE(C6, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
1155	PIN_DECL_1(C6, GPIOR6, MDC1);
1156
1157	#define A5 143
1158	SIG_EXPR_LIST_DECL_SINGLE(A5, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
1159	PIN_DECL_1(A5, GPIOR7, MDIO1);
1160
1161	FUNC_GROUP_DECL(MDIO1, C6, A5);
1162
1163	#define U21 144
1164	#define U21_DESC SIG_DESC_SET(SCU8C, 0)
1165	SIG_EXPR_DECL_SINGLE(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC);
1166	SIG_EXPR_DECL_SINGLE(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC);
1167	SIG_EXPR_DECL_SINGLE(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC);
1168	SIG_EXPR_LIST_DECL(ROMD4, ROM,
1169	SIG_EXPR_PTR(ROMD4, ROM8),
1170	SIG_EXPR_PTR(ROMD4, ROM16),
1171	SIG_EXPR_PTR(ROMD4, ROM16S));
1172	SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM);
1173	SIG_EXPR_DECL_SINGLE(VPODE, VPO12, U21_DESC, VPO12_DESC);
1174	SIG_EXPR_DECL_SINGLE(VPODE, VPO24, U21_DESC, VPO12_DESC);
1175	SIG_EXPR_LIST_DECL_DUAL(U21, VPODE, VPO12, VPO24);
1176	PIN_DECL_2(U21, GPIOS0, ROMD4, VPODE);
1177
1178	#define T19 145
1179	#define T19_DESC SIG_DESC_SET(SCU8C, 1)
1180	SIG_EXPR_DECL_SINGLE(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC);
1181	SIG_EXPR_DECL_SINGLE(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC);
1182	SIG_EXPR_DECL_SINGLE(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC);
1183	SIG_EXPR_LIST_DECL(ROMD5, ROM,
1184	SIG_EXPR_PTR(ROMD5, ROM8),
1185	SIG_EXPR_PTR(ROMD5, ROM16),
1186	SIG_EXPR_PTR(ROMD5, ROM16S));
1187	SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM);
1188	SIG_EXPR_DECL_SINGLE(VPOHS, VPO12, T19_DESC, VPO12_DESC);
1189	SIG_EXPR_DECL_SINGLE(VPOHS, VPO24, T19_DESC, VPO24_DESC);
1190	SIG_EXPR_LIST_DECL_DUAL(T19, VPOHS, VPO12, VPO24);
1191	PIN_DECL_2(T19, GPIOS1, ROMD5, VPOHS);
1192
1193	#define V22 146
1194	#define V22_DESC SIG_DESC_SET(SCU8C, 2)
1195	SIG_EXPR_DECL_SINGLE(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC);
1196	SIG_EXPR_DECL_SINGLE(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC);
1197	SIG_EXPR_DECL_SINGLE(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC);
1198	SIG_EXPR_LIST_DECL(ROMD6, ROM,
1199	SIG_EXPR_PTR(ROMD6, ROM8),
1200	SIG_EXPR_PTR(ROMD6, ROM16),
1201	SIG_EXPR_PTR(ROMD6, ROM16S));
1202	SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM);
1203	SIG_EXPR_DECL_SINGLE(VPOVS, VPO12, V22_DESC, VPO12_DESC);
1204	SIG_EXPR_DECL_SINGLE(VPOVS, VPO24, V22_DESC, VPO24_DESC);
1205	SIG_EXPR_LIST_DECL_DUAL(V22, VPOVS, VPO12, VPO24);
1206	PIN_DECL_2(V22, GPIOS2, ROMD6, VPOVS);
1207
1208	#define U20 147
1209	#define U20_DESC SIG_DESC_SET(SCU8C, 3)
1210	SIG_EXPR_DECL_SINGLE(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC);
1211	SIG_EXPR_DECL_SINGLE(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC);
1212	SIG_EXPR_DECL_SINGLE(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC);
1213	SIG_EXPR_LIST_DECL(ROMD7, ROM,
1214	SIG_EXPR_PTR(ROMD7, ROM8),
1215	SIG_EXPR_PTR(ROMD7, ROM16),
1216	SIG_EXPR_PTR(ROMD7, ROM16S));
1217	SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM);
1218	SIG_EXPR_DECL_SINGLE(VPOCLK, VPO12, U20_DESC, VPO12_DESC);
1219	SIG_EXPR_DECL_SINGLE(VPOCLK, VPO24, U20_DESC, VPO24_DESC);
1220	SIG_EXPR_LIST_DECL_DUAL(U20, VPOCLK, VPO12, VPO24);
1221	PIN_DECL_2(U20, GPIOS3, ROMD7, VPOCLK);
1222
1223	#define R18 148
1224	#define ROMOE_DESC SIG_DESC_SET(SCU8C, 4)
1225	SIG_EXPR_LIST_DECL_SINGLE(R18, GPIOS4, GPIOS4);
1226	SIG_EXPR_DECL_SINGLE(ROMOE, ROM8, ROMOE_DESC);
1227	SIG_EXPR_DECL_SINGLE(ROMOE, ROM16, ROMOE_DESC);
1228	SIG_EXPR_DECL_SINGLE(ROMOE, ROM16S, ROMOE_DESC);
1229	SIG_EXPR_LIST_DECL(ROMOE, ROM,
1230	SIG_EXPR_PTR(ROMOE, ROM8),
1231	SIG_EXPR_PTR(ROMOE, ROM16),
1232	SIG_EXPR_PTR(ROMOE, ROM16S));
1233	SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM);
1234	PIN_DECL_(R18, SIG_EXPR_LIST_PTR(R18, ROMOE), SIG_EXPR_LIST_PTR(R18, GPIOS4));
1235
1236	#define N21 149
1237	#define ROMWE_DESC SIG_DESC_SET(SCU8C, 5)
1238	SIG_EXPR_LIST_DECL_SINGLE(N21, GPIOS5, GPIOS5);
1239	SIG_EXPR_DECL_SINGLE(ROMWE, ROM8, ROMWE_DESC);
1240	SIG_EXPR_DECL_SINGLE(ROMWE, ROM16, ROMWE_DESC);
1241	SIG_EXPR_DECL_SINGLE(ROMWE, ROM16S, ROMWE_DESC);
1242	SIG_EXPR_LIST_DECL(ROMWE, ROM,
1243	SIG_EXPR_PTR(ROMWE, ROM8),
1244	SIG_EXPR_PTR(ROMWE, ROM16),
1245	SIG_EXPR_PTR(ROMWE, ROM16S));
1246	SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM);
1247	PIN_DECL_(N21, SIG_EXPR_LIST_PTR(N21, ROMWE), SIG_EXPR_LIST_PTR(N21, GPIOS5));
1248
1249	#define L22 150
1250	#define L22_DESC SIG_DESC_SET(SCU8C, 6)
1251	SIG_EXPR_DECL_SINGLE(ROMA22, ROM8, L22_DESC, VPO_OFF_12);
1252	SIG_EXPR_DECL_SINGLE(ROMA22, ROM16, L22_DESC, VPO_OFF_12);
1253	SIG_EXPR_DECL_SINGLE(ROMA22, ROM16S, L22_DESC, VPO_OFF_12);
1254	SIG_EXPR_LIST_DECL(ROMA22, ROM,
1255	SIG_EXPR_PTR(ROMA22, ROM8),
1256	SIG_EXPR_PTR(ROMA22, ROM16),
1257	SIG_EXPR_PTR(ROMA22, ROM16S));
1258	SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM);
1259	SIG_EXPR_LIST_DECL_SINGLE(L22, VPOR4, VPO24, L22_DESC, VPO_24_OFF);
1260	PIN_DECL_2(L22, GPIOS6, ROMA22, VPOR4);
1261
1262	#define K18 151
1263	#define K18_DESC SIG_DESC_SET(SCU8C, 7)
1264	SIG_EXPR_DECL_SINGLE(ROMA23, ROM8, K18_DESC, VPO_OFF_12);
1265	SIG_EXPR_DECL_SINGLE(ROMA23, ROM16, K18_DESC, VPO_OFF_12);
1266	SIG_EXPR_DECL_SINGLE(ROMA23, ROM16S, K18_DESC, VPO_OFF_12);
1267	SIG_EXPR_LIST_DECL(ROMA23, ROM,
1268	SIG_EXPR_PTR(ROMA23, ROM8),
1269	SIG_EXPR_PTR(ROMA23, ROM16),
1270	SIG_EXPR_PTR(ROMA23, ROM16S));
1271	SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM);
1272	SIG_EXPR_LIST_DECL_SINGLE(K18, VPOR5, VPO24, K18_DESC, VPO_24_OFF);
1273	PIN_DECL_2(K18, GPIOS7, ROMA23, VPOR5);
1274
1275	#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
1276
1277	#define A12 152
1278	SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
1279	SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC);
1280	SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1);
1281	PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0),
1282	SIG_EXPR_LIST_PTR(A12, RMII1TXEN),
1283	SIG_EXPR_LIST_PTR(A12, RGMII1TXCK));
1284
1285	#define B12 153
1286	SIG_EXPR_LIST_DECL_SINGLE(B12, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
1287	SIG_EXPR_LIST_DECL_SINGLE(B12, DASHB12, RMII1, RMII1_DESC);
1288	SIG_EXPR_LIST_DECL_SINGLE(B12, RGMII1TXCTL, RGMII1);
1289	PIN_DECL_(B12, SIG_EXPR_LIST_PTR(B12, GPIOT1), SIG_EXPR_LIST_PTR(B12, DASHB12),
1290	SIG_EXPR_LIST_PTR(B12, RGMII1TXCTL));
1291
1292	#define C12 154
1293	SIG_EXPR_LIST_DECL_SINGLE(C12, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
1294	SIG_EXPR_LIST_DECL_SINGLE(C12, RMII1TXD0, RMII1, RMII1_DESC);
1295	SIG_EXPR_LIST_DECL_SINGLE(C12, RGMII1TXD0, RGMII1);
1296	PIN_DECL_(C12, SIG_EXPR_LIST_PTR(C12, GPIOT2),
1297	SIG_EXPR_LIST_PTR(C12, RMII1TXD0),
1298	SIG_EXPR_LIST_PTR(C12, RGMII1TXD0));
1299
1300	#define D12 155
1301	SIG_EXPR_LIST_DECL_SINGLE(D12, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
1302	SIG_EXPR_LIST_DECL_SINGLE(D12, RMII1TXD1, RMII1, RMII1_DESC);
1303	SIG_EXPR_LIST_DECL_SINGLE(D12, RGMII1TXD1, RGMII1);
1304	PIN_DECL_(D12, SIG_EXPR_LIST_PTR(D12, GPIOT3),
1305	SIG_EXPR_LIST_PTR(D12, RMII1TXD1),
1306	SIG_EXPR_LIST_PTR(D12, RGMII1TXD1));
1307
1308	#define E12 156
1309	SIG_EXPR_LIST_DECL_SINGLE(E12, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
1310	SIG_EXPR_LIST_DECL_SINGLE(E12, DASHE12, RMII1, RMII1_DESC);
1311	SIG_EXPR_LIST_DECL_SINGLE(E12, RGMII1TXD2, RGMII1);
1312	PIN_DECL_(E12, SIG_EXPR_LIST_PTR(E12, GPIOT4), SIG_EXPR_LIST_PTR(E12, DASHE12),
1313	SIG_EXPR_LIST_PTR(E12, RGMII1TXD2));
1314
1315	#define A13 157
1316	SIG_EXPR_LIST_DECL_SINGLE(A13, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
1317	SIG_EXPR_LIST_DECL_SINGLE(A13, DASHA13, RMII1, RMII1_DESC);
1318	SIG_EXPR_LIST_DECL_SINGLE(A13, RGMII1TXD3, RGMII1);
1319	PIN_DECL_(A13, SIG_EXPR_LIST_PTR(A13, GPIOT5), SIG_EXPR_LIST_PTR(A13, DASHA13),
1320	SIG_EXPR_LIST_PTR(A13, RGMII1TXD3));
1321
1322	#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
1323
1324	#define D9 158
1325	SIG_EXPR_LIST_DECL_SINGLE(D9, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
1326	SIG_EXPR_LIST_DECL_SINGLE(D9, RMII2TXEN, RMII2, RMII2_DESC);
1327	SIG_EXPR_LIST_DECL_SINGLE(D9, RGMII2TXCK, RGMII2);
1328	PIN_DECL_(D9, SIG_EXPR_LIST_PTR(D9, GPIOT6), SIG_EXPR_LIST_PTR(D9, RMII2TXEN),
1329	SIG_EXPR_LIST_PTR(D9, RGMII2TXCK));
1330
1331	#define E9 159
1332	SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
1333	SIG_EXPR_LIST_DECL_SINGLE(E9, DASHE9, RMII2, RMII2_DESC);
1334	SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII2TXCTL, RGMII2);
1335	PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT7), SIG_EXPR_LIST_PTR(E9, DASHE9),
1336	SIG_EXPR_LIST_PTR(E9, RGMII2TXCTL));
1337
1338	#define A10 160
1339	SIG_EXPR_LIST_DECL_SINGLE(A10, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
1340	SIG_EXPR_LIST_DECL_SINGLE(A10, RMII2TXD0, RMII2, RMII2_DESC);
1341	SIG_EXPR_LIST_DECL_SINGLE(A10, RGMII2TXD0, RGMII2);
1342	PIN_DECL_(A10, SIG_EXPR_LIST_PTR(A10, GPIOU0),
1343	SIG_EXPR_LIST_PTR(A10, RMII2TXD0),
1344	SIG_EXPR_LIST_PTR(A10, RGMII2TXD0));
1345
1346	#define B10 161
1347	SIG_EXPR_LIST_DECL_SINGLE(B10, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
1348	SIG_EXPR_LIST_DECL_SINGLE(B10, RMII2TXD1, RMII2, RMII2_DESC);
1349	SIG_EXPR_LIST_DECL_SINGLE(B10, RGMII2TXD1, RGMII2);
1350	PIN_DECL_(B10, SIG_EXPR_LIST_PTR(B10, GPIOU1),
1351	SIG_EXPR_LIST_PTR(B10, RMII2TXD1),
1352	SIG_EXPR_LIST_PTR(B10, RGMII2TXD1));
1353
1354	#define C10 162
1355	SIG_EXPR_LIST_DECL_SINGLE(C10, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
1356	SIG_EXPR_LIST_DECL_SINGLE(C10, DASHC10, RMII2, RMII2_DESC);
1357	SIG_EXPR_LIST_DECL_SINGLE(C10, RGMII2TXD2, RGMII2);
1358	PIN_DECL_(C10, SIG_EXPR_LIST_PTR(C10, GPIOU2), SIG_EXPR_LIST_PTR(C10, DASHC10),
1359	SIG_EXPR_LIST_PTR(C10, RGMII2TXD2));
1360
1361	#define D10 163
1362	SIG_EXPR_LIST_DECL_SINGLE(D10, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
1363	SIG_EXPR_LIST_DECL_SINGLE(D10, DASHD10, RMII2, RMII2_DESC);
1364	SIG_EXPR_LIST_DECL_SINGLE(D10, RGMII2TXD3, RGMII2);
1365	PIN_DECL_(D10, SIG_EXPR_LIST_PTR(D10, GPIOU3), SIG_EXPR_LIST_PTR(D10, DASHD10),
1366	SIG_EXPR_LIST_PTR(D10, RGMII2TXD3));
1367
1368	#define E11 164
1369	SIG_EXPR_LIST_DECL_SINGLE(E11, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
1370	SIG_EXPR_LIST_DECL_SINGLE(E11, RMII1RCLK, RMII1, RMII1_DESC);
1371	SIG_EXPR_LIST_DECL_SINGLE(E11, RGMII1RXCK, RGMII1);
1372	PIN_DECL_(E11, SIG_EXPR_LIST_PTR(E11, GPIOU4),
1373	SIG_EXPR_LIST_PTR(E11, RMII1RCLK),
1374	SIG_EXPR_LIST_PTR(E11, RGMII1RXCK));
1375
1376	#define D11 165
1377	SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
1378	SIG_EXPR_LIST_DECL_SINGLE(D11, DASHD11, RMII1, RMII1_DESC);
1379	SIG_EXPR_LIST_DECL_SINGLE(D11, RGMII1RXCTL, RGMII1);
1380	PIN_DECL_(D11, SIG_EXPR_LIST_PTR(D11, GPIOU5), SIG_EXPR_LIST_PTR(D11, DASHD11),
1381	SIG_EXPR_LIST_PTR(D11, RGMII1RXCTL));
1382
1383	#define C11 166
1384	SIG_EXPR_LIST_DECL_SINGLE(C11, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
1385	SIG_EXPR_LIST_DECL_SINGLE(C11, RMII1RXD0, RMII1, RMII1_DESC);
1386	SIG_EXPR_LIST_DECL_SINGLE(C11, RGMII1RXD0, RGMII1);
1387	PIN_DECL_(C11, SIG_EXPR_LIST_PTR(C11, GPIOU6),
1388	SIG_EXPR_LIST_PTR(C11, RMII1RXD0),
1389	SIG_EXPR_LIST_PTR(C11, RGMII1RXD0));
1390
1391	#define B11 167
1392	SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
1393	SIG_EXPR_LIST_DECL_SINGLE(B11, RMII1RXD1, RMII1, RMII1_DESC);
1394	SIG_EXPR_LIST_DECL_SINGLE(B11, RGMII1RXD1, RGMII1);
1395	PIN_DECL_(B11, SIG_EXPR_LIST_PTR(B11, GPIOU7),
1396	SIG_EXPR_LIST_PTR(B11, RMII1RXD1),
1397	SIG_EXPR_LIST_PTR(B11, RGMII1RXD1));
1398
1399	#define A11 168
1400	SIG_EXPR_LIST_DECL_SINGLE(A11, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
1401	SIG_EXPR_LIST_DECL_SINGLE(A11, RMII1CRSDV, RMII1, RMII1_DESC);
1402	SIG_EXPR_LIST_DECL_SINGLE(A11, RGMII1RXD2, RGMII1);
1403	PIN_DECL_(A11, SIG_EXPR_LIST_PTR(A11, GPIOV0),
1404	SIG_EXPR_LIST_PTR(A11, RMII1CRSDV),
1405	SIG_EXPR_LIST_PTR(A11, RGMII1RXD2));
1406
1407	#define E10 169
1408	SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
1409	SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC);
1410	SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1);
1411	PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1),
1412	SIG_EXPR_LIST_PTR(E10, RMII1RXER),
1413	SIG_EXPR_LIST_PTR(E10, RGMII1RXD3));
1414
1415	#define C9 170
1416	SIG_EXPR_LIST_DECL_SINGLE(C9, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
1417	SIG_EXPR_LIST_DECL_SINGLE(C9, RMII2RCLK, RMII2, RMII2_DESC);
1418	SIG_EXPR_LIST_DECL_SINGLE(C9, RGMII2RXCK, RGMII2);
1419	PIN_DECL_(C9, SIG_EXPR_LIST_PTR(C9, GPIOV2), SIG_EXPR_LIST_PTR(C9, RMII2RCLK),
1420	SIG_EXPR_LIST_PTR(C9, RGMII2RXCK));
1421
1422	#define B9 171
1423	SIG_EXPR_LIST_DECL_SINGLE(B9, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
1424	SIG_EXPR_LIST_DECL_SINGLE(B9, DASHB9, RMII2, RMII2_DESC);
1425	SIG_EXPR_LIST_DECL_SINGLE(B9, RGMII2RXCTL, RGMII2);
1426	PIN_DECL_(B9, SIG_EXPR_LIST_PTR(B9, GPIOV3), SIG_EXPR_LIST_PTR(B9, DASHB9),
1427	SIG_EXPR_LIST_PTR(B9, RGMII2RXCTL));
1428
1429	#define A9 172
1430	SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
1431	SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC);
1432	SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2);
1433	PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0),
1434	SIG_EXPR_LIST_PTR(A9, RGMII2RXD0));
1435
1436	#define E8 173
1437	SIG_EXPR_LIST_DECL_SINGLE(E8, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
1438	SIG_EXPR_LIST_DECL_SINGLE(E8, RMII2RXD1, RMII2, RMII2_DESC);
1439	SIG_EXPR_LIST_DECL_SINGLE(E8, RGMII2RXD1, RGMII2);
1440	PIN_DECL_(E8, SIG_EXPR_LIST_PTR(E8, GPIOV5), SIG_EXPR_LIST_PTR(E8, RMII2RXD1),
1441	SIG_EXPR_LIST_PTR(E8, RGMII2RXD1));
1442
1443	#define D8 174
1444	SIG_EXPR_LIST_DECL_SINGLE(D8, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
1445	SIG_EXPR_LIST_DECL_SINGLE(D8, RMII2CRSDV, RMII2, RMII2_DESC);
1446	SIG_EXPR_LIST_DECL_SINGLE(D8, RGMII2RXD2, RGMII2);
1447	PIN_DECL_(D8, SIG_EXPR_LIST_PTR(D8, GPIOV6), SIG_EXPR_LIST_PTR(D8, RMII2CRSDV),
1448	SIG_EXPR_LIST_PTR(D8, RGMII2RXD2));
1449
1450	#define C8 175
1451	SIG_EXPR_LIST_DECL_SINGLE(C8, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
1452	SIG_EXPR_LIST_DECL_SINGLE(C8, RMII2RXER, RMII2, RMII2_DESC);
1453	SIG_EXPR_LIST_DECL_SINGLE(C8, RGMII2RXD3, RGMII2);
1454	PIN_DECL_(C8, SIG_EXPR_LIST_PTR(C8, GPIOV7), SIG_EXPR_LIST_PTR(C8, RMII2RXER),
1455	SIG_EXPR_LIST_PTR(C8, RGMII2RXD3));
1456
1457	FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
1458	E10);
1459	FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
1460	E10);
1461
1462	FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
1463	FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
1464
1465	#define L5 176
1466	SIG_EXPR_LIST_DECL_SINGLE(L5, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
1467	SIG_EXPR_LIST_DECL_SINGLE(L5, ADC0, ADC0);
1468	PIN_DECL_(L5, SIG_EXPR_LIST_PTR(L5, GPIOW0), SIG_EXPR_LIST_PTR(L5, ADC0));
1469	FUNC_GROUP_DECL(ADC0, L5);
1470
1471	#define L4 177
1472	SIG_EXPR_LIST_DECL_SINGLE(L4, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
1473	SIG_EXPR_LIST_DECL_SINGLE(L4, ADC1, ADC1);
1474	PIN_DECL_(L4, SIG_EXPR_LIST_PTR(L4, GPIOW1), SIG_EXPR_LIST_PTR(L4, ADC1));
1475	FUNC_GROUP_DECL(ADC1, L4);
1476
1477	#define L3 178
1478	SIG_EXPR_LIST_DECL_SINGLE(L3, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
1479	SIG_EXPR_LIST_DECL_SINGLE(L3, ADC2, ADC2);
1480	PIN_DECL_(L3, SIG_EXPR_LIST_PTR(L3, GPIOW2), SIG_EXPR_LIST_PTR(L3, ADC2));
1481	FUNC_GROUP_DECL(ADC2, L3);
1482
1483	#define L2 179
1484	SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
1485	SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3);
1486	PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3));
1487	FUNC_GROUP_DECL(ADC3, L2);
1488
1489	#define L1 180
1490	SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
1491	SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4);
1492	PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4));
1493	FUNC_GROUP_DECL(ADC4, L1);
1494
1495	#define M5 181
1496	SIG_EXPR_LIST_DECL_SINGLE(M5, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
1497	SIG_EXPR_LIST_DECL_SINGLE(M5, ADC5, ADC5);
1498	PIN_DECL_(M5, SIG_EXPR_LIST_PTR(M5, GPIOW5), SIG_EXPR_LIST_PTR(M5, ADC5));
1499	FUNC_GROUP_DECL(ADC5, M5);
1500
1501	#define M4 182
1502	SIG_EXPR_LIST_DECL_SINGLE(M4, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
1503	SIG_EXPR_LIST_DECL_SINGLE(M4, ADC6, ADC6);
1504	PIN_DECL_(M4, SIG_EXPR_LIST_PTR(M4, GPIOW6), SIG_EXPR_LIST_PTR(M4, ADC6));
1505	FUNC_GROUP_DECL(ADC6, M4);
1506
1507	#define M3 183
1508	SIG_EXPR_LIST_DECL_SINGLE(M3, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
1509	SIG_EXPR_LIST_DECL_SINGLE(M3, ADC7, ADC7);
1510	PIN_DECL_(M3, SIG_EXPR_LIST_PTR(M3, GPIOW7), SIG_EXPR_LIST_PTR(M3, ADC7));
1511	FUNC_GROUP_DECL(ADC7, M3);
1512
1513	#define M2 184
1514	SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
1515	SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8);
1516	PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8));
1517	FUNC_GROUP_DECL(ADC8, M2);
1518
1519	#define M1 185
1520	SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
1521	SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9);
1522	PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9));
1523	FUNC_GROUP_DECL(ADC9, M1);
1524
1525	#define N5 186
1526	SIG_EXPR_LIST_DECL_SINGLE(N5, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
1527	SIG_EXPR_LIST_DECL_SINGLE(N5, ADC10, ADC10);
1528	PIN_DECL_(N5, SIG_EXPR_LIST_PTR(N5, GPIOX2), SIG_EXPR_LIST_PTR(N5, ADC10));
1529	FUNC_GROUP_DECL(ADC10, N5);
1530
1531	#define N4 187
1532	SIG_EXPR_LIST_DECL_SINGLE(N4, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
1533	SIG_EXPR_LIST_DECL_SINGLE(N4, ADC11, ADC11);
1534	PIN_DECL_(N4, SIG_EXPR_LIST_PTR(N4, GPIOX3), SIG_EXPR_LIST_PTR(N4, ADC11));
1535	FUNC_GROUP_DECL(ADC11, N4);
1536
1537	#define N3 188
1538	SIG_EXPR_LIST_DECL_SINGLE(N3, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
1539	SIG_EXPR_LIST_DECL_SINGLE(N3, ADC12, ADC12);
1540	PIN_DECL_(N3, SIG_EXPR_LIST_PTR(N3, GPIOX4), SIG_EXPR_LIST_PTR(N3, ADC12));
1541	FUNC_GROUP_DECL(ADC12, N3);
1542
1543	#define N2 189
1544	SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
1545	SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13);
1546	PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13));
1547	FUNC_GROUP_DECL(ADC13, N2);
1548
1549	#define N1 190
1550	SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
1551	SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14);
1552	PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14));
1553	FUNC_GROUP_DECL(ADC14, N1);
1554
1555	#define P5 191
1556	SIG_EXPR_LIST_DECL_SINGLE(P5, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
1557	SIG_EXPR_LIST_DECL_SINGLE(P5, ADC15, ADC15);
1558	PIN_DECL_(P5, SIG_EXPR_LIST_PTR(P5, GPIOX7), SIG_EXPR_LIST_PTR(P5, ADC15));
1559	FUNC_GROUP_DECL(ADC15, P5);
1560
1561	#define C21 192
1562	SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
1563	SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
1564	SIG_EXPR_LIST_DECL_DUAL(C21, SIOS3, SIOS3, ACPI);
1565	PIN_DECL_1(C21, GPIOY0, SIOS3);
1566	FUNC_GROUP_DECL(SIOS3, C21);
1567
1568	#define F20 193
1569	SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
1570	SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
1571	SIG_EXPR_LIST_DECL_DUAL(F20, SIOS5, SIOS5, ACPI);
1572	PIN_DECL_1(F20, GPIOY1, SIOS5);
1573	FUNC_GROUP_DECL(SIOS5, F20);
1574
1575	#define G20 194
1576	SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
1577	SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
1578	SIG_EXPR_LIST_DECL_DUAL(G20, SIOPWREQ, SIOPWREQ, ACPI);
1579	PIN_DECL_1(G20, GPIOY2, SIOPWREQ);
1580	FUNC_GROUP_DECL(SIOPWREQ, G20);
1581
1582	#define K20 195
1583	SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
1584	SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
1585	SIG_EXPR_LIST_DECL_DUAL(K20, SIOONCTRL, SIOONCTRL, ACPI);
1586	PIN_DECL_1(K20, GPIOY3, SIOONCTRL);
1587	FUNC_GROUP_DECL(SIOONCTRL, K20);
1588
1589	FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20);
1590
1591	#define R22 200
1592	#define R22_DESC SIG_DESC_SET(SCUA4, 16)
1593	SIG_EXPR_DECL_SINGLE(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC);
1594	SIG_EXPR_DECL_SINGLE(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC);
1595	SIG_EXPR_LIST_DECL_DUAL(R22, ROMA2, ROM8, ROM16);
1596	SIG_EXPR_DECL_SINGLE(VPOB0, VPO12, R22_DESC, VPO12_DESC);
1597	SIG_EXPR_DECL_SINGLE(VPOB0, VPO24, R22_DESC, VPO24_DESC);
1598	SIG_EXPR_DECL_SINGLE(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC);
1599	SIG_EXPR_LIST_DECL(VPOB0, VPO,
1600	SIG_EXPR_PTR(VPOB0, VPO12),
1601	SIG_EXPR_PTR(VPOB0, VPO24),
1602	SIG_EXPR_PTR(VPOB0, VPOOFF1));
1603	SIG_EXPR_LIST_ALIAS(R22, VPOB0, VPO);
1604	PIN_DECL_2(R22, GPIOZ0, ROMA2, VPOB0);
1605
1606	#define P18 201
1607	#define P18_DESC SIG_DESC_SET(SCUA4, 17)
1608	SIG_EXPR_DECL_SINGLE(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC);
1609	SIG_EXPR_DECL_SINGLE(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC);
1610	SIG_EXPR_LIST_DECL_DUAL(P18, ROMA3, ROM8, ROM16);
1611	SIG_EXPR_DECL_SINGLE(VPOB1, VPO12, P18_DESC, VPO12_DESC);
1612	SIG_EXPR_DECL_SINGLE(VPOB1, VPO24, P18_DESC, VPO24_DESC);
1613	SIG_EXPR_DECL_SINGLE(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC);
1614	SIG_EXPR_LIST_DECL(VPOB1, VPO,
1615	SIG_EXPR_PTR(VPOB1, VPO12),
1616	SIG_EXPR_PTR(VPOB1, VPO24),
1617	SIG_EXPR_PTR(VPOB1, VPOOFF1));
1618	SIG_EXPR_LIST_ALIAS(P18, VPOB1, VPO);
1619	PIN_DECL_2(P18, GPIOZ1, ROMA3, VPOB1);
1620
1621	#define P19 202
1622	#define P19_DESC SIG_DESC_SET(SCUA4, 18)
1623	SIG_EXPR_DECL_SINGLE(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC);
1624	SIG_EXPR_DECL_SINGLE(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC);
1625	SIG_EXPR_LIST_DECL_DUAL(P19, ROMA4, ROM8, ROM16);
1626	SIG_EXPR_DECL_SINGLE(VPOB2, VPO12, P19_DESC, VPO12_DESC);
1627	SIG_EXPR_DECL_SINGLE(VPOB2, VPO24, P19_DESC, VPO24_DESC);
1628	SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC);
1629	SIG_EXPR_LIST_DECL(VPOB2, VPO,
1630	SIG_EXPR_PTR(VPOB2, VPO12),
1631	SIG_EXPR_PTR(VPOB2, VPO24),
1632	SIG_EXPR_PTR(VPOB2, VPOOFF1));
1633	SIG_EXPR_LIST_ALIAS(P19, VPOB2, VPO);
1634	PIN_DECL_2(P19, GPIOZ2, ROMA4, VPOB2);
1635
1636	#define P20 203
1637	#define P20_DESC SIG_DESC_SET(SCUA4, 19)
1638	SIG_EXPR_DECL_SINGLE(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC);
1639	SIG_EXPR_DECL_SINGLE(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC);
1640	SIG_EXPR_LIST_DECL_DUAL(P20, ROMA5, ROM8, ROM16);
1641	SIG_EXPR_DECL_SINGLE(VPOB3, VPO12, P20_DESC, VPO12_DESC);
1642	SIG_EXPR_DECL_SINGLE(VPOB3, VPO24, P20_DESC, VPO24_DESC);
1643	SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC);
1644	SIG_EXPR_LIST_DECL(VPOB3, VPO,
1645	SIG_EXPR_PTR(VPOB3, VPO12),
1646	SIG_EXPR_PTR(VPOB3, VPO24),
1647	SIG_EXPR_PTR(VPOB3, VPOOFF1));
1648	SIG_EXPR_LIST_ALIAS(P20, VPOB3, VPO);
1649	PIN_DECL_2(P20, GPIOZ3, ROMA5, VPOB3);
1650
1651	#define P21 204
1652	#define P21_DESC SIG_DESC_SET(SCUA4, 20)
1653	SIG_EXPR_DECL_SINGLE(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC);
1654	SIG_EXPR_DECL_SINGLE(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC);
1655	SIG_EXPR_LIST_DECL_DUAL(P21, ROMA6, ROM8, ROM16);
1656	SIG_EXPR_DECL_SINGLE(VPOB4, VPO12, P21_DESC, VPO12_DESC);
1657	SIG_EXPR_DECL_SINGLE(VPOB4, VPO24, P21_DESC, VPO24_DESC);
1658	SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC);
1659	SIG_EXPR_LIST_DECL(VPOB4, VPO,
1660	SIG_EXPR_PTR(VPOB4, VPO12),
1661	SIG_EXPR_PTR(VPOB4, VPO24),
1662	SIG_EXPR_PTR(VPOB4, VPOOFF1));
1663	SIG_EXPR_LIST_ALIAS(P21, VPOB4, VPO);
1664	PIN_DECL_2(P21, GPIOZ4, ROMA6, VPOB4);
1665
1666	#define P22 205
1667	#define P22_DESC SIG_DESC_SET(SCUA4, 21)
1668	SIG_EXPR_DECL_SINGLE(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC);
1669	SIG_EXPR_DECL_SINGLE(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC);
1670	SIG_EXPR_LIST_DECL_DUAL(P22, ROMA7, ROM8, ROM16);
1671	SIG_EXPR_DECL_SINGLE(VPOB5, VPO12, P22_DESC, VPO12_DESC);
1672	SIG_EXPR_DECL_SINGLE(VPOB5, VPO24, P22_DESC, VPO24_DESC);
1673	SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC);
1674	SIG_EXPR_LIST_DECL(VPOB5, VPO,
1675	SIG_EXPR_PTR(VPOB5, VPO12),
1676	SIG_EXPR_PTR(VPOB5, VPO24),
1677	SIG_EXPR_PTR(VPOB5, VPOOFF1));
1678	SIG_EXPR_LIST_ALIAS(P22, VPOB5, VPO);
1679	PIN_DECL_2(P22, GPIOZ5, ROMA7, VPOB5);
1680
1681	#define M19 206
1682	#define M19_DESC SIG_DESC_SET(SCUA4, 22)
1683	SIG_EXPR_DECL_SINGLE(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC);
1684	SIG_EXPR_DECL_SINGLE(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC);
1685	SIG_EXPR_LIST_DECL_DUAL(M19, ROMA8, ROM8, ROM16);
1686	SIG_EXPR_DECL_SINGLE(VPOB6, VPO12, M19_DESC, VPO12_DESC);
1687	SIG_EXPR_DECL_SINGLE(VPOB6, VPO24, M19_DESC, VPO24_DESC);
1688	SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC);
1689	SIG_EXPR_LIST_DECL(VPOB6, VPO,
1690	SIG_EXPR_PTR(VPOB6, VPO12),
1691	SIG_EXPR_PTR(VPOB6, VPO24),
1692	SIG_EXPR_PTR(VPOB6, VPOOFF1));
1693	SIG_EXPR_LIST_ALIAS(M19, VPOB6, VPO);
1694	PIN_DECL_2(M19, GPIOZ6, ROMA8, VPOB6);
1695
1696	#define M20 207
1697	#define M20_DESC SIG_DESC_SET(SCUA4, 23)
1698	SIG_EXPR_DECL_SINGLE(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC);
1699	SIG_EXPR_DECL_SINGLE(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC);
1700	SIG_EXPR_LIST_DECL_DUAL(M20, ROMA9, ROM8, ROM16);
1701	SIG_EXPR_DECL_SINGLE(VPOB7, VPO12, M20_DESC, VPO12_DESC);
1702	SIG_EXPR_DECL_SINGLE(VPOB7, VPO24, M20_DESC, VPO24_DESC);
1703	SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC);
1704	SIG_EXPR_LIST_DECL(VPOB7, VPO,
1705	SIG_EXPR_PTR(VPOB7, VPO12),
1706	SIG_EXPR_PTR(VPOB7, VPO24),
1707	SIG_EXPR_PTR(VPOB7, VPOOFF1));
1708	SIG_EXPR_LIST_ALIAS(M20, VPOB7, VPO);
1709	PIN_DECL_2(M20, GPIOZ7, ROMA9, VPOB7);
1710
1711	#define M21 208
1712	#define M21_DESC SIG_DESC_SET(SCUA4, 24)
1713	SIG_EXPR_DECL_SINGLE(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC);
1714	SIG_EXPR_DECL_SINGLE(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC);
1715	SIG_EXPR_LIST_DECL_DUAL(M21, ROMA10, ROM8, ROM16);
1716	SIG_EXPR_DECL_SINGLE(VPOG0, VPO12, M21_DESC, VPO12_DESC);
1717	SIG_EXPR_DECL_SINGLE(VPOG0, VPO24, M21_DESC, VPO24_DESC);
1718	SIG_EXPR_DECL_SINGLE(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC);
1719	SIG_EXPR_LIST_DECL(VPOG0, VPO,
1720	SIG_EXPR_PTR(VPOG0, VPO12),
1721	SIG_EXPR_PTR(VPOG0, VPO24),
1722	SIG_EXPR_PTR(VPOG0, VPOOFF1));
1723	SIG_EXPR_LIST_ALIAS(M21, VPOG0, VPO);
1724	PIN_DECL_2(M21, GPIOAA0, ROMA10, VPOG0);
1725
1726	#define M22 209
1727	#define M22_DESC SIG_DESC_SET(SCUA4, 25)
1728	SIG_EXPR_DECL_SINGLE(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC);
1729	SIG_EXPR_DECL_SINGLE(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC);
1730	SIG_EXPR_LIST_DECL_DUAL(M22, ROMA11, ROM8, ROM16);
1731	SIG_EXPR_DECL_SINGLE(VPOG1, VPO12, M22_DESC, VPO12_DESC);
1732	SIG_EXPR_DECL_SINGLE(VPOG1, VPO24, M22_DESC, VPO24_DESC);
1733	SIG_EXPR_DECL_SINGLE(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC);
1734	SIG_EXPR_LIST_DECL(VPOG1, VPO,
1735	SIG_EXPR_PTR(VPOG1, VPO12),
1736	SIG_EXPR_PTR(VPOG1, VPO24),
1737	SIG_EXPR_PTR(VPOG1, VPOOFF1));
1738	SIG_EXPR_LIST_ALIAS(M22, VPOG1, VPO);
1739	PIN_DECL_2(M22, GPIOAA1, ROMA11, VPOG1);
1740
1741	#define L18 210
1742	#define L18_DESC SIG_DESC_SET(SCUA4, 26)
1743	SIG_EXPR_DECL_SINGLE(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC);
1744	SIG_EXPR_DECL_SINGLE(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC);
1745	SIG_EXPR_LIST_DECL_DUAL(L18, ROMA12, ROM8, ROM16);
1746	SIG_EXPR_DECL_SINGLE(VPOG2, VPO12, L18_DESC, VPO12_DESC);
1747	SIG_EXPR_DECL_SINGLE(VPOG2, VPO24, L18_DESC, VPO24_DESC);
1748	SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC);
1749	SIG_EXPR_LIST_DECL(VPOG2, VPO,
1750	SIG_EXPR_PTR(VPOG2, VPO12),
1751	SIG_EXPR_PTR(VPOG2, VPO24),
1752	SIG_EXPR_PTR(VPOG2, VPOOFF1));
1753	SIG_EXPR_LIST_ALIAS(L18, VPOG2, VPO);
1754	PIN_DECL_2(L18, GPIOAA2, ROMA12, VPOG2);
1755
1756	#define L19 211
1757	#define L19_DESC SIG_DESC_SET(SCUA4, 27)
1758	SIG_EXPR_DECL_SINGLE(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC);
1759	SIG_EXPR_DECL_SINGLE(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC);
1760	SIG_EXPR_LIST_DECL_DUAL(L19, ROMA13, ROM8, ROM16);
1761	SIG_EXPR_DECL_SINGLE(VPOG3, VPO12, L19_DESC, VPO12_DESC);
1762	SIG_EXPR_DECL_SINGLE(VPOG3, VPO24, L19_DESC, VPO24_DESC);
1763	SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC);
1764	SIG_EXPR_LIST_DECL(VPOG3, VPO,
1765	SIG_EXPR_PTR(VPOG3, VPO12),
1766	SIG_EXPR_PTR(VPOG3, VPO24),
1767	SIG_EXPR_PTR(VPOG3, VPOOFF1));
1768	SIG_EXPR_LIST_ALIAS(L19, VPOG3, VPO);
1769	PIN_DECL_2(L19, GPIOAA3, ROMA13, VPOG3);
1770
1771	#define L20 212
1772	#define L20_DESC SIG_DESC_SET(SCUA4, 28)
1773	SIG_EXPR_DECL_SINGLE(ROMA14, ROM8, L20_DESC, VPO_OFF_12);
1774	SIG_EXPR_DECL_SINGLE(ROMA14, ROM16, L20_DESC, VPO_OFF_12);
1775	SIG_EXPR_LIST_DECL_DUAL(L20, ROMA14, ROM8, ROM16);
1776	SIG_EXPR_DECL_SINGLE(VPOG4, VPO24, L20_DESC, VPO24_DESC);
1777	SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC);
1778	SIG_EXPR_LIST_DECL_DUAL(L20, VPOG4, VPO24, VPOOFF1);
1779	PIN_DECL_2(L20, GPIOAA4, ROMA14, VPOG4);
1780
1781	#define L21 213
1782	#define L21_DESC SIG_DESC_SET(SCUA4, 29)
1783	SIG_EXPR_DECL_SINGLE(ROMA15, ROM8, L21_DESC, VPO_OFF_12);
1784	SIG_EXPR_DECL_SINGLE(ROMA15, ROM16, L21_DESC, VPO_OFF_12);
1785	SIG_EXPR_LIST_DECL_DUAL(L21, ROMA15, ROM8, ROM16);
1786	SIG_EXPR_DECL_SINGLE(VPOG5, VPO24, L21_DESC, VPO24_DESC);
1787	SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC);
1788	SIG_EXPR_LIST_DECL_DUAL(L21, VPOG5, VPO24, VPOOFF1);
1789	PIN_DECL_2(L21, GPIOAA5, ROMA15, VPOG5);
1790
1791	#define T18 214
1792	#define T18_DESC SIG_DESC_SET(SCUA4, 30)
1793	SIG_EXPR_DECL_SINGLE(ROMA16, ROM8, T18_DESC, VPO_OFF_12);
1794	SIG_EXPR_DECL_SINGLE(ROMA16, ROM16, T18_DESC, VPO_OFF_12);
1795	SIG_EXPR_LIST_DECL_DUAL(T18, ROMA16, ROM8, ROM16);
1796	SIG_EXPR_DECL_SINGLE(VPOG6, VPO24, T18_DESC, VPO24_DESC);
1797	SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC);
1798	SIG_EXPR_LIST_DECL_DUAL(T18, VPOG6, VPO24, VPOOFF1);
1799	PIN_DECL_2(T18, GPIOAA6, ROMA16, VPOG6);
1800
1801	#define N18 215
1802	#define N18_DESC SIG_DESC_SET(SCUA4, 31)
1803	SIG_EXPR_DECL_SINGLE(ROMA17, ROM8, N18_DESC, VPO_OFF_12);
1804	SIG_EXPR_DECL_SINGLE(ROMA17, ROM16, N18_DESC, VPO_OFF_12);
1805	SIG_EXPR_LIST_DECL_DUAL(N18, ROMA17, ROM8, ROM16);
1806	SIG_EXPR_DECL_SINGLE(VPOG7, VPO24, N18_DESC, VPO24_DESC);
1807	SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC);
1808	SIG_EXPR_LIST_DECL_DUAL(N18, VPOG7, VPO24, VPOOFF1);
1809	PIN_DECL_2(N18, GPIOAA7, ROMA17, VPOG7);
1810
1811	#define N19 216
1812	#define N19_DESC SIG_DESC_SET(SCUA8, 0)
1813	SIG_EXPR_DECL_SINGLE(ROMA18, ROM8, N19_DESC, VPO_OFF_12);
1814	SIG_EXPR_DECL_SINGLE(ROMA18, ROM16, N19_DESC, VPO_OFF_12);
1815	SIG_EXPR_LIST_DECL_DUAL(N19, ROMA18, ROM8, ROM16);
1816	SIG_EXPR_DECL_SINGLE(VPOR0, VPO24, N19_DESC, VPO24_DESC);
1817	SIG_EXPR_DECL_SINGLE(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC);
1818	SIG_EXPR_LIST_DECL_DUAL(N19, VPOR0, VPO24, VPOOFF1);
1819	PIN_DECL_2(N19, GPIOAB0, ROMA18, VPOR0);
1820
1821	#define M18 217
1822	#define M18_DESC SIG_DESC_SET(SCUA8, 1)
1823	SIG_EXPR_DECL_SINGLE(ROMA19, ROM8, M18_DESC, VPO_OFF_12);
1824	SIG_EXPR_DECL_SINGLE(ROMA19, ROM16, M18_DESC, VPO_OFF_12);
1825	SIG_EXPR_LIST_DECL_DUAL(M18, ROMA19, ROM8, ROM16);
1826	SIG_EXPR_DECL_SINGLE(VPOR1, VPO24, M18_DESC, VPO24_DESC);
1827	SIG_EXPR_DECL_SINGLE(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC);
1828	SIG_EXPR_LIST_DECL_DUAL(M18, VPOR1, VPO24, VPOOFF1);
1829	PIN_DECL_2(M18, GPIOAB1, ROMA19, VPOR1);
1830
1831	#define N22 218
1832	#define N22_DESC SIG_DESC_SET(SCUA8, 2)
1833	SIG_EXPR_DECL_SINGLE(ROMA20, ROM8, N22_DESC, VPO_OFF_12);
1834	SIG_EXPR_DECL_SINGLE(ROMA20, ROM16, N22_DESC, VPO_OFF_12);
1835	SIG_EXPR_LIST_DECL_DUAL(N22, ROMA20, ROM8, ROM16);
1836	SIG_EXPR_DECL_SINGLE(VPOR2, VPO24, N22_DESC, VPO24_DESC);
1837	SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC);
1838	SIG_EXPR_LIST_DECL_DUAL(N22, VPOR2, VPO24, VPOOFF1);
1839	PIN_DECL_2(N22, GPIOAB2, ROMA20, VPOR2);
1840
1841	#define N20 219
1842	#define N20_DESC SIG_DESC_SET(SCUA8, 3)
1843	SIG_EXPR_DECL_SINGLE(ROMA21, ROM8, N20_DESC, VPO_OFF_12);
1844	SIG_EXPR_DECL_SINGLE(ROMA21, ROM16, N20_DESC, VPO_OFF_12);
1845	SIG_EXPR_LIST_DECL_DUAL(N20, ROMA21, ROM8, ROM16);
1846	SIG_EXPR_DECL_SINGLE(VPOR3, VPO24, N20_DESC, VPO24_DESC);
1847	SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC);
1848	SIG_EXPR_LIST_DECL_DUAL(N20, VPOR3, VPO24, VPOOFF1);
1849	PIN_DECL_2(N20, GPIOAB3, ROMA21, VPOR3);
1850
1851	FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
1852	U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18,
1853	L19, L20, L21, T18, N18, N19, M18, N22, N20);
1854	FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
1855	A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
1856	P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18,
1857	N18, N19, M18, N22, N20);
1858	FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
1859	M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22,
1860	N20);
1861	FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
1862	P20, P21, P22, M19, M20, M21, M22, L18, L19);
1863
1864	#define USB11H2_DESC SIG_DESC_SET(SCU90, 3)
1865	#define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0)
1866
1867	#define K4 220
1868	SIG_EXPR_LIST_DECL_SINGLE(K4, USB11HDP2, USB11H2, USB11H2_DESC);
1869	SIG_EXPR_LIST_DECL_SINGLE(K4, USB11DP1, USB11D1, USB11D1_DESC);
1870	PIN_DECL_(K4, SIG_EXPR_LIST_PTR(K4, USB11HDP2),
1871	SIG_EXPR_LIST_PTR(K4, USB11DP1));
1872
1873	#define K3 221
1874	SIG_EXPR_LIST_DECL_SINGLE(K3, USB11HDN1, USB11H2, USB11H2_DESC);
1875	SIG_EXPR_LIST_DECL_SINGLE(K3, USB11DDN1, USB11D1, USB11D1_DESC);
1876	PIN_DECL_(K3, SIG_EXPR_LIST_PTR(K3, USB11HDN1),
1877	SIG_EXPR_LIST_PTR(K3, USB11DDN1));
1878
1879	FUNC_GROUP_DECL(USB11H2, K4, K3);
1880	FUNC_GROUP_DECL(USB11D1, K4, K3);
1881
1882	#define USB2H1_DESC SIG_DESC_SET(SCU90, 29)
1883	#define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0)
1884
1885	#define AB21 222
1886	SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2HDP1, USB2H1, USB2H1_DESC);
1887	SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2DDP1, USB2D1, USB2D1_DESC);
1888	PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, USB2HDP1),
1889	SIG_EXPR_LIST_PTR(AB21, USB2DDP1));
1890
1891	#define AB20 223
1892	SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2HDN1, USB2H1, USB2H1_DESC);
1893	SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2DDN1, USB2D1, USB2D1_DESC);
1894	PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, USB2HDN1),
1895	SIG_EXPR_LIST_PTR(AB20, USB2DDN1));
1896
1897	FUNC_GROUP_DECL(USB2H1, AB21, AB20);
1898	FUNC_GROUP_DECL(USB2D1, AB21, AB20);
1899
1900	/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
1901	* pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
1902	*/
1903	#define ASPEED_G4_NR_PINS 224
1904
1905	/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
1906
1907	static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
1908	ASPEED_PINCTRL_PIN(A1),
1909	ASPEED_PINCTRL_PIN(A10),
1910	ASPEED_PINCTRL_PIN(A11),
1911	ASPEED_PINCTRL_PIN(A12),
1912	ASPEED_PINCTRL_PIN(A13),
1913	ASPEED_PINCTRL_PIN(A14),
1914	ASPEED_PINCTRL_PIN(A15),
1915	ASPEED_PINCTRL_PIN(A16),
1916	ASPEED_PINCTRL_PIN(A17),
1917	ASPEED_PINCTRL_PIN(A18),
1918	ASPEED_PINCTRL_PIN(A19),
1919	ASPEED_PINCTRL_PIN(A2),
1920	ASPEED_PINCTRL_PIN(A20),
1921	ASPEED_PINCTRL_PIN(A3),
1922	ASPEED_PINCTRL_PIN(A4),
1923	ASPEED_PINCTRL_PIN(A5),
1924	ASPEED_PINCTRL_PIN(A6),
1925	ASPEED_PINCTRL_PIN(A7),
1926	ASPEED_PINCTRL_PIN(A8),
1927	ASPEED_PINCTRL_PIN(A9),
1928	ASPEED_PINCTRL_PIN(AA1),
1929	ASPEED_PINCTRL_PIN(AA2),
1930	ASPEED_PINCTRL_PIN(AA22),
1931	ASPEED_PINCTRL_PIN(AA3),
1932	ASPEED_PINCTRL_PIN(AA4),
1933	ASPEED_PINCTRL_PIN(AA5),
1934	ASPEED_PINCTRL_PIN(AA6),
1935	ASPEED_PINCTRL_PIN(AA7),
1936	ASPEED_PINCTRL_PIN(AB1),
1937	ASPEED_PINCTRL_PIN(AB2),
1938	ASPEED_PINCTRL_PIN(AB3),
1939	ASPEED_PINCTRL_PIN(AB4),
1940	ASPEED_PINCTRL_PIN(AB5),
1941	ASPEED_PINCTRL_PIN(AB6),
1942	ASPEED_PINCTRL_PIN(AB7),
1943	ASPEED_PINCTRL_PIN(AB20),
1944	ASPEED_PINCTRL_PIN(AB21),
1945	ASPEED_PINCTRL_PIN(B1),
1946	ASPEED_PINCTRL_PIN(B10),
1947	ASPEED_PINCTRL_PIN(B11),
1948	ASPEED_PINCTRL_PIN(B12),
1949	ASPEED_PINCTRL_PIN(B13),
1950	ASPEED_PINCTRL_PIN(B14),
1951	ASPEED_PINCTRL_PIN(B15),
1952	ASPEED_PINCTRL_PIN(B16),
1953	ASPEED_PINCTRL_PIN(B17),
1954	ASPEED_PINCTRL_PIN(B18),
1955	ASPEED_PINCTRL_PIN(B19),
1956	ASPEED_PINCTRL_PIN(B2),
1957	ASPEED_PINCTRL_PIN(B22),
1958	ASPEED_PINCTRL_PIN(B3),
1959	ASPEED_PINCTRL_PIN(B4),
1960	ASPEED_PINCTRL_PIN(B5),
1961	ASPEED_PINCTRL_PIN(B6),
1962	ASPEED_PINCTRL_PIN(B7),
1963	ASPEED_PINCTRL_PIN(B9),
1964	ASPEED_PINCTRL_PIN(C1),
1965	ASPEED_PINCTRL_PIN(C10),
1966	ASPEED_PINCTRL_PIN(C11),
1967	ASPEED_PINCTRL_PIN(C12),
1968	ASPEED_PINCTRL_PIN(C13),
1969	ASPEED_PINCTRL_PIN(C14),
1970	ASPEED_PINCTRL_PIN(C15),
1971	ASPEED_PINCTRL_PIN(C16),
1972	ASPEED_PINCTRL_PIN(C17),
1973	ASPEED_PINCTRL_PIN(C18),
1974	ASPEED_PINCTRL_PIN(C2),
1975	ASPEED_PINCTRL_PIN(C20),
1976	ASPEED_PINCTRL_PIN(C21),
1977	ASPEED_PINCTRL_PIN(C22),
1978	ASPEED_PINCTRL_PIN(C3),
1979	ASPEED_PINCTRL_PIN(C4),
1980	ASPEED_PINCTRL_PIN(C5),
1981	ASPEED_PINCTRL_PIN(C6),
1982	ASPEED_PINCTRL_PIN(C7),
1983	ASPEED_PINCTRL_PIN(C8),
1984	ASPEED_PINCTRL_PIN(C9),
1985	ASPEED_PINCTRL_PIN(D1),
1986	ASPEED_PINCTRL_PIN(D10),
1987	ASPEED_PINCTRL_PIN(D11),
1988	ASPEED_PINCTRL_PIN(D12),
1989	ASPEED_PINCTRL_PIN(D13),
1990	ASPEED_PINCTRL_PIN(D14),
1991	ASPEED_PINCTRL_PIN(D15),
1992	ASPEED_PINCTRL_PIN(D16),
1993	ASPEED_PINCTRL_PIN(D17),
1994	ASPEED_PINCTRL_PIN(D18),
1995	ASPEED_PINCTRL_PIN(D19),
1996	ASPEED_PINCTRL_PIN(D2),
1997	ASPEED_PINCTRL_PIN(D3),
1998	ASPEED_PINCTRL_PIN(D4),
1999	ASPEED_PINCTRL_PIN(D5),
2000	ASPEED_PINCTRL_PIN(D6),
2001	ASPEED_PINCTRL_PIN(D7),
2002	ASPEED_PINCTRL_PIN(D8),
2003	ASPEED_PINCTRL_PIN(D9),
2004	ASPEED_PINCTRL_PIN(E10),
2005	ASPEED_PINCTRL_PIN(E11),
2006	ASPEED_PINCTRL_PIN(E12),
2007	ASPEED_PINCTRL_PIN(E13),
2008	ASPEED_PINCTRL_PIN(E14),
2009	ASPEED_PINCTRL_PIN(E15),
2010	ASPEED_PINCTRL_PIN(E16),
2011	ASPEED_PINCTRL_PIN(E18),
2012	ASPEED_PINCTRL_PIN(E19),
2013	ASPEED_PINCTRL_PIN(E2),
2014	ASPEED_PINCTRL_PIN(E20),
2015	ASPEED_PINCTRL_PIN(E3),
2016	ASPEED_PINCTRL_PIN(E5),
2017	ASPEED_PINCTRL_PIN(E6),
2018	ASPEED_PINCTRL_PIN(E7),
2019	ASPEED_PINCTRL_PIN(E8),
2020	ASPEED_PINCTRL_PIN(E9),
2021	ASPEED_PINCTRL_PIN(F18),
2022	ASPEED_PINCTRL_PIN(F20),
2023	ASPEED_PINCTRL_PIN(F3),
2024	ASPEED_PINCTRL_PIN(F4),
2025	ASPEED_PINCTRL_PIN(F5),
2026	ASPEED_PINCTRL_PIN(G18),
2027	ASPEED_PINCTRL_PIN(G19),
2028	ASPEED_PINCTRL_PIN(G20),
2029	ASPEED_PINCTRL_PIN(G5),
2030	ASPEED_PINCTRL_PIN(H1),
2031	ASPEED_PINCTRL_PIN(H18),
2032	ASPEED_PINCTRL_PIN(H19),
2033	ASPEED_PINCTRL_PIN(H2),
2034	ASPEED_PINCTRL_PIN(H20),
2035	ASPEED_PINCTRL_PIN(H3),
2036	ASPEED_PINCTRL_PIN(H4),
2037	ASPEED_PINCTRL_PIN(J20),
2038	ASPEED_PINCTRL_PIN(J21),
2039	ASPEED_PINCTRL_PIN(J3),
2040	ASPEED_PINCTRL_PIN(J4),
2041	ASPEED_PINCTRL_PIN(J5),
2042	ASPEED_PINCTRL_PIN(K18),
2043	ASPEED_PINCTRL_PIN(K20),
2044	ASPEED_PINCTRL_PIN(K3),
2045	ASPEED_PINCTRL_PIN(K4),
2046	ASPEED_PINCTRL_PIN(K5),
2047	ASPEED_PINCTRL_PIN(L1),
2048	ASPEED_PINCTRL_PIN(L18),
2049	ASPEED_PINCTRL_PIN(L19),
2050	ASPEED_PINCTRL_PIN(L2),
2051	ASPEED_PINCTRL_PIN(L20),
2052	ASPEED_PINCTRL_PIN(L21),
2053	ASPEED_PINCTRL_PIN(L22),
2054	ASPEED_PINCTRL_PIN(L3),
2055	ASPEED_PINCTRL_PIN(L4),
2056	ASPEED_PINCTRL_PIN(L5),
2057	ASPEED_PINCTRL_PIN(M1),
2058	ASPEED_PINCTRL_PIN(M18),
2059	ASPEED_PINCTRL_PIN(M19),
2060	ASPEED_PINCTRL_PIN(M2),
2061	ASPEED_PINCTRL_PIN(M20),
2062	ASPEED_PINCTRL_PIN(M21),
2063	ASPEED_PINCTRL_PIN(M22),
2064	ASPEED_PINCTRL_PIN(M3),
2065	ASPEED_PINCTRL_PIN(M4),
2066	ASPEED_PINCTRL_PIN(M5),
2067	ASPEED_PINCTRL_PIN(N1),
2068	ASPEED_PINCTRL_PIN(N18),
2069	ASPEED_PINCTRL_PIN(N19),
2070	ASPEED_PINCTRL_PIN(N2),
2071	ASPEED_PINCTRL_PIN(N20),
2072	ASPEED_PINCTRL_PIN(N21),
2073	ASPEED_PINCTRL_PIN(N22),
2074	ASPEED_PINCTRL_PIN(N3),
2075	ASPEED_PINCTRL_PIN(N4),
2076	ASPEED_PINCTRL_PIN(N5),
2077	ASPEED_PINCTRL_PIN(P18),
2078	ASPEED_PINCTRL_PIN(P19),
2079	ASPEED_PINCTRL_PIN(P20),
2080	ASPEED_PINCTRL_PIN(P21),
2081	ASPEED_PINCTRL_PIN(P22),
2082	ASPEED_PINCTRL_PIN(P5),
2083	ASPEED_PINCTRL_PIN(R18),
2084	ASPEED_PINCTRL_PIN(R22),
2085	ASPEED_PINCTRL_PIN(T1),
2086	ASPEED_PINCTRL_PIN(T18),
2087	ASPEED_PINCTRL_PIN(T19),
2088	ASPEED_PINCTRL_PIN(T2),
2089	ASPEED_PINCTRL_PIN(T4),
2090	ASPEED_PINCTRL_PIN(T5),
2091	ASPEED_PINCTRL_PIN(U1),
2092	ASPEED_PINCTRL_PIN(U18),
2093	ASPEED_PINCTRL_PIN(U19),
2094	ASPEED_PINCTRL_PIN(U2),
2095	ASPEED_PINCTRL_PIN(U20),
2096	ASPEED_PINCTRL_PIN(U21),
2097	ASPEED_PINCTRL_PIN(U3),
2098	ASPEED_PINCTRL_PIN(U4),
2099	ASPEED_PINCTRL_PIN(U5),
2100	ASPEED_PINCTRL_PIN(V1),
2101	ASPEED_PINCTRL_PIN(V2),
2102	ASPEED_PINCTRL_PIN(V20),
2103	ASPEED_PINCTRL_PIN(V21),
2104	ASPEED_PINCTRL_PIN(V22),
2105	ASPEED_PINCTRL_PIN(V3),
2106	ASPEED_PINCTRL_PIN(V4),
2107	ASPEED_PINCTRL_PIN(V5),
2108	ASPEED_PINCTRL_PIN(V6),
2109	ASPEED_PINCTRL_PIN(V7),
2110	ASPEED_PINCTRL_PIN(W1),
2111	ASPEED_PINCTRL_PIN(W2),
2112	ASPEED_PINCTRL_PIN(W21),
2113	ASPEED_PINCTRL_PIN(W22),
2114	ASPEED_PINCTRL_PIN(W3),
2115	ASPEED_PINCTRL_PIN(W4),
2116	ASPEED_PINCTRL_PIN(W5),
2117	ASPEED_PINCTRL_PIN(W6),
2118	ASPEED_PINCTRL_PIN(W7),
2119	ASPEED_PINCTRL_PIN(Y1),
2120	ASPEED_PINCTRL_PIN(Y2),
2121	ASPEED_PINCTRL_PIN(Y21),
2122	ASPEED_PINCTRL_PIN(Y22),
2123	ASPEED_PINCTRL_PIN(Y3),
2124	ASPEED_PINCTRL_PIN(Y4),
2125	ASPEED_PINCTRL_PIN(Y5),
2126	ASPEED_PINCTRL_PIN(Y6),
2127	ASPEED_PINCTRL_PIN(Y7),
2128	};
2129
2130	static const struct aspeed_pin_group aspeed_g4_groups[] = {
2131	ASPEED_PINCTRL_GROUP(ACPI),
2132	ASPEED_PINCTRL_GROUP(ADC0),
2133	ASPEED_PINCTRL_GROUP(ADC1),
2134	ASPEED_PINCTRL_GROUP(ADC10),
2135	ASPEED_PINCTRL_GROUP(ADC11),
2136	ASPEED_PINCTRL_GROUP(ADC12),
2137	ASPEED_PINCTRL_GROUP(ADC13),
2138	ASPEED_PINCTRL_GROUP(ADC14),
2139	ASPEED_PINCTRL_GROUP(ADC15),
2140	ASPEED_PINCTRL_GROUP(ADC2),
2141	ASPEED_PINCTRL_GROUP(ADC3),
2142	ASPEED_PINCTRL_GROUP(ADC4),
2143	ASPEED_PINCTRL_GROUP(ADC5),
2144	ASPEED_PINCTRL_GROUP(ADC6),
2145	ASPEED_PINCTRL_GROUP(ADC7),
2146	ASPEED_PINCTRL_GROUP(ADC8),
2147	ASPEED_PINCTRL_GROUP(ADC9),
2148	ASPEED_PINCTRL_GROUP(BMCINT),
2149	ASPEED_PINCTRL_GROUP(DDCCLK),
2150	ASPEED_PINCTRL_GROUP(DDCDAT),
2151	ASPEED_PINCTRL_GROUP(EXTRST),
2152	ASPEED_PINCTRL_GROUP(FLACK),
2153	ASPEED_PINCTRL_GROUP(FLBUSY),
2154	ASPEED_PINCTRL_GROUP(FLWP),
2155	ASPEED_PINCTRL_GROUP(GPID),
2156	ASPEED_PINCTRL_GROUP(GPID0),
2157	ASPEED_PINCTRL_GROUP(GPID2),
2158	ASPEED_PINCTRL_GROUP(GPID4),
2159	ASPEED_PINCTRL_GROUP(GPID6),
2160	ASPEED_PINCTRL_GROUP(GPIE0),
2161	ASPEED_PINCTRL_GROUP(GPIE2),
2162	ASPEED_PINCTRL_GROUP(GPIE4),
2163	ASPEED_PINCTRL_GROUP(GPIE6),
2164	ASPEED_PINCTRL_GROUP(I2C10),
2165	ASPEED_PINCTRL_GROUP(I2C11),
2166	ASPEED_PINCTRL_GROUP(I2C12),
2167	ASPEED_PINCTRL_GROUP(I2C13),
2168	ASPEED_PINCTRL_GROUP(I2C14),
2169	ASPEED_PINCTRL_GROUP(I2C3),
2170	ASPEED_PINCTRL_GROUP(I2C4),
2171	ASPEED_PINCTRL_GROUP(I2C5),
2172	ASPEED_PINCTRL_GROUP(I2C6),
2173	ASPEED_PINCTRL_GROUP(I2C7),
2174	ASPEED_PINCTRL_GROUP(I2C8),
2175	ASPEED_PINCTRL_GROUP(I2C9),
2176	ASPEED_PINCTRL_GROUP(LPCPD),
2177	ASPEED_PINCTRL_GROUP(LPCPME),
2178	ASPEED_PINCTRL_GROUP(LPCRST),
2179	ASPEED_PINCTRL_GROUP(LPCSMI),
2180	ASPEED_PINCTRL_GROUP(MAC1LINK),
2181	ASPEED_PINCTRL_GROUP(MAC2LINK),
2182	ASPEED_PINCTRL_GROUP(MDIO1),
2183	ASPEED_PINCTRL_GROUP(MDIO2),
2184	ASPEED_PINCTRL_GROUP(NCTS1),
2185	ASPEED_PINCTRL_GROUP(NCTS2),
2186	ASPEED_PINCTRL_GROUP(NCTS3),
2187	ASPEED_PINCTRL_GROUP(NCTS4),
2188	ASPEED_PINCTRL_GROUP(NDCD1),
2189	ASPEED_PINCTRL_GROUP(NDCD2),
2190	ASPEED_PINCTRL_GROUP(NDCD3),
2191	ASPEED_PINCTRL_GROUP(NDCD4),
2192	ASPEED_PINCTRL_GROUP(NDSR1),
2193	ASPEED_PINCTRL_GROUP(NDSR2),
2194	ASPEED_PINCTRL_GROUP(NDSR3),
2195	ASPEED_PINCTRL_GROUP(NDSR4),
2196	ASPEED_PINCTRL_GROUP(NDTR1),
2197	ASPEED_PINCTRL_GROUP(NDTR2),
2198	ASPEED_PINCTRL_GROUP(NDTR3),
2199	ASPEED_PINCTRL_GROUP(NDTR4),
2200	ASPEED_PINCTRL_GROUP(NDTS4),
2201	ASPEED_PINCTRL_GROUP(NRI1),
2202	ASPEED_PINCTRL_GROUP(NRI2),
2203	ASPEED_PINCTRL_GROUP(NRI3),
2204	ASPEED_PINCTRL_GROUP(NRI4),
2205	ASPEED_PINCTRL_GROUP(NRTS1),
2206	ASPEED_PINCTRL_GROUP(NRTS2),
2207	ASPEED_PINCTRL_GROUP(NRTS3),
2208	ASPEED_PINCTRL_GROUP(OSCCLK),
2209	ASPEED_PINCTRL_GROUP(PWM0),
2210	ASPEED_PINCTRL_GROUP(PWM1),
2211	ASPEED_PINCTRL_GROUP(PWM2),
2212	ASPEED_PINCTRL_GROUP(PWM3),
2213	ASPEED_PINCTRL_GROUP(PWM4),
2214	ASPEED_PINCTRL_GROUP(PWM5),
2215	ASPEED_PINCTRL_GROUP(PWM6),
2216	ASPEED_PINCTRL_GROUP(PWM7),
2217	ASPEED_PINCTRL_GROUP(RGMII1),
2218	ASPEED_PINCTRL_GROUP(RGMII2),
2219	ASPEED_PINCTRL_GROUP(RMII1),
2220	ASPEED_PINCTRL_GROUP(RMII2),
2221	ASPEED_PINCTRL_GROUP(ROM16),
2222	ASPEED_PINCTRL_GROUP(ROM8),
2223	ASPEED_PINCTRL_GROUP(ROMCS1),
2224	ASPEED_PINCTRL_GROUP(ROMCS2),
2225	ASPEED_PINCTRL_GROUP(ROMCS3),
2226	ASPEED_PINCTRL_GROUP(ROMCS4),
2227	ASPEED_PINCTRL_GROUP(RXD1),
2228	ASPEED_PINCTRL_GROUP(RXD2),
2229	ASPEED_PINCTRL_GROUP(RXD3),
2230	ASPEED_PINCTRL_GROUP(RXD4),
2231	ASPEED_PINCTRL_GROUP(SALT1),
2232	ASPEED_PINCTRL_GROUP(SALT2),
2233	ASPEED_PINCTRL_GROUP(SALT3),
2234	ASPEED_PINCTRL_GROUP(SALT4),
2235	ASPEED_PINCTRL_GROUP(SD1),
2236	ASPEED_PINCTRL_GROUP(SD2),
2237	ASPEED_PINCTRL_GROUP(SGPMCK),
2238	ASPEED_PINCTRL_GROUP(SGPMI),
2239	ASPEED_PINCTRL_GROUP(SGPMLD),
2240	ASPEED_PINCTRL_GROUP(SGPMO),
2241	ASPEED_PINCTRL_GROUP(SGPSCK),
2242	ASPEED_PINCTRL_GROUP(SGPSI0),
2243	ASPEED_PINCTRL_GROUP(SGPSI1),
2244	ASPEED_PINCTRL_GROUP(SGPSLD),
2245	ASPEED_PINCTRL_GROUP(SIOONCTRL),
2246	ASPEED_PINCTRL_GROUP(SIOPBI),
2247	ASPEED_PINCTRL_GROUP(SIOPBO),
2248	ASPEED_PINCTRL_GROUP(SIOPWREQ),
2249	ASPEED_PINCTRL_GROUP(SIOPWRGD),
2250	ASPEED_PINCTRL_GROUP(SIOS3),
2251	ASPEED_PINCTRL_GROUP(SIOS5),
2252	ASPEED_PINCTRL_GROUP(SIOSCI),
2253	ASPEED_PINCTRL_GROUP(SPI1),
2254	ASPEED_PINCTRL_GROUP(SPI1DEBUG),
2255	ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
2256	ASPEED_PINCTRL_GROUP(SPICS1),
2257	ASPEED_PINCTRL_GROUP(TIMER3),
2258	ASPEED_PINCTRL_GROUP(TIMER4),
2259	ASPEED_PINCTRL_GROUP(TIMER5),
2260	ASPEED_PINCTRL_GROUP(TIMER6),
2261	ASPEED_PINCTRL_GROUP(TIMER7),
2262	ASPEED_PINCTRL_GROUP(TIMER8),
2263	ASPEED_PINCTRL_GROUP(TXD1),
2264	ASPEED_PINCTRL_GROUP(TXD2),
2265	ASPEED_PINCTRL_GROUP(TXD3),
2266	ASPEED_PINCTRL_GROUP(TXD4),
2267	ASPEED_PINCTRL_GROUP(UART6),
2268	ASPEED_PINCTRL_GROUP(USB11D1),
2269	ASPEED_PINCTRL_GROUP(USB11H2),
2270	ASPEED_PINCTRL_GROUP(USB2D1),
2271	ASPEED_PINCTRL_GROUP(USB2H1),
2272	ASPEED_PINCTRL_GROUP(USBCKI),
2273	ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
2274	ASPEED_PINCTRL_GROUP(VGAHS),
2275	ASPEED_PINCTRL_GROUP(VGAVS),
2276	ASPEED_PINCTRL_GROUP(VPI18),
2277	ASPEED_PINCTRL_GROUP(VPI24),
2278	ASPEED_PINCTRL_GROUP(VPI30),
2279	ASPEED_PINCTRL_GROUP(VPO12),
2280	ASPEED_PINCTRL_GROUP(VPO24),
2281	ASPEED_PINCTRL_GROUP(WDTRST1),
2282	ASPEED_PINCTRL_GROUP(WDTRST2),
2283	};
2284
2285	static const struct aspeed_pin_function aspeed_g4_functions[] = {
2286	ASPEED_PINCTRL_FUNC(ACPI),
2287	ASPEED_PINCTRL_FUNC(ADC0),
2288	ASPEED_PINCTRL_FUNC(ADC1),
2289	ASPEED_PINCTRL_FUNC(ADC10),
2290	ASPEED_PINCTRL_FUNC(ADC11),
2291	ASPEED_PINCTRL_FUNC(ADC12),
2292	ASPEED_PINCTRL_FUNC(ADC13),
2293	ASPEED_PINCTRL_FUNC(ADC14),
2294	ASPEED_PINCTRL_FUNC(ADC15),
2295	ASPEED_PINCTRL_FUNC(ADC2),
2296	ASPEED_PINCTRL_FUNC(ADC3),
2297	ASPEED_PINCTRL_FUNC(ADC4),
2298	ASPEED_PINCTRL_FUNC(ADC5),
2299	ASPEED_PINCTRL_FUNC(ADC6),
2300	ASPEED_PINCTRL_FUNC(ADC7),
2301	ASPEED_PINCTRL_FUNC(ADC8),
2302	ASPEED_PINCTRL_FUNC(ADC9),
2303	ASPEED_PINCTRL_FUNC(BMCINT),
2304	ASPEED_PINCTRL_FUNC(DDCCLK),
2305	ASPEED_PINCTRL_FUNC(DDCDAT),
2306	ASPEED_PINCTRL_FUNC(EXTRST),
2307	ASPEED_PINCTRL_FUNC(FLACK),
2308	ASPEED_PINCTRL_FUNC(FLBUSY),
2309	ASPEED_PINCTRL_FUNC(FLWP),
2310	ASPEED_PINCTRL_FUNC(GPID),
2311	ASPEED_PINCTRL_FUNC(GPID0),
2312	ASPEED_PINCTRL_FUNC(GPID2),
2313	ASPEED_PINCTRL_FUNC(GPID4),
2314	ASPEED_PINCTRL_FUNC(GPID6),
2315	ASPEED_PINCTRL_FUNC(GPIE0),
2316	ASPEED_PINCTRL_FUNC(GPIE2),
2317	ASPEED_PINCTRL_FUNC(GPIE4),
2318	ASPEED_PINCTRL_FUNC(GPIE6),
2319	ASPEED_PINCTRL_FUNC(I2C10),
2320	ASPEED_PINCTRL_FUNC(I2C11),
2321	ASPEED_PINCTRL_FUNC(I2C12),
2322	ASPEED_PINCTRL_FUNC(I2C13),
2323	ASPEED_PINCTRL_FUNC(I2C14),
2324	ASPEED_PINCTRL_FUNC(I2C3),
2325	ASPEED_PINCTRL_FUNC(I2C4),
2326	ASPEED_PINCTRL_FUNC(I2C5),
2327	ASPEED_PINCTRL_FUNC(I2C6),
2328	ASPEED_PINCTRL_FUNC(I2C7),
2329	ASPEED_PINCTRL_FUNC(I2C8),
2330	ASPEED_PINCTRL_FUNC(I2C9),
2331	ASPEED_PINCTRL_FUNC(LPCPD),
2332	ASPEED_PINCTRL_FUNC(LPCPME),
2333	ASPEED_PINCTRL_FUNC(LPCRST),
2334	ASPEED_PINCTRL_FUNC(LPCSMI),
2335	ASPEED_PINCTRL_FUNC(MAC1LINK),
2336	ASPEED_PINCTRL_FUNC(MAC2LINK),
2337	ASPEED_PINCTRL_FUNC(MDIO1),
2338	ASPEED_PINCTRL_FUNC(MDIO2),
2339	ASPEED_PINCTRL_FUNC(NCTS1),
2340	ASPEED_PINCTRL_FUNC(NCTS2),
2341	ASPEED_PINCTRL_FUNC(NCTS3),
2342	ASPEED_PINCTRL_FUNC(NCTS4),
2343	ASPEED_PINCTRL_FUNC(NDCD1),
2344	ASPEED_PINCTRL_FUNC(NDCD2),
2345	ASPEED_PINCTRL_FUNC(NDCD3),
2346	ASPEED_PINCTRL_FUNC(NDCD4),
2347	ASPEED_PINCTRL_FUNC(NDSR1),
2348	ASPEED_PINCTRL_FUNC(NDSR2),
2349	ASPEED_PINCTRL_FUNC(NDSR3),
2350	ASPEED_PINCTRL_FUNC(NDSR4),
2351	ASPEED_PINCTRL_FUNC(NDTR1),
2352	ASPEED_PINCTRL_FUNC(NDTR2),
2353	ASPEED_PINCTRL_FUNC(NDTR3),
2354	ASPEED_PINCTRL_FUNC(NDTR4),
2355	ASPEED_PINCTRL_FUNC(NDTS4),
2356	ASPEED_PINCTRL_FUNC(NRI1),
2357	ASPEED_PINCTRL_FUNC(NRI2),
2358	ASPEED_PINCTRL_FUNC(NRI3),
2359	ASPEED_PINCTRL_FUNC(NRI4),
2360	ASPEED_PINCTRL_FUNC(NRTS1),
2361	ASPEED_PINCTRL_FUNC(NRTS2),
2362	ASPEED_PINCTRL_FUNC(NRTS3),
2363	ASPEED_PINCTRL_FUNC(OSCCLK),
2364	ASPEED_PINCTRL_FUNC(PWM0),
2365	ASPEED_PINCTRL_FUNC(PWM1),
2366	ASPEED_PINCTRL_FUNC(PWM2),
2367	ASPEED_PINCTRL_FUNC(PWM3),
2368	ASPEED_PINCTRL_FUNC(PWM4),
2369	ASPEED_PINCTRL_FUNC(PWM5),
2370	ASPEED_PINCTRL_FUNC(PWM6),
2371	ASPEED_PINCTRL_FUNC(PWM7),
2372	ASPEED_PINCTRL_FUNC(RGMII1),
2373	ASPEED_PINCTRL_FUNC(RGMII2),
2374	ASPEED_PINCTRL_FUNC(RMII1),
2375	ASPEED_PINCTRL_FUNC(RMII2),
2376	ASPEED_PINCTRL_FUNC(ROM16),
2377	ASPEED_PINCTRL_FUNC(ROM8),
2378	ASPEED_PINCTRL_FUNC(ROMCS1),
2379	ASPEED_PINCTRL_FUNC(ROMCS2),
2380	ASPEED_PINCTRL_FUNC(ROMCS3),
2381	ASPEED_PINCTRL_FUNC(ROMCS4),
2382	ASPEED_PINCTRL_FUNC(RXD1),
2383	ASPEED_PINCTRL_FUNC(RXD2),
2384	ASPEED_PINCTRL_FUNC(RXD3),
2385	ASPEED_PINCTRL_FUNC(RXD4),
2386	ASPEED_PINCTRL_FUNC(SALT1),
2387	ASPEED_PINCTRL_FUNC(SALT2),
2388	ASPEED_PINCTRL_FUNC(SALT3),
2389	ASPEED_PINCTRL_FUNC(SALT4),
2390	ASPEED_PINCTRL_FUNC(SD1),
2391	ASPEED_PINCTRL_FUNC(SD2),
2392	ASPEED_PINCTRL_FUNC(SGPMCK),
2393	ASPEED_PINCTRL_FUNC(SGPMI),
2394	ASPEED_PINCTRL_FUNC(SGPMLD),
2395	ASPEED_PINCTRL_FUNC(SGPMO),
2396	ASPEED_PINCTRL_FUNC(SGPSCK),
2397	ASPEED_PINCTRL_FUNC(SGPSI0),
2398	ASPEED_PINCTRL_FUNC(SGPSI1),
2399	ASPEED_PINCTRL_FUNC(SGPSLD),
2400	ASPEED_PINCTRL_FUNC(SIOONCTRL),
2401	ASPEED_PINCTRL_FUNC(SIOPBI),
2402	ASPEED_PINCTRL_FUNC(SIOPBO),
2403	ASPEED_PINCTRL_FUNC(SIOPWREQ),
2404	ASPEED_PINCTRL_FUNC(SIOPWRGD),
2405	ASPEED_PINCTRL_FUNC(SIOS3),
2406	ASPEED_PINCTRL_FUNC(SIOS5),
2407	ASPEED_PINCTRL_FUNC(SIOSCI),
2408	ASPEED_PINCTRL_FUNC(SPI1),
2409	ASPEED_PINCTRL_FUNC(SPI1DEBUG),
2410	ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
2411	ASPEED_PINCTRL_FUNC(SPICS1),
2412	ASPEED_PINCTRL_FUNC(TIMER3),
2413	ASPEED_PINCTRL_FUNC(TIMER4),
2414	ASPEED_PINCTRL_FUNC(TIMER5),
2415	ASPEED_PINCTRL_FUNC(TIMER6),
2416	ASPEED_PINCTRL_FUNC(TIMER7),
2417	ASPEED_PINCTRL_FUNC(TIMER8),
2418	ASPEED_PINCTRL_FUNC(TXD1),
2419	ASPEED_PINCTRL_FUNC(TXD2),
2420	ASPEED_PINCTRL_FUNC(TXD3),
2421	ASPEED_PINCTRL_FUNC(TXD4),
2422	ASPEED_PINCTRL_FUNC(UART6),
2423	ASPEED_PINCTRL_FUNC(USB11D1),
2424	ASPEED_PINCTRL_FUNC(USB11H2),
2425	ASPEED_PINCTRL_FUNC(USB2D1),
2426	ASPEED_PINCTRL_FUNC(USB2H1),
2427	ASPEED_PINCTRL_FUNC(USBCKI),
2428	ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
2429	ASPEED_PINCTRL_FUNC(VGAHS),
2430	ASPEED_PINCTRL_FUNC(VGAVS),
2431	ASPEED_PINCTRL_FUNC(VPI18),
2432	ASPEED_PINCTRL_FUNC(VPI24),
2433	ASPEED_PINCTRL_FUNC(VPI30),
2434	ASPEED_PINCTRL_FUNC(VPO12),
2435	ASPEED_PINCTRL_FUNC(VPO24),
2436	ASPEED_PINCTRL_FUNC(WDTRST1),
2437	ASPEED_PINCTRL_FUNC(WDTRST2),
2438	};
2439
2440	static const struct aspeed_pin_config aspeed_g4_configs[] = {
2441	/* GPIO banks ranges [A, B], [D, J], [M, R] */
2442	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
2443	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
2444	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17),
2445	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17),
2446	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19),
2447	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19),
2448	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
2449	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
2450	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21),
2451	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21),
2452	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22),
2453	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22),
2454	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
2455	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
2456	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24),
2457	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24),
2458	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
2459	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
2460	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26),
2461	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26),
2462	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27),
2463	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27),
2464	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28),
2465	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28),
2466	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29),
2467	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29),
2468	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30),
2469	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30),
2470	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31),
2471	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31),
2472
2473	/* GPIOs T[0-5] (RGMII1 Tx pins) */
2474	ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
2475	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
2476	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12),
2477
2478	/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2479	ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11),
2480	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14),
2481	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14),
2482
2483	/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2484	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
2485	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
2486
2487	/* GPIOs V[2-7] (RGMII2 Rx pins) */
2488	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
2489	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
2490
2491	/* ADC pull-downs (SCUA8[19:4]) */
2492	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4),
2493	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4),
2494	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5),
2495	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5),
2496	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6),
2497	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6),
2498	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
2499	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
2500	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
2501	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
2502	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9),
2503	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9),
2504	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10),
2505	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10),
2506	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11),
2507	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11),
2508	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
2509	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
2510	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
2511	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
2512	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14),
2513	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14),
2514	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
2515	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
2516	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16),
2517	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16),
2518	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
2519	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
2520	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
2521	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
2522	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19),
2523	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19),
2524
2525	/*
2526	* Debounce settings for GPIOs D and E passthrough mode are in
2527	* SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
2528	* banks D and E is handled by the GPIO driver - GPIO passthrough is
2529	* treated like any other non-GPIO mux function. There is a catch
2530	* however, in that the debounce period is configured in the GPIO
2531	* controller. Due to this tangle between GPIO and pinctrl we don't yet
2532	* fully support pass-through debounce.
2533	*/
2534	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20),
2535	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21),
2536	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22),
2537	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23),
2538	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
2539	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
2540	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26),
2541	ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27),
2542	};
2543
2544	static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
2545	const struct aspeed_sig_expr *expr,
2546	bool enable)
2547	{
2548	int ret;
2549	int i;
2550
2551	for (i = 0; i < expr->ndescs; i++) {
2552	const struct aspeed_sig_desc *desc = &expr->descs[i];
2553	u32 pattern = enable ? desc->enable : desc->disable;
2554	u32 val = (pattern << __ffs(desc->mask));
2555
2556	if (!ctx->maps[desc->ip])
2557	return -ENODEV;
2558
2559	/*
2560	* Strap registers are configured in hardware or by early-boot
2561	* firmware. Treat them as read-only despite that we can write
2562	* them. This may mean that certain functions cannot be
2563	* deconfigured and is the reason we re-evaluate after writing
2564	* all descriptor bits.
2565	*
2566	* We make two exceptions to the read-only rule:
2567	*
2568	* - The passthrough mode of GPIO ports D and E are commonly
2569	* used with front-panel buttons to allow normal operation
2570	* of the host if the BMC is powered off or fails to boot.
2571	* Once the BMC has booted, the loopback mode must be
2572	* disabled for the BMC to control host power-on and reset.
2573	*
2574	* - The operating mode of the SPI1 interface is simply
2575	* strapped incorrectly on some systems and requires a
2576	* software fixup, which we allow to be done via pinctrl.
2577	*/
2578	if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
2579	!(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12))))
2580	continue;
2581
2582	if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
2583	continue;
2584
2585	ret = regmap_update_bits(map: ctx->maps[desc->ip], reg: desc->reg,
2586	mask: desc->mask, val);
2587
2588	if (ret)
2589	return ret;
2590	}
2591
2592	ret = aspeed_sig_expr_eval(ctx, expr, enabled: enable);
2593	if (ret < 0)
2594	return ret;
2595
2596	if (!ret)
2597	return -EPERM;
2598
2599	return 0;
2600	}
2601
2602	static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = {
2603	{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
2604	{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2605	{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2606	{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
2607	{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
2608	};
2609
2610	static const struct aspeed_pinmux_ops aspeed_g4_ops = {
2611	.set = aspeed_g4_sig_expr_set,
2612	};
2613
2614	static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
2615	.pins = aspeed_g4_pins,
2616	.npins = ARRAY_SIZE(aspeed_g4_pins),
2617	.pinmux = {
2618	.ops = &aspeed_g4_ops,
2619	.groups = aspeed_g4_groups,
2620	.ngroups = ARRAY_SIZE(aspeed_g4_groups),
2621	.functions = aspeed_g4_functions,
2622	.nfunctions = ARRAY_SIZE(aspeed_g4_functions),
2623	},
2624	.configs = aspeed_g4_configs,
2625	.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
2626	.confmaps = aspeed_g4_pin_config_map,
2627	.nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map),
2628	};
2629
2630	static const struct pinmux_ops aspeed_g4_pinmux_ops = {
2631	.get_functions_count = aspeed_pinmux_get_fn_count,
2632	.get_function_name = aspeed_pinmux_get_fn_name,
2633	.get_function_groups = aspeed_pinmux_get_fn_groups,
2634	.set_mux = aspeed_pinmux_set_mux,
2635	.gpio_request_enable = aspeed_gpio_request_enable,
2636	.strict = true,
2637	};
2638
2639	static const struct pinctrl_ops aspeed_g4_pinctrl_ops = {
2640	.get_groups_count = aspeed_pinctrl_get_groups_count,
2641	.get_group_name = aspeed_pinctrl_get_group_name,
2642	.get_group_pins = aspeed_pinctrl_get_group_pins,
2643	.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
2644	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2645	.dt_free_map = pinctrl_utils_free_map,
2646	};
2647
2648	static const struct pinconf_ops aspeed_g4_conf_ops = {
2649	.is_generic = true,
2650	.pin_config_get = aspeed_pin_config_get,
2651	.pin_config_set = aspeed_pin_config_set,
2652	.pin_config_group_get = aspeed_pin_config_group_get,
2653	.pin_config_group_set = aspeed_pin_config_group_set,
2654	};
2655
2656	static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
2657	.name = "aspeed-g4-pinctrl",
2658	.pins = aspeed_g4_pins,
2659	.npins = ARRAY_SIZE(aspeed_g4_pins),
2660	.pctlops = &aspeed_g4_pinctrl_ops,
2661	.pmxops = &aspeed_g4_pinmux_ops,
2662	.confops = &aspeed_g4_conf_ops,
2663	};
2664
2665	static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
2666	{
2667	int i;
2668
2669	for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++)
2670	aspeed_g4_pins[i].number = i;
2671
2672	return aspeed_pinctrl_probe(pdev, pdesc: &aspeed_g4_pinctrl_desc,
2673	pdata: &aspeed_g4_pinctrl_data);
2674	}
2675
2676	static const struct of_device_id aspeed_g4_pinctrl_of_match[] = {
2677	{ .compatible = "aspeed,ast2400-pinctrl", },
2678	/*
2679	* The aspeed,g4-pinctrl compatible has been removed the from the
2680	* bindings, but keep the match in case of old devicetrees.
2681	*/
2682	{ .compatible = "aspeed,g4-pinctrl", },
2683	{ },
2684	};
2685
2686	static struct platform_driver aspeed_g4_pinctrl_driver = {
2687	.probe = aspeed_g4_pinctrl_probe,
2688	.driver = {
2689	.name = "aspeed-g4-pinctrl",
2690	.of_match_table = aspeed_g4_pinctrl_of_match,
2691	},
2692	};
2693
2694	static int aspeed_g4_pinctrl_init(void)
2695	{
2696	return platform_driver_register(&aspeed_g4_pinctrl_driver);
2697	}
2698
2699	arch_initcall(aspeed_g4_pinctrl_init);
2700