1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // |
3 | // Core driver for the imx pin controller |
4 | // |
5 | // Copyright (C) 2012 Freescale Semiconductor, Inc. |
6 | // Copyright (C) 2012 Linaro Ltd. |
7 | // |
8 | // Author: Dong Aisheng <dong.aisheng@linaro.org> |
9 | |
10 | #include <linux/err.h> |
11 | #include <linux/init.h> |
12 | #include <linux/io.h> |
13 | #include <linux/mfd/syscon.h> |
14 | #include <linux/module.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/regmap.h> |
19 | #include <linux/seq_file.h> |
20 | #include <linux/slab.h> |
21 | |
22 | #include <linux/pinctrl/machine.h> |
23 | #include <linux/pinctrl/pinconf.h> |
24 | #include <linux/pinctrl/pinctrl.h> |
25 | #include <linux/pinctrl/pinmux.h> |
26 | |
27 | #include "../core.h" |
28 | #include "../pinconf.h" |
29 | #include "../pinmux.h" |
30 | #include "pinctrl-imx.h" |
31 | |
32 | /* The bits in CONFIG cell defined in binding doc*/ |
33 | #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ |
34 | #define IMX_PAD_SION 0x40000000 /* set SION */ |
35 | |
36 | static inline const struct group_desc *imx_pinctrl_find_group_by_name( |
37 | struct pinctrl_dev *pctldev, |
38 | const char *name) |
39 | { |
40 | const struct group_desc *grp = NULL; |
41 | int i; |
42 | |
43 | for (i = 0; i < pctldev->num_groups; i++) { |
44 | grp = pinctrl_generic_get_group(pctldev, group_selector: i); |
45 | if (grp && !strcmp(grp->grp.name, name)) |
46 | break; |
47 | } |
48 | |
49 | return grp; |
50 | } |
51 | |
52 | static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
53 | unsigned offset) |
54 | { |
55 | seq_printf(m: s, fmt: "%s" , dev_name(dev: pctldev->dev)); |
56 | } |
57 | |
58 | static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, |
59 | struct device_node *np, |
60 | struct pinctrl_map **map, unsigned *num_maps) |
61 | { |
62 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
63 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
64 | const struct group_desc *grp; |
65 | struct pinctrl_map *new_map; |
66 | struct device_node *parent; |
67 | struct imx_pin *pin; |
68 | int map_num = 1; |
69 | int i, j; |
70 | |
71 | /* |
72 | * first find the group of this node and check if we need create |
73 | * config maps for pins |
74 | */ |
75 | grp = imx_pinctrl_find_group_by_name(pctldev, name: np->name); |
76 | if (!grp) { |
77 | dev_err(ipctl->dev, "unable to find group for node %pOFn\n" , np); |
78 | return -EINVAL; |
79 | } |
80 | |
81 | if (info->flags & IMX_USE_SCU) { |
82 | map_num += grp->grp.npins; |
83 | } else { |
84 | for (i = 0; i < grp->grp.npins; i++) { |
85 | pin = &((struct imx_pin *)(grp->data))[i]; |
86 | if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) |
87 | map_num++; |
88 | } |
89 | } |
90 | |
91 | new_map = kmalloc_array(n: map_num, size: sizeof(struct pinctrl_map), |
92 | GFP_KERNEL); |
93 | if (!new_map) |
94 | return -ENOMEM; |
95 | |
96 | *map = new_map; |
97 | *num_maps = map_num; |
98 | |
99 | /* create mux map */ |
100 | parent = of_get_parent(node: np); |
101 | if (!parent) { |
102 | kfree(objp: new_map); |
103 | return -EINVAL; |
104 | } |
105 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
106 | new_map[0].data.mux.function = parent->name; |
107 | new_map[0].data.mux.group = np->name; |
108 | of_node_put(node: parent); |
109 | |
110 | /* create config map */ |
111 | new_map++; |
112 | for (i = j = 0; i < grp->grp.npins; i++) { |
113 | pin = &((struct imx_pin *)(grp->data))[i]; |
114 | |
115 | /* |
116 | * We only create config maps for SCU pads or MMIO pads that |
117 | * are not using the default config(a.k.a IMX_NO_PAD_CTL) |
118 | */ |
119 | if (!(info->flags & IMX_USE_SCU) && |
120 | (pin->conf.mmio.config & IMX_NO_PAD_CTL)) |
121 | continue; |
122 | |
123 | new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; |
124 | new_map[j].data.configs.group_or_pin = |
125 | pin_get_name(pctldev, pin: pin->pin); |
126 | |
127 | if (info->flags & IMX_USE_SCU) { |
128 | /* |
129 | * For SCU case, we set mux and conf together |
130 | * in one IPC call |
131 | */ |
132 | new_map[j].data.configs.configs = |
133 | (unsigned long *)&pin->conf.scu; |
134 | new_map[j].data.configs.num_configs = 2; |
135 | } else { |
136 | new_map[j].data.configs.configs = |
137 | &pin->conf.mmio.config; |
138 | new_map[j].data.configs.num_configs = 1; |
139 | } |
140 | |
141 | j++; |
142 | } |
143 | |
144 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n" , |
145 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
146 | |
147 | return 0; |
148 | } |
149 | |
150 | static void imx_dt_free_map(struct pinctrl_dev *pctldev, |
151 | struct pinctrl_map *map, unsigned num_maps) |
152 | { |
153 | kfree(objp: map); |
154 | } |
155 | |
156 | static const struct pinctrl_ops imx_pctrl_ops = { |
157 | .get_groups_count = pinctrl_generic_get_group_count, |
158 | .get_group_name = pinctrl_generic_get_group_name, |
159 | .get_group_pins = pinctrl_generic_get_group_pins, |
160 | .pin_dbg_show = imx_pin_dbg_show, |
161 | .dt_node_to_map = imx_dt_node_to_map, |
162 | .dt_free_map = imx_dt_free_map, |
163 | }; |
164 | |
165 | static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, |
166 | struct imx_pin *pin) |
167 | { |
168 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
169 | struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; |
170 | const struct imx_pin_reg *pin_reg; |
171 | unsigned int pin_id; |
172 | |
173 | pin_id = pin->pin; |
174 | pin_reg = &ipctl->pin_regs[pin_id]; |
175 | |
176 | if (pin_reg->mux_reg == -1) { |
177 | dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n" , |
178 | info->pins[pin_id].name); |
179 | return 0; |
180 | } |
181 | |
182 | if (info->flags & SHARE_MUX_CONF_REG) { |
183 | u32 reg; |
184 | |
185 | reg = readl(addr: ipctl->base + pin_reg->mux_reg); |
186 | reg &= ~info->mux_mask; |
187 | reg |= (pin_mmio->mux_mode << info->mux_shift); |
188 | writel(val: reg, addr: ipctl->base + pin_reg->mux_reg); |
189 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n" , |
190 | pin_reg->mux_reg, reg); |
191 | } else { |
192 | writel(val: pin_mmio->mux_mode, addr: ipctl->base + pin_reg->mux_reg); |
193 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n" , |
194 | pin_reg->mux_reg, pin_mmio->mux_mode); |
195 | } |
196 | |
197 | /* |
198 | * If the select input value begins with 0xff, it's a quirky |
199 | * select input and the value should be interpreted as below. |
200 | * 31 23 15 7 0 |
201 | * | 0xff | shift | width | select | |
202 | * It's used to work around the problem that the select |
203 | * input for some pin is not implemented in the select |
204 | * input register but in some general purpose register. |
205 | * We encode the select input value, width and shift of |
206 | * the bit field into input_val cell of pin function ID |
207 | * in device tree, and then decode them here for setting |
208 | * up the select input bits in general purpose register. |
209 | */ |
210 | if (pin_mmio->input_val >> 24 == 0xff) { |
211 | u32 val = pin_mmio->input_val; |
212 | u8 select = val & 0xff; |
213 | u8 width = (val >> 8) & 0xff; |
214 | u8 shift = (val >> 16) & 0xff; |
215 | u32 mask = ((1 << width) - 1) << shift; |
216 | /* |
217 | * The input_reg[i] here is actually some IOMUXC general |
218 | * purpose register, not regular select input register. |
219 | */ |
220 | val = readl(addr: ipctl->base + pin_mmio->input_reg); |
221 | val &= ~mask; |
222 | val |= select << shift; |
223 | writel(val, addr: ipctl->base + pin_mmio->input_reg); |
224 | } else if (pin_mmio->input_reg) { |
225 | /* |
226 | * Regular select input register can never be at offset |
227 | * 0, and we only print register value for regular case. |
228 | */ |
229 | if (ipctl->input_sel_base) |
230 | writel(val: pin_mmio->input_val, addr: ipctl->input_sel_base + |
231 | pin_mmio->input_reg); |
232 | else |
233 | writel(val: pin_mmio->input_val, addr: ipctl->base + |
234 | pin_mmio->input_reg); |
235 | dev_dbg(ipctl->dev, |
236 | "==>select_input: offset 0x%x val 0x%x\n" , |
237 | pin_mmio->input_reg, pin_mmio->input_val); |
238 | } |
239 | |
240 | return 0; |
241 | } |
242 | |
243 | static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
244 | unsigned group) |
245 | { |
246 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
247 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
248 | struct function_desc *func; |
249 | struct group_desc *grp; |
250 | struct imx_pin *pin; |
251 | unsigned int npins; |
252 | int i, err; |
253 | |
254 | /* |
255 | * Configure the mux mode for each pin in the group for a specific |
256 | * function. |
257 | */ |
258 | grp = pinctrl_generic_get_group(pctldev, group_selector: group); |
259 | if (!grp) |
260 | return -EINVAL; |
261 | |
262 | func = pinmux_generic_get_function(pctldev, selector); |
263 | if (!func) |
264 | return -EINVAL; |
265 | |
266 | npins = grp->grp.npins; |
267 | |
268 | dev_dbg(ipctl->dev, "enable function %s group %s\n" , |
269 | func->name, grp->grp.name); |
270 | |
271 | for (i = 0; i < npins; i++) { |
272 | /* |
273 | * For IMX_USE_SCU case, we postpone the mux setting |
274 | * until config is set as we can set them together |
275 | * in one IPC call |
276 | */ |
277 | pin = &((struct imx_pin *)(grp->data))[i]; |
278 | if (!(info->flags & IMX_USE_SCU)) { |
279 | err = imx_pmx_set_one_pin_mmio(ipctl, pin); |
280 | if (err) |
281 | return err; |
282 | } |
283 | } |
284 | |
285 | return 0; |
286 | } |
287 | |
288 | struct pinmux_ops imx_pmx_ops = { |
289 | .get_functions_count = pinmux_generic_get_function_count, |
290 | .get_function_name = pinmux_generic_get_function_name, |
291 | .get_function_groups = pinmux_generic_get_function_groups, |
292 | .set_mux = imx_pmx_set, |
293 | }; |
294 | |
295 | static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, |
296 | unsigned long *config) |
297 | { |
298 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
299 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
300 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; |
301 | |
302 | if (pin_reg->conf_reg == -1) { |
303 | dev_err(ipctl->dev, "Pin(%s) does not support config function\n" , |
304 | info->pins[pin_id].name); |
305 | return -EINVAL; |
306 | } |
307 | |
308 | *config = readl(addr: ipctl->base + pin_reg->conf_reg); |
309 | |
310 | if (info->flags & SHARE_MUX_CONF_REG) |
311 | *config &= ~info->mux_mask; |
312 | |
313 | return 0; |
314 | } |
315 | |
316 | static int imx_pinconf_get(struct pinctrl_dev *pctldev, |
317 | unsigned pin_id, unsigned long *config) |
318 | { |
319 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
320 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
321 | |
322 | if (info->flags & IMX_USE_SCU) |
323 | return info->imx_pinconf_get(pctldev, pin_id, config); |
324 | else |
325 | return imx_pinconf_get_mmio(pctldev, pin_id, config); |
326 | } |
327 | |
328 | static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, |
329 | unsigned pin_id, unsigned long *configs, |
330 | unsigned num_configs) |
331 | { |
332 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
333 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
334 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; |
335 | int i; |
336 | |
337 | if (pin_reg->conf_reg == -1) { |
338 | dev_err(ipctl->dev, "Pin(%s) does not support config function\n" , |
339 | info->pins[pin_id].name); |
340 | return -EINVAL; |
341 | } |
342 | |
343 | dev_dbg(ipctl->dev, "pinconf set pin %s\n" , |
344 | info->pins[pin_id].name); |
345 | |
346 | for (i = 0; i < num_configs; i++) { |
347 | if (info->flags & SHARE_MUX_CONF_REG) { |
348 | u32 reg; |
349 | reg = readl(addr: ipctl->base + pin_reg->conf_reg); |
350 | reg &= info->mux_mask; |
351 | reg |= configs[i]; |
352 | writel(val: reg, addr: ipctl->base + pin_reg->conf_reg); |
353 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n" , |
354 | pin_reg->conf_reg, reg); |
355 | } else { |
356 | writel(val: configs[i], addr: ipctl->base + pin_reg->conf_reg); |
357 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n" , |
358 | pin_reg->conf_reg, configs[i]); |
359 | } |
360 | } /* for each config */ |
361 | |
362 | return 0; |
363 | } |
364 | |
365 | static int imx_pinconf_set(struct pinctrl_dev *pctldev, |
366 | unsigned pin_id, unsigned long *configs, |
367 | unsigned num_configs) |
368 | { |
369 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
370 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
371 | |
372 | if (info->flags & IMX_USE_SCU) |
373 | return info->imx_pinconf_set(pctldev, pin_id, |
374 | configs, num_configs); |
375 | else |
376 | return imx_pinconf_set_mmio(pctldev, pin_id, |
377 | configs, num_configs); |
378 | } |
379 | |
380 | static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
381 | struct seq_file *s, unsigned pin_id) |
382 | { |
383 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); |
384 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
385 | const struct imx_pin_reg *pin_reg; |
386 | unsigned long config; |
387 | int ret; |
388 | |
389 | if (info->flags & IMX_USE_SCU) { |
390 | ret = info->imx_pinconf_get(pctldev, pin_id, &config); |
391 | if (ret) { |
392 | dev_err(ipctl->dev, "failed to get %s pinconf\n" , |
393 | pin_get_name(pctldev, pin_id)); |
394 | seq_puts(m: s, s: "N/A" ); |
395 | return; |
396 | } |
397 | } else { |
398 | pin_reg = &ipctl->pin_regs[pin_id]; |
399 | if (pin_reg->conf_reg == -1) { |
400 | seq_puts(m: s, s: "N/A" ); |
401 | return; |
402 | } |
403 | |
404 | config = readl(addr: ipctl->base + pin_reg->conf_reg); |
405 | } |
406 | |
407 | seq_printf(m: s, fmt: "0x%lx" , config); |
408 | } |
409 | |
410 | static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
411 | struct seq_file *s, unsigned group) |
412 | { |
413 | struct group_desc *grp; |
414 | unsigned long config; |
415 | const char *name; |
416 | int i, ret; |
417 | |
418 | if (group >= pctldev->num_groups) |
419 | return; |
420 | |
421 | seq_puts(m: s, s: "\n" ); |
422 | grp = pinctrl_generic_get_group(pctldev, group_selector: group); |
423 | if (!grp) |
424 | return; |
425 | |
426 | for (i = 0; i < grp->grp.npins; i++) { |
427 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; |
428 | |
429 | name = pin_get_name(pctldev, pin: pin->pin); |
430 | ret = imx_pinconf_get(pctldev, pin_id: pin->pin, config: &config); |
431 | if (ret) |
432 | return; |
433 | seq_printf(m: s, fmt: " %s: 0x%lx\n" , name, config); |
434 | } |
435 | } |
436 | |
437 | static const struct pinconf_ops imx_pinconf_ops = { |
438 | .pin_config_get = imx_pinconf_get, |
439 | .pin_config_set = imx_pinconf_set, |
440 | .pin_config_dbg_show = imx_pinconf_dbg_show, |
441 | .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, |
442 | }; |
443 | |
444 | /* |
445 | * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID |
446 | * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. |
447 | * |
448 | * PIN_FUNC_ID format: |
449 | * Default: |
450 | * <mux_reg conf_reg input_reg mux_mode input_val> |
451 | * SHARE_MUX_CONF_REG: |
452 | * <mux_conf_reg input_reg mux_mode input_val> |
453 | * IMX_USE_SCU: |
454 | * <pin_id mux_mode> |
455 | */ |
456 | #define FSL_PIN_SIZE 24 |
457 | #define FSL_PIN_SHARE_SIZE 20 |
458 | #define FSL_SCU_PIN_SIZE 12 |
459 | |
460 | static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, |
461 | unsigned int *pin_id, struct imx_pin *pin, |
462 | const __be32 **list_p, |
463 | struct device_node *np) |
464 | { |
465 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
466 | struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; |
467 | struct imx_pin_reg *pin_reg; |
468 | const __be32 *list = *list_p; |
469 | u32 mux_reg, conf_reg; |
470 | u32 config; |
471 | |
472 | mux_reg = be32_to_cpu(*list++); |
473 | |
474 | if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) |
475 | mux_reg = -1; |
476 | |
477 | if (info->flags & SHARE_MUX_CONF_REG) { |
478 | conf_reg = mux_reg; |
479 | } else { |
480 | conf_reg = be32_to_cpu(*list++); |
481 | if (!conf_reg) |
482 | conf_reg = -1; |
483 | } |
484 | |
485 | *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; |
486 | pin_reg = &ipctl->pin_regs[*pin_id]; |
487 | pin->pin = *pin_id; |
488 | pin_reg->mux_reg = mux_reg; |
489 | pin_reg->conf_reg = conf_reg; |
490 | pin_mmio->input_reg = be32_to_cpu(*list++); |
491 | pin_mmio->mux_mode = be32_to_cpu(*list++); |
492 | pin_mmio->input_val = be32_to_cpu(*list++); |
493 | |
494 | config = be32_to_cpu(*list++); |
495 | |
496 | /* SION bit is in mux register */ |
497 | if (config & IMX_PAD_SION) |
498 | pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; |
499 | pin_mmio->config = config & ~IMX_PAD_SION; |
500 | |
501 | *list_p = list; |
502 | |
503 | dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx" , info->pins[*pin_id].name, |
504 | pin_mmio->mux_mode, pin_mmio->config); |
505 | } |
506 | |
507 | static int imx_pinctrl_parse_groups(struct device_node *np, |
508 | struct group_desc *grp, |
509 | struct imx_pinctrl *ipctl, |
510 | u32 index) |
511 | { |
512 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
513 | struct imx_pin *pin; |
514 | unsigned int *pins; |
515 | int size, pin_size; |
516 | const __be32 *list; |
517 | int i; |
518 | |
519 | dev_dbg(ipctl->dev, "group(%d): %pOFn\n" , index, np); |
520 | |
521 | if (info->flags & IMX_USE_SCU) |
522 | pin_size = FSL_SCU_PIN_SIZE; |
523 | else if (info->flags & SHARE_MUX_CONF_REG) |
524 | pin_size = FSL_PIN_SHARE_SIZE; |
525 | else |
526 | pin_size = FSL_PIN_SIZE; |
527 | |
528 | /* Initialise group */ |
529 | grp->grp.name = np->name; |
530 | |
531 | /* |
532 | * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, |
533 | * do sanity check and calculate pins number |
534 | * |
535 | * First try legacy 'fsl,pins' property, then fall back to the |
536 | * generic 'pinmux'. |
537 | * |
538 | * Note: for generic 'pinmux' case, there's no CONFIG part in |
539 | * the binding format. |
540 | */ |
541 | list = of_get_property(node: np, name: "fsl,pins" , lenp: &size); |
542 | if (!list) { |
543 | list = of_get_property(node: np, name: "pinmux" , lenp: &size); |
544 | if (!list) { |
545 | dev_err(ipctl->dev, |
546 | "no fsl,pins and pins property in node %pOF\n" , np); |
547 | return -EINVAL; |
548 | } |
549 | } |
550 | |
551 | /* we do not check return since it's safe node passed down */ |
552 | if (!size || size % pin_size) { |
553 | dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n" , np); |
554 | return -EINVAL; |
555 | } |
556 | |
557 | grp->grp.npins = size / pin_size; |
558 | grp->data = devm_kcalloc(dev: ipctl->dev, n: grp->grp.npins, size: sizeof(*pin), GFP_KERNEL); |
559 | if (!grp->data) |
560 | return -ENOMEM; |
561 | |
562 | pins = devm_kcalloc(dev: ipctl->dev, n: grp->grp.npins, size: sizeof(*pins), GFP_KERNEL); |
563 | if (!pins) |
564 | return -ENOMEM; |
565 | grp->grp.pins = pins; |
566 | |
567 | for (i = 0; i < grp->grp.npins; i++) { |
568 | pin = &((struct imx_pin *)(grp->data))[i]; |
569 | if (info->flags & IMX_USE_SCU) |
570 | info->imx_pinctrl_parse_pin(ipctl, &pins[i], pin, &list); |
571 | else |
572 | imx_pinctrl_parse_pin_mmio(ipctl, pin_id: &pins[i], pin, list_p: &list, np); |
573 | } |
574 | |
575 | return 0; |
576 | } |
577 | |
578 | static int imx_pinctrl_parse_functions(struct device_node *np, |
579 | struct imx_pinctrl *ipctl, |
580 | u32 index) |
581 | { |
582 | struct pinctrl_dev *pctl = ipctl->pctl; |
583 | struct device_node *child; |
584 | struct function_desc *func; |
585 | struct group_desc *grp; |
586 | const char **group_names; |
587 | u32 i; |
588 | |
589 | dev_dbg(pctl->dev, "parse function(%d): %pOFn\n" , index, np); |
590 | |
591 | func = pinmux_generic_get_function(pctldev: pctl, selector: index); |
592 | if (!func) |
593 | return -EINVAL; |
594 | |
595 | /* Initialise function */ |
596 | func->name = np->name; |
597 | func->num_group_names = of_get_child_count(np); |
598 | if (func->num_group_names == 0) { |
599 | dev_info(ipctl->dev, "no groups defined in %pOF\n" , np); |
600 | return -EINVAL; |
601 | } |
602 | |
603 | group_names = devm_kcalloc(dev: ipctl->dev, n: func->num_group_names, |
604 | size: sizeof(char *), GFP_KERNEL); |
605 | if (!group_names) |
606 | return -ENOMEM; |
607 | i = 0; |
608 | for_each_child_of_node(np, child) |
609 | group_names[i++] = child->name; |
610 | func->group_names = group_names; |
611 | |
612 | i = 0; |
613 | for_each_child_of_node(np, child) { |
614 | grp = devm_kzalloc(dev: ipctl->dev, size: sizeof(*grp), GFP_KERNEL); |
615 | if (!grp) { |
616 | of_node_put(node: child); |
617 | return -ENOMEM; |
618 | } |
619 | |
620 | mutex_lock(&ipctl->mutex); |
621 | radix_tree_insert(&pctl->pin_group_tree, |
622 | index: ipctl->group_index++, grp); |
623 | mutex_unlock(lock: &ipctl->mutex); |
624 | |
625 | imx_pinctrl_parse_groups(np: child, grp, ipctl, index: i++); |
626 | } |
627 | |
628 | return 0; |
629 | } |
630 | |
631 | /* |
632 | * Check if the DT contains pins in the direct child nodes. This indicates the |
633 | * newer DT format to store pins. This function returns true if the first found |
634 | * fsl,pins property is in a child of np. Otherwise false is returned. |
635 | */ |
636 | static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) |
637 | { |
638 | struct device_node *function_np; |
639 | struct device_node *pinctrl_np; |
640 | |
641 | for_each_child_of_node(np, function_np) { |
642 | if (of_property_read_bool(np: function_np, propname: "fsl,pins" )) { |
643 | of_node_put(node: function_np); |
644 | return true; |
645 | } |
646 | |
647 | for_each_child_of_node(function_np, pinctrl_np) { |
648 | if (of_property_read_bool(np: pinctrl_np, propname: "fsl,pins" )) { |
649 | of_node_put(node: pinctrl_np); |
650 | of_node_put(node: function_np); |
651 | return false; |
652 | } |
653 | } |
654 | } |
655 | |
656 | return true; |
657 | } |
658 | |
659 | static int imx_pinctrl_probe_dt(struct platform_device *pdev, |
660 | struct imx_pinctrl *ipctl) |
661 | { |
662 | struct device_node *np = pdev->dev.of_node; |
663 | struct device_node *child; |
664 | struct pinctrl_dev *pctl = ipctl->pctl; |
665 | u32 nfuncs = 0; |
666 | u32 i = 0; |
667 | bool flat_funcs; |
668 | |
669 | if (!np) |
670 | return -ENODEV; |
671 | |
672 | flat_funcs = imx_pinctrl_dt_is_flat_functions(np); |
673 | if (flat_funcs) { |
674 | nfuncs = 1; |
675 | } else { |
676 | nfuncs = of_get_child_count(np); |
677 | if (nfuncs == 0) { |
678 | dev_err(&pdev->dev, "no functions defined\n" ); |
679 | return -EINVAL; |
680 | } |
681 | } |
682 | |
683 | for (i = 0; i < nfuncs; i++) { |
684 | struct function_desc *function; |
685 | |
686 | function = devm_kzalloc(dev: &pdev->dev, size: sizeof(*function), |
687 | GFP_KERNEL); |
688 | if (!function) |
689 | return -ENOMEM; |
690 | |
691 | mutex_lock(&ipctl->mutex); |
692 | radix_tree_insert(&pctl->pin_function_tree, index: i, function); |
693 | mutex_unlock(lock: &ipctl->mutex); |
694 | } |
695 | pctl->num_functions = nfuncs; |
696 | |
697 | ipctl->group_index = 0; |
698 | if (flat_funcs) { |
699 | pctl->num_groups = of_get_child_count(np); |
700 | } else { |
701 | pctl->num_groups = 0; |
702 | for_each_child_of_node(np, child) |
703 | pctl->num_groups += of_get_child_count(np: child); |
704 | } |
705 | |
706 | if (flat_funcs) { |
707 | imx_pinctrl_parse_functions(np, ipctl, index: 0); |
708 | } else { |
709 | i = 0; |
710 | for_each_child_of_node(np, child) |
711 | imx_pinctrl_parse_functions(np: child, ipctl, index: i++); |
712 | } |
713 | |
714 | return 0; |
715 | } |
716 | |
717 | int imx_pinctrl_probe(struct platform_device *pdev, |
718 | const struct imx_pinctrl_soc_info *info) |
719 | { |
720 | struct regmap_config config = { .name = "gpr" }; |
721 | struct device_node *dev_np = pdev->dev.of_node; |
722 | struct pinctrl_desc *imx_pinctrl_desc; |
723 | struct device_node *np; |
724 | struct imx_pinctrl *ipctl; |
725 | struct regmap *gpr; |
726 | int ret, i; |
727 | |
728 | if (!info || !info->pins || !info->npins) { |
729 | dev_err(&pdev->dev, "wrong pinctrl info\n" ); |
730 | return -EINVAL; |
731 | } |
732 | |
733 | if (info->gpr_compatible) { |
734 | gpr = syscon_regmap_lookup_by_compatible(s: info->gpr_compatible); |
735 | if (!IS_ERR(ptr: gpr)) |
736 | regmap_attach_dev(dev: &pdev->dev, map: gpr, config: &config); |
737 | } |
738 | |
739 | /* Create state holders etc for this driver */ |
740 | ipctl = devm_kzalloc(dev: &pdev->dev, size: sizeof(*ipctl), GFP_KERNEL); |
741 | if (!ipctl) |
742 | return -ENOMEM; |
743 | |
744 | if (!(info->flags & IMX_USE_SCU)) { |
745 | ipctl->pin_regs = devm_kmalloc_array(dev: &pdev->dev, n: info->npins, |
746 | size: sizeof(*ipctl->pin_regs), |
747 | GFP_KERNEL); |
748 | if (!ipctl->pin_regs) |
749 | return -ENOMEM; |
750 | |
751 | for (i = 0; i < info->npins; i++) { |
752 | ipctl->pin_regs[i].mux_reg = -1; |
753 | ipctl->pin_regs[i].conf_reg = -1; |
754 | } |
755 | |
756 | ipctl->base = devm_platform_ioremap_resource(pdev, index: 0); |
757 | if (IS_ERR(ptr: ipctl->base)) |
758 | return PTR_ERR(ptr: ipctl->base); |
759 | |
760 | if (of_property_read_bool(np: dev_np, propname: "fsl,input-sel" )) { |
761 | np = of_parse_phandle(np: dev_np, phandle_name: "fsl,input-sel" , index: 0); |
762 | if (!np) { |
763 | dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n" ); |
764 | return -EINVAL; |
765 | } |
766 | |
767 | ipctl->input_sel_base = of_iomap(node: np, index: 0); |
768 | of_node_put(node: np); |
769 | if (!ipctl->input_sel_base) { |
770 | dev_err(&pdev->dev, |
771 | "iomuxc input select base address not found\n" ); |
772 | return -ENOMEM; |
773 | } |
774 | } |
775 | } |
776 | |
777 | imx_pinctrl_desc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*imx_pinctrl_desc), |
778 | GFP_KERNEL); |
779 | if (!imx_pinctrl_desc) |
780 | return -ENOMEM; |
781 | |
782 | imx_pinctrl_desc->name = dev_name(dev: &pdev->dev); |
783 | imx_pinctrl_desc->pins = info->pins; |
784 | imx_pinctrl_desc->npins = info->npins; |
785 | imx_pinctrl_desc->pctlops = &imx_pctrl_ops; |
786 | imx_pinctrl_desc->pmxops = &imx_pmx_ops; |
787 | imx_pinctrl_desc->confops = &imx_pinconf_ops; |
788 | imx_pinctrl_desc->owner = THIS_MODULE; |
789 | |
790 | /* platform specific callback */ |
791 | imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; |
792 | |
793 | mutex_init(&ipctl->mutex); |
794 | |
795 | ipctl->info = info; |
796 | ipctl->dev = &pdev->dev; |
797 | platform_set_drvdata(pdev, data: ipctl); |
798 | ret = devm_pinctrl_register_and_init(dev: &pdev->dev, |
799 | pctldesc: imx_pinctrl_desc, driver_data: ipctl, |
800 | pctldev: &ipctl->pctl); |
801 | if (ret) { |
802 | dev_err(&pdev->dev, "could not register IMX pinctrl driver\n" ); |
803 | return ret; |
804 | } |
805 | |
806 | ret = imx_pinctrl_probe_dt(pdev, ipctl); |
807 | if (ret) { |
808 | dev_err(&pdev->dev, "fail to probe dt properties\n" ); |
809 | return ret; |
810 | } |
811 | |
812 | dev_info(&pdev->dev, "initialized IMX pinctrl driver\n" ); |
813 | |
814 | return pinctrl_enable(pctldev: ipctl->pctl); |
815 | } |
816 | EXPORT_SYMBOL_GPL(imx_pinctrl_probe); |
817 | |
818 | static int __maybe_unused imx_pinctrl_suspend(struct device *dev) |
819 | { |
820 | struct imx_pinctrl *ipctl = dev_get_drvdata(dev); |
821 | |
822 | return pinctrl_force_sleep(pctldev: ipctl->pctl); |
823 | } |
824 | |
825 | static int __maybe_unused imx_pinctrl_resume(struct device *dev) |
826 | { |
827 | struct imx_pinctrl *ipctl = dev_get_drvdata(dev); |
828 | |
829 | return pinctrl_force_default(pctldev: ipctl->pctl); |
830 | } |
831 | |
832 | const struct dev_pm_ops imx_pinctrl_pm_ops = { |
833 | SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, |
834 | imx_pinctrl_resume) |
835 | }; |
836 | EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops); |
837 | |
838 | MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>" ); |
839 | MODULE_DESCRIPTION("NXP i.MX common pinctrl driver" ); |
840 | MODULE_LICENSE("GPL v2" ); |
841 | |