1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // |
3 | // i.MX1 pinctrl driver based on imx pinmux core |
4 | // |
5 | // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
6 | |
7 | #include <linux/init.h> |
8 | #include <linux/of.h> |
9 | #include <linux/platform_device.h> |
10 | #include <linux/pinctrl/pinctrl.h> |
11 | |
12 | #include "pinctrl-imx1.h" |
13 | |
14 | #define PAD_ID(port, pin) ((port) * 32 + (pin)) |
15 | #define PA 0 |
16 | #define PB 1 |
17 | #define PC 2 |
18 | #define PD 3 |
19 | |
20 | enum imx1_pads { |
21 | MX1_PAD_A24 = PAD_ID(PA, 0), |
22 | MX1_PAD_TIN = PAD_ID(PA, 1), |
23 | MX1_PAD_PWMO = PAD_ID(PA, 2), |
24 | MX1_PAD_CSI_MCLK = PAD_ID(PA, 3), |
25 | MX1_PAD_CSI_D0 = PAD_ID(PA, 4), |
26 | MX1_PAD_CSI_D1 = PAD_ID(PA, 5), |
27 | MX1_PAD_CSI_D2 = PAD_ID(PA, 6), |
28 | MX1_PAD_CSI_D3 = PAD_ID(PA, 7), |
29 | MX1_PAD_CSI_D4 = PAD_ID(PA, 8), |
30 | MX1_PAD_CSI_D5 = PAD_ID(PA, 9), |
31 | MX1_PAD_CSI_D6 = PAD_ID(PA, 10), |
32 | MX1_PAD_CSI_D7 = PAD_ID(PA, 11), |
33 | MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12), |
34 | MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13), |
35 | MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14), |
36 | MX1_PAD_I2C_SDA = PAD_ID(PA, 15), |
37 | MX1_PAD_I2C_SCL = PAD_ID(PA, 16), |
38 | MX1_PAD_DTACK = PAD_ID(PA, 17), |
39 | MX1_PAD_BCLK = PAD_ID(PA, 18), |
40 | MX1_PAD_LBA = PAD_ID(PA, 19), |
41 | MX1_PAD_ECB = PAD_ID(PA, 20), |
42 | MX1_PAD_A0 = PAD_ID(PA, 21), |
43 | MX1_PAD_CS4 = PAD_ID(PA, 22), |
44 | MX1_PAD_CS5 = PAD_ID(PA, 23), |
45 | MX1_PAD_A16 = PAD_ID(PA, 24), |
46 | MX1_PAD_A17 = PAD_ID(PA, 25), |
47 | MX1_PAD_A18 = PAD_ID(PA, 26), |
48 | MX1_PAD_A19 = PAD_ID(PA, 27), |
49 | MX1_PAD_A20 = PAD_ID(PA, 28), |
50 | MX1_PAD_A21 = PAD_ID(PA, 29), |
51 | MX1_PAD_A22 = PAD_ID(PA, 30), |
52 | MX1_PAD_A23 = PAD_ID(PA, 31), |
53 | MX1_PAD_SD_DAT0 = PAD_ID(PB, 8), |
54 | MX1_PAD_SD_DAT1 = PAD_ID(PB, 9), |
55 | MX1_PAD_SD_DAT2 = PAD_ID(PB, 10), |
56 | MX1_PAD_SD_DAT3 = PAD_ID(PB, 11), |
57 | MX1_PAD_SD_SCLK = PAD_ID(PB, 12), |
58 | MX1_PAD_SD_CMD = PAD_ID(PB, 13), |
59 | MX1_PAD_SIM_SVEN = PAD_ID(PB, 14), |
60 | MX1_PAD_SIM_PD = PAD_ID(PB, 15), |
61 | MX1_PAD_SIM_TX = PAD_ID(PB, 16), |
62 | MX1_PAD_SIM_RX = PAD_ID(PB, 17), |
63 | MX1_PAD_SIM_RST = PAD_ID(PB, 18), |
64 | MX1_PAD_SIM_CLK = PAD_ID(PB, 19), |
65 | MX1_PAD_USBD_AFE = PAD_ID(PB, 20), |
66 | MX1_PAD_USBD_OE = PAD_ID(PB, 21), |
67 | MX1_PAD_USBD_RCV = PAD_ID(PB, 22), |
68 | MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23), |
69 | MX1_PAD_USBD_VP = PAD_ID(PB, 24), |
70 | MX1_PAD_USBD_VM = PAD_ID(PB, 25), |
71 | MX1_PAD_USBD_VPO = PAD_ID(PB, 26), |
72 | MX1_PAD_USBD_VMO = PAD_ID(PB, 27), |
73 | MX1_PAD_UART2_CTS = PAD_ID(PB, 28), |
74 | MX1_PAD_UART2_RTS = PAD_ID(PB, 29), |
75 | MX1_PAD_UART2_TXD = PAD_ID(PB, 30), |
76 | MX1_PAD_UART2_RXD = PAD_ID(PB, 31), |
77 | MX1_PAD_SSI_RXFS = PAD_ID(PC, 3), |
78 | MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4), |
79 | MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5), |
80 | MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6), |
81 | MX1_PAD_SSI_TXFS = PAD_ID(PC, 7), |
82 | MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8), |
83 | MX1_PAD_UART1_CTS = PAD_ID(PC, 9), |
84 | MX1_PAD_UART1_RTS = PAD_ID(PC, 10), |
85 | MX1_PAD_UART1_TXD = PAD_ID(PC, 11), |
86 | MX1_PAD_UART1_RXD = PAD_ID(PC, 12), |
87 | MX1_PAD_SPI1_RDY = PAD_ID(PC, 13), |
88 | MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14), |
89 | MX1_PAD_SPI1_SS = PAD_ID(PC, 15), |
90 | MX1_PAD_SPI1_MISO = PAD_ID(PC, 16), |
91 | MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17), |
92 | MX1_PAD_BT13 = PAD_ID(PC, 19), |
93 | MX1_PAD_BT12 = PAD_ID(PC, 20), |
94 | MX1_PAD_BT11 = PAD_ID(PC, 21), |
95 | MX1_PAD_BT10 = PAD_ID(PC, 22), |
96 | MX1_PAD_BT9 = PAD_ID(PC, 23), |
97 | MX1_PAD_BT8 = PAD_ID(PC, 24), |
98 | MX1_PAD_BT7 = PAD_ID(PC, 25), |
99 | MX1_PAD_BT6 = PAD_ID(PC, 26), |
100 | MX1_PAD_BT5 = PAD_ID(PC, 27), |
101 | MX1_PAD_BT4 = PAD_ID(PC, 28), |
102 | MX1_PAD_BT3 = PAD_ID(PC, 29), |
103 | MX1_PAD_BT2 = PAD_ID(PC, 30), |
104 | MX1_PAD_BT1 = PAD_ID(PC, 31), |
105 | MX1_PAD_LSCLK = PAD_ID(PD, 6), |
106 | MX1_PAD_REV = PAD_ID(PD, 7), |
107 | MX1_PAD_CLS = PAD_ID(PD, 8), |
108 | MX1_PAD_PS = PAD_ID(PD, 9), |
109 | MX1_PAD_SPL_SPR = PAD_ID(PD, 10), |
110 | MX1_PAD_CONTRAST = PAD_ID(PD, 11), |
111 | MX1_PAD_ACD_OE = PAD_ID(PD, 12), |
112 | MX1_PAD_LP_HSYNC = PAD_ID(PD, 13), |
113 | MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14), |
114 | MX1_PAD_LD0 = PAD_ID(PD, 15), |
115 | MX1_PAD_LD1 = PAD_ID(PD, 16), |
116 | MX1_PAD_LD2 = PAD_ID(PD, 17), |
117 | MX1_PAD_LD3 = PAD_ID(PD, 18), |
118 | MX1_PAD_LD4 = PAD_ID(PD, 19), |
119 | MX1_PAD_LD5 = PAD_ID(PD, 20), |
120 | MX1_PAD_LD6 = PAD_ID(PD, 21), |
121 | MX1_PAD_LD7 = PAD_ID(PD, 22), |
122 | MX1_PAD_LD8 = PAD_ID(PD, 23), |
123 | MX1_PAD_LD9 = PAD_ID(PD, 24), |
124 | MX1_PAD_LD10 = PAD_ID(PD, 25), |
125 | MX1_PAD_LD11 = PAD_ID(PD, 26), |
126 | MX1_PAD_LD12 = PAD_ID(PD, 27), |
127 | MX1_PAD_LD13 = PAD_ID(PD, 28), |
128 | MX1_PAD_LD14 = PAD_ID(PD, 29), |
129 | MX1_PAD_LD15 = PAD_ID(PD, 30), |
130 | MX1_PAD_TMR2OUT = PAD_ID(PD, 31), |
131 | }; |
132 | |
133 | /* Pad names for the pinmux subsystem */ |
134 | static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = { |
135 | IMX_PINCTRL_PIN(MX1_PAD_A24), |
136 | IMX_PINCTRL_PIN(MX1_PAD_TIN), |
137 | IMX_PINCTRL_PIN(MX1_PAD_PWMO), |
138 | IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK), |
139 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D0), |
140 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D1), |
141 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D2), |
142 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D3), |
143 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D4), |
144 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D5), |
145 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D6), |
146 | IMX_PINCTRL_PIN(MX1_PAD_CSI_D7), |
147 | IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC), |
148 | IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC), |
149 | IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK), |
150 | IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA), |
151 | IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL), |
152 | IMX_PINCTRL_PIN(MX1_PAD_DTACK), |
153 | IMX_PINCTRL_PIN(MX1_PAD_BCLK), |
154 | IMX_PINCTRL_PIN(MX1_PAD_LBA), |
155 | IMX_PINCTRL_PIN(MX1_PAD_ECB), |
156 | IMX_PINCTRL_PIN(MX1_PAD_A0), |
157 | IMX_PINCTRL_PIN(MX1_PAD_CS4), |
158 | IMX_PINCTRL_PIN(MX1_PAD_CS5), |
159 | IMX_PINCTRL_PIN(MX1_PAD_A16), |
160 | IMX_PINCTRL_PIN(MX1_PAD_A17), |
161 | IMX_PINCTRL_PIN(MX1_PAD_A18), |
162 | IMX_PINCTRL_PIN(MX1_PAD_A19), |
163 | IMX_PINCTRL_PIN(MX1_PAD_A20), |
164 | IMX_PINCTRL_PIN(MX1_PAD_A21), |
165 | IMX_PINCTRL_PIN(MX1_PAD_A22), |
166 | IMX_PINCTRL_PIN(MX1_PAD_A23), |
167 | IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0), |
168 | IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1), |
169 | IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2), |
170 | IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3), |
171 | IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK), |
172 | IMX_PINCTRL_PIN(MX1_PAD_SD_CMD), |
173 | IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN), |
174 | IMX_PINCTRL_PIN(MX1_PAD_SIM_PD), |
175 | IMX_PINCTRL_PIN(MX1_PAD_SIM_TX), |
176 | IMX_PINCTRL_PIN(MX1_PAD_SIM_RX), |
177 | IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK), |
178 | IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE), |
179 | IMX_PINCTRL_PIN(MX1_PAD_USBD_OE), |
180 | IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV), |
181 | IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND), |
182 | IMX_PINCTRL_PIN(MX1_PAD_USBD_VP), |
183 | IMX_PINCTRL_PIN(MX1_PAD_USBD_VM), |
184 | IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO), |
185 | IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO), |
186 | IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS), |
187 | IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS), |
188 | IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD), |
189 | IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD), |
190 | IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS), |
191 | IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK), |
192 | IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT), |
193 | IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT), |
194 | IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS), |
195 | IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK), |
196 | IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS), |
197 | IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS), |
198 | IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD), |
199 | IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD), |
200 | IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY), |
201 | IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK), |
202 | IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS), |
203 | IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO), |
204 | IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI), |
205 | IMX_PINCTRL_PIN(MX1_PAD_BT13), |
206 | IMX_PINCTRL_PIN(MX1_PAD_BT12), |
207 | IMX_PINCTRL_PIN(MX1_PAD_BT11), |
208 | IMX_PINCTRL_PIN(MX1_PAD_BT10), |
209 | IMX_PINCTRL_PIN(MX1_PAD_BT9), |
210 | IMX_PINCTRL_PIN(MX1_PAD_BT8), |
211 | IMX_PINCTRL_PIN(MX1_PAD_BT7), |
212 | IMX_PINCTRL_PIN(MX1_PAD_BT6), |
213 | IMX_PINCTRL_PIN(MX1_PAD_BT5), |
214 | IMX_PINCTRL_PIN(MX1_PAD_BT4), |
215 | IMX_PINCTRL_PIN(MX1_PAD_BT3), |
216 | IMX_PINCTRL_PIN(MX1_PAD_BT2), |
217 | IMX_PINCTRL_PIN(MX1_PAD_BT1), |
218 | IMX_PINCTRL_PIN(MX1_PAD_LSCLK), |
219 | IMX_PINCTRL_PIN(MX1_PAD_REV), |
220 | IMX_PINCTRL_PIN(MX1_PAD_CLS), |
221 | IMX_PINCTRL_PIN(MX1_PAD_PS), |
222 | IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR), |
223 | IMX_PINCTRL_PIN(MX1_PAD_CONTRAST), |
224 | IMX_PINCTRL_PIN(MX1_PAD_ACD_OE), |
225 | IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC), |
226 | IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC), |
227 | IMX_PINCTRL_PIN(MX1_PAD_LD0), |
228 | IMX_PINCTRL_PIN(MX1_PAD_LD1), |
229 | IMX_PINCTRL_PIN(MX1_PAD_LD2), |
230 | IMX_PINCTRL_PIN(MX1_PAD_LD3), |
231 | IMX_PINCTRL_PIN(MX1_PAD_LD4), |
232 | IMX_PINCTRL_PIN(MX1_PAD_LD5), |
233 | IMX_PINCTRL_PIN(MX1_PAD_LD6), |
234 | IMX_PINCTRL_PIN(MX1_PAD_LD7), |
235 | IMX_PINCTRL_PIN(MX1_PAD_LD8), |
236 | IMX_PINCTRL_PIN(MX1_PAD_LD9), |
237 | IMX_PINCTRL_PIN(MX1_PAD_LD10), |
238 | IMX_PINCTRL_PIN(MX1_PAD_LD11), |
239 | IMX_PINCTRL_PIN(MX1_PAD_LD12), |
240 | IMX_PINCTRL_PIN(MX1_PAD_LD13), |
241 | IMX_PINCTRL_PIN(MX1_PAD_LD14), |
242 | IMX_PINCTRL_PIN(MX1_PAD_LD15), |
243 | IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT), |
244 | }; |
245 | |
246 | static struct imx1_pinctrl_soc_info imx1_pinctrl_info = { |
247 | .pins = imx1_pinctrl_pads, |
248 | .npins = ARRAY_SIZE(imx1_pinctrl_pads), |
249 | }; |
250 | |
251 | static int __init imx1_pinctrl_probe(struct platform_device *pdev) |
252 | { |
253 | return imx1_pinctrl_core_probe(pdev, info: &imx1_pinctrl_info); |
254 | } |
255 | |
256 | static const struct of_device_id imx1_pinctrl_of_match[] = { |
257 | { .compatible = "fsl,imx1-iomuxc" , }, |
258 | { } |
259 | }; |
260 | |
261 | static struct platform_driver imx1_pinctrl_driver = { |
262 | .driver = { |
263 | .name = "imx1-pinctrl" , |
264 | .of_match_table = imx1_pinctrl_of_match, |
265 | .suppress_bind_attrs = true, |
266 | }, |
267 | }; |
268 | builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe); |
269 | |