1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2016 Freescale Semiconductor, Inc.
4// Copyright (C) 2017 NXP
5//
6// Author: Dong Aisheng <aisheng.dong@nxp.com>
7
8#include <linux/err.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/mod_devicetable.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/pinctrl.h>
14
15#include "pinctrl-imx.h"
16
17enum imx7ulp_pads {
18 IMX7ULP_PAD_PTC0 = 0,
19 IMX7ULP_PAD_PTC1,
20 IMX7ULP_PAD_PTC2,
21 IMX7ULP_PAD_PTC3,
22 IMX7ULP_PAD_PTC4,
23 IMX7ULP_PAD_PTC5,
24 IMX7ULP_PAD_PTC6,
25 IMX7ULP_PAD_PTC7,
26 IMX7ULP_PAD_PTC8,
27 IMX7ULP_PAD_PTC9,
28 IMX7ULP_PAD_PTC10,
29 IMX7ULP_PAD_PTC11,
30 IMX7ULP_PAD_PTC12,
31 IMX7ULP_PAD_PTC13,
32 IMX7ULP_PAD_PTC14,
33 IMX7ULP_PAD_PTC15,
34 IMX7ULP_PAD_PTC16,
35 IMX7ULP_PAD_PTC17,
36 IMX7ULP_PAD_PTC18,
37 IMX7ULP_PAD_PTC19,
38 IMX7ULP_PAD_RESERVE0,
39 IMX7ULP_PAD_RESERVE1,
40 IMX7ULP_PAD_RESERVE2,
41 IMX7ULP_PAD_RESERVE3,
42 IMX7ULP_PAD_RESERVE4,
43 IMX7ULP_PAD_RESERVE5,
44 IMX7ULP_PAD_RESERVE6,
45 IMX7ULP_PAD_RESERVE7,
46 IMX7ULP_PAD_RESERVE8,
47 IMX7ULP_PAD_RESERVE9,
48 IMX7ULP_PAD_RESERVE10,
49 IMX7ULP_PAD_RESERVE11,
50 IMX7ULP_PAD_PTD0,
51 IMX7ULP_PAD_PTD1,
52 IMX7ULP_PAD_PTD2,
53 IMX7ULP_PAD_PTD3,
54 IMX7ULP_PAD_PTD4,
55 IMX7ULP_PAD_PTD5,
56 IMX7ULP_PAD_PTD6,
57 IMX7ULP_PAD_PTD7,
58 IMX7ULP_PAD_PTD8,
59 IMX7ULP_PAD_PTD9,
60 IMX7ULP_PAD_PTD10,
61 IMX7ULP_PAD_PTD11,
62 IMX7ULP_PAD_RESERVE12,
63 IMX7ULP_PAD_RESERVE13,
64 IMX7ULP_PAD_RESERVE14,
65 IMX7ULP_PAD_RESERVE15,
66 IMX7ULP_PAD_RESERVE16,
67 IMX7ULP_PAD_RESERVE17,
68 IMX7ULP_PAD_RESERVE18,
69 IMX7ULP_PAD_RESERVE19,
70 IMX7ULP_PAD_RESERVE20,
71 IMX7ULP_PAD_RESERVE21,
72 IMX7ULP_PAD_RESERVE22,
73 IMX7ULP_PAD_RESERVE23,
74 IMX7ULP_PAD_RESERVE24,
75 IMX7ULP_PAD_RESERVE25,
76 IMX7ULP_PAD_RESERVE26,
77 IMX7ULP_PAD_RESERVE27,
78 IMX7ULP_PAD_RESERVE28,
79 IMX7ULP_PAD_RESERVE29,
80 IMX7ULP_PAD_RESERVE30,
81 IMX7ULP_PAD_RESERVE31,
82 IMX7ULP_PAD_PTE0,
83 IMX7ULP_PAD_PTE1,
84 IMX7ULP_PAD_PTE2,
85 IMX7ULP_PAD_PTE3,
86 IMX7ULP_PAD_PTE4,
87 IMX7ULP_PAD_PTE5,
88 IMX7ULP_PAD_PTE6,
89 IMX7ULP_PAD_PTE7,
90 IMX7ULP_PAD_PTE8,
91 IMX7ULP_PAD_PTE9,
92 IMX7ULP_PAD_PTE10,
93 IMX7ULP_PAD_PTE11,
94 IMX7ULP_PAD_PTE12,
95 IMX7ULP_PAD_PTE13,
96 IMX7ULP_PAD_PTE14,
97 IMX7ULP_PAD_PTE15,
98 IMX7ULP_PAD_RESERVE32,
99 IMX7ULP_PAD_RESERVE33,
100 IMX7ULP_PAD_RESERVE34,
101 IMX7ULP_PAD_RESERVE35,
102 IMX7ULP_PAD_RESERVE36,
103 IMX7ULP_PAD_RESERVE37,
104 IMX7ULP_PAD_RESERVE38,
105 IMX7ULP_PAD_RESERVE39,
106 IMX7ULP_PAD_RESERVE40,
107 IMX7ULP_PAD_RESERVE41,
108 IMX7ULP_PAD_RESERVE42,
109 IMX7ULP_PAD_RESERVE43,
110 IMX7ULP_PAD_RESERVE44,
111 IMX7ULP_PAD_RESERVE45,
112 IMX7ULP_PAD_RESERVE46,
113 IMX7ULP_PAD_RESERVE47,
114 IMX7ULP_PAD_PTF0,
115 IMX7ULP_PAD_PTF1,
116 IMX7ULP_PAD_PTF2,
117 IMX7ULP_PAD_PTF3,
118 IMX7ULP_PAD_PTF4,
119 IMX7ULP_PAD_PTF5,
120 IMX7ULP_PAD_PTF6,
121 IMX7ULP_PAD_PTF7,
122 IMX7ULP_PAD_PTF8,
123 IMX7ULP_PAD_PTF9,
124 IMX7ULP_PAD_PTF10,
125 IMX7ULP_PAD_PTF11,
126 IMX7ULP_PAD_PTF12,
127 IMX7ULP_PAD_PTF13,
128 IMX7ULP_PAD_PTF14,
129 IMX7ULP_PAD_PTF15,
130 IMX7ULP_PAD_PTF16,
131 IMX7ULP_PAD_PTF17,
132 IMX7ULP_PAD_PTF18,
133 IMX7ULP_PAD_PTF19,
134};
135
136/* Pad names for the pinmux subsystem */
137static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
138 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
139 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
140 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
141 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
142 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
143 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
144 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
145 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
146 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
147 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
148 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
149 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
150 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
151 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
152 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
153 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
154 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
155 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
156 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
157 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
158 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
159 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
160 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
161 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
162 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
163 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
164 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
165 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
166 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
167 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
168 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
169 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
170 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
171 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
172 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
173 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
174 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
175 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
176 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
177 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
178 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
179 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
180 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
181 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
182 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
183 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
184 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
185 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
186 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
187 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
188 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
189 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
190 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
191 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
192 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
193 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
194 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
195 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
196 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
197 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
198 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
199 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
200 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
201 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
202 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
203 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
204 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
205 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
206 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
207 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
208 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
209 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
210 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
211 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
212 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
213 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
214 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
215 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
216 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
217 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
218 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
219 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
220 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
221 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
222 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
223 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
224 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
225 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
226 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
227 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
228 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
229 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
230 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
231 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
232 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
233 IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
234 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
235 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
236 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
237 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
238 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
239 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
240 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
241 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
242 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
243 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
244 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
245 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
246 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
247 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
248 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
249 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
250 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
251 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
252 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
253 IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
254};
255
256#define BM_OBE_ENABLED BIT(17)
257#define BM_IBE_ENABLED BIT(16)
258#define BM_MUX_MODE 0xf00
259#define BP_MUX_MODE 8
260
261static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
262 struct pinctrl_gpio_range *range,
263 unsigned offset, bool input)
264{
265 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
266 const struct imx_pin_reg *pin_reg;
267 u32 reg;
268
269 pin_reg = &ipctl->pin_regs[offset];
270 if (pin_reg->mux_reg == -1)
271 return -EINVAL;
272
273 reg = readl(addr: ipctl->base + pin_reg->mux_reg);
274 if (input)
275 reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
276 else
277 reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
278 writel(val: reg, addr: ipctl->base + pin_reg->mux_reg);
279
280 return 0;
281}
282
283static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
284 .pins = imx7ulp_pinctrl_pads,
285 .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
286 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
287 .gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
288 .mux_mask = BM_MUX_MODE,
289 .mux_shift = BP_MUX_MODE,
290};
291
292static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
293 { .compatible = "fsl,imx7ulp-iomuxc1", },
294 { /* sentinel */ }
295};
296
297static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
298{
299 return imx_pinctrl_probe(pdev, info: &imx7ulp_pinctrl_info);
300}
301
302static struct platform_driver imx7ulp_pinctrl_driver = {
303 .driver = {
304 .name = "imx7ulp-pinctrl",
305 .of_match_table = imx7ulp_pinctrl_of_match,
306 .suppress_bind_attrs = true,
307 },
308 .probe = imx7ulp_pinctrl_probe,
309};
310
311static int __init imx7ulp_pinctrl_init(void)
312{
313 return platform_driver_register(&imx7ulp_pinctrl_driver);
314}
315arch_initcall(imx7ulp_pinctrl_init);
316

source code of linux/drivers/pinctrl/freescale/pinctrl-imx7ulp.c