1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Pinctrl GPIO driver for Intel Baytrail |
4 | * |
5 | * Copyright (c) 2012-2013, Intel Corporation |
6 | * Author: Mathias Nyman <mathias.nyman@linux.intel.com> |
7 | */ |
8 | |
9 | #include <linux/acpi.h> |
10 | #include <linux/array_size.h> |
11 | #include <linux/bitops.h> |
12 | #include <linux/cleanup.h> |
13 | #include <linux/gpio/driver.h> |
14 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/io.h> |
17 | #include <linux/module.h> |
18 | #include <linux/types.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/pm.h> |
21 | #include <linux/property.h> |
22 | #include <linux/seq_file.h> |
23 | #include <linux/string_helpers.h> |
24 | |
25 | #include <linux/pinctrl/pinctrl.h> |
26 | #include <linux/pinctrl/pinmux.h> |
27 | #include <linux/pinctrl/pinconf.h> |
28 | #include <linux/pinctrl/pinconf-generic.h> |
29 | |
30 | #include "pinctrl-intel.h" |
31 | |
32 | /* memory mapped register offsets */ |
33 | #define BYT_CONF0_REG 0x000 |
34 | #define BYT_CONF1_REG 0x004 |
35 | #define BYT_VAL_REG 0x008 |
36 | #define BYT_DFT_REG 0x00c |
37 | #define BYT_INT_STAT_REG 0x800 |
38 | #define BYT_DIRECT_IRQ_REG 0x980 |
39 | #define BYT_DEBOUNCE_REG 0x9d0 |
40 | |
41 | /* BYT_CONF0_REG register bits */ |
42 | #define BYT_IODEN BIT(31) |
43 | #define BYT_DIRECT_IRQ_EN BIT(27) |
44 | #define BYT_TRIG_MASK GENMASK(26, 24) |
45 | #define BYT_TRIG_NEG BIT(26) |
46 | #define BYT_TRIG_POS BIT(25) |
47 | #define BYT_TRIG_LVL BIT(24) |
48 | #define BYT_DEBOUNCE_EN BIT(20) |
49 | #define BYT_GLITCH_FILTER_EN BIT(19) |
50 | #define BYT_GLITCH_F_SLOW_CLK BIT(17) |
51 | #define BYT_GLITCH_F_FAST_CLK BIT(16) |
52 | #define BYT_PULL_STR_SHIFT 9 |
53 | #define BYT_PULL_STR_MASK GENMASK(10, 9) |
54 | #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) |
55 | #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) |
56 | #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) |
57 | #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) |
58 | #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) |
59 | #define BYT_PULL_ASSIGN_DOWN BIT(8) |
60 | #define BYT_PULL_ASSIGN_UP BIT(7) |
61 | #define BYT_PIN_MUX GENMASK(2, 0) |
62 | |
63 | /* BYT_VAL_REG register bits */ |
64 | #define BYT_DIR_MASK GENMASK(2, 1) |
65 | #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ |
66 | #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ |
67 | #define BYT_LEVEL BIT(0) |
68 | |
69 | #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) |
70 | #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) |
71 | |
72 | /* BYT_DEBOUNCE_REG bits */ |
73 | #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) |
74 | #define BYT_DEBOUNCE_PULSE_375US 1 |
75 | #define BYT_DEBOUNCE_PULSE_750US 2 |
76 | #define BYT_DEBOUNCE_PULSE_1500US 3 |
77 | #define BYT_DEBOUNCE_PULSE_3MS 4 |
78 | #define BYT_DEBOUNCE_PULSE_6MS 5 |
79 | #define BYT_DEBOUNCE_PULSE_12MS 6 |
80 | #define BYT_DEBOUNCE_PULSE_24MS 7 |
81 | |
82 | #define BYT_NGPIO_SCORE 102 |
83 | #define BYT_NGPIO_NCORE 28 |
84 | #define BYT_NGPIO_SUS 44 |
85 | |
86 | #define BYT_SCORE_ACPI_UID "1" |
87 | #define BYT_NCORE_ACPI_UID "2" |
88 | #define BYT_SUS_ACPI_UID "3" |
89 | |
90 | /* |
91 | * This is the function value most pins have for GPIO muxing. If the value |
92 | * differs from the default one, it must be explicitly mentioned. Otherwise, the |
93 | * pin control implementation will set the muxing value to default GPIO if it |
94 | * does not find a match for the requested function. |
95 | */ |
96 | #define BYT_DEFAULT_GPIO_MUX 0 |
97 | #define BYT_ALTER_GPIO_MUX 1 |
98 | |
99 | struct intel_pad_context { |
100 | u32 conf0; |
101 | u32 val; |
102 | }; |
103 | |
104 | #define (p, n, map) \ |
105 | { \ |
106 | .pin_base = (p), \ |
107 | .npins = (n), \ |
108 | .pad_map = (map),\ |
109 | } |
110 | |
111 | /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ |
112 | static const struct pinctrl_pin_desc byt_score_pins[] = { |
113 | PINCTRL_PIN(0, "SATA_GP0" ), |
114 | PINCTRL_PIN(1, "SATA_GP1" ), |
115 | PINCTRL_PIN(2, "SATA_LED#" ), |
116 | PINCTRL_PIN(3, "PCIE_CLKREQ0" ), |
117 | PINCTRL_PIN(4, "PCIE_CLKREQ1" ), |
118 | PINCTRL_PIN(5, "PCIE_CLKREQ2" ), |
119 | PINCTRL_PIN(6, "PCIE_CLKREQ3" ), |
120 | PINCTRL_PIN(7, "SD3_WP" ), |
121 | PINCTRL_PIN(8, "HDA_RST" ), |
122 | PINCTRL_PIN(9, "HDA_SYNC" ), |
123 | PINCTRL_PIN(10, "HDA_CLK" ), |
124 | PINCTRL_PIN(11, "HDA_SDO" ), |
125 | PINCTRL_PIN(12, "HDA_SDI0" ), |
126 | PINCTRL_PIN(13, "HDA_SDI1" ), |
127 | PINCTRL_PIN(14, "GPIO_S0_SC14" ), |
128 | PINCTRL_PIN(15, "GPIO_S0_SC15" ), |
129 | PINCTRL_PIN(16, "MMC1_CLK" ), |
130 | PINCTRL_PIN(17, "MMC1_D0" ), |
131 | PINCTRL_PIN(18, "MMC1_D1" ), |
132 | PINCTRL_PIN(19, "MMC1_D2" ), |
133 | PINCTRL_PIN(20, "MMC1_D3" ), |
134 | PINCTRL_PIN(21, "MMC1_D4" ), |
135 | PINCTRL_PIN(22, "MMC1_D5" ), |
136 | PINCTRL_PIN(23, "MMC1_D6" ), |
137 | PINCTRL_PIN(24, "MMC1_D7" ), |
138 | PINCTRL_PIN(25, "MMC1_CMD" ), |
139 | PINCTRL_PIN(26, "MMC1_RST" ), |
140 | PINCTRL_PIN(27, "SD2_CLK" ), |
141 | PINCTRL_PIN(28, "SD2_D0" ), |
142 | PINCTRL_PIN(29, "SD2_D1" ), |
143 | PINCTRL_PIN(30, "SD2_D2" ), |
144 | PINCTRL_PIN(31, "SD2_D3_CD" ), |
145 | PINCTRL_PIN(32, "SD2_CMD" ), |
146 | PINCTRL_PIN(33, "SD3_CLK" ), |
147 | PINCTRL_PIN(34, "SD3_D0" ), |
148 | PINCTRL_PIN(35, "SD3_D1" ), |
149 | PINCTRL_PIN(36, "SD3_D2" ), |
150 | PINCTRL_PIN(37, "SD3_D3" ), |
151 | PINCTRL_PIN(38, "SD3_CD" ), |
152 | PINCTRL_PIN(39, "SD3_CMD" ), |
153 | PINCTRL_PIN(40, "SD3_1P8EN" ), |
154 | PINCTRL_PIN(41, "SD3_PWREN#" ), |
155 | PINCTRL_PIN(42, "ILB_LPC_AD0" ), |
156 | PINCTRL_PIN(43, "ILB_LPC_AD1" ), |
157 | PINCTRL_PIN(44, "ILB_LPC_AD2" ), |
158 | PINCTRL_PIN(45, "ILB_LPC_AD3" ), |
159 | PINCTRL_PIN(46, "ILB_LPC_FRAME" ), |
160 | PINCTRL_PIN(47, "ILB_LPC_CLK0" ), |
161 | PINCTRL_PIN(48, "ILB_LPC_CLK1" ), |
162 | PINCTRL_PIN(49, "ILB_LPC_CLKRUN" ), |
163 | PINCTRL_PIN(50, "ILB_LPC_SERIRQ" ), |
164 | PINCTRL_PIN(51, "PCU_SMB_DATA" ), |
165 | PINCTRL_PIN(52, "PCU_SMB_CLK" ), |
166 | PINCTRL_PIN(53, "PCU_SMB_ALERT" ), |
167 | PINCTRL_PIN(54, "ILB_8254_SPKR" ), |
168 | PINCTRL_PIN(55, "GPIO_S0_SC55" ), |
169 | PINCTRL_PIN(56, "GPIO_S0_SC56" ), |
170 | PINCTRL_PIN(57, "GPIO_S0_SC57" ), |
171 | PINCTRL_PIN(58, "GPIO_S0_SC58" ), |
172 | PINCTRL_PIN(59, "GPIO_S0_SC59" ), |
173 | PINCTRL_PIN(60, "GPIO_S0_SC60" ), |
174 | PINCTRL_PIN(61, "GPIO_S0_SC61" ), |
175 | PINCTRL_PIN(62, "LPE_I2S2_CLK" ), |
176 | PINCTRL_PIN(63, "LPE_I2S2_FRM" ), |
177 | PINCTRL_PIN(64, "LPE_I2S2_DATAIN" ), |
178 | PINCTRL_PIN(65, "LPE_I2S2_DATAOUT" ), |
179 | PINCTRL_PIN(66, "SIO_SPI_CS" ), |
180 | PINCTRL_PIN(67, "SIO_SPI_MISO" ), |
181 | PINCTRL_PIN(68, "SIO_SPI_MOSI" ), |
182 | PINCTRL_PIN(69, "SIO_SPI_CLK" ), |
183 | PINCTRL_PIN(70, "SIO_UART1_RXD" ), |
184 | PINCTRL_PIN(71, "SIO_UART1_TXD" ), |
185 | PINCTRL_PIN(72, "SIO_UART1_RTS" ), |
186 | PINCTRL_PIN(73, "SIO_UART1_CTS" ), |
187 | PINCTRL_PIN(74, "SIO_UART2_RXD" ), |
188 | PINCTRL_PIN(75, "SIO_UART2_TXD" ), |
189 | PINCTRL_PIN(76, "SIO_UART2_RTS" ), |
190 | PINCTRL_PIN(77, "SIO_UART2_CTS" ), |
191 | PINCTRL_PIN(78, "SIO_I2C0_DATA" ), |
192 | PINCTRL_PIN(79, "SIO_I2C0_CLK" ), |
193 | PINCTRL_PIN(80, "SIO_I2C1_DATA" ), |
194 | PINCTRL_PIN(81, "SIO_I2C1_CLK" ), |
195 | PINCTRL_PIN(82, "SIO_I2C2_DATA" ), |
196 | PINCTRL_PIN(83, "SIO_I2C2_CLK" ), |
197 | PINCTRL_PIN(84, "SIO_I2C3_DATA" ), |
198 | PINCTRL_PIN(85, "SIO_I2C3_CLK" ), |
199 | PINCTRL_PIN(86, "SIO_I2C4_DATA" ), |
200 | PINCTRL_PIN(87, "SIO_I2C4_CLK" ), |
201 | PINCTRL_PIN(88, "SIO_I2C5_DATA" ), |
202 | PINCTRL_PIN(89, "SIO_I2C5_CLK" ), |
203 | PINCTRL_PIN(90, "SIO_I2C6_DATA" ), |
204 | PINCTRL_PIN(91, "SIO_I2C6_CLK" ), |
205 | PINCTRL_PIN(92, "GPIO_S0_SC92" ), |
206 | PINCTRL_PIN(93, "GPIO_S0_SC93" ), |
207 | PINCTRL_PIN(94, "SIO_PWM0" ), |
208 | PINCTRL_PIN(95, "SIO_PWM1" ), |
209 | PINCTRL_PIN(96, "PMC_PLT_CLK0" ), |
210 | PINCTRL_PIN(97, "PMC_PLT_CLK1" ), |
211 | PINCTRL_PIN(98, "PMC_PLT_CLK2" ), |
212 | PINCTRL_PIN(99, "PMC_PLT_CLK3" ), |
213 | PINCTRL_PIN(100, "PMC_PLT_CLK4" ), |
214 | PINCTRL_PIN(101, "PMC_PLT_CLK5" ), |
215 | }; |
216 | |
217 | static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { |
218 | 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, |
219 | 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, |
220 | 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, |
221 | 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, |
222 | 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, |
223 | 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, |
224 | 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, |
225 | 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, |
226 | 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, |
227 | 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, |
228 | 97, 100, |
229 | }; |
230 | |
231 | /* SCORE groups */ |
232 | static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; |
233 | static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; |
234 | |
235 | static const unsigned int byt_score_pwm0_pins[] = { 94 }; |
236 | static const unsigned int byt_score_pwm1_pins[] = { 95 }; |
237 | |
238 | static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; |
239 | |
240 | static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; |
241 | static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; |
242 | static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; |
243 | static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; |
244 | static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; |
245 | static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; |
246 | static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; |
247 | |
248 | static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; |
249 | static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; |
250 | static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; |
251 | |
252 | static const unsigned int byt_score_sdcard_pins[] = { |
253 | 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, |
254 | }; |
255 | static const unsigned int byt_score_sdcard_mux_values[] = { |
256 | 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
257 | }; |
258 | |
259 | static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; |
260 | |
261 | static const unsigned int byt_score_emmc_pins[] = { |
262 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, |
263 | }; |
264 | |
265 | static const unsigned int byt_score_ilb_lpc_pins[] = { |
266 | 42, 43, 44, 45, 46, 47, 48, 49, 50, |
267 | }; |
268 | |
269 | static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; |
270 | |
271 | static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; |
272 | static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; |
273 | static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; |
274 | static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; |
275 | static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; |
276 | static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; |
277 | |
278 | static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; |
279 | |
280 | static const struct intel_pingroup byt_score_groups[] = { |
281 | PIN_GROUP("uart1_grp" , byt_score_uart1_pins, 1), |
282 | PIN_GROUP("uart2_grp" , byt_score_uart2_pins, 1), |
283 | PIN_GROUP("pwm0_grp" , byt_score_pwm0_pins, 1), |
284 | PIN_GROUP("pwm1_grp" , byt_score_pwm1_pins, 1), |
285 | PIN_GROUP("ssp2_grp" , byt_score_ssp2_pins, 1), |
286 | PIN_GROUP("sio_spi_grp" , byt_score_sio_spi_pins, 1), |
287 | PIN_GROUP("i2c5_grp" , byt_score_i2c5_pins, 1), |
288 | PIN_GROUP("i2c6_grp" , byt_score_i2c6_pins, 1), |
289 | PIN_GROUP("i2c4_grp" , byt_score_i2c4_pins, 1), |
290 | PIN_GROUP("i2c3_grp" , byt_score_i2c3_pins, 1), |
291 | PIN_GROUP("i2c2_grp" , byt_score_i2c2_pins, 1), |
292 | PIN_GROUP("i2c1_grp" , byt_score_i2c1_pins, 1), |
293 | PIN_GROUP("i2c0_grp" , byt_score_i2c0_pins, 1), |
294 | PIN_GROUP("ssp0_grp" , byt_score_ssp0_pins, 1), |
295 | PIN_GROUP("ssp1_grp" , byt_score_ssp1_pins, 1), |
296 | PIN_GROUP("sdcard_grp" , byt_score_sdcard_pins, byt_score_sdcard_mux_values), |
297 | PIN_GROUP("sdio_grp" , byt_score_sdio_pins, 1), |
298 | PIN_GROUP("emmc_grp" , byt_score_emmc_pins, 1), |
299 | PIN_GROUP("lpc_grp" , byt_score_ilb_lpc_pins, 1), |
300 | PIN_GROUP("sata_grp" , byt_score_sata_pins, 1), |
301 | PIN_GROUP("plt_clk0_grp" , byt_score_plt_clk0_pins, 1), |
302 | PIN_GROUP("plt_clk1_grp" , byt_score_plt_clk1_pins, 1), |
303 | PIN_GROUP("plt_clk2_grp" , byt_score_plt_clk2_pins, 1), |
304 | PIN_GROUP("plt_clk3_grp" , byt_score_plt_clk3_pins, 1), |
305 | PIN_GROUP("plt_clk4_grp" , byt_score_plt_clk4_pins, 1), |
306 | PIN_GROUP("plt_clk5_grp" , byt_score_plt_clk5_pins, 1), |
307 | PIN_GROUP("smbus_grp" , byt_score_smbus_pins, 1), |
308 | }; |
309 | |
310 | static const char * const byt_score_uart_groups[] = { |
311 | "uart1_grp" , "uart2_grp" , |
312 | }; |
313 | static const char * const byt_score_pwm_groups[] = { |
314 | "pwm0_grp" , "pwm1_grp" , |
315 | }; |
316 | static const char * const byt_score_ssp_groups[] = { |
317 | "ssp0_grp" , "ssp1_grp" , "ssp2_grp" , |
318 | }; |
319 | static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; |
320 | static const char * const byt_score_i2c_groups[] = { |
321 | "i2c0_grp" , "i2c1_grp" , "i2c2_grp" , "i2c3_grp" , "i2c4_grp" , "i2c5_grp" , |
322 | "i2c6_grp" , |
323 | }; |
324 | static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; |
325 | static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; |
326 | static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; |
327 | static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; |
328 | static const char * const byt_score_sata_groups[] = { "sata_grp" }; |
329 | static const char * const byt_score_plt_clk_groups[] = { |
330 | "plt_clk0_grp" , "plt_clk1_grp" , "plt_clk2_grp" , "plt_clk3_grp" , |
331 | "plt_clk4_grp" , "plt_clk5_grp" , |
332 | }; |
333 | static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; |
334 | static const char * const byt_score_gpio_groups[] = { |
335 | "uart1_grp" , "uart2_grp" , "pwm0_grp" , "pwm1_grp" , "ssp0_grp" , |
336 | "ssp1_grp" , "ssp2_grp" , "sio_spi_grp" , "i2c0_grp" , "i2c1_grp" , |
337 | "i2c2_grp" , "i2c3_grp" , "i2c4_grp" , "i2c5_grp" , "i2c6_grp" , |
338 | "sdcard_grp" , "sdio_grp" , "emmc_grp" , "lpc_grp" , "sata_grp" , |
339 | "plt_clk0_grp" , "plt_clk1_grp" , "plt_clk2_grp" , "plt_clk3_grp" , |
340 | "plt_clk4_grp" , "plt_clk5_grp" , "smbus_grp" , |
341 | }; |
342 | |
343 | static const struct intel_function byt_score_functions[] = { |
344 | FUNCTION("uart" , byt_score_uart_groups), |
345 | FUNCTION("pwm" , byt_score_pwm_groups), |
346 | FUNCTION("ssp" , byt_score_ssp_groups), |
347 | FUNCTION("spi" , byt_score_spi_groups), |
348 | FUNCTION("i2c" , byt_score_i2c_groups), |
349 | FUNCTION("sdcard" , byt_score_sdcard_groups), |
350 | FUNCTION("sdio" , byt_score_sdio_groups), |
351 | FUNCTION("emmc" , byt_score_emmc_groups), |
352 | FUNCTION("lpc" , byt_score_lpc_groups), |
353 | FUNCTION("sata" , byt_score_sata_groups), |
354 | FUNCTION("plt_clk" , byt_score_plt_clk_groups), |
355 | FUNCTION("smbus" , byt_score_smbus_groups), |
356 | FUNCTION("gpio" , byt_score_gpio_groups), |
357 | }; |
358 | |
359 | static const struct intel_community byt_score_communities[] = { |
360 | COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), |
361 | }; |
362 | |
363 | static const struct intel_pinctrl_soc_data byt_score_soc_data = { |
364 | .uid = BYT_SCORE_ACPI_UID, |
365 | .pins = byt_score_pins, |
366 | .npins = ARRAY_SIZE(byt_score_pins), |
367 | .groups = byt_score_groups, |
368 | .ngroups = ARRAY_SIZE(byt_score_groups), |
369 | .functions = byt_score_functions, |
370 | .nfunctions = ARRAY_SIZE(byt_score_functions), |
371 | .communities = byt_score_communities, |
372 | .ncommunities = ARRAY_SIZE(byt_score_communities), |
373 | }; |
374 | |
375 | /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ |
376 | static const struct pinctrl_pin_desc byt_sus_pins[] = { |
377 | PINCTRL_PIN(0, "GPIO_S50" ), |
378 | PINCTRL_PIN(1, "GPIO_S51" ), |
379 | PINCTRL_PIN(2, "GPIO_S52" ), |
380 | PINCTRL_PIN(3, "GPIO_S53" ), |
381 | PINCTRL_PIN(4, "GPIO_S54" ), |
382 | PINCTRL_PIN(5, "GPIO_S55" ), |
383 | PINCTRL_PIN(6, "GPIO_S56" ), |
384 | PINCTRL_PIN(7, "GPIO_S57" ), |
385 | PINCTRL_PIN(8, "GPIO_S58" ), |
386 | PINCTRL_PIN(9, "GPIO_S59" ), |
387 | PINCTRL_PIN(10, "GPIO_S510" ), |
388 | PINCTRL_PIN(11, "PMC_SUSPWRDNACK" ), |
389 | PINCTRL_PIN(12, "PMC_SUSCLK0" ), |
390 | PINCTRL_PIN(13, "GPIO_S513" ), |
391 | PINCTRL_PIN(14, "USB_ULPI_RST" ), |
392 | PINCTRL_PIN(15, "PMC_WAKE_PCIE0#" ), |
393 | PINCTRL_PIN(16, "PMC_PWRBTN" ), |
394 | PINCTRL_PIN(17, "GPIO_S517" ), |
395 | PINCTRL_PIN(18, "PMC_SUS_STAT" ), |
396 | PINCTRL_PIN(19, "USB_OC0" ), |
397 | PINCTRL_PIN(20, "USB_OC1" ), |
398 | PINCTRL_PIN(21, "PCU_SPI_CS1" ), |
399 | PINCTRL_PIN(22, "GPIO_S522" ), |
400 | PINCTRL_PIN(23, "GPIO_S523" ), |
401 | PINCTRL_PIN(24, "GPIO_S524" ), |
402 | PINCTRL_PIN(25, "GPIO_S525" ), |
403 | PINCTRL_PIN(26, "GPIO_S526" ), |
404 | PINCTRL_PIN(27, "GPIO_S527" ), |
405 | PINCTRL_PIN(28, "GPIO_S528" ), |
406 | PINCTRL_PIN(29, "GPIO_S529" ), |
407 | PINCTRL_PIN(30, "GPIO_S530" ), |
408 | PINCTRL_PIN(31, "USB_ULPI_CLK" ), |
409 | PINCTRL_PIN(32, "USB_ULPI_DATA0" ), |
410 | PINCTRL_PIN(33, "USB_ULPI_DATA1" ), |
411 | PINCTRL_PIN(34, "USB_ULPI_DATA2" ), |
412 | PINCTRL_PIN(35, "USB_ULPI_DATA3" ), |
413 | PINCTRL_PIN(36, "USB_ULPI_DATA4" ), |
414 | PINCTRL_PIN(37, "USB_ULPI_DATA5" ), |
415 | PINCTRL_PIN(38, "USB_ULPI_DATA6" ), |
416 | PINCTRL_PIN(39, "USB_ULPI_DATA7" ), |
417 | PINCTRL_PIN(40, "USB_ULPI_DIR" ), |
418 | PINCTRL_PIN(41, "USB_ULPI_NXT" ), |
419 | PINCTRL_PIN(42, "USB_ULPI_STP" ), |
420 | PINCTRL_PIN(43, "USB_ULPI_REFCLK" ), |
421 | }; |
422 | |
423 | static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { |
424 | 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, |
425 | 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, |
426 | 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, |
427 | 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, |
428 | 52, 53, 59, 40, |
429 | }; |
430 | |
431 | static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; |
432 | static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; |
433 | static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; |
434 | |
435 | static const unsigned int byt_sus_usb_ulpi_pins[] = { |
436 | 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, |
437 | }; |
438 | static const unsigned int byt_sus_usb_ulpi_mode_values[] = { |
439 | 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
440 | }; |
441 | static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { |
442 | 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
443 | }; |
444 | |
445 | static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; |
446 | static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; |
447 | static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; |
448 | |
449 | static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; |
450 | static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; |
451 | |
452 | static const struct intel_pingroup byt_sus_groups[] = { |
453 | PIN_GROUP("usb_oc_grp" , byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), |
454 | PIN_GROUP("usb_ulpi_grp" , byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), |
455 | PIN_GROUP("pcu_spi_grp" , byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), |
456 | PIN_GROUP("usb_oc_grp_gpio" , byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), |
457 | PIN_GROUP("usb_ulpi_grp_gpio" , byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), |
458 | PIN_GROUP("pcu_spi_grp_gpio" , byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), |
459 | PIN_GROUP("pmu_clk1_grp" , byt_sus_pmu_clk1_pins, 1), |
460 | PIN_GROUP("pmu_clk2_grp" , byt_sus_pmu_clk2_pins, 1), |
461 | }; |
462 | |
463 | static const char * const byt_sus_usb_groups[] = { |
464 | "usb_oc_grp" , "usb_ulpi_grp" , |
465 | }; |
466 | static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; |
467 | static const char * const byt_sus_pmu_clk_groups[] = { |
468 | "pmu_clk1_grp" , "pmu_clk2_grp" , |
469 | }; |
470 | static const char * const byt_sus_gpio_groups[] = { |
471 | "usb_oc_grp_gpio" , "usb_ulpi_grp_gpio" , "pcu_spi_grp_gpio" , |
472 | "pmu_clk1_grp" , "pmu_clk2_grp" , |
473 | }; |
474 | |
475 | static const struct intel_function byt_sus_functions[] = { |
476 | FUNCTION("usb" , byt_sus_usb_groups), |
477 | FUNCTION("spi" , byt_sus_spi_groups), |
478 | FUNCTION("gpio" , byt_sus_gpio_groups), |
479 | FUNCTION("pmu_clk" , byt_sus_pmu_clk_groups), |
480 | }; |
481 | |
482 | static const struct intel_community byt_sus_communities[] = { |
483 | COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), |
484 | }; |
485 | |
486 | static const struct intel_pinctrl_soc_data byt_sus_soc_data = { |
487 | .uid = BYT_SUS_ACPI_UID, |
488 | .pins = byt_sus_pins, |
489 | .npins = ARRAY_SIZE(byt_sus_pins), |
490 | .groups = byt_sus_groups, |
491 | .ngroups = ARRAY_SIZE(byt_sus_groups), |
492 | .functions = byt_sus_functions, |
493 | .nfunctions = ARRAY_SIZE(byt_sus_functions), |
494 | .communities = byt_sus_communities, |
495 | .ncommunities = ARRAY_SIZE(byt_sus_communities), |
496 | }; |
497 | |
498 | static const struct pinctrl_pin_desc byt_ncore_pins[] = { |
499 | PINCTRL_PIN(0, "HV_DDI0_HPD" ), |
500 | PINCTRL_PIN(1, "HV_DDI0_DDC_SDA" ), |
501 | PINCTRL_PIN(2, "HV_DDI0_DDC_SCL" ), |
502 | PINCTRL_PIN(3, "PANEL0_VDDEN" ), |
503 | PINCTRL_PIN(4, "PANEL0_BKLTEN" ), |
504 | PINCTRL_PIN(5, "PANEL0_BKLTCTL" ), |
505 | PINCTRL_PIN(6, "HV_DDI1_HPD" ), |
506 | PINCTRL_PIN(7, "HV_DDI1_DDC_SDA" ), |
507 | PINCTRL_PIN(8, "HV_DDI1_DDC_SCL" ), |
508 | PINCTRL_PIN(9, "PANEL1_VDDEN" ), |
509 | PINCTRL_PIN(10, "PANEL1_BKLTEN" ), |
510 | PINCTRL_PIN(11, "PANEL1_BKLTCTL" ), |
511 | PINCTRL_PIN(12, "GP_INTD_DSI_TE1" ), |
512 | PINCTRL_PIN(13, "HV_DDI2_DDC_SDA" ), |
513 | PINCTRL_PIN(14, "HV_DDI2_DDC_SCL" ), |
514 | PINCTRL_PIN(15, "GP_CAMERASB00" ), |
515 | PINCTRL_PIN(16, "GP_CAMERASB01" ), |
516 | PINCTRL_PIN(17, "GP_CAMERASB02" ), |
517 | PINCTRL_PIN(18, "GP_CAMERASB03" ), |
518 | PINCTRL_PIN(19, "GP_CAMERASB04" ), |
519 | PINCTRL_PIN(20, "GP_CAMERASB05" ), |
520 | PINCTRL_PIN(21, "GP_CAMERASB06" ), |
521 | PINCTRL_PIN(22, "GP_CAMERASB07" ), |
522 | PINCTRL_PIN(23, "GP_CAMERASB08" ), |
523 | PINCTRL_PIN(24, "GP_CAMERASB09" ), |
524 | PINCTRL_PIN(25, "GP_CAMERASB10" ), |
525 | PINCTRL_PIN(26, "GP_CAMERASB11" ), |
526 | PINCTRL_PIN(27, "GP_INTD_DSI_TE2" ), |
527 | }; |
528 | |
529 | static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { |
530 | 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, |
531 | 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, |
532 | 3, 6, 10, 13, 2, 5, 9, 7, |
533 | }; |
534 | |
535 | static const struct intel_community byt_ncore_communities[] = { |
536 | COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), |
537 | }; |
538 | |
539 | static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { |
540 | .uid = BYT_NCORE_ACPI_UID, |
541 | .pins = byt_ncore_pins, |
542 | .npins = ARRAY_SIZE(byt_ncore_pins), |
543 | .communities = byt_ncore_communities, |
544 | .ncommunities = ARRAY_SIZE(byt_ncore_communities), |
545 | }; |
546 | |
547 | static const struct intel_pinctrl_soc_data *byt_soc_data[] = { |
548 | &byt_score_soc_data, |
549 | &byt_sus_soc_data, |
550 | &byt_ncore_soc_data, |
551 | NULL |
552 | }; |
553 | |
554 | static DEFINE_RAW_SPINLOCK(byt_lock); |
555 | |
556 | static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, |
557 | int reg) |
558 | { |
559 | struct intel_community *comm = intel_get_community(pctrl: vg, pin: offset); |
560 | u32 reg_offset; |
561 | |
562 | if (!comm) |
563 | return NULL; |
564 | |
565 | offset -= comm->pin_base; |
566 | switch (reg) { |
567 | case BYT_INT_STAT_REG: |
568 | reg_offset = (offset / 32) * 4; |
569 | break; |
570 | case BYT_DEBOUNCE_REG: |
571 | reg_offset = 0; |
572 | break; |
573 | default: |
574 | reg_offset = comm->pad_map[offset] * 16; |
575 | break; |
576 | } |
577 | |
578 | return comm->pad_regs + reg_offset + reg; |
579 | } |
580 | |
581 | static const struct pinctrl_ops byt_pinctrl_ops = { |
582 | .get_groups_count = intel_get_groups_count, |
583 | .get_group_name = intel_get_group_name, |
584 | .get_group_pins = intel_get_group_pins, |
585 | }; |
586 | |
587 | static void byt_set_group_simple_mux(struct intel_pinctrl *vg, |
588 | const struct intel_pingroup group, |
589 | unsigned int func) |
590 | { |
591 | int i; |
592 | |
593 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
594 | |
595 | for (i = 0; i < group.grp.npins; i++) { |
596 | void __iomem *padcfg0; |
597 | u32 value; |
598 | |
599 | padcfg0 = byt_gpio_reg(vg, offset: group.grp.pins[i], BYT_CONF0_REG); |
600 | if (!padcfg0) { |
601 | dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n" , |
602 | group.grp.name, i); |
603 | continue; |
604 | } |
605 | |
606 | value = readl(addr: padcfg0); |
607 | value &= ~BYT_PIN_MUX; |
608 | value |= func; |
609 | writel(val: value, addr: padcfg0); |
610 | } |
611 | } |
612 | |
613 | static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, |
614 | const struct intel_pingroup group, |
615 | const unsigned int *func) |
616 | { |
617 | int i; |
618 | |
619 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
620 | |
621 | for (i = 0; i < group.grp.npins; i++) { |
622 | void __iomem *padcfg0; |
623 | u32 value; |
624 | |
625 | padcfg0 = byt_gpio_reg(vg, offset: group.grp.pins[i], BYT_CONF0_REG); |
626 | if (!padcfg0) { |
627 | dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n" , |
628 | group.grp.name, i); |
629 | continue; |
630 | } |
631 | |
632 | value = readl(addr: padcfg0); |
633 | value &= ~BYT_PIN_MUX; |
634 | value |= func[i]; |
635 | writel(val: value, addr: padcfg0); |
636 | } |
637 | } |
638 | |
639 | static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, |
640 | unsigned int group_selector) |
641 | { |
642 | struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); |
643 | const struct intel_function func = vg->soc->functions[func_selector]; |
644 | const struct intel_pingroup group = vg->soc->groups[group_selector]; |
645 | |
646 | if (group.modes) |
647 | byt_set_group_mixed_mux(vg, group, func: group.modes); |
648 | else if (!strcmp(func.func.name, "gpio" )) |
649 | byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); |
650 | else |
651 | byt_set_group_simple_mux(vg, group, func: group.mode); |
652 | |
653 | return 0; |
654 | } |
655 | |
656 | static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) |
657 | { |
658 | /* SCORE pin 92-93 */ |
659 | if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && |
660 | offset >= 92 && offset <= 93) |
661 | return BYT_ALTER_GPIO_MUX; |
662 | |
663 | /* SUS pin 11-21 */ |
664 | if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && |
665 | offset >= 11 && offset <= 21) |
666 | return BYT_ALTER_GPIO_MUX; |
667 | |
668 | return BYT_DEFAULT_GPIO_MUX; |
669 | } |
670 | |
671 | static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) |
672 | { |
673 | void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); |
674 | u32 value; |
675 | |
676 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
677 | |
678 | value = readl(addr: reg); |
679 | |
680 | /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ |
681 | if (!(value & BYT_DIRECT_IRQ_EN)) |
682 | value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); |
683 | |
684 | writel(val: value, addr: reg); |
685 | } |
686 | |
687 | static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, |
688 | struct pinctrl_gpio_range *range, |
689 | unsigned int offset) |
690 | { |
691 | struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev: pctl_dev); |
692 | void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); |
693 | u32 value, gpio_mux; |
694 | |
695 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
696 | |
697 | /* |
698 | * In most cases, func pin mux 000 means GPIO function. |
699 | * But, some pins may have func pin mux 001 represents |
700 | * GPIO function. |
701 | * |
702 | * Because there are devices out there where some pins were not |
703 | * configured correctly we allow changing the mux value from |
704 | * request (but print out warning about that). |
705 | */ |
706 | value = readl(addr: reg) & BYT_PIN_MUX; |
707 | gpio_mux = byt_get_gpio_mux(vg, offset); |
708 | if (gpio_mux == value) |
709 | return 0; |
710 | |
711 | value = readl(addr: reg) & ~BYT_PIN_MUX; |
712 | value |= gpio_mux; |
713 | writel(val: value, addr: reg); |
714 | |
715 | dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n" , offset); |
716 | |
717 | return 0; |
718 | } |
719 | |
720 | static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, |
721 | struct pinctrl_gpio_range *range, |
722 | unsigned int offset) |
723 | { |
724 | struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev: pctl_dev); |
725 | |
726 | byt_gpio_clear_triggering(vg, offset); |
727 | } |
728 | |
729 | static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, |
730 | unsigned int offset) |
731 | { |
732 | void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); |
733 | |
734 | /* |
735 | * Before making any direction modifications, do a check if gpio is set |
736 | * for direct IRQ. On Bay Trail, setting GPIO to output does not make |
737 | * sense, so let's at least inform the caller before they shoot |
738 | * themselves in the foot. |
739 | */ |
740 | if (readl(addr: conf_reg) & BYT_DIRECT_IRQ_EN) |
741 | dev_info_once(vg->dev, |
742 | "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n" , |
743 | offset); |
744 | } |
745 | |
746 | static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, |
747 | struct pinctrl_gpio_range *range, |
748 | unsigned int offset, |
749 | bool input) |
750 | { |
751 | struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev: pctl_dev); |
752 | void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
753 | u32 value; |
754 | |
755 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
756 | |
757 | value = readl(addr: val_reg); |
758 | value &= ~BYT_DIR_MASK; |
759 | if (input) |
760 | value |= BYT_OUTPUT_EN; |
761 | else |
762 | byt_gpio_direct_irq_check(vg, offset); |
763 | |
764 | writel(val: value, addr: val_reg); |
765 | |
766 | return 0; |
767 | } |
768 | |
769 | static const struct pinmux_ops byt_pinmux_ops = { |
770 | .get_functions_count = intel_get_functions_count, |
771 | .get_function_name = intel_get_function_name, |
772 | .get_function_groups = intel_get_function_groups, |
773 | .set_mux = byt_set_mux, |
774 | .gpio_request_enable = byt_gpio_request_enable, |
775 | .gpio_disable_free = byt_gpio_disable_free, |
776 | .gpio_set_direction = byt_gpio_set_direction, |
777 | }; |
778 | |
779 | static void byt_get_pull_strength(u32 reg, u16 *strength) |
780 | { |
781 | switch (reg & BYT_PULL_STR_MASK) { |
782 | case BYT_PULL_STR_2K: |
783 | *strength = 2000; |
784 | break; |
785 | case BYT_PULL_STR_10K: |
786 | *strength = 10000; |
787 | break; |
788 | case BYT_PULL_STR_20K: |
789 | *strength = 20000; |
790 | break; |
791 | case BYT_PULL_STR_40K: |
792 | *strength = 40000; |
793 | break; |
794 | } |
795 | } |
796 | |
797 | static int byt_set_pull_strength(u32 *reg, u16 strength) |
798 | { |
799 | *reg &= ~BYT_PULL_STR_MASK; |
800 | |
801 | switch (strength) { |
802 | case 1: /* Set default strength value in case none is given */ |
803 | case 2000: |
804 | *reg |= BYT_PULL_STR_2K; |
805 | break; |
806 | case 10000: |
807 | *reg |= BYT_PULL_STR_10K; |
808 | break; |
809 | case 20000: |
810 | *reg |= BYT_PULL_STR_20K; |
811 | break; |
812 | case 40000: |
813 | *reg |= BYT_PULL_STR_40K; |
814 | break; |
815 | default: |
816 | return -EINVAL; |
817 | } |
818 | |
819 | return 0; |
820 | } |
821 | |
822 | static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset) |
823 | { |
824 | void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
825 | u32 value; |
826 | |
827 | value = readl(addr: reg); |
828 | if (!(value & BYT_INPUT_EN)) |
829 | return; |
830 | |
831 | /* |
832 | * Pull assignment is only applicable in input mode. If |
833 | * chip is not in input mode, set it and warn about it. |
834 | */ |
835 | value &= ~BYT_INPUT_EN; |
836 | writel(val: value, addr: reg); |
837 | dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n" , offset); |
838 | } |
839 | |
840 | static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, |
841 | unsigned long *config) |
842 | { |
843 | struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev: pctl_dev); |
844 | enum pin_config_param param = pinconf_to_config_param(config: *config); |
845 | void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); |
846 | void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
847 | void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); |
848 | u32 conf, pull, val, debounce; |
849 | u16 arg = 0; |
850 | |
851 | scoped_guard(raw_spinlock_irqsave, &byt_lock) { |
852 | conf = readl(addr: conf_reg); |
853 | val = readl(addr: val_reg); |
854 | } |
855 | |
856 | pull = conf & BYT_PULL_ASSIGN_MASK; |
857 | |
858 | switch (param) { |
859 | case PIN_CONFIG_BIAS_DISABLE: |
860 | if (pull) |
861 | return -EINVAL; |
862 | break; |
863 | case PIN_CONFIG_BIAS_PULL_DOWN: |
864 | /* Pull assignment is only applicable in input mode */ |
865 | if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) |
866 | return -EINVAL; |
867 | |
868 | byt_get_pull_strength(reg: conf, strength: &arg); |
869 | |
870 | break; |
871 | case PIN_CONFIG_BIAS_PULL_UP: |
872 | /* Pull assignment is only applicable in input mode */ |
873 | if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) |
874 | return -EINVAL; |
875 | |
876 | byt_get_pull_strength(reg: conf, strength: &arg); |
877 | |
878 | break; |
879 | case PIN_CONFIG_INPUT_DEBOUNCE: |
880 | if (!(conf & BYT_DEBOUNCE_EN)) |
881 | return -EINVAL; |
882 | |
883 | scoped_guard(raw_spinlock_irqsave, &byt_lock) |
884 | debounce = readl(addr: db_reg); |
885 | |
886 | switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { |
887 | case BYT_DEBOUNCE_PULSE_375US: |
888 | arg = 375; |
889 | break; |
890 | case BYT_DEBOUNCE_PULSE_750US: |
891 | arg = 750; |
892 | break; |
893 | case BYT_DEBOUNCE_PULSE_1500US: |
894 | arg = 1500; |
895 | break; |
896 | case BYT_DEBOUNCE_PULSE_3MS: |
897 | arg = 3000; |
898 | break; |
899 | case BYT_DEBOUNCE_PULSE_6MS: |
900 | arg = 6000; |
901 | break; |
902 | case BYT_DEBOUNCE_PULSE_12MS: |
903 | arg = 12000; |
904 | break; |
905 | case BYT_DEBOUNCE_PULSE_24MS: |
906 | arg = 24000; |
907 | break; |
908 | default: |
909 | return -EINVAL; |
910 | } |
911 | |
912 | break; |
913 | default: |
914 | return -ENOTSUPP; |
915 | } |
916 | |
917 | *config = pinconf_to_config_packed(param, argument: arg); |
918 | |
919 | return 0; |
920 | } |
921 | |
922 | static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, |
923 | unsigned int offset, |
924 | unsigned long *configs, |
925 | unsigned int num_configs) |
926 | { |
927 | struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev: pctl_dev); |
928 | void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); |
929 | void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); |
930 | u32 conf, db_pulse, debounce; |
931 | enum pin_config_param param; |
932 | int i, ret; |
933 | u32 arg; |
934 | |
935 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
936 | |
937 | conf = readl(addr: conf_reg); |
938 | |
939 | for (i = 0; i < num_configs; i++) { |
940 | param = pinconf_to_config_param(config: configs[i]); |
941 | arg = pinconf_to_config_argument(config: configs[i]); |
942 | |
943 | switch (param) { |
944 | case PIN_CONFIG_BIAS_DISABLE: |
945 | conf &= ~BYT_PULL_ASSIGN_MASK; |
946 | break; |
947 | case PIN_CONFIG_BIAS_PULL_DOWN: |
948 | byt_gpio_force_input_mode(vg, offset); |
949 | |
950 | conf &= ~BYT_PULL_ASSIGN_MASK; |
951 | conf |= BYT_PULL_ASSIGN_DOWN; |
952 | ret = byt_set_pull_strength(reg: &conf, strength: arg); |
953 | if (ret) |
954 | return ret; |
955 | |
956 | break; |
957 | case PIN_CONFIG_BIAS_PULL_UP: |
958 | byt_gpio_force_input_mode(vg, offset); |
959 | |
960 | conf &= ~BYT_PULL_ASSIGN_MASK; |
961 | conf |= BYT_PULL_ASSIGN_UP; |
962 | ret = byt_set_pull_strength(reg: &conf, strength: arg); |
963 | if (ret) |
964 | return ret; |
965 | |
966 | break; |
967 | case PIN_CONFIG_INPUT_DEBOUNCE: |
968 | switch (arg) { |
969 | case 0: |
970 | db_pulse = 0; |
971 | break; |
972 | case 375: |
973 | db_pulse = BYT_DEBOUNCE_PULSE_375US; |
974 | break; |
975 | case 750: |
976 | db_pulse = BYT_DEBOUNCE_PULSE_750US; |
977 | break; |
978 | case 1500: |
979 | db_pulse = BYT_DEBOUNCE_PULSE_1500US; |
980 | break; |
981 | case 3000: |
982 | db_pulse = BYT_DEBOUNCE_PULSE_3MS; |
983 | break; |
984 | case 6000: |
985 | db_pulse = BYT_DEBOUNCE_PULSE_6MS; |
986 | break; |
987 | case 12000: |
988 | db_pulse = BYT_DEBOUNCE_PULSE_12MS; |
989 | break; |
990 | case 24000: |
991 | db_pulse = BYT_DEBOUNCE_PULSE_24MS; |
992 | break; |
993 | default: |
994 | return -EINVAL; |
995 | } |
996 | |
997 | if (db_pulse) { |
998 | debounce = readl(addr: db_reg); |
999 | debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; |
1000 | writel(val: debounce, addr: db_reg); |
1001 | |
1002 | conf |= BYT_DEBOUNCE_EN; |
1003 | } else { |
1004 | conf &= ~BYT_DEBOUNCE_EN; |
1005 | } |
1006 | |
1007 | break; |
1008 | default: |
1009 | return -ENOTSUPP; |
1010 | } |
1011 | } |
1012 | |
1013 | writel(val: conf, addr: conf_reg); |
1014 | |
1015 | return 0; |
1016 | } |
1017 | |
1018 | static const struct pinconf_ops byt_pinconf_ops = { |
1019 | .is_generic = true, |
1020 | .pin_config_get = byt_pin_config_get, |
1021 | .pin_config_set = byt_pin_config_set, |
1022 | }; |
1023 | |
1024 | static const struct pinctrl_desc byt_pinctrl_desc = { |
1025 | .pctlops = &byt_pinctrl_ops, |
1026 | .pmxops = &byt_pinmux_ops, |
1027 | .confops = &byt_pinconf_ops, |
1028 | .owner = THIS_MODULE, |
1029 | }; |
1030 | |
1031 | static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) |
1032 | { |
1033 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1034 | void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
1035 | u32 val; |
1036 | |
1037 | scoped_guard(raw_spinlock_irqsave, &byt_lock) |
1038 | val = readl(addr: reg); |
1039 | |
1040 | return !!(val & BYT_LEVEL); |
1041 | } |
1042 | |
1043 | static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) |
1044 | { |
1045 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1046 | void __iomem *reg; |
1047 | u32 old_val; |
1048 | |
1049 | reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
1050 | if (!reg) |
1051 | return; |
1052 | |
1053 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1054 | |
1055 | old_val = readl(addr: reg); |
1056 | if (value) |
1057 | writel(val: old_val | BYT_LEVEL, addr: reg); |
1058 | else |
1059 | writel(val: old_val & ~BYT_LEVEL, addr: reg); |
1060 | } |
1061 | |
1062 | static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
1063 | { |
1064 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1065 | void __iomem *reg; |
1066 | u32 value; |
1067 | |
1068 | reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
1069 | if (!reg) |
1070 | return -EINVAL; |
1071 | |
1072 | scoped_guard(raw_spinlock_irqsave, &byt_lock) |
1073 | value = readl(addr: reg); |
1074 | |
1075 | if (!(value & BYT_OUTPUT_EN)) |
1076 | return GPIO_LINE_DIRECTION_OUT; |
1077 | if (!(value & BYT_INPUT_EN)) |
1078 | return GPIO_LINE_DIRECTION_IN; |
1079 | |
1080 | return -EINVAL; |
1081 | } |
1082 | |
1083 | static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
1084 | { |
1085 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1086 | void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
1087 | u32 reg; |
1088 | |
1089 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1090 | |
1091 | reg = readl(addr: val_reg); |
1092 | reg &= ~BYT_DIR_MASK; |
1093 | reg |= BYT_OUTPUT_EN; |
1094 | writel(val: reg, addr: val_reg); |
1095 | |
1096 | return 0; |
1097 | } |
1098 | |
1099 | /* |
1100 | * Note despite the temptation this MUST NOT be converted into a call to |
1101 | * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this |
1102 | * MUST be done as a single BYT_VAL_REG register write. |
1103 | * See the commit message of the commit adding this comment for details. |
1104 | */ |
1105 | static int byt_gpio_direction_output(struct gpio_chip *chip, |
1106 | unsigned int offset, int value) |
1107 | { |
1108 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1109 | void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); |
1110 | u32 reg; |
1111 | |
1112 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1113 | |
1114 | byt_gpio_direct_irq_check(vg, offset); |
1115 | |
1116 | reg = readl(addr: val_reg); |
1117 | reg &= ~BYT_DIR_MASK; |
1118 | if (value) |
1119 | reg |= BYT_LEVEL; |
1120 | else |
1121 | reg &= ~BYT_LEVEL; |
1122 | |
1123 | writel(val: reg, addr: val_reg); |
1124 | |
1125 | return 0; |
1126 | } |
1127 | |
1128 | static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
1129 | { |
1130 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1131 | int i; |
1132 | u32 conf0, val; |
1133 | |
1134 | for (i = 0; i < vg->soc->npins; i++) { |
1135 | const struct intel_community *comm; |
1136 | void __iomem *conf_reg, *val_reg; |
1137 | const char *pull_str = NULL; |
1138 | const char *pull = NULL; |
1139 | unsigned int pin; |
1140 | |
1141 | pin = vg->soc->pins[i].number; |
1142 | |
1143 | conf_reg = byt_gpio_reg(vg, offset: pin, BYT_CONF0_REG); |
1144 | if (!conf_reg) { |
1145 | seq_printf(m: s, fmt: "Pin %i: can't retrieve CONF0\n" , pin); |
1146 | continue; |
1147 | } |
1148 | |
1149 | val_reg = byt_gpio_reg(vg, offset: pin, BYT_VAL_REG); |
1150 | if (!val_reg) { |
1151 | seq_printf(m: s, fmt: "Pin %i: can't retrieve VAL\n" , pin); |
1152 | continue; |
1153 | } |
1154 | |
1155 | scoped_guard(raw_spinlock_irqsave, &byt_lock) { |
1156 | conf0 = readl(addr: conf_reg); |
1157 | val = readl(addr: val_reg); |
1158 | } |
1159 | |
1160 | comm = intel_get_community(pctrl: vg, pin); |
1161 | if (!comm) { |
1162 | seq_printf(m: s, fmt: "Pin %i: can't retrieve community\n" , pin); |
1163 | continue; |
1164 | } |
1165 | |
1166 | char *label __free(kfree) = gpiochip_dup_line_label(gc: chip, offset: i); |
1167 | if (IS_ERR(ptr: label)) |
1168 | continue; |
1169 | |
1170 | switch (conf0 & BYT_PULL_ASSIGN_MASK) { |
1171 | case BYT_PULL_ASSIGN_UP: |
1172 | pull = "up" ; |
1173 | break; |
1174 | case BYT_PULL_ASSIGN_DOWN: |
1175 | pull = "down" ; |
1176 | break; |
1177 | } |
1178 | |
1179 | switch (conf0 & BYT_PULL_STR_MASK) { |
1180 | case BYT_PULL_STR_2K: |
1181 | pull_str = "2k" ; |
1182 | break; |
1183 | case BYT_PULL_STR_10K: |
1184 | pull_str = "10k" ; |
1185 | break; |
1186 | case BYT_PULL_STR_20K: |
1187 | pull_str = "20k" ; |
1188 | break; |
1189 | case BYT_PULL_STR_40K: |
1190 | pull_str = "40k" ; |
1191 | break; |
1192 | } |
1193 | |
1194 | seq_printf(m: s, |
1195 | fmt: " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s" , |
1196 | pin, |
1197 | label ?: "Unrequested" , |
1198 | val & BYT_INPUT_EN ? " " : "in" , |
1199 | val & BYT_OUTPUT_EN ? " " : "out" , |
1200 | str_hi_lo(v: val & BYT_LEVEL), |
1201 | comm->pad_map[i], comm->pad_map[i] * 16, |
1202 | conf0 & 0x7, |
1203 | conf0 & BYT_TRIG_NEG ? " fall" : " " , |
1204 | conf0 & BYT_TRIG_POS ? " rise" : " " , |
1205 | conf0 & BYT_TRIG_LVL ? " level" : " " ); |
1206 | |
1207 | if (pull && pull_str) |
1208 | seq_printf(m: s, fmt: " %-4s %-3s" , pull, pull_str); |
1209 | else |
1210 | seq_puts(m: s, s: " " ); |
1211 | |
1212 | if (conf0 & BYT_IODEN) |
1213 | seq_puts(m: s, s: " open-drain" ); |
1214 | |
1215 | seq_puts(m: s, s: "\n" ); |
1216 | } |
1217 | } |
1218 | |
1219 | static const struct gpio_chip byt_gpio_chip = { |
1220 | .owner = THIS_MODULE, |
1221 | .request = gpiochip_generic_request, |
1222 | .free = gpiochip_generic_free, |
1223 | .get_direction = byt_gpio_get_direction, |
1224 | .direction_input = byt_gpio_direction_input, |
1225 | .direction_output = byt_gpio_direction_output, |
1226 | .get = byt_gpio_get, |
1227 | .set = byt_gpio_set, |
1228 | .set_config = gpiochip_generic_config, |
1229 | .dbg_show = byt_gpio_dbg_show, |
1230 | }; |
1231 | |
1232 | static void byt_irq_ack(struct irq_data *d) |
1233 | { |
1234 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1235 | struct intel_pinctrl *vg = gpiochip_get_data(gc); |
1236 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1237 | void __iomem *reg; |
1238 | |
1239 | reg = byt_gpio_reg(vg, offset: hwirq, BYT_INT_STAT_REG); |
1240 | if (!reg) |
1241 | return; |
1242 | |
1243 | guard(raw_spinlock)(l: &byt_lock); |
1244 | |
1245 | writel(BIT(hwirq % 32), addr: reg); |
1246 | } |
1247 | |
1248 | static void byt_irq_mask(struct irq_data *d) |
1249 | { |
1250 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1251 | struct intel_pinctrl *vg = gpiochip_get_data(gc); |
1252 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1253 | |
1254 | byt_gpio_clear_triggering(vg, offset: hwirq); |
1255 | gpiochip_disable_irq(gc, offset: hwirq); |
1256 | } |
1257 | |
1258 | static void byt_irq_unmask(struct irq_data *d) |
1259 | { |
1260 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1261 | struct intel_pinctrl *vg = gpiochip_get_data(gc); |
1262 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1263 | void __iomem *reg; |
1264 | u32 value; |
1265 | |
1266 | gpiochip_enable_irq(gc, offset: hwirq); |
1267 | |
1268 | reg = byt_gpio_reg(vg, offset: hwirq, BYT_CONF0_REG); |
1269 | if (!reg) |
1270 | return; |
1271 | |
1272 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1273 | |
1274 | value = readl(addr: reg); |
1275 | |
1276 | switch (irqd_get_trigger_type(d)) { |
1277 | case IRQ_TYPE_LEVEL_HIGH: |
1278 | value |= BYT_TRIG_LVL; |
1279 | fallthrough; |
1280 | case IRQ_TYPE_EDGE_RISING: |
1281 | value |= BYT_TRIG_POS; |
1282 | break; |
1283 | case IRQ_TYPE_LEVEL_LOW: |
1284 | value |= BYT_TRIG_LVL; |
1285 | fallthrough; |
1286 | case IRQ_TYPE_EDGE_FALLING: |
1287 | value |= BYT_TRIG_NEG; |
1288 | break; |
1289 | case IRQ_TYPE_EDGE_BOTH: |
1290 | value |= (BYT_TRIG_NEG | BYT_TRIG_POS); |
1291 | break; |
1292 | } |
1293 | |
1294 | writel(val: value, addr: reg); |
1295 | } |
1296 | |
1297 | static int byt_irq_type(struct irq_data *d, unsigned int type) |
1298 | { |
1299 | struct intel_pinctrl *vg = gpiochip_get_data(gc: irq_data_get_irq_chip_data(d)); |
1300 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1301 | void __iomem *reg; |
1302 | u32 value; |
1303 | |
1304 | reg = byt_gpio_reg(vg, offset: hwirq, BYT_CONF0_REG); |
1305 | if (!reg) |
1306 | return -EINVAL; |
1307 | |
1308 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1309 | |
1310 | value = readl(addr: reg); |
1311 | |
1312 | WARN(value & BYT_DIRECT_IRQ_EN, |
1313 | "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing" ); |
1314 | |
1315 | /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits |
1316 | * are used to indicate high and low level triggering |
1317 | */ |
1318 | value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | |
1319 | BYT_TRIG_LVL); |
1320 | /* Enable glitch filtering */ |
1321 | value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | |
1322 | BYT_GLITCH_F_FAST_CLK; |
1323 | |
1324 | writel(val: value, addr: reg); |
1325 | |
1326 | if (type & IRQ_TYPE_EDGE_BOTH) |
1327 | irq_set_handler_locked(data: d, handler: handle_edge_irq); |
1328 | else if (type & IRQ_TYPE_LEVEL_MASK) |
1329 | irq_set_handler_locked(data: d, handler: handle_level_irq); |
1330 | |
1331 | return 0; |
1332 | } |
1333 | |
1334 | static const struct irq_chip byt_gpio_irq_chip = { |
1335 | .name = "BYT-GPIO" , |
1336 | .irq_ack = byt_irq_ack, |
1337 | .irq_mask = byt_irq_mask, |
1338 | .irq_unmask = byt_irq_unmask, |
1339 | .irq_set_type = byt_irq_type, |
1340 | .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, |
1341 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
1342 | }; |
1343 | |
1344 | static void byt_gpio_irq_handler(struct irq_desc *desc) |
1345 | { |
1346 | struct irq_data *data = irq_desc_get_irq_data(desc); |
1347 | struct intel_pinctrl *vg = gpiochip_get_data(gc: irq_desc_get_handler_data(desc)); |
1348 | struct irq_chip *chip = irq_data_get_irq_chip(d: data); |
1349 | u32 base, pin; |
1350 | void __iomem *reg; |
1351 | unsigned long pending; |
1352 | |
1353 | /* check from GPIO controller which pin triggered the interrupt */ |
1354 | for (base = 0; base < vg->chip.ngpio; base += 32) { |
1355 | reg = byt_gpio_reg(vg, offset: base, BYT_INT_STAT_REG); |
1356 | |
1357 | if (!reg) { |
1358 | dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n" , base / 32, base); |
1359 | continue; |
1360 | } |
1361 | |
1362 | scoped_guard(raw_spinlock, &byt_lock) |
1363 | pending = readl(addr: reg); |
1364 | for_each_set_bit(pin, &pending, 32) |
1365 | generic_handle_domain_irq(domain: vg->chip.irq.domain, hwirq: base + pin); |
1366 | } |
1367 | chip->irq_eoi(data); |
1368 | } |
1369 | |
1370 | static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) |
1371 | { |
1372 | int direct_irq, ioapic_direct_irq_base; |
1373 | u8 *match, direct_irq_mux[16]; |
1374 | u32 trig; |
1375 | |
1376 | memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, |
1377 | sizeof(direct_irq_mux)); |
1378 | match = memchr(p: direct_irq_mux, c: pin, size: sizeof(direct_irq_mux)); |
1379 | if (!match) { |
1380 | dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n" , pin); |
1381 | return false; |
1382 | } |
1383 | |
1384 | direct_irq = match - direct_irq_mux; |
1385 | /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ |
1386 | ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; |
1387 | dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n" , pin, |
1388 | direct_irq, direct_irq + ioapic_direct_irq_base); |
1389 | |
1390 | /* |
1391 | * Testing has shown that the way direct IRQs work is that the combination of the |
1392 | * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ |
1393 | * trigger block, which normally sets the status flag in the IRQ status reg at |
1394 | * 0x800, to one of the IO-APIC pins according to the mux registers. |
1395 | * |
1396 | * This means that: |
1397 | * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block |
1398 | * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly |
1399 | * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, |
1400 | * selecting edge mode operation then on the first edge the IO-APIC pin goes |
1401 | * high, but since no write-to-clear write will be done to the IRQ status reg |
1402 | * at 0x800, the detected edge condition will never get cleared. |
1403 | */ |
1404 | trig = conf0 & BYT_TRIG_MASK; |
1405 | if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && |
1406 | trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { |
1407 | dev_warn(vg->dev, |
1408 | FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n" , |
1409 | pin, conf0); |
1410 | return false; |
1411 | } |
1412 | |
1413 | return true; |
1414 | } |
1415 | |
1416 | static void byt_init_irq_valid_mask(struct gpio_chip *chip, |
1417 | unsigned long *valid_mask, |
1418 | unsigned int ngpios) |
1419 | { |
1420 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1421 | void __iomem *reg; |
1422 | u32 value; |
1423 | int i; |
1424 | |
1425 | /* |
1426 | * Clear interrupt triggers for all pins that are GPIOs and |
1427 | * do not use direct IRQ mode. This will prevent spurious |
1428 | * interrupts from misconfigured pins. |
1429 | */ |
1430 | for (i = 0; i < vg->soc->npins; i++) { |
1431 | unsigned int pin = vg->soc->pins[i].number; |
1432 | |
1433 | reg = byt_gpio_reg(vg, offset: pin, BYT_CONF0_REG); |
1434 | if (!reg) { |
1435 | dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n" , i); |
1436 | continue; |
1437 | } |
1438 | |
1439 | value = readl(addr: reg); |
1440 | if (value & BYT_DIRECT_IRQ_EN) { |
1441 | if (byt_direct_irq_sanity_check(vg, pin: i, conf0: value)) { |
1442 | clear_bit(nr: i, addr: valid_mask); |
1443 | } else { |
1444 | value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | |
1445 | BYT_TRIG_NEG | BYT_TRIG_LVL); |
1446 | writel(val: value, addr: reg); |
1447 | } |
1448 | } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, offset: i)) { |
1449 | byt_gpio_clear_triggering(vg, offset: i); |
1450 | dev_dbg(vg->dev, "disabling GPIO %d\n" , i); |
1451 | } |
1452 | } |
1453 | } |
1454 | |
1455 | static int byt_gpio_irq_init_hw(struct gpio_chip *chip) |
1456 | { |
1457 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1458 | void __iomem *reg; |
1459 | u32 base, value; |
1460 | |
1461 | /* clear interrupt status trigger registers */ |
1462 | for (base = 0; base < vg->soc->npins; base += 32) { |
1463 | reg = byt_gpio_reg(vg, offset: base, BYT_INT_STAT_REG); |
1464 | |
1465 | if (!reg) { |
1466 | dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n" , base / 32, base); |
1467 | continue; |
1468 | } |
1469 | |
1470 | writel(val: 0xffffffff, addr: reg); |
1471 | /* make sure trigger bits are cleared, if not then a pin |
1472 | might be misconfigured in bios */ |
1473 | value = readl(addr: reg); |
1474 | if (value) |
1475 | dev_err(vg->dev, |
1476 | "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n" , |
1477 | base / 32, value); |
1478 | } |
1479 | |
1480 | return 0; |
1481 | } |
1482 | |
1483 | static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) |
1484 | { |
1485 | struct intel_pinctrl *vg = gpiochip_get_data(gc: chip); |
1486 | struct device *dev = vg->dev; |
1487 | int ret; |
1488 | |
1489 | ret = gpiochip_add_pin_range(gc: chip, pinctl_name: dev_name(dev), gpio_offset: 0, pin_offset: 0, npins: vg->soc->npins); |
1490 | if (ret) |
1491 | dev_err(dev, "failed to add GPIO pin range\n" ); |
1492 | |
1493 | return ret; |
1494 | } |
1495 | |
1496 | static int byt_gpio_probe(struct intel_pinctrl *vg) |
1497 | { |
1498 | struct platform_device *pdev = to_platform_device(vg->dev); |
1499 | struct gpio_chip *gc; |
1500 | int irq, ret; |
1501 | |
1502 | /* Set up gpio chip */ |
1503 | vg->chip = byt_gpio_chip; |
1504 | gc = &vg->chip; |
1505 | gc->label = dev_name(dev: vg->dev); |
1506 | gc->base = -1; |
1507 | gc->can_sleep = false; |
1508 | gc->add_pin_ranges = byt_gpio_add_pin_ranges; |
1509 | gc->parent = vg->dev; |
1510 | gc->ngpio = vg->soc->npins; |
1511 | |
1512 | #ifdef CONFIG_PM_SLEEP |
1513 | vg->context.pads = devm_kcalloc(dev: vg->dev, n: gc->ngpio, size: sizeof(*vg->context.pads), |
1514 | GFP_KERNEL); |
1515 | if (!vg->context.pads) |
1516 | return -ENOMEM; |
1517 | #endif |
1518 | |
1519 | /* set up interrupts */ |
1520 | irq = platform_get_irq_optional(pdev, 0); |
1521 | if (irq > 0) { |
1522 | struct gpio_irq_chip *girq; |
1523 | |
1524 | girq = &gc->irq; |
1525 | gpio_irq_chip_set_chip(girq, chip: &byt_gpio_irq_chip); |
1526 | girq->init_hw = byt_gpio_irq_init_hw; |
1527 | girq->init_valid_mask = byt_init_irq_valid_mask; |
1528 | girq->parent_handler = byt_gpio_irq_handler; |
1529 | girq->num_parents = 1; |
1530 | girq->parents = devm_kcalloc(dev: vg->dev, n: girq->num_parents, |
1531 | size: sizeof(*girq->parents), GFP_KERNEL); |
1532 | if (!girq->parents) |
1533 | return -ENOMEM; |
1534 | girq->parents[0] = irq; |
1535 | girq->default_type = IRQ_TYPE_NONE; |
1536 | girq->handler = handle_bad_irq; |
1537 | } |
1538 | |
1539 | ret = devm_gpiochip_add_data(vg->dev, gc, vg); |
1540 | if (ret) { |
1541 | dev_err(vg->dev, "failed adding byt-gpio chip\n" ); |
1542 | return ret; |
1543 | } |
1544 | |
1545 | return ret; |
1546 | } |
1547 | |
1548 | static int byt_set_soc_data(struct intel_pinctrl *vg, |
1549 | const struct intel_pinctrl_soc_data *soc) |
1550 | { |
1551 | struct platform_device *pdev = to_platform_device(vg->dev); |
1552 | int i; |
1553 | |
1554 | vg->soc = soc; |
1555 | |
1556 | vg->ncommunities = vg->soc->ncommunities; |
1557 | vg->communities = devm_kcalloc(dev: vg->dev, n: vg->ncommunities, |
1558 | size: sizeof(*vg->communities), GFP_KERNEL); |
1559 | if (!vg->communities) |
1560 | return -ENOMEM; |
1561 | |
1562 | for (i = 0; i < vg->soc->ncommunities; i++) { |
1563 | struct intel_community *comm = vg->communities + i; |
1564 | |
1565 | *comm = vg->soc->communities[i]; |
1566 | |
1567 | comm->pad_regs = devm_platform_ioremap_resource(pdev, index: 0); |
1568 | if (IS_ERR(ptr: comm->pad_regs)) |
1569 | return PTR_ERR(ptr: comm->pad_regs); |
1570 | } |
1571 | |
1572 | return 0; |
1573 | } |
1574 | |
1575 | static const struct acpi_device_id byt_gpio_acpi_match[] = { |
1576 | { "INT33B2" , (kernel_ulong_t)byt_soc_data }, |
1577 | { "INT33FC" , (kernel_ulong_t)byt_soc_data }, |
1578 | { } |
1579 | }; |
1580 | |
1581 | static int byt_pinctrl_probe(struct platform_device *pdev) |
1582 | { |
1583 | const struct intel_pinctrl_soc_data *soc_data; |
1584 | struct device *dev = &pdev->dev; |
1585 | struct intel_pinctrl *vg; |
1586 | int ret; |
1587 | |
1588 | soc_data = intel_pinctrl_get_soc_data(pdev); |
1589 | if (IS_ERR(ptr: soc_data)) |
1590 | return PTR_ERR(ptr: soc_data); |
1591 | |
1592 | vg = devm_kzalloc(dev, size: sizeof(*vg), GFP_KERNEL); |
1593 | if (!vg) |
1594 | return -ENOMEM; |
1595 | |
1596 | vg->dev = dev; |
1597 | ret = byt_set_soc_data(vg, soc: soc_data); |
1598 | if (ret) { |
1599 | dev_err(dev, "failed to set soc data\n" ); |
1600 | return ret; |
1601 | } |
1602 | |
1603 | vg->pctldesc = byt_pinctrl_desc; |
1604 | vg->pctldesc.name = dev_name(dev); |
1605 | vg->pctldesc.pins = vg->soc->pins; |
1606 | vg->pctldesc.npins = vg->soc->npins; |
1607 | |
1608 | vg->pctldev = devm_pinctrl_register(dev, pctldesc: &vg->pctldesc, driver_data: vg); |
1609 | if (IS_ERR(ptr: vg->pctldev)) { |
1610 | dev_err(dev, "failed to register pinctrl driver\n" ); |
1611 | return PTR_ERR(ptr: vg->pctldev); |
1612 | } |
1613 | |
1614 | ret = byt_gpio_probe(vg); |
1615 | if (ret) |
1616 | return ret; |
1617 | |
1618 | platform_set_drvdata(pdev, data: vg); |
1619 | |
1620 | return 0; |
1621 | } |
1622 | |
1623 | static int byt_gpio_suspend(struct device *dev) |
1624 | { |
1625 | struct intel_pinctrl *vg = dev_get_drvdata(dev); |
1626 | int i; |
1627 | |
1628 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1629 | |
1630 | for (i = 0; i < vg->soc->npins; i++) { |
1631 | void __iomem *reg; |
1632 | u32 value; |
1633 | unsigned int pin = vg->soc->pins[i].number; |
1634 | |
1635 | reg = byt_gpio_reg(vg, offset: pin, BYT_CONF0_REG); |
1636 | if (!reg) { |
1637 | dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n" , i); |
1638 | continue; |
1639 | } |
1640 | value = readl(addr: reg) & BYT_CONF0_RESTORE_MASK; |
1641 | vg->context.pads[i].conf0 = value; |
1642 | |
1643 | reg = byt_gpio_reg(vg, offset: pin, BYT_VAL_REG); |
1644 | if (!reg) { |
1645 | dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n" , i); |
1646 | continue; |
1647 | } |
1648 | value = readl(addr: reg) & BYT_VAL_RESTORE_MASK; |
1649 | vg->context.pads[i].val = value; |
1650 | } |
1651 | |
1652 | return 0; |
1653 | } |
1654 | |
1655 | static int byt_gpio_resume(struct device *dev) |
1656 | { |
1657 | struct intel_pinctrl *vg = dev_get_drvdata(dev); |
1658 | int i; |
1659 | |
1660 | guard(raw_spinlock_irqsave)(l: &byt_lock); |
1661 | |
1662 | for (i = 0; i < vg->soc->npins; i++) { |
1663 | void __iomem *reg; |
1664 | u32 value; |
1665 | unsigned int pin = vg->soc->pins[i].number; |
1666 | |
1667 | reg = byt_gpio_reg(vg, offset: pin, BYT_CONF0_REG); |
1668 | if (!reg) { |
1669 | dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n" , i); |
1670 | continue; |
1671 | } |
1672 | value = readl(addr: reg); |
1673 | if ((value & BYT_CONF0_RESTORE_MASK) != |
1674 | vg->context.pads[i].conf0) { |
1675 | value &= ~BYT_CONF0_RESTORE_MASK; |
1676 | value |= vg->context.pads[i].conf0; |
1677 | writel(val: value, addr: reg); |
1678 | dev_info(dev, "restored pin %d CONF0 %#08x" , i, value); |
1679 | } |
1680 | |
1681 | reg = byt_gpio_reg(vg, offset: pin, BYT_VAL_REG); |
1682 | if (!reg) { |
1683 | dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n" , i); |
1684 | continue; |
1685 | } |
1686 | value = readl(addr: reg); |
1687 | if ((value & BYT_VAL_RESTORE_MASK) != |
1688 | vg->context.pads[i].val) { |
1689 | u32 v; |
1690 | |
1691 | v = value & ~BYT_VAL_RESTORE_MASK; |
1692 | v |= vg->context.pads[i].val; |
1693 | if (v != value) { |
1694 | writel(val: v, addr: reg); |
1695 | dev_dbg(dev, "restored pin %d VAL %#08x\n" , i, v); |
1696 | } |
1697 | } |
1698 | } |
1699 | |
1700 | return 0; |
1701 | } |
1702 | |
1703 | static const struct dev_pm_ops byt_gpio_pm_ops = { |
1704 | LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) |
1705 | }; |
1706 | |
1707 | static struct platform_driver byt_gpio_driver = { |
1708 | .probe = byt_pinctrl_probe, |
1709 | .driver = { |
1710 | .name = "byt_gpio" , |
1711 | .pm = pm_sleep_ptr(&byt_gpio_pm_ops), |
1712 | .acpi_match_table = byt_gpio_acpi_match, |
1713 | .suppress_bind_attrs = true, |
1714 | }, |
1715 | }; |
1716 | |
1717 | static int __init byt_gpio_init(void) |
1718 | { |
1719 | return platform_driver_register(&byt_gpio_driver); |
1720 | } |
1721 | subsys_initcall(byt_gpio_init); |
1722 | |
1723 | MODULE_IMPORT_NS(PINCTRL_INTEL); |
1724 | |